From patchwork Mon Oct 17 12:35:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 13008824 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B514BC433FE for ; Mon, 17 Oct 2022 12:37:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=bg+EbLZlYh0+QHkK4IVJPFv4nTd1AL239oi106LFcLI=; b=LFO1ZUpuyR0xl4 fSTcbJpCNCf8fKVk7uD4yrg9KfhtfyIFhKtD6pMUKLK0NgoPRJ5q0mLcIIv8Ykd8DOYJTbS78vTrn lc55KybJuupRROpsrLnr1MqkPX0lYP912lu0fsCnghxtY7+H6WJQhnucDZFig3HYz5Ist2Du21xD2 eZRuvbSlk1tOfmZJqxclOo/G+GOa0CqCYpM8aBITcnZKPZ8tj+4F//wxHm66iw2yDKg/fy49gOAiG kBX0RpyR5p+X3p1Q5Q4kRNRiWY3yjzgeWvgUq2Zk4ptlaiCPF1KbRfvxZdn+XWsHY8h3yPUThl3in IxeQmVRx+HGJ5TRVc8Xg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1okPM6-00BaKD-9F; Mon, 17 Oct 2022 12:36:30 +0000 Received: from phobos.denx.de ([2a01:238:438b:c500:173d:9f52:ddab:ee01]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1okPLo-00Ba4Q-Iz for linux-arm-kernel@lists.infradead.org; Mon, 17 Oct 2022 12:36:17 +0000 Received: from tr.lan (ip-86-49-12-201.bb.vodafone.cz [86.49.12.201]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: marex@denx.de) by phobos.denx.de (Postfix) with ESMTPSA id C5FCE84E06; Mon, 17 Oct 2022 14:36:09 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1666010170; bh=DOvVtvyEibseifnPm8t7YwwjmceGYzm+7tMYlHa6jfY=; h=From:To:Cc:Subject:Date:From; b=YCcTIoov2rPyqnA8K7RskVsUFjfSlg05RTbVUM9HtBBpjU3X4GhhQMgotpsT1y+q2 yzHSLC6DiM2HP9aXYC6Fa7gdQOOhW8PbASonrJlAWEghHLOGBFfepLbiczMZUlEHe+ geGSWI4kJJLML8NaY2EagGtK92ji5O28775be2HAePPopiQkNAo0y3rtcNnvq94D2S /Qc2caohLKGMQOUl7Z8XvkM2DBzeM+ya2bhvrA3QzXNSi+5d30Hc6sWBaH7aJ8rCuv p8xLKbGrlvI8EWRfpch15iK2p4aLuraEmKf5KBbZqlhR+AcfXhC/AagJh82k9/c4xC MjDa6W0w2NeSQ== From: Marek Vasut To: linux-arm-kernel@lists.infradead.org Cc: Marek Vasut , Abhyuday Godhasara , Harsha , Michal Simek , Rajan Vaja , Ronak Jain , Tanmay Shah Subject: [PATCH] firmware: xilinx: Do not call IOCTL_SET_SD_TAPDELAY for value 0 Date: Mon, 17 Oct 2022 14:35:55 +0200 Message-Id: <20221017123555.97629-1-marex@denx.de> X-Mailer: git-send-email 2.35.1 MIME-Version: 1.0 X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221017_053613_024282_42BC5A88 X-CRM114-Status: GOOD ( 11.59 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org In case the tap delay required by Arasan SDHCI is set to 0, the current embeddedsw firmware unconditionally writes IOU_SLCR SD_ITAPDLY to 0x100 (SD0_ITAPDLYENA=1, SD0_ITAPDLYSEL=0). Previous behavior was to keep the IOU_SLCR SD_ITAPDLY set to 0x0. There is some sort of difference in the behavior between SD0_ITAPDLYENA=1/0 with the same SD0_ITAPDLYSEL=0, even though the behavior should be identical -- zero delay added to rxclk_in line. The former breaks HS200 training in low temperature conditions. Avoid writing the IOU_SLCR SD_ITAPDLY register in case value is 0 to keep the register at value 0x0 to reinstate the previous behavior that was present in Xilinx downstream fork of Linux 4.19.y and which prevented breakage of HS200 training in low temperature conditions. Note that the embeddedsw firmware does not permit clearing the SD_ITAPDLY SD0_ITAPDLYENA bit, this bit can only ever be set by the firmware and it is often impossible to update the possibly broken firmware. Signed-off-by: Marek Vasut --- Cc: Abhyuday Godhasara Cc: Harsha Cc: Michal Simek Cc: Rajan Vaja Cc: Ronak Jain Cc: Tanmay Shah To: linux-arm-kernel@lists.infradead.org --- drivers/firmware/xilinx/zynqmp.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c index ff5cabe70a2b2..12712f64fb932 100644 --- a/drivers/firmware/xilinx/zynqmp.c +++ b/drivers/firmware/xilinx/zynqmp.c @@ -738,6 +738,9 @@ EXPORT_SYMBOL_GPL(zynqmp_pm_get_pll_frac_data); */ int zynqmp_pm_set_sd_tapdelay(u32 node_id, u32 type, u32 value) { + if (!value) + return 0; + return zynqmp_pm_invoke_fn(PM_IOCTL, node_id, IOCTL_SET_SD_TAPDELAY, type, value, NULL); }