From patchwork Tue Oct 18 03:57:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brian Norris X-Patchwork-Id: 13009846 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 464BAC4332F for ; Tue, 18 Oct 2022 03:57:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229919AbiJRD5m (ORCPT ); Mon, 17 Oct 2022 23:57:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53680 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229892AbiJRD5l (ORCPT ); Mon, 17 Oct 2022 23:57:41 -0400 Received: from mail-pl1-x62b.google.com (mail-pl1-x62b.google.com [IPv6:2607:f8b0:4864:20::62b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D546723155 for ; Mon, 17 Oct 2022 20:57:39 -0700 (PDT) Received: by mail-pl1-x62b.google.com with SMTP id n7so12674748plp.1 for ; Mon, 17 Oct 2022 20:57:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/5SY8Nah0OJo40Eqd9ufrxakceznyXcaJJucJXEE6R0=; b=m3Yt3QI6+Z/DrLslxPJ/GzJKEJbJxlIPy8KAYZmEIRcp609iOKz/1AXizo0Chsx+uk ldcx7+d5tpLrsL/TW3piXuuC9bCYwaXfh7MoSV69B5rEG0ycLHN/v2/PNpBvwi03yFqu gFUwj9zrzvuH1GSY26F8RA0v/zQ7eMhlGc7ko= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/5SY8Nah0OJo40Eqd9ufrxakceznyXcaJJucJXEE6R0=; b=N0V9NpOwHWgGewf0OqysMzlLYTRSJuXd3/odvjUmJk0K58N67VxBeikUF6p5+7FdrU PIa9Eltwa9AyzzNENFpu6LIJdppGk8wZmjcWiIhkx/xmF4ulcbyVeHSd0Up9dhX2pNQ3 N+VKeJ7AyHwer6ZZ7P+C6HMZKOGIHVi+DpSWfD6kkekXNuSV6waq5pVoVzGoI7+otXM2 /TMQz8GHArjv6sf0mmAjV6xEc2NFGkdq3r7PHlMP3WOqdPymjaNcmtNVPZy6Fn2tZ8TE OCBH5AHkPfPvxBY5f5fhEoy4Nl0YQxz9Vg2hLvUF2Mt/ZlfaYd0PgUXoGsQr0kIVS1mm 6TFQ== X-Gm-Message-State: ACrzQf33SsZ7bl4X3Q1tjvvDhh6vmehnD5zfuy59IOClq6rZbGSnUxdk lK24CbElmSU/PTE5dbotUsjMWg== X-Google-Smtp-Source: AMsMyM6NWclKdvs2x3bS5AOs5cN15w5Ryx1WxcO+ICS16eS1oY7gmJdDCaLLyh3ZZaWCGlKUVoUPWw== X-Received: by 2002:a17:902:8e84:b0:178:71f2:113c with SMTP id bg4-20020a1709028e8400b0017871f2113cmr948888plb.79.1666065459409; Mon, 17 Oct 2022 20:57:39 -0700 (PDT) Received: from localhost ([2620:15c:9d:2:2ac3:f4e2:e908:c393]) by smtp.gmail.com with UTF8SMTPSA id h9-20020aa79f49000000b00537fb1f9f25sm7972272pfr.110.2022.10.17.20.57.37 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 17 Oct 2022 20:57:38 -0700 (PDT) From: Brian Norris To: Ulf Hansson Cc: Shawn Lin , Adrian Hunter , Shawn Guo , Fabio Estevam , Faiz Abbas , NXP Linux Team , Haibo Chen , Al Cooper , linux-mmc@vger.kernel.org, Pengutronix Kernel Team , linux-kernel@vger.kernel.org, Florian Fainelli , Sascha Hauer , Thierry Reding , Michal Simek , Jonathan Hunter , Sowjanya Komatineni , linux-arm-kernel@lists.infradead.org, Broadcom internal kernel review list , Brian Norris , stable@vger.kernel.org Subject: [PATCH 1/5] mmc: sdhci-of-arasan: Fix SDHCI_RESET_ALL for CQHCI Date: Mon, 17 Oct 2022 20:57:20 -0700 Message-Id: <20221017205610.1.I29f6a2189e84e35ad89c1833793dca9e36c64297@changeid> X-Mailer: git-send-email 2.38.0.413.g74048e4d9e-goog In-Reply-To: <20221018035724.2061127-1-briannorris@chromium.org> References: <20221018035724.2061127-1-briannorris@chromium.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org SDHCI_RESET_ALL resets will reset the hardware CQE state, but we aren't tracking that properly in software. When out of sync, we may trigger various timeouts. It's not typical to perform resets while CQE is enabled, but one particular case I hit commonly enough: mmc_suspend() -> mmc_power_off(). Typically we will eventually deactivate CQE (cqhci_suspend() -> cqhci_deactivate()), but that's not guaranteed -- in particular, if we perform a partial (e.g., interrupted) system suspend. The same bug was already found and fixed for two other drivers, in v5.7 and v5.9: 5cf583f1fb9c mmc: sdhci-msm: Deactivate CQE during SDHC reset df57d73276b8 mmc: sdhci-pci: Fix SDHCI_RESET_ALL for CQHCI for Intel GLK-based controllers The latter is especially prescient, saying "other drivers using CQHCI might benefit from a similar change, if they also have CQHCI reset by SDHCI_RESET_ALL." So like these other patches, deactivate CQHCI when resetting the controller. Also, move around the DT/caps handling, because sdhci_setup_host() performs resets before we've initialized CQHCI. This is the pattern followed in other SDHCI/CQHCI drivers. Fixes: 84362d79f436 ("mmc: sdhci-of-arasan: Add CQHCI support for arasan,sdhci-5.1") Cc: Signed-off-by: Brian Norris Reviewed-by: Guenter Roeck --- drivers/mmc/host/sdhci-of-arasan.c | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/drivers/mmc/host/sdhci-of-arasan.c b/drivers/mmc/host/sdhci-of-arasan.c index 3997cad1f793..1988a703781a 100644 --- a/drivers/mmc/host/sdhci-of-arasan.c +++ b/drivers/mmc/host/sdhci-of-arasan.c @@ -366,6 +366,10 @@ static void sdhci_arasan_reset(struct sdhci_host *host, u8 mask) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); + if ((host->mmc->caps2 & MMC_CAP2_CQE) && (mask & SDHCI_RESET_ALL) && + sdhci_arasan->has_cqe) + cqhci_deactivate(host->mmc); + sdhci_reset(host, mask); if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_FORCE_CDTEST) { @@ -1521,7 +1525,8 @@ static int sdhci_arasan_register_sdclk(struct sdhci_arasan_data *sdhci_arasan, return 0; } -static int sdhci_arasan_add_host(struct sdhci_arasan_data *sdhci_arasan) +static int sdhci_arasan_add_host(struct sdhci_arasan_data *sdhci_arasan, + struct device_node *np) { struct sdhci_host *host = sdhci_arasan->host; struct cqhci_host *cq_host; @@ -1549,6 +1554,10 @@ static int sdhci_arasan_add_host(struct sdhci_arasan_data *sdhci_arasan) if (dma64) cq_host->caps |= CQHCI_TASK_DESC_SZ_128; + host->mmc->caps2 |= MMC_CAP2_CQE; + if (!of_property_read_bool(np, "disable-cqe-dcmd")) + host->mmc->caps2 |= MMC_CAP2_CQE_DCMD; + ret = cqhci_init(cq_host, host->mmc, dma64); if (ret) goto cleanup; @@ -1705,13 +1714,9 @@ static int sdhci_arasan_probe(struct platform_device *pdev) host->mmc_host_ops.start_signal_voltage_switch = sdhci_arasan_voltage_switch; sdhci_arasan->has_cqe = true; - host->mmc->caps2 |= MMC_CAP2_CQE; - - if (!of_property_read_bool(np, "disable-cqe-dcmd")) - host->mmc->caps2 |= MMC_CAP2_CQE_DCMD; } - ret = sdhci_arasan_add_host(sdhci_arasan); + ret = sdhci_arasan_add_host(sdhci_arasan, np); if (ret) goto err_add_host; From patchwork Tue Oct 18 03:57:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brian Norris X-Patchwork-Id: 13009847 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7CB52C433FE for ; Tue, 18 Oct 2022 03:57:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229837AbiJRD5q (ORCPT ); Mon, 17 Oct 2022 23:57:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53756 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229934AbiJRD5n (ORCPT ); Mon, 17 Oct 2022 23:57:43 -0400 Received: from mail-pg1-x52e.google.com (mail-pg1-x52e.google.com [IPv6:2607:f8b0:4864:20::52e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B188D87095 for ; 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Mon, 17 Oct 2022 20:57:42 -0700 (PDT) Received: from localhost ([2620:15c:9d:2:2ac3:f4e2:e908:c393]) by smtp.gmail.com with UTF8SMTPSA id r8-20020aa79628000000b0056699fcdf6bsm7127084pfg.84.2022.10.17.20.57.40 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 17 Oct 2022 20:57:41 -0700 (PDT) From: Brian Norris To: Ulf Hansson Cc: Shawn Lin , Adrian Hunter , Shawn Guo , Fabio Estevam , Faiz Abbas , NXP Linux Team , Haibo Chen , Al Cooper , linux-mmc@vger.kernel.org, Pengutronix Kernel Team , linux-kernel@vger.kernel.org, Florian Fainelli , Sascha Hauer , Thierry Reding , Michal Simek , Jonathan Hunter , Sowjanya Komatineni , linux-arm-kernel@lists.infradead.org, Broadcom internal kernel review list , Brian Norris Subject: [PATCH 2/5] mmc: sdhci-brcmstb: Fix SDHCI_RESET_ALL for CQHCI Date: Mon, 17 Oct 2022 20:57:21 -0700 Message-Id: <20221017205610.2.I6a715feab6d01f760455865e968ecf0d85036018@changeid> X-Mailer: git-send-email 2.38.0.413.g74048e4d9e-goog In-Reply-To: <20221018035724.2061127-1-briannorris@chromium.org> References: <20221018035724.2061127-1-briannorris@chromium.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org [[ NOTE: this is completely untested by the author, but included solely because, as noted in commit df57d73276b8 ("mmc: sdhci-pci: Fix SDHCI_RESET_ALL for CQHCI for Intel GLK-based controllers"), "other drivers using CQHCI might benefit from a similar change, if they also have CQHCI reset by SDHCI_RESET_ALL." We've now seen the same bug on at least MSM, Arasan, and Intel hardware. ]] SDHCI_RESET_ALL resets will reset the hardware CQE state, but we aren't tracking that properly in software. When out of sync, we may trigger various timeouts. It's not typical to perform resets while CQE is enabled, but this may occur in some suspend or error recovery scenarios. Move around the CQE caps handling, because sdhci_setup_host() performs resets before we've initialized CQHCI. This is the pattern followed in other SDHCI/CQHCI drivers. Fixes: d46ba2d17f90 ("mmc: sdhci-brcmstb: Add support for Command Queuing (CQE)") Signed-off-by: Brian Norris --- drivers/mmc/host/sdhci-brcmstb.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci-brcmstb.c b/drivers/mmc/host/sdhci-brcmstb.c index aff36a933ebe..7f4bb362b923 100644 --- a/drivers/mmc/host/sdhci-brcmstb.c +++ b/drivers/mmc/host/sdhci-brcmstb.c @@ -55,6 +55,10 @@ static void brcmstb_reset(struct sdhci_host *host, u8 mask) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); struct sdhci_brcmstb_priv *priv = sdhci_pltfm_priv(pltfm_host); + if ((host->mmc->caps2 & MMC_CAP2_CQE) && (mask & SDHCI_RESET_ALL) && + (priv->flags & BRCMSTB_PRIV_FLAGS_HAS_CQE)) + cqhci_deactivate(host->mmc); + sdhci_reset(host, mask); /* Reset will clear this, so re-enable it */ @@ -209,7 +213,6 @@ static int sdhci_brcmstb_add_host(struct sdhci_host *host, return sdhci_add_host(host); dev_dbg(mmc_dev(host->mmc), "CQE is enabled\n"); - host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; ret = sdhci_setup_host(host); if (ret) return ret; @@ -230,6 +233,8 @@ static int sdhci_brcmstb_add_host(struct sdhci_host *host, cq_host->caps |= CQHCI_TASK_DESC_SZ_128; } + host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; + ret = cqhci_init(cq_host, host->mmc, dma64); if (ret) goto cleanup; From patchwork Tue Oct 18 03:57:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brian Norris X-Patchwork-Id: 13009848 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 25092C4332F for ; Tue, 18 Oct 2022 03:57:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230071AbiJRD5v (ORCPT ); Mon, 17 Oct 2022 23:57:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53868 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229933AbiJRD5r (ORCPT ); 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Mon, 17 Oct 2022 20:57:44 -0700 (PDT) From: Brian Norris To: Ulf Hansson Cc: Shawn Lin , Adrian Hunter , Shawn Guo , Fabio Estevam , Faiz Abbas , NXP Linux Team , Haibo Chen , Al Cooper , linux-mmc@vger.kernel.org, Pengutronix Kernel Team , linux-kernel@vger.kernel.org, Florian Fainelli , Sascha Hauer , Thierry Reding , Michal Simek , Jonathan Hunter , Sowjanya Komatineni , linux-arm-kernel@lists.infradead.org, Broadcom internal kernel review list , Brian Norris Subject: [PATCH 3/5] mms: sdhci-esdhc-imx: Fix SDHCI_RESET_ALL for CQHCI Date: Mon, 17 Oct 2022 20:57:22 -0700 Message-Id: <20221017205610.3.I7d01f9ad11bacdc9213dee61b7918982aea39115@changeid> X-Mailer: git-send-email 2.38.0.413.g74048e4d9e-goog In-Reply-To: <20221018035724.2061127-1-briannorris@chromium.org> References: <20221018035724.2061127-1-briannorris@chromium.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org [[ NOTE: this is completely untested by the author, but included solely because, as noted in commit df57d73276b8 ("mmc: sdhci-pci: Fix SDHCI_RESET_ALL for CQHCI for Intel GLK-based controllers"), "other drivers using CQHCI might benefit from a similar change, if they also have CQHCI reset by SDHCI_RESET_ALL." We've now seen the same bug on at least MSM, Arasan, and Intel hardware. ]] SDHCI_RESET_ALL resets will reset the hardware CQE state, but we aren't tracking that properly in software. When out of sync, we may trigger various timeouts. It's not typical to perform resets while CQE is enabled, but this may occur in some suspend or error recovery scenarios. Fixes: bb6e358169bf ("mmc: sdhci-esdhc-imx: add CMDQ support") Signed-off-by: Brian Norris --- drivers/mmc/host/sdhci-esdhc-imx.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c index 55981b0f0b10..222c83929e20 100644 --- a/drivers/mmc/host/sdhci-esdhc-imx.c +++ b/drivers/mmc/host/sdhci-esdhc-imx.c @@ -1288,6 +1288,13 @@ static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing) static void esdhc_reset(struct sdhci_host *host, u8 mask) { + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); + + if ((host->mmc->caps2 & MMC_CAP2_CQE) && (mask & SDHCI_RESET_ALL) && + imx_data->socdata->flags & ESDHC_FLAG_CQHCI) + cqhci_deactivate(host->mmc); + sdhci_reset(host, mask); sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); From patchwork Tue Oct 18 03:57:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brian Norris X-Patchwork-Id: 13009849 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AAEDDC433FE for ; Tue, 18 Oct 2022 03:58:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229751AbiJRD6W (ORCPT ); Mon, 17 Oct 2022 23:58:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53992 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230055AbiJRD5v (ORCPT ); Mon, 17 Oct 2022 23:57:51 -0400 Received: from mail-pf1-x432.google.com (mail-pf1-x432.google.com [IPv6:2607:f8b0:4864:20::432]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4966487FB6 for ; Mon, 17 Oct 2022 20:57:48 -0700 (PDT) Received: by mail-pf1-x432.google.com with SMTP id f140so12956507pfa.1 for ; Mon, 17 Oct 2022 20:57:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=LqIOfq4+r44BDEcAbAIaLunotKmu+d/0VAL/CFG/GZs=; b=UekqlQkGh6UA8fFw7UouK9kSktK5V9gIlB1tDGL6hleXWJrwAzg8cmt1FAgpk8CgWl a3uPfVhIqkx3w5XeROlfWH4A16t0gISqd0MOKefaZXYRf+hQ1/yA6Gu57WPgkCwc3tpv 7V4LoIT4ltSkFehTqR+xHgMgI+oJkDSxXtuqA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=LqIOfq4+r44BDEcAbAIaLunotKmu+d/0VAL/CFG/GZs=; b=RofQypNeShxJOj3DBVNAgcMSWa8lOdBSyLC28s8JUzH+ff/5Efny2IKMTZp4LzSK35 vr6YQ+uceWAwgbnnn+Vl6nXcUUx7gftFI05VpbfI0UR0vSe8dIt3GwIntkbBQu0mkTLO OTjiqZimOwIobeCCpipboefKHHMtdnXta4LxeDPCHtlm+KGToRbawf7hC+YESfaEhJ// mZOB1Z8jhJcvPrkhx09O8ZSg+Gfe/mzQNCy8B0nSq/PDvJgCBJ07tDkkxR+hOtj5bLAM l1246Jgr0HwPPhdnb/2hdWHEa+cz3NdRXpPasZIwjGZeZr/lnA13efHKmYakYqn6nvuY ojHA== X-Gm-Message-State: ACrzQf1RpZiG4VQOxqsu7gVqDebfj4T3DuFhFL7oKEm5b1i5rROqqJj4 ZpWgJZbmqqkWu82N3QcKf8srZw== X-Google-Smtp-Source: AMsMyM6ho3Yw2H44oOTg6yArRKh/f8YfOPn8UWoMF7c3LUoPZjSnRUSD0v76EISvEqYfqFagdhozeg== X-Received: by 2002:a63:f07:0:b0:440:5c6e:5833 with SMTP id e7-20020a630f07000000b004405c6e5833mr972776pgl.375.1666065467479; Mon, 17 Oct 2022 20:57:47 -0700 (PDT) Received: from localhost ([2620:15c:9d:2:2ac3:f4e2:e908:c393]) by smtp.gmail.com with UTF8SMTPSA id y69-20020a62ce48000000b0054124008c14sm7955449pfg.154.2022.10.17.20.57.45 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 17 Oct 2022 20:57:47 -0700 (PDT) From: Brian Norris To: Ulf Hansson Cc: Shawn Lin , Adrian Hunter , Shawn Guo , Fabio Estevam , Faiz Abbas , NXP Linux Team , Haibo Chen , Al Cooper , linux-mmc@vger.kernel.org, Pengutronix Kernel Team , linux-kernel@vger.kernel.org, Florian Fainelli , Sascha Hauer , Thierry Reding , Michal Simek , Jonathan Hunter , Sowjanya Komatineni , linux-arm-kernel@lists.infradead.org, Broadcom internal kernel review list , Brian Norris Subject: [PATCH 4/5] mmc: sdhci-tegra: Fix SDHCI_RESET_ALL for CQHCI Date: Mon, 17 Oct 2022 20:57:23 -0700 Message-Id: <20221017205610.4.I418c9eaaf754880fcd2698113e8c3ef821a944d7@changeid> X-Mailer: git-send-email 2.38.0.413.g74048e4d9e-goog In-Reply-To: <20221018035724.2061127-1-briannorris@chromium.org> References: <20221018035724.2061127-1-briannorris@chromium.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org [[ NOTE: this is completely untested by the author, but included solely because, as noted in commit df57d73276b8 ("mmc: sdhci-pci: Fix SDHCI_RESET_ALL for CQHCI for Intel GLK-based controllers"), "other drivers using CQHCI might benefit from a similar change, if they also have CQHCI reset by SDHCI_RESET_ALL." We've now seen the same bug on at least MSM, Arasan, and Intel hardware. ]] SDHCI_RESET_ALL resets will reset the hardware CQE state, but we aren't tracking that properly in software. When out of sync, we may trigger various timeouts. It's not typical to perform resets while CQE is enabled, but this may occur in some suspend or error recovery scenarios. Fixes: 3c4019f97978 ("mmc: tegra: HW Command Queue Support for Tegra SDMMC") Signed-off-by: Brian Norris --- drivers/mmc/host/sdhci-tegra.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c index 2d2d8260c681..d1d1ae9b2a86 100644 --- a/drivers/mmc/host/sdhci-tegra.c +++ b/drivers/mmc/host/sdhci-tegra.c @@ -367,6 +367,10 @@ static void tegra_sdhci_reset(struct sdhci_host *host, u8 mask) const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; u32 misc_ctrl, clk_ctrl, pad_ctrl; + if ((host->mmc->caps2 & MMC_CAP2_CQE) && (mask & SDHCI_RESET_ALL) && + tegra_host->enable_hwcq) + cqhci_deactivate(host->mmc); + sdhci_reset(host, mask); if (!(mask & SDHCI_RESET_ALL)) From patchwork Tue Oct 18 03:57:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brian Norris X-Patchwork-Id: 13009850 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B4756C433FE for ; Tue, 18 Oct 2022 03:58:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229939AbiJRD60 (ORCPT ); Mon, 17 Oct 2022 23:58:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54086 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230008AbiJRD5y (ORCPT ); Mon, 17 Oct 2022 23:57:54 -0400 Received: from mail-pl1-x635.google.com (mail-pl1-x635.google.com [IPv6:2607:f8b0:4864:20::635]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D2AB988DCB for ; Mon, 17 Oct 2022 20:57:51 -0700 (PDT) Received: by mail-pl1-x635.google.com with SMTP id 10so12705748pli.0 for ; Mon, 17 Oct 2022 20:57:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9p3m7T6e0mIj8rcCXtywVHD8sGWIzKCyjF4TP7KLyZQ=; b=F4EZTL9tVgb/GVZL3Pq3dG+YSUlqemGjgd1HKl8uW7Zv3ivDiffA8tbC7/7dWruKax 2LCuvRHAppGUX8X6oBUrN2c9Rq3xqt9/4nqMIWNlL+g8QUFp5AYvLHJji2VTBRoAUEDs 1E5N2J25qZgWy/Rxdk6krea1cWV1M/bcTxVsw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9p3m7T6e0mIj8rcCXtywVHD8sGWIzKCyjF4TP7KLyZQ=; b=E2LaSLzUZWNvxnjOMB/dT3PK+yrayqXQ918qzwRGvYUrri8nH4ZIis/EZYN9x6O+DX 1q30NMaaIjBNtWvsAr0LSawhNid9jnP5nB5j2b+xc7IQdMtiwG23trFj0YV8QwDQAtQ4 DasMTtp8e9AeopfzygagnsLsdMRNKf9eBpZpRhQeR+D0hBboLip+AUxPNQZIG+Ldj6bj ByYWdLlF5GsW/q3j7CgpCr/l8TLzPx6ic6ZDXu2b/A9MD0TzGK0rNt1t2xb2fYNQK/aa LD6vT0hnUaGgMt9X2vj2hlH4HGkXq3VAdjW2ye/JD68HGwbnxyPniBgTgAy94h1KuT3Y T6Dw== X-Gm-Message-State: ACrzQf3YPYawH1ES7JUkX5ONYIcalg13zOL6PQwt3uAH6qKnbZWAxFA/ 593N0W8l4wOXJwE/mfhc9cwXKQ== X-Google-Smtp-Source: AMsMyM4Oi5SI4xxHrO4wJahkDYqAgw2comRgFo0posUVaiivWN51Whl+zPIHJrd+P7q1UiVjJiRzBg== X-Received: by 2002:a17:90b:384f:b0:20d:4761:3394 with SMTP id nl15-20020a17090b384f00b0020d47613394mr1319039pjb.144.1666065470226; Mon, 17 Oct 2022 20:57:50 -0700 (PDT) Received: from localhost ([2620:15c:9d:2:2ac3:f4e2:e908:c393]) by smtp.gmail.com with UTF8SMTPSA id q23-20020a635c17000000b0043a0de69c94sm6805583pgb.14.2022.10.17.20.57.48 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 17 Oct 2022 20:57:49 -0700 (PDT) From: Brian Norris To: Ulf Hansson Cc: Shawn Lin , Adrian Hunter , Shawn Guo , Fabio Estevam , Faiz Abbas , NXP Linux Team , Haibo Chen , Al Cooper , linux-mmc@vger.kernel.org, Pengutronix Kernel Team , linux-kernel@vger.kernel.org, Florian Fainelli , Sascha Hauer , Thierry Reding , Michal Simek , Jonathan Hunter , Sowjanya Komatineni , linux-arm-kernel@lists.infradead.org, Broadcom internal kernel review list , Brian Norris Subject: [PATCH 5/5] mmc: sdhci_am654: Fix SDHCI_RESET_ALL for CQHCI Date: Mon, 17 Oct 2022 20:57:24 -0700 Message-Id: <20221017205610.5.I35ca9d6220ba48304438b992a76647ca8e5b126f@changeid> X-Mailer: git-send-email 2.38.0.413.g74048e4d9e-goog In-Reply-To: <20221018035724.2061127-1-briannorris@chromium.org> References: <20221018035724.2061127-1-briannorris@chromium.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org [[ NOTE: this is completely untested by the author, but included solely because, as noted in commit df57d73276b8 ("mmc: sdhci-pci: Fix SDHCI_RESET_ALL for CQHCI for Intel GLK-based controllers"), "other drivers using CQHCI might benefit from a similar change, if they also have CQHCI reset by SDHCI_RESET_ALL." We've now seen the same bug on at least MSM, Arasan, and Intel hardware. ]] SDHCI_RESET_ALL resets will reset the hardware CQE state, but we aren't tracking that properly in software. When out of sync, we may trigger various timeouts. It's not typical to perform resets while CQE is enabled, but this may occur in some suspend or error recovery scenarios. Fixes: f545702b74f9 ("mmc: sdhci_am654: Add Support for Command Queuing Engine to J721E") Signed-off-by: Brian Norris --- drivers/mmc/host/sdhci_am654.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/mmc/host/sdhci_am654.c b/drivers/mmc/host/sdhci_am654.c index 8f1023480e12..187a21086791 100644 --- a/drivers/mmc/host/sdhci_am654.c +++ b/drivers/mmc/host/sdhci_am654.c @@ -378,6 +378,9 @@ static void sdhci_am654_reset(struct sdhci_host *host, u8 mask) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); + if ((host->mmc->caps2 & MMC_CAP2_CQE) && (mask & SDHCI_RESET_ALL)) + cqhci_deactivate(host->mmc); + sdhci_reset(host, mask); if (sdhci_am654->quirks & SDHCI_AM654_QUIRK_FORCE_CDTEST) {