From patchwork Tue Oct 18 08:58:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Siddharth Vadapalli X-Patchwork-Id: 13010165 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D97E0C4332F for ; Tue, 18 Oct 2022 08:58:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230117AbiJRI6v (ORCPT ); Tue, 18 Oct 2022 04:58:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47538 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231137AbiJRI6q (ORCPT ); Tue, 18 Oct 2022 04:58:46 -0400 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BB97B5601B; Tue, 18 Oct 2022 01:58:44 -0700 (PDT) Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 29I8wKVS043072; Tue, 18 Oct 2022 03:58:20 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1666083500; bh=fiJqSuC8rqk4lF90DGjukNBCSWf2butQagXjLdw25pw=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=UD34uEE5FF+e7q48GYYHr2joWia1WkYWGYJG3ogPrvRlCNAPe9TPOoK2jDvEmtd9f w6zQfdtbHJktURQF8Yj6gmlkVRaJ3oQG2AJrmbzX24JN4bP/uQbyYQbZiQFJmMxm5z xOkUN3CGk+0Gc9OcIR3rmLlmXyDOrEk/g0DD2+to= Received: from DLEE100.ent.ti.com (dlee100.ent.ti.com [157.170.170.30]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 29I8wKk2014881 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 18 Oct 2022 03:58:20 -0500 Received: from DLEE100.ent.ti.com (157.170.170.30) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6; Tue, 18 Oct 2022 03:58:20 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6 via Frontend Transport; Tue, 18 Oct 2022 03:58:20 -0500 Received: from uda0492258.dhcp.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 29I8wAcP010100; Tue, 18 Oct 2022 03:58:15 -0500 From: Siddharth Vadapalli To: , , , , , , , , , , CC: , , , , Subject: [PATCH v2 1/3] dt-bindings: net: ti: k3-am654-cpsw-nuss: Update bindings for J721e CPSW9G Date: Tue, 18 Oct 2022 14:28:08 +0530 Message-ID: <20221018085810.151327-2-s-vadapalli@ti.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221018085810.151327-1-s-vadapalli@ti.com> References: <20221018085810.151327-1-s-vadapalli@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org Update bindings for TI K3 J721e SoC which contains 9 ports (8 external ports) CPSW9G module and add compatible for it. Changes made: - Add new compatible ti,j721e-cpswxg-nuss for CPSW9G. - Extend pattern properties for new compatible. - Change maximum number of CPSW ports to 8 for new compatible. Signed-off-by: Siddharth Vadapalli --- .../bindings/net/ti,k3-am654-cpsw-nuss.yaml | 23 +++++++++++++++++-- 1 file changed, 21 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/net/ti,k3-am654-cpsw-nuss.yaml b/Documentation/devicetree/bindings/net/ti,k3-am654-cpsw-nuss.yaml index 821974815dec..ec4b57e43e88 100644 --- a/Documentation/devicetree/bindings/net/ti,k3-am654-cpsw-nuss.yaml +++ b/Documentation/devicetree/bindings/net/ti,k3-am654-cpsw-nuss.yaml @@ -57,6 +57,7 @@ properties: - ti,am654-cpsw-nuss - ti,j7200-cpswxg-nuss - ti,j721e-cpsw-nuss + - ti,j721e-cpswxg-nuss - ti,am642-cpsw-nuss reg: @@ -111,7 +112,7 @@ properties: const: 0 patternProperties: - "^port@[1-4]$": + "^port@[1-8]$": type: object description: CPSWxG NUSS external ports @@ -121,7 +122,7 @@ properties: properties: reg: minimum: 1 - maximum: 4 + maximum: 8 description: CPSW port number phys: @@ -181,6 +182,21 @@ required: - '#size-cells' allOf: + - if: + not: + properties: + compatible: + contains: + const: ti,j721e-cpswxg-nuss + then: + properties: + ethernet-ports: + patternProperties: + "^port@[5-8]$": false + properties: + reg: + maximum: 4 + - if: not: properties: @@ -192,6 +208,9 @@ allOf: ethernet-ports: patternProperties: "^port@[3-4]$": false + properties: + reg: + maximum: 2 additionalProperties: false From patchwork Tue Oct 18 08:58:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Siddharth Vadapalli X-Patchwork-Id: 13010163 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 57254C433FE for ; Tue, 18 Oct 2022 08:58:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230136AbiJRI6o (ORCPT ); Tue, 18 Oct 2022 04:58:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47462 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230117AbiJRI6j (ORCPT ); Tue, 18 Oct 2022 04:58:39 -0400 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0E45743E6C; Tue, 18 Oct 2022 01:58:38 -0700 (PDT) Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 29I8wO1e041998; Tue, 18 Oct 2022 03:58:24 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1666083504; bh=YWx1XDLf8Fl9cqZIj0Gsk1/WG+6R5ZNcITJYTKSR0nQ=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Q7PrCT5OvDI/UY5oLtO+1AnaQQXD/9sp+b96xcDkWwdvrXZpuYPX43ExPGxj/psMh la71S5OpzyE6ikATx6DLwf13yzWxFMZq1xDhBEtDMC61HFG8o/IaEau+6Vb9amMk/g gpvu2HedNN/iYCcF/KHsOBT9qPamYr/IQa0VxfMo= Received: from DFLE111.ent.ti.com (dfle111.ent.ti.com [10.64.6.32]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 29I8wONe126566 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 18 Oct 2022 03:58:24 -0500 Received: from DFLE113.ent.ti.com (10.64.6.34) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6; Tue, 18 Oct 2022 03:58:24 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6 via Frontend Transport; Tue, 18 Oct 2022 03:58:24 -0500 Received: from uda0492258.dhcp.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 29I8wAcQ010100; Tue, 18 Oct 2022 03:58:20 -0500 From: Siddharth Vadapalli To: , , , , , , , , , , CC: , , , , Subject: [PATCH v2 2/3] net: ethernet: ti: am65-cpsw: Enable QSGMII mode for J721e CPSW9G Date: Tue, 18 Oct 2022 14:28:09 +0530 Message-ID: <20221018085810.151327-3-s-vadapalli@ti.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221018085810.151327-1-s-vadapalli@ti.com> References: <20221018085810.151327-1-s-vadapalli@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org CPSW9G in J721e supports additional modes like QSGMII. Add new compatible for J721e in am65-cpsw driver. Signed-off-by: Siddharth Vadapalli --- drivers/net/ethernet/ti/am65-cpsw-nuss.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/net/ethernet/ti/am65-cpsw-nuss.c b/drivers/net/ethernet/ti/am65-cpsw-nuss.c index 7f86068f3ff6..91e294afc3ad 100644 --- a/drivers/net/ethernet/ti/am65-cpsw-nuss.c +++ b/drivers/net/ethernet/ti/am65-cpsw-nuss.c @@ -2642,11 +2642,19 @@ static const struct am65_cpsw_pdata j7200_cpswxg_pdata = { .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII), }; +static const struct am65_cpsw_pdata j721e_cpswxg_pdata = { + .quirks = 0, + .ale_dev_id = "am64-cpswxg", + .fdqring_mode = K3_RINGACC_RING_MODE_MESSAGE, + .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII), +}; + static const struct of_device_id am65_cpsw_nuss_of_mtable[] = { { .compatible = "ti,am654-cpsw-nuss", .data = &am65x_sr1_0}, { .compatible = "ti,j721e-cpsw-nuss", .data = &j721e_pdata}, { .compatible = "ti,am642-cpsw-nuss", .data = &am64x_cpswxg_pdata}, { .compatible = "ti,j7200-cpswxg-nuss", .data = &j7200_cpswxg_pdata}, + { .compatible = "ti,j721e-cpswxg-nuss", .data = &j721e_cpswxg_pdata}, { /* sentinel */ }, }; MODULE_DEVICE_TABLE(of, am65_cpsw_nuss_of_mtable); From patchwork Tue Oct 18 08:58:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Siddharth Vadapalli X-Patchwork-Id: 13010164 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6DE66C433FE for ; Tue, 18 Oct 2022 08:58:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231153AbiJRI6r (ORCPT ); Tue, 18 Oct 2022 04:58:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47520 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230239AbiJRI6n (ORCPT ); Tue, 18 Oct 2022 04:58:43 -0400 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D230553A7D; Tue, 18 Oct 2022 01:58:41 -0700 (PDT) Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 29I8wTXO042014; Tue, 18 Oct 2022 03:58:29 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1666083509; bh=YkULLNGYTCiKKV3uTi6aQb+TYdDAV94MFgivkAOeMeU=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=M/k2ew09yjWhkh2bjwGbP16KWzPey6WbuksRdUqnWjIzpyfyMU7++7AcB6bGo8/9e Jl5zc7JOmlc8kJefWYTRLiIYldaOoVYu+I8nr+f1+oSu7nucd3UvqhqKQDn08k26Cj rMkxPLfdqeapLRLrkavCAsoo0/AWF06o2XFT++6E= Received: from DLEE112.ent.ti.com (dlee112.ent.ti.com [157.170.170.23]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 29I8wTaI030340 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 18 Oct 2022 03:58:29 -0500 Received: from DLEE115.ent.ti.com (157.170.170.26) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6; Tue, 18 Oct 2022 03:58:28 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6 via Frontend Transport; Tue, 18 Oct 2022 03:58:29 -0500 Received: from uda0492258.dhcp.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 29I8wAcR010100; Tue, 18 Oct 2022 03:58:24 -0500 From: Siddharth Vadapalli To: , , , , , , , , , , CC: , , , , Subject: [PATCH v2 3/3] net: ethernet: ti: am65-cpsw: Add support for SERDES configuration Date: Tue, 18 Oct 2022 14:28:10 +0530 Message-ID: <20221018085810.151327-4-s-vadapalli@ti.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221018085810.151327-1-s-vadapalli@ti.com> References: <20221018085810.151327-1-s-vadapalli@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org Use PHY framework APIs to initialize the SERDES PHY connected to CPSW MAC. Define the functions am65_cpsw_disable_phy(), am65_cpsw_enable_phy(), am65_cpsw_disable_serdes_phy() and am65_cpsw_init_serdes_phy(). Power on and initialize the SerDes PHY in am65_cpsw_nuss_init_slave_ports() by invoking am65_cpsw_init_serdes_phy(). Power off the SerDes PHY in am65_cpsw_nuss_remove() by invoking am65_cpsw_disable_serdes_phy(). Signed-off-by: Siddharth Vadapalli --- drivers/net/ethernet/ti/am65-cpsw-nuss.c | 65 ++++++++++++++++++++++++ 1 file changed, 65 insertions(+) diff --git a/drivers/net/ethernet/ti/am65-cpsw-nuss.c b/drivers/net/ethernet/ti/am65-cpsw-nuss.c index 91e294afc3ad..519ebd371dd8 100644 --- a/drivers/net/ethernet/ti/am65-cpsw-nuss.c +++ b/drivers/net/ethernet/ti/am65-cpsw-nuss.c @@ -1403,6 +1403,65 @@ static const struct net_device_ops am65_cpsw_nuss_netdev_ops = { .ndo_get_devlink_port = am65_cpsw_ndo_get_devlink_port, }; +static void am65_cpsw_disable_phy(struct phy *phy) +{ + phy_power_off(phy); + phy_exit(phy); +} + +static int am65_cpsw_enable_phy(struct phy *phy) +{ + int ret; + + ret = phy_init(phy); + if (ret < 0) + return ret; + + ret = phy_power_on(phy); + if (ret < 0) { + phy_exit(phy); + return ret; + } + + return 0; +} + +static void am65_cpsw_disable_serdes_phy(struct am65_cpsw_common *common) +{ + struct device_node *node, *port_np; + struct device *dev = common->dev; + const char *name = "serdes-phy"; + struct phy *phy; + + node = of_get_child_by_name(dev->of_node, "ethernet-ports"); + + for_each_child_of_node(node, port_np) { + phy = devm_of_phy_get(dev, port_np, name); + am65_cpsw_disable_phy(phy); + } +} + +static int am65_cpsw_init_serdes_phy(struct device *dev, struct device_node *port_np) +{ + const char *name = "serdes-phy"; + struct phy *phy; + int ret; + + phy = devm_of_phy_get(dev, port_np, name); + if (PTR_ERR(phy) == -ENODEV) + return 0; + + ret = am65_cpsw_enable_phy(phy); + if (ret < 0) + goto err_phy; + + return 0; + +err_phy: + devm_phy_put(dev, phy); + return ret; +} + static void am65_cpsw_nuss_mac_config(struct phylink_config *config, unsigned int mode, const struct phylink_link_state *state) { @@ -1880,6 +1939,11 @@ static int am65_cpsw_nuss_init_slave_ports(struct am65_cpsw_common *common) goto of_node_put; } + /* Initialize the phy for the port */ + ret = am65_cpsw_init_serdes_phy(dev, port_np); + if (ret) + return ret; + port->slave.mac_only = of_property_read_bool(port_np, "ti,mac-only"); @@ -2833,6 +2897,7 @@ static int am65_cpsw_nuss_remove(struct platform_device *pdev) am65_cpsw_nuss_phylink_cleanup(common); am65_cpsw_unregister_devlink(common); + am65_cpsw_disable_serdes_phy(common); am65_cpsw_unregister_notifiers(common); /* must unregister ndevs here because DD release_driver routine calls