From patchwork Tue Oct 18 14:08:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 13010604 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9C510C433FE for ; Tue, 18 Oct 2022 14:09:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230299AbiJROJp (ORCPT ); Tue, 18 Oct 2022 10:09:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49346 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230222AbiJROJj (ORCPT ); Tue, 18 Oct 2022 10:09:39 -0400 Received: from mail-pg1-x532.google.com (mail-pg1-x532.google.com [IPv6:2607:f8b0:4864:20::532]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 965CB1181D for ; Tue, 18 Oct 2022 07:09:32 -0700 (PDT) Received: by mail-pg1-x532.google.com with SMTP id bh13so13406742pgb.4 for ; Tue, 18 Oct 2022 07:09:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=DJ8EjICPlgkYNwiFOpcHJ6SbyD+51vA+/JJMHoSStf8=; b=DIiVRpTZRgqn7mHHz/kXbgBRQWCfm2s97L3rwVoI4dG6J52yjFY2SVTHFsH8fU6VZm /RvPt+tl6WGEYR1ResUPrMS/42KeYVd+pRdp647iicUxX6Aol21OVuRzh2etCbw8qtC/ l2Nqvqbp7N+XWp/IaQfUpfG9oYts/b8UkmpKeZVlAdSm+lef3CSAAZUWR5AhEk69oWO0 7uPM4o4hFsmTA18pzNv7e98sM4oFUTNaKp2Y8laRZ7l06c5Jg7qH1qEdIW9szHNQtjWP H4YaWNBbOVtmjfEFwfec5UabsSQhkmde/cFciaD9gpBoMyT5oI6e7j+zvC7wMhDKF2pH SPHQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DJ8EjICPlgkYNwiFOpcHJ6SbyD+51vA+/JJMHoSStf8=; b=JBMnTrcz9gC36nbkUM41C4MOlph7xrzhrPz6mFXVHIYXZpOuV2gSmFjdoo5IJCEj0y BqFb16NgAbwBpYq9aF8h5GRqXX2AQdG1uEVNTTZwDSbqzD+8eTaY4w3h5ir01v3KFpsM SiFIl+rQ1lVlr9FQS/45KCyLX51aCoErC9rAcaQB9/5add0TKTMbuTTPCQ9od2TIlVGS IRW9X4vpzoaIo2oPZIiuZ/8TyM3UEQmSKwC99M5bqvSXroXJwm2tAmET3IbDQ44f8gby g08j9ztQsuBR+JTiNSmU+Ukx/3R8xNif2qNUsuiH8HcElNwX69IoXrsDngtofIRrg+7W zKWw== X-Gm-Message-State: ACrzQf2I8LCohwfjTYUBBfqouqUeoKHb/Uampt1NlqrzRo/33m5egQNM 8y6slS6+Rskb63e6IkS2ofxUPA== X-Google-Smtp-Source: AMsMyM69Uz8/PcJIrUM+0yjYGd50qOw660QtgpbTUtcTNy4NBoT6+fHn1XtOY2k1bdRlyQSxdVWLnw== X-Received: by 2002:a05:6a00:1828:b0:563:24ea:5728 with SMTP id y40-20020a056a00182800b0056324ea5728mr3201327pfa.3.1666102171473; Tue, 18 Oct 2022 07:09:31 -0700 (PDT) Received: from anup-ubuntu64-vm.. ([171.76.86.161]) by smtp.gmail.com with ESMTPSA id z15-20020a17090a170f00b002009db534d1sm8119913pjd.24.2022.10.18.07.09.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Oct 2022 07:09:30 -0700 (PDT) From: Anup Patel To: Will Deacon , julien.thierry.kdev@gmail.com, maz@kernel.org Cc: Paolo Bonzini , Atish Patra , Alistair Francis , Anup Patel , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, Anup Patel Subject: [PATCH kvmtool 1/6] Update UAPI headers based on Linux-6.1-rc1 Date: Tue, 18 Oct 2022 19:38:49 +0530 Message-Id: <20221018140854.69846-2-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221018140854.69846-1-apatel@ventanamicro.com> References: <20221018140854.69846-1-apatel@ventanamicro.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org We update all UAPI headers based on Linux-6.1-rc1 so that we can use latest features. Signed-off-by: Anup Patel --- arm/aarch64/include/asm/kvm.h | 6 ++++-- include/linux/kvm.h | 1 + include/linux/virtio_blk.h | 19 +++++++++++++++++++ include/linux/virtio_net.h | 14 +++++++------- include/linux/virtio_ring.h | 16 +++++++++++----- riscv/include/asm/kvm.h | 4 ++++ 6 files changed, 46 insertions(+), 14 deletions(-) diff --git a/arm/aarch64/include/asm/kvm.h b/arm/aarch64/include/asm/kvm.h index 3bb1343..316917b 100644 --- a/arm/aarch64/include/asm/kvm.h +++ b/arm/aarch64/include/asm/kvm.h @@ -75,9 +75,11 @@ struct kvm_regs { /* KVM_ARM_SET_DEVICE_ADDR ioctl id encoding */ #define KVM_ARM_DEVICE_TYPE_SHIFT 0 -#define KVM_ARM_DEVICE_TYPE_MASK (0xffff << KVM_ARM_DEVICE_TYPE_SHIFT) +#define KVM_ARM_DEVICE_TYPE_MASK GENMASK(KVM_ARM_DEVICE_TYPE_SHIFT + 15, \ + KVM_ARM_DEVICE_TYPE_SHIFT) #define KVM_ARM_DEVICE_ID_SHIFT 16 -#define KVM_ARM_DEVICE_ID_MASK (0xffff << KVM_ARM_DEVICE_ID_SHIFT) +#define KVM_ARM_DEVICE_ID_MASK GENMASK(KVM_ARM_DEVICE_ID_SHIFT + 15, \ + KVM_ARM_DEVICE_ID_SHIFT) /* Supported device IDs */ #define KVM_ARM_DEVICE_VGIC_V2 0 diff --git a/include/linux/kvm.h b/include/linux/kvm.h index eed0315..0d5d441 100644 --- a/include/linux/kvm.h +++ b/include/linux/kvm.h @@ -1177,6 +1177,7 @@ struct kvm_ppc_resize_hpt { #define KVM_CAP_VM_DISABLE_NX_HUGE_PAGES 220 #define KVM_CAP_S390_ZPCI_OP 221 #define KVM_CAP_S390_CPU_TOPOLOGY 222 +#define KVM_CAP_DIRTY_LOG_RING_ACQ_REL 223 #ifdef KVM_CAP_IRQ_ROUTING diff --git a/include/linux/virtio_blk.h b/include/linux/virtio_blk.h index d888f01..58e70b2 100644 --- a/include/linux/virtio_blk.h +++ b/include/linux/virtio_blk.h @@ -40,6 +40,7 @@ #define VIRTIO_BLK_F_MQ 12 /* support more than one vq */ #define VIRTIO_BLK_F_DISCARD 13 /* DISCARD is supported */ #define VIRTIO_BLK_F_WRITE_ZEROES 14 /* WRITE ZEROES is supported */ +#define VIRTIO_BLK_F_SECURE_ERASE 16 /* Secure Erase is supported */ /* Legacy feature bits */ #ifndef VIRTIO_BLK_NO_LEGACY @@ -121,6 +122,21 @@ struct virtio_blk_config { __u8 write_zeroes_may_unmap; __u8 unused1[3]; + + /* the next 3 entries are guarded by VIRTIO_BLK_F_SECURE_ERASE */ + /* + * The maximum secure erase sectors (in 512-byte sectors) for + * one segment. + */ + __virtio32 max_secure_erase_sectors; + /* + * The maximum number of secure erase segments in a + * secure erase command. + */ + __virtio32 max_secure_erase_seg; + /* Secure erase commands must be aligned to this number of sectors. */ + __virtio32 secure_erase_sector_alignment; + } __attribute__((packed)); /* @@ -155,6 +171,9 @@ struct virtio_blk_config { /* Write zeroes command */ #define VIRTIO_BLK_T_WRITE_ZEROES 13 +/* Secure erase command */ +#define VIRTIO_BLK_T_SECURE_ERASE 14 + #ifndef VIRTIO_BLK_NO_LEGACY /* Barrier before this op. */ #define VIRTIO_BLK_T_BARRIER 0x80000000 diff --git a/include/linux/virtio_net.h b/include/linux/virtio_net.h index 29ced55..6cb842e 100644 --- a/include/linux/virtio_net.h +++ b/include/linux/virtio_net.h @@ -56,7 +56,7 @@ #define VIRTIO_NET_F_MQ 22 /* Device supports Receive Flow * Steering */ #define VIRTIO_NET_F_CTRL_MAC_ADDR 23 /* Set MAC address */ -#define VIRTIO_NET_F_NOTF_COAL 53 /* Guest can handle notifications coalescing */ +#define VIRTIO_NET_F_NOTF_COAL 53 /* Device supports notifications coalescing */ #define VIRTIO_NET_F_HASH_REPORT 57 /* Supports hash report */ #define VIRTIO_NET_F_RSS 60 /* Supports RSS RX steering */ #define VIRTIO_NET_F_RSC_EXT 61 /* extended coalescing info */ @@ -364,24 +364,24 @@ struct virtio_net_hash_config { */ #define VIRTIO_NET_CTRL_NOTF_COAL 6 /* - * Set the tx-usecs/tx-max-packets patameters. - * tx-usecs - Maximum number of usecs to delay a TX notification. - * tx-max-packets - Maximum number of packets to send before a TX notification. + * Set the tx-usecs/tx-max-packets parameters. */ struct virtio_net_ctrl_coal_tx { + /* Maximum number of packets to send before a TX notification */ __le32 tx_max_packets; + /* Maximum number of usecs to delay a TX notification */ __le32 tx_usecs; }; #define VIRTIO_NET_CTRL_NOTF_COAL_TX_SET 0 /* - * Set the rx-usecs/rx-max-packets patameters. - * rx-usecs - Maximum number of usecs to delay a RX notification. - * rx-max-frames - Maximum number of packets to receive before a RX notification. + * Set the rx-usecs/rx-max-packets parameters. */ struct virtio_net_ctrl_coal_rx { + /* Maximum number of packets to receive before a RX notification */ __le32 rx_max_packets; + /* Maximum number of usecs to delay a RX notification */ __le32 rx_usecs; }; diff --git a/include/linux/virtio_ring.h b/include/linux/virtio_ring.h index 476d3e5..f8c20d3 100644 --- a/include/linux/virtio_ring.h +++ b/include/linux/virtio_ring.h @@ -93,15 +93,21 @@ #define VRING_USED_ALIGN_SIZE 4 #define VRING_DESC_ALIGN_SIZE 16 -/* Virtio ring descriptors: 16 bytes. These can chain together via "next". */ +/** + * struct vring_desc - Virtio ring descriptors, + * 16 bytes long. These can chain together via @next. + * + * @addr: buffer address (guest-physical) + * @len: buffer length + * @flags: descriptor flags + * @next: index of the next descriptor in the chain, + * if the VRING_DESC_F_NEXT flag is set. We chain unused + * descriptors via this, too. + */ struct vring_desc { - /* Address (guest-physical). */ __virtio64 addr; - /* Length. */ __virtio32 len; - /* The flags as indicated above. */ __virtio16 flags; - /* We chain unused descriptors via this, too */ __virtio16 next; }; diff --git a/riscv/include/asm/kvm.h b/riscv/include/asm/kvm.h index 7351417..8985ff2 100644 --- a/riscv/include/asm/kvm.h +++ b/riscv/include/asm/kvm.h @@ -48,6 +48,7 @@ struct kvm_sregs { /* CONFIG registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */ struct kvm_riscv_config { unsigned long isa; + unsigned long zicbom_block_size; }; /* CORE registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */ @@ -98,6 +99,9 @@ enum KVM_RISCV_ISA_EXT_ID { KVM_RISCV_ISA_EXT_M, KVM_RISCV_ISA_EXT_SVPBMT, KVM_RISCV_ISA_EXT_SSTC, + KVM_RISCV_ISA_EXT_SVINVAL, + KVM_RISCV_ISA_EXT_ZIHINTPAUSE, + KVM_RISCV_ISA_EXT_ZICBOM, KVM_RISCV_ISA_EXT_MAX, }; From patchwork Tue Oct 18 14:08:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 13010605 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CCEA7C433FE for ; Tue, 18 Oct 2022 14:09:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230291AbiJROJv (ORCPT ); Tue, 18 Oct 2022 10:09:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49314 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230203AbiJROJo (ORCPT ); Tue, 18 Oct 2022 10:09:44 -0400 Received: from mail-pg1-x529.google.com (mail-pg1-x529.google.com [IPv6:2607:f8b0:4864:20::529]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 641EE17421 for ; Tue, 18 Oct 2022 07:09:37 -0700 (PDT) Received: by mail-pg1-x529.google.com with SMTP id b5so13409989pgb.6 for ; Tue, 18 Oct 2022 07:09:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=fQSIDFFVuF+EIt2cEUFNJqH3Rmj/qJAjRYREvcssnEc=; b=UoN1IAs8s/3Fu4+iotE3z0nvVddkbZfV9io2+cQEJ2uRjvmOc42FChGgaW7/2ZArc4 JykfKy8B2cQUacgccfC95J4iDc23qv7j+3R3fqAeat29lA+5vOfGACIAbI115WSFyEH0 Q9m/+w6FZpsdtvfrTdlLpteF9SAMBXzuI49N1uLhuD3QCuMFMoSYWaCQSW/BkSsniE+B zsjUaTtRhVvF1WC7ll/gWzlrAAh5pCdQJeMAefLl3GELEy3oPzu2mO1J9d5ZLfTpITPe DG6yQELJ2F/Z3h2OJJLxVJ6QV95wW7wvlMvX6c4y2JD1Twyb0B+bwmAfWcxaRnYPmMOC payQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fQSIDFFVuF+EIt2cEUFNJqH3Rmj/qJAjRYREvcssnEc=; b=XB6+1BtNoNmCsXjQo1X9KUVGBA7TpHQCjaELtvlVL2+ifkQw7cpGCWKBQKWk7qt7Ny wI9I84W08vLoshiwc0I+J8uiYDKN5sx6AQUMdBmjA7GkA4WUUDk1ytlJEJH1GNDNO7pN 0Uno+Es9nCJb8qQJkUTYXOQetPEbblNGvGd3PUPc9w2KS+FuHt4C4lPBNlMu/pE1uN8d qhb4kz7f/I5LlBxXn2iS2litZUVVJGRIky/18Bq5pCYxmsf6KlmpnCNue24AyXyaneG8 f6M7hCLc4zDpd6wzdioC0ZKNgnKg8pWX9iKVD2YhyQod5gGGYy1GXeiQYN51P1ayHyEf Adkw== X-Gm-Message-State: ACrzQf2bCzOJ1TUBTT5ZyXxhfUj+5/4Kl4CFcEdgbhmPyGD+PjXmZ8I1 LVDaDLbrmmjxT5Xw6zW7u5CMng== X-Google-Smtp-Source: AMsMyM4QqTc9RDg38FTb9jRNWuxsRXJuswFnY9rJKOUgJhDITlN1G5Ec8NTaf6OwumSzrdOyJpl96Q== X-Received: by 2002:a63:145d:0:b0:44b:f115:f90f with SMTP id 29-20020a63145d000000b0044bf115f90fmr2822412pgu.157.1666102176161; Tue, 18 Oct 2022 07:09:36 -0700 (PDT) Received: from anup-ubuntu64-vm.. ([171.76.86.161]) by smtp.gmail.com with ESMTPSA id z15-20020a17090a170f00b002009db534d1sm8119913pjd.24.2022.10.18.07.09.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Oct 2022 07:09:35 -0700 (PDT) From: Anup Patel To: Will Deacon , julien.thierry.kdev@gmail.com, maz@kernel.org Cc: Paolo Bonzini , Atish Patra , Alistair Francis , Anup Patel , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, Anup Patel Subject: [PATCH kvmtool 2/6] riscv: Add Svinval extension support Date: Tue, 18 Oct 2022 19:38:50 +0530 Message-Id: <20221018140854.69846-3-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221018140854.69846-1-apatel@ventanamicro.com> References: <20221018140854.69846-1-apatel@ventanamicro.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Svinval extension allows the guest OS to perform range based TLB maintenance efficiently. Add the Svinval extensiont to the device tree if it is supported by the host. Signed-off-by: Anup Patel --- riscv/fdt.c | 1 + 1 file changed, 1 insertion(+) diff --git a/riscv/fdt.c b/riscv/fdt.c index e3d7717..42bc062 100644 --- a/riscv/fdt.c +++ b/riscv/fdt.c @@ -19,6 +19,7 @@ struct isa_ext_info { struct isa_ext_info isa_info_arr[] = { {"svpbmt", KVM_RISCV_ISA_EXT_SVPBMT}, {"sstc", KVM_RISCV_ISA_EXT_SSTC}, + {"svinval", KVM_RISCV_ISA_EXT_SVINVAL}, }; static void dump_fdt(const char *dtb_file, void *fdt) From patchwork Tue Oct 18 14:08:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 13010606 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0385DC433FE for ; Tue, 18 Oct 2022 14:10:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230471AbiJROJ7 (ORCPT ); Tue, 18 Oct 2022 10:09:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49346 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230259AbiJROJs (ORCPT ); Tue, 18 Oct 2022 10:09:48 -0400 Received: from mail-pj1-x102b.google.com (mail-pj1-x102b.google.com [IPv6:2607:f8b0:4864:20::102b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4C7251F605 for ; Tue, 18 Oct 2022 07:09:44 -0700 (PDT) Received: by mail-pj1-x102b.google.com with SMTP id l1-20020a17090a72c100b0020a6949a66aso14119258pjk.1 for ; Tue, 18 Oct 2022 07:09:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=r2IpBJzC/KZLEhOakHFoNifjUYgUg4NurhrpOreBu/A=; b=i7BNkwhBmRa911t30Yz5CURDDoTYRau2vSyCQvKiKh5hBnfXfXdPATcb5C3HeuPbOO ZP848bhXlrfsq3kgizUEIYjnbfqggU5ahRGXNM90LmQdWnYU1snwdCJXHoJX2ThjUOiF ZX1UahzlEP4mVTQC+Pk5k4kPGHD3hndG0C00NmK+8rdXEEq4Je5wWKA9nUwoXfF0y+7V /du2jQfJzvAJZmXXAMQibYgcG/dNIyrpTLKEpnF78gUfF+G8pJcxYC9PsZUFJlsv4XYV HX7WA/MjzJQ/ZBaUUhn8GZLor4BWOmWJ4kZeKN07aWMr9uFq+9RQ6jMM+yOpqtF+GKuZ d5sQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=r2IpBJzC/KZLEhOakHFoNifjUYgUg4NurhrpOreBu/A=; b=YeCxn/HIv7FBD3JNv+d9Ew8du1IHn7Wa5i+6ae280jM6MwuDsC/r0I6tMIkBgNIf23 3VkOf/qDUJk7kYFTNEfLLxprP+IV7c22G5+CycVP8yp+6V+ZXK9GhF3Ruyfz1pCrP5nB +bfGZNqWDrrqe3HQJNPZt0b/h3Ub/vmQ0PgWAgAyDXSNAzqNAEnG4VlkScrRvRZdstx2 huBmenTTTQ4dmFclS8jf+ytl+PFhJk3UTvYKS5x9I5ZtmH42ot+YU+vYseObLqPZsK7b Tu/HOfZ/OD9VzG7dHSt+6Bs9oBKaZ+mdgzFKLhsLK3fuTTpc9QCotivR19AUvciL+lyj xKVw== X-Gm-Message-State: ACrzQf1ROmq167sF+yxiZtmtMITaSiP/4Z791DDXgDIqgiWqu7M3pu++ N666WbMB5cHmYWHqgltXc52XyQ== X-Google-Smtp-Source: AMsMyM5/1xD9nchl7YiD8PnipajH6ICLb8WzrqA2KonCjgdXWURk46jUpTdgmv0uhbUdbiWOuwle4Q== X-Received: by 2002:a17:903:240d:b0:183:9bab:9c3 with SMTP id e13-20020a170903240d00b001839bab09c3mr3318161plo.48.1666102183918; Tue, 18 Oct 2022 07:09:43 -0700 (PDT) Received: from anup-ubuntu64-vm.. ([171.76.86.161]) by smtp.gmail.com with ESMTPSA id z15-20020a17090a170f00b002009db534d1sm8119913pjd.24.2022.10.18.07.09.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Oct 2022 07:09:40 -0700 (PDT) From: Anup Patel To: Will Deacon , julien.thierry.kdev@gmail.com, maz@kernel.org Cc: Paolo Bonzini , Atish Patra , Alistair Francis , Anup Patel , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, Mayuresh Chitale Subject: [PATCH kvmtool 3/6] riscv: Add zihintpause extension support Date: Tue, 18 Oct 2022 19:38:51 +0530 Message-Id: <20221018140854.69846-4-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221018140854.69846-1-apatel@ventanamicro.com> References: <20221018140854.69846-1-apatel@ventanamicro.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Mayuresh Chitale The zihintpause extension allows software to use the PAUSE instruction to reduce energy consumption while executing spin-wait code sequences. Add the zihintpause extension to the device tree if it is supported by the host. Signed-off-by: Mayuresh Chitale --- riscv/fdt.c | 1 + 1 file changed, 1 insertion(+) diff --git a/riscv/fdt.c b/riscv/fdt.c index 42bc062..ef0bc47 100644 --- a/riscv/fdt.c +++ b/riscv/fdt.c @@ -20,6 +20,7 @@ struct isa_ext_info isa_info_arr[] = { {"svpbmt", KVM_RISCV_ISA_EXT_SVPBMT}, {"sstc", KVM_RISCV_ISA_EXT_SSTC}, {"svinval", KVM_RISCV_ISA_EXT_SVINVAL}, + {"zihintpause", KVM_RISCV_ISA_EXT_ZIHINTPAUSE}, }; static void dump_fdt(const char *dtb_file, void *fdt) From patchwork Tue Oct 18 14:08:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 13010607 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B35F2C4332F for ; Tue, 18 Oct 2022 14:10:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231311AbiJROKI (ORCPT ); Tue, 18 Oct 2022 10:10:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51232 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230366AbiJROJ5 (ORCPT ); Tue, 18 Oct 2022 10:09:57 -0400 Received: from mail-pl1-x632.google.com (mail-pl1-x632.google.com [IPv6:2607:f8b0:4864:20::632]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8DC7924BFD for ; Tue, 18 Oct 2022 07:09:49 -0700 (PDT) Received: by mail-pl1-x632.google.com with SMTP id k9so13508303pll.11 for ; Tue, 18 Oct 2022 07:09:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=mi3OAs84SzVBPhryxf2ZsSZ37TjM6IJmsjgpojTEKnM=; b=ea2VyPaevGOuNcc9XN5oBXqCdIxVdzh3HulObLalOaK18xQ5BGToy8ZdTMjE7CX+lW WWOJ6zom4emXHhj2L/w/h/IKCe0YHShrva+t8QFYeWg6+fNqAtCTTlcqX2e04o2iJBn+ a1ymN+x4CAQlwSYyXe/mwamYNsyL5sxl0e//d88oJjyiJOHxzpFleZvzYcMU+tSoiJLY SnDQGOt4C9sB8El4gWrgj5x5erEaOT+Prq7nUnOVXhVl29eF7ago2EpPSL2XYJ9Weg9c VC9BED7C7BmemQeJCqOZ3o8W2r201oNXRPce2UUsHCX0oSeCX1s4yT7J4gXi03+Ad93z jbaA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mi3OAs84SzVBPhryxf2ZsSZ37TjM6IJmsjgpojTEKnM=; b=amdnJJcLuHRN3+xDB7ytC07mEzuQOjdSU0+Ycl8qWUp0Zl8Tv2peFcXG+fOxb4gETa 8vTET9qfiQHfx0m12zjK9dAc2ryMAWPPVOR1ObfmmUk66J1dN71YFhhN/qsv3jOiouPa 5Hxc4ZmVMlSPi0SoQlVF8p1kOSuCNOjnvIZsFufDn1nQrDvvyujjvGm9f6XVosNcV5Kf GLwlvzyqN3pF6cDsQ0i1YUO+Lz1Zn2SuxL+EO03BDQhN9YwAgvYfLuWTkNXkTbh/3jwO l7FVLVmsTbOnkwgQBsLgMTi3bb7dW6q8HnDi7zz9vNnZLSQ3mclKdTVvYfIQDlvGynQR NaFw== X-Gm-Message-State: ACrzQf1FEXNUdYvODDfz36FZ1d8PVDngBJ+U7yQDaibN1IKwd0lLNh0N qrHfuC3GHMlmUEPPVfZt6YN6ow== X-Google-Smtp-Source: AMsMyM45WVWO8hcChugqdDf8Q8WxPdJUKNE3dnIWHgszCH6BwMey/owW3t6zGZv685a1AmzVTV60aA== X-Received: by 2002:a17:903:1250:b0:185:40c6:3c2c with SMTP id u16-20020a170903125000b0018540c63c2cmr3436236plh.64.1666102188179; Tue, 18 Oct 2022 07:09:48 -0700 (PDT) Received: from anup-ubuntu64-vm.. ([171.76.86.161]) by smtp.gmail.com with ESMTPSA id z15-20020a17090a170f00b002009db534d1sm8119913pjd.24.2022.10.18.07.09.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Oct 2022 07:09:47 -0700 (PDT) From: Anup Patel To: Will Deacon , julien.thierry.kdev@gmail.com, maz@kernel.org Cc: Paolo Bonzini , Atish Patra , Alistair Francis , Anup Patel , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, Andrew Jones Subject: [PATCH kvmtool 4/6] riscv: Move reg encoding helpers to kvm-cpu-arch.h Date: Tue, 18 Oct 2022 19:38:52 +0530 Message-Id: <20221018140854.69846-5-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221018140854.69846-1-apatel@ventanamicro.com> References: <20221018140854.69846-1-apatel@ventanamicro.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Andrew Jones We'll need one of these helpers in the next patch in another file. Let's proactively move them all now, since others may some day also be useful. Signed-off-by: Andrew Jones --- riscv/fdt.c | 2 -- riscv/include/kvm/kvm-cpu-arch.h | 19 +++++++++++++++++++ riscv/kvm-cpu.c | 16 ---------------- 3 files changed, 19 insertions(+), 18 deletions(-) diff --git a/riscv/fdt.c b/riscv/fdt.c index ef0bc47..8d6da11 100644 --- a/riscv/fdt.c +++ b/riscv/fdt.c @@ -9,8 +9,6 @@ #include #include -#define RISCV_ISA_EXT_REG(id) __kvm_reg_id(KVM_REG_RISCV_ISA_EXT, \ - id, KVM_REG_SIZE_ULONG) struct isa_ext_info { const char *name; unsigned long ext_id; diff --git a/riscv/include/kvm/kvm-cpu-arch.h b/riscv/include/kvm/kvm-cpu-arch.h index 4b3e602..e014839 100644 --- a/riscv/include/kvm/kvm-cpu-arch.h +++ b/riscv/include/kvm/kvm-cpu-arch.h @@ -18,6 +18,25 @@ static inline __u64 __kvm_reg_id(__u64 type, __u64 idx, __u64 size) #define KVM_REG_SIZE_ULONG KVM_REG_SIZE_U32 #endif +#define RISCV_CONFIG_REG(name) __kvm_reg_id(KVM_REG_RISCV_CONFIG, \ + KVM_REG_RISCV_CONFIG_REG(name), \ + KVM_REG_SIZE_ULONG) + +#define RISCV_ISA_EXT_REG(id) __kvm_reg_id(KVM_REG_RISCV_ISA_EXT, \ + id, KVM_REG_SIZE_ULONG) + +#define RISCV_CORE_REG(name) __kvm_reg_id(KVM_REG_RISCV_CORE, \ + KVM_REG_RISCV_CORE_REG(name), \ + KVM_REG_SIZE_ULONG) + +#define RISCV_CSR_REG(name) __kvm_reg_id(KVM_REG_RISCV_CSR, \ + KVM_REG_RISCV_CSR_REG(name), \ + KVM_REG_SIZE_ULONG) + +#define RISCV_TIMER_REG(name) __kvm_reg_id(KVM_REG_RISCV_TIMER, \ + KVM_REG_RISCV_TIMER_REG(name), \ + KVM_REG_SIZE_U64) + struct kvm_cpu { pthread_t thread; diff --git a/riscv/kvm-cpu.c b/riscv/kvm-cpu.c index a17b957..f98bd7a 100644 --- a/riscv/kvm-cpu.c +++ b/riscv/kvm-cpu.c @@ -18,22 +18,6 @@ int kvm_cpu__get_debug_fd(void) return debug_fd; } -#define RISCV_CONFIG_REG(name) __kvm_reg_id(KVM_REG_RISCV_CONFIG, \ - KVM_REG_RISCV_CONFIG_REG(name), \ - KVM_REG_SIZE_ULONG) - -#define RISCV_CORE_REG(name) __kvm_reg_id(KVM_REG_RISCV_CORE, \ - KVM_REG_RISCV_CORE_REG(name), \ - KVM_REG_SIZE_ULONG) - -#define RISCV_CSR_REG(name) __kvm_reg_id(KVM_REG_RISCV_CSR, \ - KVM_REG_RISCV_CSR_REG(name), \ - KVM_REG_SIZE_ULONG) - -#define RISCV_TIMER_REG(name) __kvm_reg_id(KVM_REG_RISCV_TIMER, \ - KVM_REG_RISCV_TIMER_REG(name), \ - KVM_REG_SIZE_U64) - struct kvm_cpu *kvm_cpu__arch_init(struct kvm *kvm, unsigned long cpu_id) { struct kvm_cpu *vcpu; From patchwork Tue Oct 18 14:08:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 13010608 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D4D3AC4332F for ; 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([171.76.86.161]) by smtp.gmail.com with ESMTPSA id z15-20020a17090a170f00b002009db534d1sm8119913pjd.24.2022.10.18.07.09.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Oct 2022 07:09:51 -0700 (PDT) From: Anup Patel To: Will Deacon , julien.thierry.kdev@gmail.com, maz@kernel.org Cc: Paolo Bonzini , Atish Patra , Alistair Francis , Anup Patel , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, Andrew Jones Subject: [PATCH kvmtool 5/6] riscv: Add Zicbom extension support Date: Tue, 18 Oct 2022 19:38:53 +0530 Message-Id: <20221018140854.69846-6-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221018140854.69846-1-apatel@ventanamicro.com> References: <20221018140854.69846-1-apatel@ventanamicro.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Andrew Jones When the Zicbom extension is available expose it to the guest. Also provide the guest the size of the cache block through DT. Signed-off-by: Andrew Jones --- riscv/fdt.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/riscv/fdt.c b/riscv/fdt.c index 8d6da11..30d3460 100644 --- a/riscv/fdt.c +++ b/riscv/fdt.c @@ -19,6 +19,7 @@ struct isa_ext_info isa_info_arr[] = { {"sstc", KVM_RISCV_ISA_EXT_SSTC}, {"svinval", KVM_RISCV_ISA_EXT_SVINVAL}, {"zihintpause", KVM_RISCV_ISA_EXT_ZIHINTPAUSE}, + {"zicbom", KVM_RISCV_ISA_EXT_ZICBOM}, }; static void dump_fdt(const char *dtb_file, void *fdt) @@ -44,6 +45,7 @@ static void generate_cpu_nodes(void *fdt, struct kvm *kvm) int cpu, pos, i, index, valid_isa_len; const char *valid_isa_order = "IEMAFDQCLBJTPVNSUHKORWXYZG"; int arr_sz = ARRAY_SIZE(isa_info_arr); + unsigned long cbom_blksz = 0; _FDT(fdt_begin_node(fdt, "cpus")); _FDT(fdt_property_cell(fdt, "#address-cells", 0x1)); @@ -78,6 +80,13 @@ static void generate_cpu_nodes(void *fdt, struct kvm *kvm) /* This extension is not available in hardware */ continue; + if (isa_info_arr[i].ext_id == KVM_RISCV_ISA_EXT_ZICBOM && !cbom_blksz) { + reg.id = RISCV_CONFIG_REG(zicbom_block_size); + reg.addr = (unsigned long)&cbom_blksz; + if (ioctl(vcpu->vcpu_fd, KVM_GET_ONE_REG, ®) < 0) + die("KVM_GET_ONE_REG failed (config.zicbom_block_size)"); + } + if ((strlen(isa_info_arr[i].name) + pos + 1) >= CPU_ISA_MAX_LEN) { pr_warning("Insufficient space to append ISA exension\n"); break; @@ -97,6 +106,8 @@ static void generate_cpu_nodes(void *fdt, struct kvm *kvm) _FDT(fdt_property_string(fdt, "mmu-type", "riscv,sv32")); _FDT(fdt_property_string(fdt, "riscv,isa", cpu_isa)); + if (cbom_blksz) + _FDT(fdt_property_cell(fdt, "riscv,cbom-block-size", cbom_blksz)); _FDT(fdt_property_cell(fdt, "reg", cpu)); _FDT(fdt_property_string(fdt, "status", "okay")); From patchwork Tue Oct 18 14:08:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 13010609 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 62BC2C433FE for ; Tue, 18 Oct 2022 14:10:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229794AbiJROK2 (ORCPT ); Tue, 18 Oct 2022 10:10:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50422 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230153AbiJROKL (ORCPT ); Tue, 18 Oct 2022 10:10:11 -0400 Received: from mail-pg1-x52d.google.com (mail-pg1-x52d.google.com [IPv6:2607:f8b0:4864:20::52d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CDB016BCF7 for ; Tue, 18 Oct 2022 07:09:58 -0700 (PDT) Received: by mail-pg1-x52d.google.com with SMTP id h185so13391326pgc.10 for ; Tue, 18 Oct 2022 07:09:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=bBfZW7huZRaUPHCG2pJCuC4fPZwNRaIcm45ZbImuxjw=; b=YKJlhWUIVRtbhA7RWD520FMIgOj6eHf3PqSSdsEdl5U2hpaO9vIMbakcJOMFBHkY7J 5aqwMrNugYJoxaIwILiz6Z2VyIgsZ0eo4RjS/Ki3BFuCF/qLNzWLPTxkRLwgWR45vyBk wLurMDu33hjYgfzuomHUvXqHF++BA9JbDLttpsV8u1L4pbcdY+lUFbIffkioRzImFUfG g9xhMqo4gtX2Aa1mEYGXA0n4uQ97/jhiWyrlzXFsfEzmN5vUQJVMYt3pAmfON82Rymi6 AoiF0Q4XSIHycMWEbxPZqJYYMRaPth1fsrQUeYV8eJnvD2x0fh11q1ouo0Q2kckIA/pG VwwA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=bBfZW7huZRaUPHCG2pJCuC4fPZwNRaIcm45ZbImuxjw=; b=cH6YLDnSAukl7ZNOlHaQAeqnT9ufA79GDdsaNkrN8BoaX+KfUXii9zsTPXmdFHN4gn X9jX8oWGLf8CFOZAM9T1pQdLHL0m9mKTsIizGZhzZ/+NJpd35rtBOgz95YSheVTE2Co/ 8vLCCr4+GNvayzGkwskVZ1RJHybf5PGo44yOE8DyKAr7Gsu0352zrlmZNkQP1V0W4ZCT AbOhm6wU0V2UDoWNzqUx1vopJq/2cjclvWhLFYl+OBwipbz4EfyoBsvwh/h69pIvzuhH aEk2FAEiuJ5mM2W6MODy/rUc8YjgqY8npIar10X7O5O4eRvyZ4CQTOPgMOU14GsWtpY8 qM6A== X-Gm-Message-State: ACrzQf2vErUovNiVQLzRuDgo4dlD85KIHV/VLtof+5rqK6pFhflaGQDB BGMBhIFbdxfIjvdAH91XbU7F2Q== X-Google-Smtp-Source: AMsMyM7LY+/379v3cJTxQCUTe6dS8kHloHhPV0vLXNyljnYJBlP2Q5KTETHo8oIz+7x/bMvxZnEjdQ== X-Received: by 2002:a05:6a00:1da1:b0:563:2e07:db1b with SMTP id z33-20020a056a001da100b005632e07db1bmr3391433pfw.22.1666102197120; Tue, 18 Oct 2022 07:09:57 -0700 (PDT) Received: from anup-ubuntu64-vm.. ([171.76.86.161]) by smtp.gmail.com with ESMTPSA id z15-20020a17090a170f00b002009db534d1sm8119913pjd.24.2022.10.18.07.09.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Oct 2022 07:09:56 -0700 (PDT) From: Anup Patel To: Will Deacon , julien.thierry.kdev@gmail.com, maz@kernel.org Cc: Paolo Bonzini , Atish Patra , Alistair Francis , Anup Patel , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, Anup Patel Subject: [PATCH kvmtool 6/6] riscv: Add --disable- options to allow user disable extensions Date: Tue, 18 Oct 2022 19:38:54 +0530 Message-Id: <20221018140854.69846-7-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221018140854.69846-1-apatel@ventanamicro.com> References: <20221018140854.69846-1-apatel@ventanamicro.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org By default, the KVM RISC-V keeps all extensions available to VCPU enabled and KVMTOOL does not disable any extension. We add --disable- command-line options in KVMTOOL RISC-V to allow users explicitly disable certain extension if they don't desire it. Signed-off-by: Anup Patel --- riscv/fdt.c | 8 ++++++++ riscv/include/kvm/kvm-config-arch.h | 18 +++++++++++++++++- 2 files changed, 25 insertions(+), 1 deletion(-) diff --git a/riscv/fdt.c b/riscv/fdt.c index 30d3460..3cdb95c 100644 --- a/riscv/fdt.c +++ b/riscv/fdt.c @@ -80,6 +80,14 @@ static void generate_cpu_nodes(void *fdt, struct kvm *kvm) /* This extension is not available in hardware */ continue; + if (kvm->cfg.arch.ext_disabled[isa_info_arr[i].ext_id]) { + isa_ext_out = 0; + if (ioctl(vcpu->vcpu_fd, KVM_SET_ONE_REG, ®) < 0) + pr_warning("Failed to disable %s ISA exension\n", + isa_info_arr[i].name); + continue; + } + if (isa_info_arr[i].ext_id == KVM_RISCV_ISA_EXT_ZICBOM && !cbom_blksz) { reg.id = RISCV_CONFIG_REG(zicbom_block_size); reg.addr = (unsigned long)&cbom_blksz; diff --git a/riscv/include/kvm/kvm-config-arch.h b/riscv/include/kvm/kvm-config-arch.h index 526fca2..188125c 100644 --- a/riscv/include/kvm/kvm-config-arch.h +++ b/riscv/include/kvm/kvm-config-arch.h @@ -5,11 +5,27 @@ struct kvm_config_arch { const char *dump_dtb_filename; + bool ext_disabled[KVM_RISCV_ISA_EXT_MAX]; }; #define OPT_ARCH_RUN(pfx, cfg) \ pfx, \ OPT_STRING('\0', "dump-dtb", &(cfg)->dump_dtb_filename, \ - ".dtb file", "Dump generated .dtb to specified file"), + ".dtb file", "Dump generated .dtb to specified file"),\ + OPT_BOOLEAN('\0', "disable-sstc", \ + &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_SSTC], \ + "Disable Sstc Extension"), \ + OPT_BOOLEAN('\0', "disable-svinval", \ + &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_SVINVAL], \ + "Disable Svinval Extension"), \ + OPT_BOOLEAN('\0', "disable-svpbmt", \ + &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_SVPBMT], \ + "Disable Svpbmt Extension"), \ + OPT_BOOLEAN('\0', "disable-zicbom", \ + &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZICBOM], \ + "Disable Zicbom Extension"), \ + OPT_BOOLEAN('\0', "disable-zihintpause", \ + &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZIHINTPAUSE],\ + "Disable Zihintpause Extension"), #endif /* KVM__KVM_CONFIG_ARCH_H */