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Reviewed-by: Rob Herring Signed-off-by: Liu Ying --- v7->v13: * No change. v6->v7: * Add Rob's R-b tag back. v5->v6: * Use graph schema. So, drop Rob's R-b tag as review is needed. v4->v5: * No change. v3->v4: * Improve compatible property by using enum instead of oneOf+const. (Rob) * Add Rob's R-b tag. v2->v3: * No change. v1->v2: * Fix yamllint warnings. * Require bypass0 and bypass1 clocks for both i.MX8qxp and i.MX8qm, as the display controller subsystem spec does say that they exist. * Use new dt binding way to add clocks in the example. * Trivial tweaks for the example. .../bindings/display/imx/fsl,imx8qxp-dpu.yaml | 387 ++++++++++++++++++ 1 file changed, 387 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dpu.yaml diff --git a/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dpu.yaml b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dpu.yaml new file mode 100644 index 000000000000..6b05c586cd9d --- /dev/null +++ b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dpu.yaml @@ -0,0 +1,387 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dpu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX8qm/qxp Display Processing Unit + +maintainers: + - Liu Ying + +description: | + The Freescale i.MX8qm/qxp Display Processing Unit(DPU) is comprised of two + main components that include a blit engine for 2D graphics accelerations + and a display controller for display output processing, as well as a command + sequencer. + +properties: + compatible: + enum: + - fsl,imx8qxp-dpu + - fsl,imx8qm-dpu + + reg: + maxItems: 1 + + interrupts: + items: + - description: | + store9 shadow load interrupt(blit engine) + - description: | + store9 frame complete interrupt(blit engine) + - description: | + store9 sequence complete interrupt(blit engine) + - description: | + extdst0 shadow load interrupt + (display controller, content stream 0) + - description: | + extdst0 frame complete interrupt + (display controller, content stream 0) + - description: | + extdst0 sequence complete interrupt + (display controller, content stream 0) + - description: | + extdst4 shadow load interrupt + (display controller, safety stream 0) + - description: | + extdst4 frame complete interrupt + (display controller, safety stream 0) + - description: | + extdst4 sequence complete interrupt + (display controller, safety stream 0) + - description: | + extdst1 shadow load interrupt + (display controller, content stream 1) + - description: | + extdst1 frame complete interrupt + (display controller, content stream 1) + - description: | + extdst1 sequence complete interrupt + (display controller, content stream 1) + - description: | + extdst5 shadow load interrupt + (display controller, safety stream 1) + - description: | + extdst5 frame complete interrupt + (display controller, safety stream 1) + - description: | + extdst5 sequence complete interrupt + (display controller, safety stream 1) + - description: | + disengcfg0 shadow load interrupt + (display controller, display stream 0) + - description: | + disengcfg0 frame complete interrupt + (display controller, display stream 0) + - description: | + disengcfg0 sequence complete interrupt + (display controller, display stream 0) + - description: | + framegen0 programmable interrupt0 + (display controller, display stream 0) + - description: | + framegen0 programmable interrupt1 + (display controller, display stream 0) + - description: | + framegen0 programmable interrupt2 + (display controller, display stream 0) + - description: | + framegen0 programmable interrupt3 + (display controller, display stream 0) + - description: | + signature0 shadow load interrupt + (display controller, display stream 0) + - description: | + signature0 measurement valid interrupt + (display controller, display stream 0) + - description: | + signature0 error condition interrupt + (display controller, display stream 0) + - description: | + disengcfg1 shadow load interrupt + (display controller, display stream 1) + - description: | + disengcfg1 frame complete interrupt + (display controller, display stream 1) + - description: | + disengcfg1 sequence complete interrupt + (display controller, display stream 1) + - description: | + framegen1 programmable interrupt0 + (display controller, display stream 1) + - description: | + framegen1 programmable interrupt1 + (display controller, display stream 1) + - description: | + framegen1 programmable interrupt2 + (display controller, display stream 1) + - description: | + framegen1 programmable interrupt3 + (display controller, display stream 1) + - description: | + signature1 shadow load interrupt + (display controller, display stream 1) + - description: | + signature1 measurement valid interrupt + (display controller, display stream 1) + - description: | + signature1 error condition interrupt + (display controller, display stream 1) + - description: | + command sequencer error condition interrupt(command sequencer) + - description: | + common control software interrupt0(common control) + - description: | + common control software interrupt1(common control) + - description: | + common control software interrupt2(common control) + - description: | + common control software interrupt3(common control) + - description: | + framegen0 synchronization status activated interrupt + (display controller, safety stream 0) + - description: | + framegen0 synchronization status deactivated interrupt + (display controller, safety stream 0) + - description: | + framegen0 synchronization status activated interrupt + (display controller, content stream 0) + - description: | + framegen0 synchronization status deactivated interrupt + (display controller, content stream 0) + - description: | + framegen1 synchronization status activated interrupt + (display controller, safety stream 1) + - description: | + framegen1 synchronization status deactivated interrupt + (display controller, safety stream 1) + - description: | + framegen1 synchronization status activated interrupt + (display controller, content stream 1) + - description: | + framegen1 synchronization status deactivated interrupt + (display controller, content stream 1) + + interrupt-names: + items: + - const: store9_shdload + - const: store9_framecomplete + - const: store9_seqcomplete + - const: extdst0_shdload + - const: extdst0_framecomplete + - const: extdst0_seqcomplete + - const: extdst4_shdload + - const: extdst4_framecomplete + - const: extdst4_seqcomplete + - const: extdst1_shdload + - const: extdst1_framecomplete + - const: extdst1_seqcomplete + - const: extdst5_shdload + - const: extdst5_framecomplete + - const: extdst5_seqcomplete + - const: disengcfg_shdload0 + - const: disengcfg_framecomplete0 + - const: disengcfg_seqcomplete0 + - const: framegen0_int0 + - const: framegen0_int1 + - const: framegen0_int2 + - const: framegen0_int3 + - const: sig0_shdload + - const: sig0_valid + - const: sig0_error + - const: disengcfg_shdload1 + - const: disengcfg_framecomplete1 + - const: disengcfg_seqcomplete1 + - const: framegen1_int0 + - const: framegen1_int1 + - const: framegen1_int2 + - const: framegen1_int3 + - const: sig1_shdload + - const: sig1_valid + - const: sig1_error + - const: cmdseq_error + - const: comctrl_sw0 + - const: comctrl_sw1 + - const: comctrl_sw2 + - const: comctrl_sw3 + - const: framegen0_primsync_on + - const: framegen0_primsync_off + - const: framegen0_secsync_on + - const: framegen0_secsync_off + - const: framegen1_primsync_on + - const: framegen1_primsync_off + - const: framegen1_secsync_on + - const: framegen1_secsync_off + + clocks: + maxItems: 8 + + clock-names: + items: + - const: axi + - const: cfg + - const: pll0 + - const: pll1 + - const: bypass0 + - const: bypass1 + - const: disp0 + - const: disp1 + + power-domains: + items: + - description: DC power-domain + - description: PLL0 power-domain + - description: PLL1 power-domain + + power-domain-names: + items: + - const: dc + - const: pll0 + - const: pll1 + + fsl,dpr-channels: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: | + List of phandle which points to DPR channels associated with + this DPU instance. + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: The DPU output port node from display stream0. + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: The DPU output port node from display stream1. + + required: + - port@0 + - port@1 + +required: + - compatible + - reg + - interrupts + - interrupt-names + - clocks + - clock-names + - power-domains + - power-domain-names + - fsl,dpr-channels + - ports + +additionalProperties: false + +examples: + - | + #include + #include + dpu@56180000 { + compatible = "fsl,imx8qxp-dpu"; + reg = <0x56180000 0x40000>; + interrupt-parent = <&dc0_irqsteer>; + interrupts = <448>, <449>, <450>, <64>, + <65>, <66>, <67>, <68>, + <69>, <70>, <193>, <194>, + <195>, <196>, <197>, <72>, + <73>, <74>, <75>, <76>, + <77>, <78>, <79>, <80>, + <81>, <199>, <200>, <201>, + <202>, <203>, <204>, <205>, + <206>, <207>, <208>, <0>, + <1>, <2>, <3>, <4>, + <82>, <83>, <84>, <85>, + <209>, <210>, <211>, <212>; + interrupt-names = "store9_shdload", + "store9_framecomplete", + "store9_seqcomplete", + "extdst0_shdload", + "extdst0_framecomplete", + "extdst0_seqcomplete", + "extdst4_shdload", + "extdst4_framecomplete", + "extdst4_seqcomplete", + "extdst1_shdload", + "extdst1_framecomplete", + "extdst1_seqcomplete", + "extdst5_shdload", + "extdst5_framecomplete", + "extdst5_seqcomplete", + "disengcfg_shdload0", + "disengcfg_framecomplete0", + "disengcfg_seqcomplete0", + "framegen0_int0", + "framegen0_int1", + "framegen0_int2", + "framegen0_int3", + "sig0_shdload", + "sig0_valid", + "sig0_error", + "disengcfg_shdload1", + "disengcfg_framecomplete1", + "disengcfg_seqcomplete1", + "framegen1_int0", + "framegen1_int1", + "framegen1_int2", + "framegen1_int3", + "sig1_shdload", + "sig1_valid", + "sig1_error", + "cmdseq_error", + "comctrl_sw0", + "comctrl_sw1", + "comctrl_sw2", + "comctrl_sw3", + "framegen0_primsync_on", + "framegen0_primsync_off", + "framegen0_secsync_on", + "framegen0_secsync_off", + "framegen1_primsync_on", + "framegen1_primsync_off", + "framegen1_secsync_on", + "framegen1_secsync_off"; + clocks = <&dc0_dpu_lpcg IMX_LPCG_CLK_5>, + <&dc0_dpu_lpcg IMX_LPCG_CLK_4>, + <&clk IMX_SC_R_DC_0_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_DC_0_PLL_1 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_DC_0_VIDEO0 IMX_SC_PM_CLK_BYPASS>, + <&clk IMX_SC_R_DC_0_VIDEO1 IMX_SC_PM_CLK_BYPASS>, + <&dc0_disp_lpcg IMX_LPCG_CLK_0>, + <&dc0_disp_lpcg IMX_LPCG_CLK_1>; + clock-names = "axi", "cfg", + "pll0", "pll1", "bypass0", "bypass1", + "disp0", "disp1"; + power-domains = <&pd IMX_SC_R_DC_0>, + <&pd IMX_SC_R_DC_0_PLL_0>, + <&pd IMX_SC_R_DC_0_PLL_1>; + power-domain-names = "dc", "pll0", "pll1"; + fsl,dpr-channels = <&dc0_dpr1_channel1>, + <&dc0_dpr1_channel2>, + <&dc0_dpr1_channel3>, + <&dc0_dpr2_channel1>, + <&dc0_dpr2_channel2>, + <&dc0_dpr2_channel3>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu0_disp0_pixel_combiner0_ch0: endpoint { + remote-endpoint = <&pixel_combiner0_ch0_dpu0_disp0>; + }; + }; + + port@1 { + reg = <1>; + dpu0_disp1_pixel_combiner0_ch1: endpoint { + remote-endpoint = <&pixel_combiner0_ch1_dpu0_disp1>; + }; + }; + }; + }; From patchwork Wed Oct 19 02:02:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Liu Ying X-Patchwork-Id: 13011266 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 63181C433FE for ; Wed, 19 Oct 2022 02:03:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; 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tzimmermann@suse.de, guido.gunther@puri.sm, marcel.ziswiler@toradex.com, laurentiu.palcu@oss.nxp.com, robh@kernel.org Subject: [PATCH v13 2/6] dt-bindings: display: imx: Add i.MX8qxp/qm PRG binding Date: Wed, 19 Oct 2022 10:02:22 +0800 Message-Id: <20221019020226.2340782-3-victor.liu@nxp.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20221019020226.2340782-1-victor.liu@nxp.com> References: <20221019020226.2340782-1-victor.liu@nxp.com> X-ClientProxiedBy: SG3P274CA0011.SGPP274.PROD.OUTLOOK.COM (2603:1096:4:be::23) To AM7PR04MB7046.eurprd04.prod.outlook.com (2603:10a6:20b:113::22) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM7PR04MB7046:EE_|VE1PR04MB7246:EE_ X-MS-Office365-Filtering-Correlation-Id: c65faeee-8e57-4e32-2b86-08dab175d276 X-LD-Processed: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 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List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This patch adds bindings for i.MX8qxp/qm Display Prefetch Resolve Gasket. Reviewed-by: Rob Herring Signed-off-by: Liu Ying --- v4->v13: * No change. v3->v4: * Improve compatible property by using enum instead of oneOf+const. (Rob) * Add Rob's R-b tag. v2->v3: * No change. v1->v2: * Use new dt binding way to add clocks in the example. .../bindings/display/imx/fsl,imx8qxp-prg.yaml | 60 +++++++++++++++++++ 1 file changed, 60 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-prg.yaml diff --git a/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-prg.yaml b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-prg.yaml new file mode 100644 index 000000000000..3ff46e0d4e73 --- /dev/null +++ b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-prg.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-prg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX8qm/qxp Display Prefetch Resolve Gasket + +maintainers: + - Liu Ying + +description: | + The i.MX8qm/qxp Prefetch Resolve Gasket (PRG) is a gasket interface between + RTRAM controller and Display Controller. The main function is to convert + the AXI interface to the RTRAM interface, which includes re-mapping the + ARADDR to a RTRAM address. + +properties: + compatible: + enum: + - fsl,imx8qxp-prg + - fsl,imx8qm-prg + + reg: + maxItems: 1 + + clocks: + items: + - description: rtram clock + - description: apb clock + + clock-names: + items: + - const: rtram + - const: apb + + power-domains: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - power-domains + +additionalProperties: false + +examples: + - | + #include + #include + prg@56040000 { + compatible = "fsl,imx8qxp-prg"; + reg = <0x56040000 0x10000>; + clocks = <&dc0_prg0_lpcg IMX_LPCG_CLK_0>, + <&dc0_prg0_lpcg IMX_LPCG_CLK_4>; + clock-names = "rtram", "apb"; + power-domains = <&pd IMX_SC_R_DC_0>; + }; From patchwork Wed Oct 19 02:02:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Liu Ying X-Patchwork-Id: 13011267 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C7E6EC4332F for ; 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Reviewed-by: Rob Herring Signed-off-by: Liu Ying --- v10->v13: * No change. v9->v10: * Add Rob's R-b tag. v8->v9: * Reference 'interrupts-extended' schema instead of 'interrupts' to require an additional interrupt(r_rtram_stall) because the reference manual does mention it, though the driver doesn't get/use it for now. Reference 'interrupt-names' schema to define the two interrupt names - 'dpr_wrap' and 'r_rtram_stall'. * Drop Rob's R-b tag, as review is needed. v4->v8: * No change. v3->v4: * Improve compatible property by using enum instead of oneOf+const. (Rob) * Add Rob's R-b tag. v2->v3: * No change. v1->v2: * Use new dt binding way to add clocks in the example. .../display/imx/fsl,imx8qxp-dprc.yaml | 100 ++++++++++++++++++ 1 file changed, 100 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dprc.yaml diff --git a/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dprc.yaml b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dprc.yaml new file mode 100644 index 000000000000..bd94254c1288 --- /dev/null +++ b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dprc.yaml @@ -0,0 +1,100 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dprc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX8qm/qxp Display Prefetch Resolve Channel + +maintainers: + - Liu Ying + +description: | + The i.MX8qm/qxp Display Prefetch Resolve Channel(DPRC) is an engine which + fetches display data before the display pipeline needs the data to drive + pixels in the active display region. This data is transformed, or resolved, + from a variety of tiled buffer formats into linear format, if needed. + The DPR works with a double bank memory structure. This memory structure is + implemented in the Resolve Tile Memory(RTRAM) and the banks are referred to + as A and B. Each bank is either 4 or 8 lines high depending on the source + frame buffer format. + +properties: + compatible: + enum: + - fsl,imx8qxp-dpr-channel + - fsl,imx8qm-dpr-channel + + reg: + maxItems: 1 + + interrupts-extended: + items: + - description: DPR wrap interrupt + - description: | + 'r_rtram_stall' interrupt which indicates relevant i.MX8qm/qxp + Prefetch Resolve Gasket(PRG) or PRGs are forcing an underflow + condition in the RTRAM. + + interrupt-names: + items: + - const: dpr_wrap + - const: r_rtram_stall + + clocks: + items: + - description: apb clock + - description: b clock + - description: rtram clock + + clock-names: + items: + - const: apb + - const: b + - const: rtram + + fsl,sc-resource: + $ref: /schemas/types.yaml#/definitions/uint32 + description: The SCU resource ID associated with this DPRC instance. + + fsl,prgs: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: | + List of phandle which points to PRG or PRGs associated with + this DPRC instance. + + power-domains: + maxItems: 1 + +required: + - compatible + - reg + - interrupts-extended + - interrupt-names + - clocks + - clock-names + - fsl,sc-resource + - fsl,prgs + - power-domains + +additionalProperties: false + +examples: + - | + #include + #include + #include + dpr-channel@56100000 { + compatible = "fsl,imx8qxp-dpr-channel"; + reg = <0x56100000 0x10000>; + interrupts-extended = <&gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, + <&dc0_irqsteer 324>; + interrupt-names = "dpr_wrap", "r_rtram_stall"; + clocks = <&dc0_dpr1_lpcg IMX_LPCG_CLK_4>, + <&dc0_dpr1_lpcg IMX_LPCG_CLK_5>, + <&dc0_rtram1_lpcg IMX_LPCG_CLK_0>; + clock-names = "apb", "b", "rtram"; + fsl,sc-resource = ; + fsl,prgs = <&dc0_prg4>, <&dc0_prg5>; + power-domains = <&pd IMX_SC_R_DC_0>; + }; From patchwork Wed Oct 19 02:02:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Liu Ying X-Patchwork-Id: 13011268 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6F971C433FE for ; Wed, 19 Oct 2022 02:04:11 +0000 (UTC) DKIM-Signature: v=1; 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Wed, 19 Oct 2022 02:01:47 +0000 From: Liu Ying To: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: p.zabel@pengutronix.de, airlied@gmail.com, daniel@ffwll.ch, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, guido.gunther@puri.sm, marcel.ziswiler@toradex.com, laurentiu.palcu@oss.nxp.com, robh@kernel.org, Daniel Vetter Subject: [PATCH v13 4/6] drm/atomic: Avoid unused-but-set-variable warning on for_each_old_plane_in_state Date: Wed, 19 Oct 2022 10:02:24 +0800 Message-Id: <20221019020226.2340782-5-victor.liu@nxp.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20221019020226.2340782-1-victor.liu@nxp.com> References: <20221019020226.2340782-1-victor.liu@nxp.com> X-ClientProxiedBy: SG3P274CA0011.SGPP274.PROD.OUTLOOK.COM (2603:1096:4:be::23) To AM7PR04MB7046.eurprd04.prod.outlook.com (2603:10a6:20b:113::22) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM7PR04MB7046:EE_|VE1PR04MB7246:EE_ X-MS-Office365-Filtering-Correlation-Id: 55d66238-c97d-441e-86cd-08dab175de5a X-LD-Processed: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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The precedent has already been set by other macros in the same file. Acked-by: Daniel Vetter Signed-off-by: Liu Ying --- v6->v13: * No change. v5->v6: * Fix commit message typo - s/Artifically/Artificially/ v4->v5: * No change. v3->v4: * Add Daniel's A-b tag. v2->v3: * Add a missing blank line. v1->v2: * No change. include/drm/drm_atomic.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/include/drm/drm_atomic.h b/include/drm/drm_atomic.h index 10b1990bc1f6..bcd6ff9d18e1 100644 --- a/include/drm/drm_atomic.h +++ b/include/drm/drm_atomic.h @@ -947,7 +947,10 @@ void drm_state_dump(struct drm_device *dev, struct drm_printer *p); (__i)++) \ for_each_if ((__state)->planes[__i].ptr && \ ((plane) = (__state)->planes[__i].ptr, \ - (old_plane_state) = (__state)->planes[__i].old_state, 1)) + (void)(plane) /* Only to avoid unused-but-set-variable warning */, \ + (old_plane_state) = (__state)->planes[__i].old_state, \ + (void)(old_plane_state) /* Only to avoid unused-but-set-variable warning */, 1)) + /** * for_each_new_plane_in_state - iterate over all planes in an atomic update * @__state: &struct drm_atomic_state pointer From patchwork Wed Oct 19 02:02:26 2022 Content-Type: text/plain; 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b=ch+hHujYIu6DO112oMiiihOX7pf7c/j44Qg9YZVtm6fhqFCAVLtSuhN7sv5BgaaKri5ixsk27E0Th5bIoPUhSHCE0JJ0fQeuXhx2+cs9P+2i1VZvCHlWvKqLG+hBGF+vYvy4ov56dB7erXn2RLd+tV8kXxPz/NKHOaA0nE2P8NE= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nxp.com; Received: from AM7PR04MB7046.eurprd04.prod.outlook.com (2603:10a6:20b:113::22) by VE1PR04MB7246.eurprd04.prod.outlook.com (2603:10a6:800:1ae::24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5723.26; Wed, 19 Oct 2022 02:02:11 +0000 Received: from AM7PR04MB7046.eurprd04.prod.outlook.com ([fe80::181b:75f7:dbc8:b4bc]) by AM7PR04MB7046.eurprd04.prod.outlook.com ([fe80::181b:75f7:dbc8:b4bc%6]) with mapi id 15.20.5723.033; Wed, 19 Oct 2022 02:02:11 +0000 From: Liu Ying To: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: p.zabel@pengutronix.de, airlied@gmail.com, daniel@ffwll.ch, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, guido.gunther@puri.sm, marcel.ziswiler@toradex.com, laurentiu.palcu@oss.nxp.com, robh@kernel.org Subject: [PATCH v13 6/6] MAINTAINERS: add maintainer for i.MX8qxp DPU DRM driver Date: Wed, 19 Oct 2022 10:02:26 +0800 Message-Id: <20221019020226.2340782-7-victor.liu@nxp.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20221019020226.2340782-1-victor.liu@nxp.com> References: <20221019020226.2340782-1-victor.liu@nxp.com> X-ClientProxiedBy: SG3P274CA0011.SGPP274.PROD.OUTLOOK.COM (2603:1096:4:be::23) To AM7PR04MB7046.eurprd04.prod.outlook.com (2603:10a6:20b:113::22) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM7PR04MB7046:EE_|VE1PR04MB7246:EE_ X-MS-Office365-Filtering-Correlation-Id: b815faae-5d8b-4c9c-49de-08dab175ef1b X-LD-Processed: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add myself as the maintainer of the i.MX8qxp DPU DRM driver. Acked-by: Laurentiu Palcu Signed-off-by: Liu Ying --- v11->v13: * No change. v10->v11: * Rebase upon v6.0-rc1. v9->v10: * Add Laurentiu's A-b tag. v1->v9: * No change. MAINTAINERS | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index cf0f18502372..a882de9ed4cb 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -6902,6 +6902,15 @@ F: Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-link.yaml F: Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pxl2dpi.yaml F: drivers/gpu/drm/bridge/imx/ +DRM DRIVERS FOR FREESCALE i.MX8QXP +M: Liu Ying +L: dri-devel@lists.freedesktop.org +S: Maintained +F: Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dprc.yaml +F: Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dpu.yaml +F: Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-prg.yaml +F: drivers/gpu/drm/imx/dpu/ + DRM DRIVERS FOR GMA500 (Poulsbo, Moorestown and derivative chipsets) M: Patrik Jakobsson L: dri-devel@lists.freedesktop.org