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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id o12-20020a170902d4cc00b0016d9d6d05f7sm12425675plg.273.2022.10.20.02.41.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Oct 2022 02:41:15 -0700 (PDT) From: Andy Chiu To: davem@davemloft.net, kuba@kernel.org, michal.simek@xilinx.com, radhey.shyam.pandey@xilinx.com Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, krzysztof.kozlowski+dt@linaro.org, robh+dt@kernel.org, pabeni@redhat.com, edumazet@google.com, andy.chiu@sifive.com, greentime.hu@sifive.com Subject: [PATCH net-next 1/2] net:xilinx_axi: set mdio frequency according to DT Date: Thu, 20 Oct 2022 17:41:05 +0800 Message-Id: <20221020094106.559266-2-andy.chiu@sifive.com> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20221020094106.559266-1-andy.chiu@sifive.com> References: <20221020094106.559266-1-andy.chiu@sifive.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org Some FPGA platforms has 80KHz MDIO bus frequency constraint when conecting Ethernet to its on-board external Marvell PHY. Thus, we may have to set MDIO clock according to the DT. Otherwise, use the default 2.5 MHz, as specified by 802.3, if the entry is not present. Signed-off-by: Andy Chiu Reviewed-by: Greentime Hu --- .../net/ethernet/xilinx/xilinx_axienet_mdio.c | 25 ++++++++++++++++--- 1 file changed, 21 insertions(+), 4 deletions(-) diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet_mdio.c b/drivers/net/ethernet/xilinx/xilinx_axienet_mdio.c index 0b3b6935c558..d07c39d3bcf0 100644 --- a/drivers/net/ethernet/xilinx/xilinx_axienet_mdio.c +++ b/drivers/net/ethernet/xilinx/xilinx_axienet_mdio.c @@ -18,6 +18,7 @@ #include "xilinx_axienet.h" #define MAX_MDIO_FREQ 2500000 /* 2.5 MHz */ +#define MDIO_CLK_DIV_MASK 0x3f /* bits[5:0] */ #define DEFAULT_HOST_CLOCK 150000000 /* 150 MHz */ /* Wait till MDIO interface is ready to accept a new transaction.*/ @@ -155,7 +156,9 @@ static int axienet_mdio_write(struct mii_bus *bus, int phy_id, int reg, **/ int axienet_mdio_enable(struct axienet_local *lp) { + u32 clk_div; u32 host_clock; + u32 mdio_freq; lp->mii_clk_div = 0; @@ -184,6 +187,13 @@ int axienet_mdio_enable(struct axienet_local *lp) host_clock); } + if (of_property_read_u32(lp->dev->of_node, "xlnx,mdio-freq", + &mdio_freq)) { + mdio_freq = MAX_MDIO_FREQ; + netdev_info(lp->ndev, "Setting default mdio clock to %u\n", + mdio_freq); + } + /* clk_div can be calculated by deriving it from the equation: * fMDIO = fHOST / ((1 + clk_div) * 2) * @@ -209,13 +219,20 @@ int axienet_mdio_enable(struct axienet_local *lp) * "clock-frequency" from the CPU */ - lp->mii_clk_div = (host_clock / (MAX_MDIO_FREQ * 2)) - 1; + clk_div = (host_clock / (mdio_freq * 2)) - 1; /* If there is any remainder from the division of - * fHOST / (MAX_MDIO_FREQ * 2), then we need to add + * fHOST / (mdio_freq * 2), then we need to add * 1 to the clock divisor or we will surely be above 2.5 MHz */ - if (host_clock % (MAX_MDIO_FREQ * 2)) - lp->mii_clk_div++; + if (host_clock % (mdio_freq * 2)) + clk_div++; + + /* Check for overflow of mii_clk_div */ + if (clk_div & ~MDIO_CLK_DIV_MASK) { + netdev_dbg(lp->ndev, "MDIO clock divisor overflow, setting to maximum value\n"); + clk_div = MDIO_CLK_DIV_MASK; + } + lp->mii_clk_div = (u8)clk_div; netdev_dbg(lp->ndev, "Setting MDIO clock divisor to %u/%u Hz host clock.\n", From patchwork Thu Oct 20 09:41:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Chiu X-Patchwork-Id: 13012914 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6FAE1C4332F for ; Thu, 20 Oct 2022 09:41:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229841AbiJTJl3 (ORCPT ); Thu, 20 Oct 2022 05:41:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58090 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229897AbiJTJl0 (ORCPT ); Thu, 20 Oct 2022 05:41:26 -0400 Received: from mail-pl1-x631.google.com (mail-pl1-x631.google.com [IPv6:2607:f8b0:4864:20::631]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 390F7191D76 for ; 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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id o12-20020a170902d4cc00b0016d9d6d05f7sm12425675plg.273.2022.10.20.02.41.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Oct 2022 02:41:18 -0700 (PDT) From: Andy Chiu To: davem@davemloft.net, kuba@kernel.org, michal.simek@xilinx.com, radhey.shyam.pandey@xilinx.com Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, krzysztof.kozlowski+dt@linaro.org, robh+dt@kernel.org, pabeni@redhat.com, edumazet@google.com, andy.chiu@sifive.com, greentime.hu@sifive.com Subject: [PATCH net-next 2/2] dt-bindings: add mdio frequency description Date: Thu, 20 Oct 2022 17:41:06 +0800 Message-Id: <20221020094106.559266-3-andy.chiu@sifive.com> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20221020094106.559266-1-andy.chiu@sifive.com> References: <20221020094106.559266-1-andy.chiu@sifive.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org Add a property to set mdio bus frequency at runtime by DT. Signed-off-by: Andy Chiu Reviewed-by: Greentime Hu --- Documentation/devicetree/bindings/net/xilinx_axienet.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/net/xilinx_axienet.txt b/Documentation/devicetree/bindings/net/xilinx_axienet.txt index 1aa4c6006cd0..d78cf402aa2a 100644 --- a/Documentation/devicetree/bindings/net/xilinx_axienet.txt +++ b/Documentation/devicetree/bindings/net/xilinx_axienet.txt @@ -43,6 +43,9 @@ Optional properties: support both 1000BaseX and SGMII modes. If set, the phy-mode should be set to match the mode selected on core reset (i.e. by the basex_or_sgmii core input line). +- xlnx,mdio-freq: Define the clock frequency of the MDIO bus. If the property + does not pressent on the DT, then the mdio driver would use + the default 2.5 MHz clock, as mentioned on 802.3 spc. - clock-names: Tuple listing input clock names. Possible clocks: s_axi_lite_clk: Clock for AXI register slave interface axis_clk: AXI4-Stream clock for TXD RXD TXC and RXS interfaces