From patchwork Thu Oct 20 20:02:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 13013989 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CA69CC433FE for ; Thu, 20 Oct 2022 20:03:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=mAUH+6/MiYF3HYjG8Mk8n9MTPcoF8BJmuM8XJ4oMPAY=; b=NvV5Mbq5tjITtI IUsIu7kIJ9vcerg9wo6GCN/rpuqwccZZDjVY/Oa1HTDUnUMsGAVWXATfcU3OrgcrjBrkHmwE/uR04 TjBd118Xtgbz6VFf335sP1X0UF84O2TTkPMK2gVM8wrLjMtETiYBaRZvVVn7a8eLpzYCsQYN5Tt+J tHq4xxj18EsR4dN7XgkJ6Mq6t+yKlDdD9iADL9rGcdnnvRuHGyl2JKl3xCJOniVtaKhHLnXmzpN1/ 3xtwZNXUf0VS3oi+SgOphUCFL54MjLM5uwMILhi3iPjcgYaGRta73UuKwr7pS06g8IElXEyPaAlsz RM/5PIh1jYhBtaAND4tw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1olbkd-001a28-VY; Thu, 20 Oct 2022 20:02:48 +0000 Received: from phobos.denx.de ([2a01:238:438b:c500:173d:9f52:ddab:ee01]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1olbkZ-001a03-Q8 for linux-arm-kernel@lists.infradead.org; Thu, 20 Oct 2022 20:02:46 +0000 Received: from tr.lan (ip-86-49-120-218.bb.vodafone.cz [86.49.120.218]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: marex@denx.de) by phobos.denx.de (Postfix) with ESMTPSA id 0889C84D6F; Thu, 20 Oct 2022 22:02:40 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1666296160; bh=R5107gnGxsSPxZdMl5GAckCeZf8gICfXf9+UzNJrsns=; h=From:To:Cc:Subject:Date:From; b=zYH4RVVwS5XfSwQsNOyAy1kj7nTl/uvHDhdKHPQWNt1LA0THyOn5WLBvlgqw9Gkzc H8U8lRzFHhWVOBvQ/gikEa/McyIJ3retZwtybYroC9pX/TMCwKOH9+F6v2o2iBV8GD YpNJyFe83EHrgQfyk3mpXDr1LdqyBVylCzc1dn/4NDuckCN/oNGbHolQ1RQcSQzMAj oXs5FEGLTzqVWw3zdOFMSNAxRDR7bKb5XwU5G3/tHugpOpMk1TwTSqeAZ1X11CZSyM X9AK0JAPAqhRPDm0hX5XM55/XD4i9wGefO85AfSdgEfj1YbfQwYRSATnzX1Joe8usL Rm5MXTfI4qWOQ== From: Marek Vasut To: linux-arm-kernel@lists.infradead.org Cc: Marek Vasut , Abhyuday Godhasara , Harsha , Michal Simek , Rajan Vaja , Ronak Jain , Tanmay Shah Subject: [PATCH v2] firmware: xilinx: Clear IOCTL_SET_SD_TAPDELAY using PM_MMIO_WRITE Date: Thu, 20 Oct 2022 22:02:23 +0200 Message-Id: <20221020200223.795142-1-marex@denx.de> X-Mailer: git-send-email 2.35.1 MIME-Version: 1.0 X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221020_130244_285209_68774312 X-CRM114-Status: GOOD ( 14.72 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org In case the tap delay required by Arasan SDHCI is set to 0, the current embeddedsw firmware unconditionally writes IOU_SLCR SD_ITAPDLY to 0x100 (SD0_ITAPDLYENA=1, SD0_ITAPDLYSEL=0). Previous behavior was to keep the IOU_SLCR SD_ITAPDLY set to 0x0. There is some sort of difference in the behavior between SD0_ITAPDLYENA=1/0 with the same SD0_ITAPDLYSEL=0, even though the behavior should be identical -- zero delay added to rxclk_in line. The former breaks HS200 training in low temperature conditions. Write IOU_SLCR SD_ITAPDLY register to 0 using PM_MMIO_WRITE which seem to allow unrestricted WRITE access (and PM_MMIO_READ which allows read access) to the entire address space. This way, it is possible to work around the defect in IOCTL_SET_SD_TAPDELAY design which does not permit clearing SDx_ITAPDLYENA bit. Note that the embeddedsw firmware does not permit clearing the SD_ITAPDLY SD0_ITAPDLYENA bit, this bit can only ever be set by the firmware and it is often impossible to update the possibly broken firmware. Signed-off-by: Marek Vasut --- Cc: Abhyuday Godhasara Cc: Harsha Cc: Michal Simek Cc: Rajan Vaja Cc: Ronak Jain Cc: Tanmay Shah To: linux-arm-kernel@lists.infradead.org --- V2: - Use PM_MMIO_WRITE to clear SD_xTAPDLYx bitfields and work around the IOCTL_SET_SD_TAPDELAY design defect. - Update commit message accordingly. --- drivers/firmware/xilinx/zynqmp.c | 29 +++++++++++++++++++++++++++-- 1 file changed, 27 insertions(+), 2 deletions(-) diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c index 6bc6b6c84241c..c0ff3efd321fc 100644 --- a/drivers/firmware/xilinx/zynqmp.c +++ b/drivers/firmware/xilinx/zynqmp.c @@ -738,8 +738,33 @@ EXPORT_SYMBOL_GPL(zynqmp_pm_get_pll_frac_data); */ int zynqmp_pm_set_sd_tapdelay(u32 node_id, u32 type, u32 value) { - return zynqmp_pm_invoke_fn(PM_IOCTL, node_id, IOCTL_SET_SD_TAPDELAY, - type, value, NULL); +#define SD_ITAPDLY 0xFF180314 +#define SD_OTAPDLYSEL 0xFF180318 + u32 reg = (type == PM_TAPDELAY_INPUT) ? SD_ITAPDLY : SD_OTAPDLYSEL; + u32 mask = (node_id == NODE_SD_0) ? GENMASK(15, 0) : GENMASK(31, 16); + + if (value) { + return zynqmp_pm_invoke_fn(PM_IOCTL, node_id, + IOCTL_SET_SD_TAPDELAY, + type, value, NULL); + } + + /* + * Work around completely misdesigned firmware API on Xilinx ZynqMP. + * The IOCTL_SET_SD_TAPDELAY firmware call allows the caller to only + * ever set IOU_SLCR SD_ITAPDLY Register SD0_ITAPDLYENA/SD1_ITAPDLYENA + * bits, but there is no matching call to clear those bits. If those + * bits are not cleared, SDMMC tuning may fail. + * + * Luckily, there are PM_MMIO_READ/PM_MMIO_WRITE calls which seem to + * allow complete unrestricted access to all address space, including + * IOU_SLCR SD_ITAPDLY Register and all the other registers, access + * to which was supposed to be protected by the current firmware API. + * + * Use PM_MMIO_READ/PM_MMIO_WRITE to re-implement the missing counter + * part of IOCTL_SET_SD_TAPDELAY which clears SDx_ITAPDLYENA bits. + */ + return zynqmp_pm_invoke_fn(PM_MMIO_WRITE, reg, mask, 0, 0, NULL); } EXPORT_SYMBOL_GPL(zynqmp_pm_set_sd_tapdelay);