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[109.15.145.210]) by smtp.googlemail.com with ESMTPSA id j8-20020a05600c1c0800b003c6b7f5567csm10325280wms.0.2022.10.21.06.31.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Oct 2022 06:31:37 -0700 (PDT) From: Amjad Ouled-Ameur Date: Fri, 21 Oct 2022 15:31:25 +0200 Subject: [PATCH v4 1/4] spi: dt-bindings: amlogic, meson-gx-spicc: Add pinctrl names for SPI signal states MIME-Version: 1.0 Message-Id: <20221004-up-aml-fix-spi-v4-1-0342d8e10c49@baylibre.com> References: <20221004-up-aml-fix-spi-v4-0-0342d8e10c49@baylibre.com> In-Reply-To: <20221004-up-aml-fix-spi-v4-0-0342d8e10c49@baylibre.com> To: Kevin Hilman , Jerome Brunet , Rob Herring , Martin Blumenstingl , Neil Armstrong , Krzysztof Kozlowski , Mark Brown Cc: linux-amlogic@lists.infradead.org, Neil Armstrong , Amjad Ouled-Ameur , Da Xue , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-Mailer: b4 0.10.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1666359095; l=2772; i=aouledameur@baylibre.com; s=20220920; h=from:subject:message-id; bh=YwA+sHh1oNU0ILalfPfygNyaqm+7p3kzynT8plbgjZM=; b=BGhgpQ4vXKhBYPR0FF4G20VfKU5D9cT5w4SDni58JwcnXH6N8b1jaWuf4JYT7enm+p4gwNRkiAwA fSJpzhrjDBdl8xybmq0EbFia14LmXlQqgMte20+x0ClV0q2aHZsR X-Developer-Key: i=aouledameur@baylibre.com; a=ed25519; pk=HgYWawSL4qLGPx+RzJ+Cuu+V8Pi/KQnDDm1wjWPMOFE= Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org SPI pins of the SPICC Controller in Meson-GX needs to be controlled by pin biais when idle. Therefore define three pinctrl names: - default: SPI pins are controlled by spi function. - idle-high: SCLK pin is pulled-up, but MOSI/MISO are still controlled by spi function. - idle-low: SCLK pin is pulled-down, but MOSI/MISO are still controlled by spi function. Reported-by: Da Xue Signed-off-by: Neil Armstrong Signed-off-by: Amjad Ouled-Ameur Reviewed-by: Krzysztof Kozlowski Reviewed-by: Martin Blumenstingl --- .../bindings/spi/amlogic,meson-gx-spicc.yaml | 75 ++++++++++++++-------- 1 file changed, 47 insertions(+), 28 deletions(-) diff --git a/Documentation/devicetree/bindings/spi/amlogic,meson-gx-spicc.yaml b/Documentation/devicetree/bindings/spi/amlogic,meson-gx-spicc.yaml index 0c10f7678178..53eb6562b979 100644 --- a/Documentation/devicetree/bindings/spi/amlogic,meson-gx-spicc.yaml +++ b/Documentation/devicetree/bindings/spi/amlogic,meson-gx-spicc.yaml @@ -10,9 +10,6 @@ title: Amlogic Meson SPI Communication Controller maintainers: - Neil Armstrong -allOf: - - $ref: "spi-controller.yaml#" - description: | The Meson SPICC is a generic SPI controller for general purpose Full-Duplex communications with dedicated 16 words RX/TX PIO FIFOs. @@ -43,31 +40,53 @@ properties: minItems: 1 maxItems: 2 -if: - properties: - compatible: - contains: - enum: - - amlogic,meson-g12a-spicc - -then: - properties: - clocks: - minItems: 2 - - clock-names: - items: - - const: core - - const: pclk - -else: - properties: - clocks: - maxItems: 1 - - clock-names: - items: - - const: core +allOf: + - $ref: "spi-controller.yaml#" + - if: + properties: + compatible: + contains: + enum: + - amlogic,meson-g12a-spicc + + then: + properties: + clocks: + minItems: 2 + + clock-names: + items: + - const: core + - const: pclk + + else: + properties: + clocks: + maxItems: 1 + + clock-names: + items: + - const: core + + - if: + properties: + compatible: + contains: + enum: + - amlogic,meson-gx-spicc + + then: + properties: + pinctrl-0: true + pinctrl-1: true + pinctrl-2: true + + pinctrl-names: + minItems: 1 + items: + - const: default + - const: idle-high + - const: idle-low required: - compatible From patchwork Fri Oct 21 13:31:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amjad Ouled-Ameur X-Patchwork-Id: 13014836 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4A1FEC352A1 for ; Fri, 21 Oct 2022 13:31:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230117AbiJUNbs (ORCPT ); Fri, 21 Oct 2022 09:31:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45034 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230498AbiJUNbn (ORCPT ); Fri, 21 Oct 2022 09:31:43 -0400 Received: from mail-wm1-x32c.google.com (mail-wm1-x32c.google.com [IPv6:2a00:1450:4864:20::32c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AF19F263D0E for ; Fri, 21 Oct 2022 06:31:39 -0700 (PDT) Received: by mail-wm1-x32c.google.com with SMTP id r8-20020a1c4408000000b003c47d5fd475so4998823wma.3 for ; Fri, 21 Oct 2022 06:31:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=dXtmdU2m8NPlsXlACt9Yoh64s/n7OnQvTgCv7hxG1ZE=; b=ebnTLIdzs1rcTFMiza2xIJxAz+pnlLeF5fNXQP6n8Lz1GDVw/qWd/L/WKBn81+0RnC FI29EzJMGqkgYAR0mudIuY0bshwjs6cwNZx+c+MxBykDx8kKHBtbUkhVs9GRlrlCXDPH KV1yeScQEe31yuOmSpaj51HPUMypvPmoaftgdCY0iM1w5JbrhXHoj4lRVclu+eBDaVAS eINikcQpj4BZbkfz5mIQ25JH5Is66WFYIjZVlZXahmXcHmXIwXOfOe4jSW9rhLc3b95f hemW6K4CuzBlmuhfE5Uk2X8CDe6bavpzRPkMSCOcQ8HnqBwnVh96fuDh1Bi0YzYTY5B5 vS5A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dXtmdU2m8NPlsXlACt9Yoh64s/n7OnQvTgCv7hxG1ZE=; b=1pRiRhZRPIkEcArgAG9ple58O7/OnRzh4MvMu20DHH6eyaJKAlASQYkRzfnfFHsjfD cFgWQmsXn1/6rhrz+rMBZ1Hy9yo+oPoh+z65t+I817S97uYuAwkNXuXKw7OLHF0qsWBX XPhliTKixQsTHYyyADNcPE9T/ABtrBHBWaqn/k18ZSauQLtcLANMIwO71FE2U9AnRGBj LW7wwDPklk2Fr+fe43LBUAyyIK9OXljCNA5FSwyk35B3/DQz57mn1TsRhfZP/AiwqIEv C+LoImAgXNr7dVZifxw918gphGEQ5ABCpfu1bSi+2txaTNdfku5DE8DjlAge++ynbwQR ArYw== X-Gm-Message-State: ACrzQf3v564he2uwNX9tQbvRSi9KqeJqagFOXQ81q613+uvHh7zB5shR jMCPwKJHywINidvvLihtrjOXaQ== X-Google-Smtp-Source: AMsMyM4y9SqyCAcklyqTWranyJ4HsqNMQgY0nqnuxSdRrjsShRsZIwxSqN1EZRJydRH0oUAVAW4qNw== X-Received: by 2002:a05:600c:4f54:b0:3c6:edec:2787 with SMTP id m20-20020a05600c4f5400b003c6edec2787mr13367112wmq.109.1666359098225; Fri, 21 Oct 2022 06:31:38 -0700 (PDT) Received: from [127.0.1.1] (210.145.15.109.rev.sfr.net. [109.15.145.210]) by smtp.googlemail.com with ESMTPSA id j8-20020a05600c1c0800b003c6b7f5567csm10325280wms.0.2022.10.21.06.31.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Oct 2022 06:31:37 -0700 (PDT) From: Amjad Ouled-Ameur Date: Fri, 21 Oct 2022 15:31:26 +0200 Subject: [PATCH v4 2/4] spi: meson-spicc: Use pinctrl to drive CLK line when idle MIME-Version: 1.0 Message-Id: <20221004-up-aml-fix-spi-v4-2-0342d8e10c49@baylibre.com> References: <20221004-up-aml-fix-spi-v4-0-0342d8e10c49@baylibre.com> In-Reply-To: <20221004-up-aml-fix-spi-v4-0-0342d8e10c49@baylibre.com> To: Kevin Hilman , Jerome Brunet , Rob Herring , Martin Blumenstingl , Neil Armstrong , Krzysztof Kozlowski , Mark Brown Cc: linux-amlogic@lists.infradead.org, Neil Armstrong , Amjad Ouled-Ameur , Da Xue , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-Mailer: b4 0.10.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1666359095; l=3653; i=aouledameur@baylibre.com; s=20220920; h=from:subject:message-id; bh=IGy2/xUGkATMfFoSdC/ARGihk37oQRhTPB+1EALz76c=; b=lVbVZDfVeI3MW+9qrIowJAsQyvBv8U545pKIoqjO0+YgyhER33t3/Zp4VbbqGrx+MhjLkqs7IHRU trZgoLn6ClcWt9mGnWI8aZXWutDyPed/A0gmPad7hkEfKs89DPgl X-Developer-Key: i=aouledameur@baylibre.com; a=ed25519; pk=HgYWawSL4qLGPx+RzJ+Cuu+V8Pi/KQnDDm1wjWPMOFE= Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Between SPI transactions, all SPI pins are in HiZ state. When using the SS signal from the SPICC controller it's not an issue because when the transaction resumes all pins come back to the right state at the same time as SS. The problem is when we use CS as a GPIO. In fact, between the GPIO CS state change and SPI pins state change from idle, you can have a missing or spurious clock transition. Set a bias on the clock depending on the clock polarity requested before CS goes active, by passing a special "idle-low" and "idle-high" pinctrl state and setting the right state at a start of a message Reported-by: Da Xue Signed-off-by: Neil Armstrong Signed-off-by: Amjad Ouled-Ameur Reviewed-by: Martin Blumenstingl --- drivers/spi/spi-meson-spicc.c | 39 ++++++++++++++++++++++++++++++++++++++- 1 file changed, 38 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-meson-spicc.c b/drivers/spi/spi-meson-spicc.c index bad201510a99..ffea38e2339c 100644 --- a/drivers/spi/spi-meson-spicc.c +++ b/drivers/spi/spi-meson-spicc.c @@ -21,6 +21,7 @@ #include #include #include +#include /* * The Meson SPICC controller could support DMA based transfers, but is not @@ -167,6 +168,9 @@ struct meson_spicc_device { unsigned long tx_remain; unsigned long rx_remain; unsigned long xfer_remain; + struct pinctrl *pinctrl; + struct pinctrl_state *pins_idle_high; + struct pinctrl_state *pins_idle_low; }; #define pow2_clk_to_spicc(_div) container_of(_div, struct meson_spicc_device, pow2_div) @@ -175,8 +179,22 @@ static void meson_spicc_oen_enable(struct meson_spicc_device *spicc) { u32 conf; - if (!spicc->data->has_oen) + if (!spicc->data->has_oen) { + /* Try to get pinctrl states for idle high/low */ + spicc->pins_idle_high = pinctrl_lookup_state(spicc->pinctrl, + "idle-high"); + if (IS_ERR(spicc->pins_idle_high)) { + dev_warn(&spicc->pdev->dev, "can't get idle-high pinctrl\n"); + spicc->pins_idle_high = NULL; + } + spicc->pins_idle_low = pinctrl_lookup_state(spicc->pinctrl, + "idle-low"); + if (IS_ERR(spicc->pins_idle_low)) { + dev_warn(&spicc->pdev->dev, "can't get idle-low pinctrl\n"); + spicc->pins_idle_low = NULL; + } return; + } conf = readl_relaxed(spicc->base + SPICC_ENH_CTL0) | SPICC_ENH_MOSI_OEN | SPICC_ENH_CLK_OEN | SPICC_ENH_CS_OEN; @@ -441,6 +459,16 @@ static int meson_spicc_prepare_message(struct spi_master *master, else conf &= ~SPICC_POL; + if (!spicc->data->has_oen) { + if (spi->mode & SPI_CPOL) { + if (spicc->pins_idle_high) + pinctrl_select_state(spicc->pinctrl, spicc->pins_idle_high); + } else { + if (spicc->pins_idle_low) + pinctrl_select_state(spicc->pinctrl, spicc->pins_idle_low); + } + } + if (spi->mode & SPI_CPHA) conf |= SPICC_PHA; else @@ -487,6 +515,9 @@ static int meson_spicc_unprepare_transfer(struct spi_master *master) /* Set default configuration, keeping datarate field */ writel_relaxed(conf, spicc->base + SPICC_CONREG); + if (!spicc->data->has_oen) + pinctrl_select_default_state(&spicc->pdev->dev); + return 0; } @@ -798,6 +829,12 @@ static int meson_spicc_probe(struct platform_device *pdev) goto out_core_clk; } + spicc->pinctrl = devm_pinctrl_get(&pdev->dev); + if (IS_ERR(spicc->pinctrl)) { + ret = PTR_ERR(spicc->pinctrl); + goto out_clk; + } + device_reset_optional(&pdev->dev); master->num_chipselect = 4; From patchwork Fri Oct 21 13:31:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amjad Ouled-Ameur X-Patchwork-Id: 13014833 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0A21EC43219 for ; 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[109.15.145.210]) by smtp.googlemail.com with ESMTPSA id j8-20020a05600c1c0800b003c6b7f5567csm10325280wms.0.2022.10.21.06.31.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Oct 2022 06:31:38 -0700 (PDT) From: Amjad Ouled-Ameur Date: Fri, 21 Oct 2022 15:31:27 +0200 Subject: [PATCH v4 3/4] arm64: dts: meson-gxl: add SPI pinctrl nodes for CLK MIME-Version: 1.0 Message-Id: <20221004-up-aml-fix-spi-v4-3-0342d8e10c49@baylibre.com> References: <20221004-up-aml-fix-spi-v4-0-0342d8e10c49@baylibre.com> In-Reply-To: <20221004-up-aml-fix-spi-v4-0-0342d8e10c49@baylibre.com> To: Kevin Hilman , Jerome Brunet , Rob Herring , Martin Blumenstingl , Neil Armstrong , Krzysztof Kozlowski , Mark Brown Cc: linux-amlogic@lists.infradead.org, Neil Armstrong , Amjad Ouled-Ameur , Da Xue , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-Mailer: b4 0.10.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1666359095; l=919; i=aouledameur@baylibre.com; s=20220920; h=from:subject:message-id; bh=1L7zyfIVhCZJcKzTBVkOA0R/6Ewhoh6l/GXCUMDjLaM=; b=Zp/yYenSqGlzVa6vYtQoBdDUo5nHcdIjN9FTC6qkrBjM8QJTMaNWtHta1JjorcWWKM9T6PQnIONB FK+jff8nD3d+Gq6IuPYIEKx63QSIxJe2nU2ZEj6BX+F4KwZCX2Ma X-Developer-Key: i=aouledameur@baylibre.com; a=ed25519; pk=HgYWawSL4qLGPx+RzJ+Cuu+V8Pi/KQnDDm1wjWPMOFE= Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Add SPICC Controller pin nodes for CLK line when idle for Amlogic GXL SoCs. Signed-off-by: Neil Armstrong Signed-off-by: Amjad Ouled-Ameur Reviewed-by: Martin Blumenstingl --- arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi index c3ac531c4f84..04e9d0f1bde0 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi @@ -429,6 +429,20 @@ mux { }; }; + spi_idle_high_pins: spi-idle-high-pins { + mux { + groups = "spi_sclk"; + bias-pull-up; + }; + }; + + spi_idle_low_pins: spi-idle-low-pins { + mux { + groups = "spi_sclk"; + bias-pull-down; + }; + }; + spi_ss0_pins: spi-ss0 { mux { groups = "spi_ss0"; From patchwork Fri Oct 21 13:31:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amjad Ouled-Ameur X-Patchwork-Id: 13014835 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1D4C8C4332F for ; Fri, 21 Oct 2022 13:31:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230505AbiJUNbr (ORCPT ); Fri, 21 Oct 2022 09:31:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45046 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229729AbiJUNbp (ORCPT ); Fri, 21 Oct 2022 09:31:45 -0400 Received: from mail-wm1-x32b.google.com (mail-wm1-x32b.google.com [IPv6:2a00:1450:4864:20::32b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A3FED26478C for ; Fri, 21 Oct 2022 06:31:41 -0700 (PDT) Received: by mail-wm1-x32b.google.com with SMTP id l32so2186369wms.2 for ; Fri, 21 Oct 2022 06:31:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=H7Qoz9jeBcfdzL9iyekJH2YPQjo48jyM8jlQ41M6YtQ=; b=J8v+969UzU9Y9w/SR7VUhM/aEcbhclODwWuAxD/2d3jJUKqh+EMU5hI0TGmOVQxIQA lYzdLAgH9Epw38urAuGMdecmgz8rRRgI6eqr3YA804isCcnKNSaTQsqntIVuaXkAZFVk 4fYlMQORa8yVEOeIfgVLEewvRKR9p4kf26uJN+hCvkmpgzxgkIHv1KQW3g60H5Vy9VAF nlgq+EpW9yRisAMhpzDniP0fSWgLqcl1k0K+J1OEHFXH01QrM9J64woxI00TTdZsX87P m7LfLYndbJiQSP0I4a+6goeJN9afeibn43oy8f45JbpTmNh7ezVzjjuoYzSLuG4cDrT+ PqTw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=H7Qoz9jeBcfdzL9iyekJH2YPQjo48jyM8jlQ41M6YtQ=; b=3yYzktrWtgJzF6WOs/zkr84kiLRjR6G60I8ZGbPd4MQsgIiLc3js4C9GHVB9Nf/+1k Wxo2a19B1w+Nr6ifV7Y+zQDA8591WQ3MmswiiOlqsKzsFHo5x6lOFPdUjs4NA3xvVHyV NmTUueZYssZiTMFYFj/J4Tz6/e8aEmhJbG3OirqL+JeT/nInyTAMgKIALx7JZMg7Ci0i W2060Nn7+qTG7cn8YDIbawS5DrhOxqv7+er44WWHP57NGurY0EYo5QvcNqf0vU3kA/In OL/HJDa14rCORKxssipbPl29aQa33wN44XxNF4TQ9HHYLbzt/7oTT3CaM+Ef9HXng26Z 36AA== X-Gm-Message-State: ACrzQf0fulniX9UnZgW9ChA7HLOLlWQDZTunS6XB+Z1SrUp/raCe4iuB hHK0XX1lB8SN7Lsqa7nYB3yNEQ== X-Google-Smtp-Source: AMsMyM7vhBSUx8oFPqKPxgekjBSxnpKkMenQ/luY5NA8wvs3PPhn5weMl3uUeZtAfwwfplq+OXGouQ== X-Received: by 2002:a05:600c:5119:b0:3c6:cae1:1512 with SMTP id o25-20020a05600c511900b003c6cae11512mr34727154wms.80.1666359100026; Fri, 21 Oct 2022 06:31:40 -0700 (PDT) Received: from [127.0.1.1] (210.145.15.109.rev.sfr.net. [109.15.145.210]) by smtp.googlemail.com with ESMTPSA id j8-20020a05600c1c0800b003c6b7f5567csm10325280wms.0.2022.10.21.06.31.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Oct 2022 06:31:39 -0700 (PDT) From: Amjad Ouled-Ameur Date: Fri, 21 Oct 2022 15:31:28 +0200 Subject: [PATCH v4 4/4] arm64: dts: meson-gxbb: add SPI pinctrl nodes for CLK MIME-Version: 1.0 Message-Id: <20221004-up-aml-fix-spi-v4-4-0342d8e10c49@baylibre.com> References: <20221004-up-aml-fix-spi-v4-0-0342d8e10c49@baylibre.com> In-Reply-To: <20221004-up-aml-fix-spi-v4-0-0342d8e10c49@baylibre.com> To: Kevin Hilman , Jerome Brunet , Rob Herring , Martin Blumenstingl , Neil Armstrong , Krzysztof Kozlowski , Mark Brown Cc: linux-amlogic@lists.infradead.org, Neil Armstrong , Amjad Ouled-Ameur , Da Xue , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-Mailer: b4 0.10.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1666359095; l=868; i=aouledameur@baylibre.com; s=20220920; h=from:subject:message-id; bh=ak0c2C3voqy+PYUNmJZvTOe1B4YCFcIjwb3vM78gKV4=; b=U08rR1DqiuMN+ZjEAxpTF5BvPqmpkiWEm+VeI5J7vmNpVuKEJ4/g+EhvlrAaKQ90o0QaPnwGQnN5 bJ4hBA7zAGFQklbeHPuuVocBB1bNTOcICPKDHttTwFahly1iqCha X-Developer-Key: i=aouledameur@baylibre.com; a=ed25519; pk=HgYWawSL4qLGPx+RzJ+Cuu+V8Pi/KQnDDm1wjWPMOFE= Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Add SPICC Controller pin nodes for CLK line when idle for Amlogic GXBB SoCs. Signed-off-by: Amjad Ouled-Ameur Reviewed-by: Neil Armstrong Reviewed-by: Martin Blumenstingl --- arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi index 7c029f552a23..923d2d8bbb9c 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi @@ -427,6 +427,20 @@ mux { }; }; + spi_idle_high_pins: spi-idle-high-pins { + mux { + groups = "spi_sclk"; + bias-pull-up; + }; + }; + + spi_idle_low_pins: spi-idle-low-pins { + mux { + groups = "spi_sclk"; + bias-pull-down; + }; + }; + spi_ss0_pins: spi-ss0 { mux { groups = "spi_ss0";