From patchwork Fri Oct 21 17:39:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Teres Alexis, Alan Previn" X-Patchwork-Id: 13015199 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B3811FA373D for ; Fri, 21 Oct 2022 17:37:51 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 718FF10E53E; Fri, 21 Oct 2022 17:37:43 +0000 (UTC) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id B593410E53E for ; Fri, 21 Oct 2022 17:37:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1666373852; x=1697909852; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=rrBy1cIC9mtNO0fAXFdljfwmTu9F3fsplIwXhxGsZGI=; b=LmP2NKPDo8SOQfcPj+QewuCyZKzO3y/jPx55zvbhW6YP2l66LnbopMXW BXlat0Jy+iCJXl1/Ah48bdmtL5yXLKeN2KrKcF6k4S6jlGLeBriKQFcs3 QznXLBf4/kF4HAIU8V42BqH1Vk73ZC9FIm1ijAY8sKqDJiRcUcgOHAF/D MVMygZLECCFVWvoyBudiIfLBgnpUfmJeDGC3IgJJMsUeAxLu0NfYv0KbZ mHziWhtgkf1KZEUlMObfmP3sjb9SNn+cM3VJVn12h6h62B/iIpIjfBE72 ZdCiIQSIuVuSQnNK48Fd6BEXd8hAMDnj3JFOsrnQANRa120u+KcRqf9mO w==; X-IronPort-AV: E=McAfee;i="6500,9779,10507"; a="286781662" X-IronPort-AV: E=Sophos;i="5.95,202,1661842800"; d="scan'208";a="286781662" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Oct 2022 10:37:32 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10507"; a="755898785" X-IronPort-AV: E=Sophos;i="5.95,202,1661842800"; d="scan'208";a="755898785" Received: from aalteres-desk.fm.intel.com ([10.80.57.53]) by orsmga004.jf.intel.com with ESMTP; 21 Oct 2022 10:37:31 -0700 From: Alan Previn To: intel-gfx@lists.freedesktop.org Date: Fri, 21 Oct 2022 10:39:41 -0700 Message-Id: <20221021173946.366210-2-alan.previn.teres.alexis@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221021173946.366210-1-alan.previn.teres.alexis@intel.com> References: <20221021173946.366210-1-alan.previn.teres.alexis@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v3 1/6] drm/i915/pxp: Make gt and pxp init/fini aware of PXP-owning-GT X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" In preparation for future MTL-PXP feature support, PXP control context should only valid on the correct gt tile. Depending on the device-info this depends on which tile owns the VEBOX and KCR. PXP is still a global feature though (despite its control-context located in the owning GT structure). Additionally, we find that the HAS_PXP macro is only used within the pxp module, That said, lets drop that HAS_PXP macro altogether and replace it with a more fitting named intel_gtpxp_is_supported and helpers so that PXP init/fini can use to verify if the referenced gt supports PXP or teelink. Add TODO for Meteorlake that will come in future series. Signed-off-by: Alan Previn --- drivers/gpu/drm/i915/i915_drv.h | 4 --- drivers/gpu/drm/i915/pxp/intel_pxp.c | 35 ++++++++++++++++---- drivers/gpu/drm/i915/pxp/intel_pxp.h | 2 ++ drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c | 2 +- 4 files changed, 32 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 7c64f8a17493..0921d1107825 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -923,10 +923,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, #define HAS_GLOBAL_MOCS_REGISTERS(dev_priv) (INTEL_INFO(dev_priv)->has_global_mocs) -#define HAS_PXP(dev_priv) ((IS_ENABLED(CONFIG_DRM_I915_PXP) && \ - INTEL_INFO(dev_priv)->has_pxp) && \ - VDBOX_MASK(to_gt(dev_priv))) - #define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch) #define HAS_GMD_ID(i915) (INTEL_INFO(i915)->has_gmd_id) diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c index 5efe61f67546..545c075bf1aa 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c @@ -44,6 +44,30 @@ struct intel_gt *pxp_to_gt(const struct intel_pxp *pxp) return container_of(pxp, struct intel_gt, pxp); } +static bool _gt_needs_teelink(struct intel_gt *gt) +{ + /* TODO: MTL won't rely on CONFIG_INTEL_MEI_PXP but on GSC engine */ + return (IS_ENABLED(CONFIG_INTEL_MEI_PXP) && intel_huc_is_loaded_by_gsc(>->uc.huc) && + intel_uc_uses_huc(>->uc)); +} + +static bool _gt_supports_pxp(struct intel_gt *gt) +{ + /* TODO: MTL won't rely on CONFIG_INTEL_MEI_PXP but on GSC engine */ + return (IS_ENABLED(CONFIG_INTEL_MEI_PXP) && IS_ENABLED(CONFIG_DRM_I915_PXP) && + INTEL_INFO((gt)->i915)->has_pxp && VDBOX_MASK(gt)); +} + +bool intel_gtpxp_is_supported(struct intel_pxp *pxp) +{ + struct intel_gt *gt = pxp_to_gt(pxp); + + if (_gt_needs_teelink(gt) || _gt_supports_pxp(gt)) + return true; + + return false; +} + bool intel_pxp_is_enabled(const struct intel_pxp *pxp) { return pxp->ce; @@ -142,22 +166,21 @@ void intel_pxp_init(struct intel_pxp *pxp) { struct intel_gt *gt = pxp_to_gt(pxp); - /* we rely on the mei PXP module */ - if (!IS_ENABLED(CONFIG_INTEL_MEI_PXP)) - return; - /* * If HuC is loaded by GSC but PXP is disabled, we can skip the init of * the full PXP session/object management and just init the tee channel. */ - if (HAS_PXP(gt->i915)) + if (_gt_supports_pxp(gt)) pxp_init_full(pxp); - else if (intel_huc_is_loaded_by_gsc(>->uc.huc) && intel_uc_uses_huc(>->uc)) + else if (_gt_needs_teelink(gt)) intel_pxp_tee_component_init(pxp); } void intel_pxp_fini(struct intel_pxp *pxp) { + if (!intel_gtpxp_is_supported(pxp)) + return; + pxp->arb_is_valid = false; intel_pxp_tee_component_fini(pxp); diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h b/drivers/gpu/drm/i915/pxp/intel_pxp.h index 2da309088c6d..c12e4d419c78 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp.h +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h @@ -13,6 +13,8 @@ struct intel_pxp; struct drm_i915_gem_object; struct intel_gt *pxp_to_gt(const struct intel_pxp *pxp); +bool intel_gtpxp_is_supported(struct intel_pxp *pxp); + bool intel_pxp_is_enabled(const struct intel_pxp *pxp); bool intel_pxp_is_active(const struct intel_pxp *pxp); diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c b/drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c index 4359e8be4101..124663cf0047 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c @@ -70,7 +70,7 @@ void intel_pxp_debugfs_register(struct intel_pxp *pxp, struct dentry *gt_root) if (!gt_root) return; - if (!HAS_PXP((pxp_to_gt(pxp)->i915))) + if (!intel_gtpxp_is_supported(pxp)) return; root = debugfs_create_dir("pxp", gt_root); From patchwork Fri Oct 21 17:39:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Teres Alexis, Alan Previn" X-Patchwork-Id: 13015198 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 20954FA373D for ; Fri, 21 Oct 2022 17:37:47 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 97DD910E5CB; Fri, 21 Oct 2022 17:37:40 +0000 (UTC) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id CFA5710E5C8 for ; Fri, 21 Oct 2022 17:37:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1666373852; x=1697909852; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=iiBJh0QUuz4bBafIYC1wrCZaRR+J2t2OJx/Iy0Ar+9A=; b=eiBzIdGSD7dPIUXuu7tpmrMCmAfod+syXVuDNTfJZx5ISP2yTwzJn2WM aDPYOguGIWFAvPx6mgAQyoe7lvt6051Z3G4P+3FG5IRZXD9hmRGmY+xzh LKPMRFjsJwyWu34hWU2RDUcDC5eMe+IsFAGuZ6hVmnsWElFNAAp5wm1Ph iJ26CoRC0glKe3HPN8NnqdkdaUvtjxcaz15WkI+HagFTRfuXjX57Z+HYV fjUWviR/3Hj2y6JNCzeEGxXib4ZIdhVkLGMQUWHKf3/v0n6DClmiGn8Rb 2nK180OJni0mfpJd8a/s133/FpqzFV7k30u5tBvHfYatXMcfa5MNHJirq w==; X-IronPort-AV: E=McAfee;i="6500,9779,10507"; a="286781664" X-IronPort-AV: E=Sophos;i="5.95,202,1661842800"; d="scan'208";a="286781664" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Oct 2022 10:37:32 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10507"; a="755898787" X-IronPort-AV: E=Sophos;i="5.95,202,1661842800"; d="scan'208";a="755898787" Received: from aalteres-desk.fm.intel.com ([10.80.57.53]) by orsmga004.jf.intel.com with ESMTP; 21 Oct 2022 10:37:31 -0700 From: Alan Previn To: intel-gfx@lists.freedesktop.org Date: Fri, 21 Oct 2022 10:39:42 -0700 Message-Id: <20221021173946.366210-3-alan.previn.teres.alexis@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221021173946.366210-1-alan.previn.teres.alexis@intel.com> References: <20221021173946.366210-1-alan.previn.teres.alexis@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v3 2/6] drm/i915/pxp: Make intel_pxp_is_enabled implicitly sort PXP-owning-GT X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Make intel_pxp_is_enabled a global check and implicitly find the PXP-owning-GT. PXP feature support is a device-config flag. In preparation for MTL PXP control-context shall reside on of the two GT's. That said, update intel_pxp_is_enabled to take in i915 as its input and internally find the right gt to check if PXP is enabled so its transparent to callers of this functions. However we also need to expose the per-gt variation of this internal pxp files to use (like what intel_pxp_enabled was prior) so also expose a new intel_gtpxp_is_enabled function for replacement. Signed-off-by: Alan Previn --- drivers/gpu/drm/i915/gem/i915_gem_context.c | 2 +- drivers/gpu/drm/i915/gem/i915_gem_create.c | 2 +- drivers/gpu/drm/i915/pxp/intel_pxp.c | 28 ++++++++++++++++++-- drivers/gpu/drm/i915/pxp/intel_pxp.h | 4 ++- drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c | 2 +- drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c | 2 +- drivers/gpu/drm/i915/pxp/intel_pxp_irq.c | 2 +- drivers/gpu/drm/i915/pxp/intel_pxp_pm.c | 8 +++--- drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 4 +-- 9 files changed, 40 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c index 1e29b1e6d186..72f47ebda75f 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c @@ -257,7 +257,7 @@ static int proto_context_set_protected(struct drm_i915_private *i915, if (!protected) { pc->uses_protected_content = false; - } else if (!intel_pxp_is_enabled(&to_gt(i915)->pxp)) { + } else if (!intel_pxp_is_enabled(i915)) { ret = -ENODEV; } else if ((pc->user_flags & BIT(UCONTEXT_RECOVERABLE)) || !(pc->user_flags & BIT(UCONTEXT_BANNABLE))) { diff --git a/drivers/gpu/drm/i915/gem/i915_gem_create.c b/drivers/gpu/drm/i915/gem/i915_gem_create.c index 33673fe7ee0a..e44803f9bec4 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_create.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_create.c @@ -384,7 +384,7 @@ static int ext_set_protected(struct i915_user_extension __user *base, void *data if (ext.flags) return -EINVAL; - if (!intel_pxp_is_enabled(&to_gt(ext_data->i915)->pxp)) + if (!intel_pxp_is_enabled(ext_data->i915)) return -ENODEV; ext_data->flags |= I915_BO_PROTECTED; diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c index 545c075bf1aa..f7c909fce97c 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c @@ -9,6 +9,7 @@ #include "intel_pxp_tee.h" #include "gem/i915_gem_context.h" #include "gt/intel_context.h" +#include "gt/intel_gt.h" #include "i915_drv.h" /** @@ -68,11 +69,34 @@ bool intel_gtpxp_is_supported(struct intel_pxp *pxp) return false; } -bool intel_pxp_is_enabled(const struct intel_pxp *pxp) +bool intel_gtpxp_is_enabled(const struct intel_pxp *pxp) { return pxp->ce; } +static struct intel_gt *_i915_to_pxp_gt(struct drm_i915_private *i915) +{ + struct intel_gt *gt = NULL; + int i = 0; + + for_each_gt(gt, i915, i) { + /* There can be only one GT that supports PXP */ + if (gt && intel_gtpxp_is_supported(>->pxp)) + return gt; + } + return NULL; +} + +bool intel_pxp_is_enabled(struct drm_i915_private *i915) +{ + struct intel_gt *gt = _i915_to_pxp_gt(i915); + + if (!gt) + return false; + + return intel_gtpxp_is_enabled(>->pxp); +} + bool intel_pxp_is_active(const struct intel_pxp *pxp) { return pxp->arb_is_valid; @@ -229,7 +253,7 @@ int intel_pxp_start(struct intel_pxp *pxp) { int ret = 0; - if (!intel_pxp_is_enabled(pxp)) + if (!intel_gtpxp_is_enabled(pxp)) return -ENODEV; if (wait_for(pxp_component_bound(pxp), 250)) diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h b/drivers/gpu/drm/i915/pxp/intel_pxp.h index c12e4d419c78..61472018bc45 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp.h +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h @@ -11,11 +11,13 @@ struct intel_pxp; struct drm_i915_gem_object; +struct drm_i915_private; struct intel_gt *pxp_to_gt(const struct intel_pxp *pxp); bool intel_gtpxp_is_supported(struct intel_pxp *pxp); +bool intel_gtpxp_is_enabled(const struct intel_pxp *pxp); -bool intel_pxp_is_enabled(const struct intel_pxp *pxp); +bool intel_pxp_is_enabled(struct drm_i915_private *i915); bool intel_pxp_is_active(const struct intel_pxp *pxp); void intel_pxp_init(struct intel_pxp *pxp); diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c index f41e45763d0d..0987bb552eaa 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c @@ -99,7 +99,7 @@ int intel_pxp_terminate_session(struct intel_pxp *pxp, u32 id) u32 *cs; int err = 0; - if (!intel_pxp_is_enabled(pxp)) + if (!intel_gtpxp_is_enabled(pxp)) return 0; rq = i915_request_create(ce); diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c b/drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c index 124663cf0047..13f517f94bae 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c @@ -18,7 +18,7 @@ static int pxp_info_show(struct seq_file *m, void *data) { struct intel_pxp *pxp = m->private; struct drm_printer p = drm_seq_file_printer(m); - bool enabled = intel_pxp_is_enabled(pxp); + bool enabled = intel_gtpxp_is_enabled(pxp); if (!enabled) { drm_printf(&p, "pxp disabled\n"); diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c b/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c index c28be430718a..8e8e5645e4fc 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c @@ -22,7 +22,7 @@ void intel_pxp_irq_handler(struct intel_pxp *pxp, u16 iir) { struct intel_gt *gt = pxp_to_gt(pxp); - if (GEM_WARN_ON(!intel_pxp_is_enabled(pxp))) + if (GEM_WARN_ON(!intel_gtpxp_is_enabled(pxp))) return; lockdep_assert_held(gt->irq_lock); diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c index 6a7d4e2ee138..c095a9e0a01f 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c @@ -11,7 +11,7 @@ void intel_pxp_suspend_prepare(struct intel_pxp *pxp) { - if (!intel_pxp_is_enabled(pxp)) + if (!intel_gtpxp_is_enabled(pxp)) return; pxp->arb_is_valid = false; @@ -23,7 +23,7 @@ void intel_pxp_suspend(struct intel_pxp *pxp) { intel_wakeref_t wakeref; - if (!intel_pxp_is_enabled(pxp)) + if (!intel_gtpxp_is_enabled(pxp)) return; with_intel_runtime_pm(&pxp_to_gt(pxp)->i915->runtime_pm, wakeref) { @@ -34,7 +34,7 @@ void intel_pxp_suspend(struct intel_pxp *pxp) void intel_pxp_resume(struct intel_pxp *pxp) { - if (!intel_pxp_is_enabled(pxp)) + if (!intel_gtpxp_is_enabled(pxp)) return; /* @@ -50,7 +50,7 @@ void intel_pxp_resume(struct intel_pxp *pxp) void intel_pxp_runtime_suspend(struct intel_pxp *pxp) { - if (!intel_pxp_is_enabled(pxp)) + if (!intel_gtpxp_is_enabled(pxp)) return; pxp->arb_is_valid = false; diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c index 052fd2f9a583..1c6bc56391b7 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c @@ -152,7 +152,7 @@ static int i915_pxp_tee_component_bind(struct device *i915_kdev, return 0; /* the component is required to fully start the PXP HW */ - if (intel_pxp_is_enabled(pxp)) + if (intel_gtpxp_is_enabled(pxp)) intel_pxp_init_hw(pxp); intel_runtime_pm_put(&i915->runtime_pm, wakeref); @@ -167,7 +167,7 @@ static void i915_pxp_tee_component_unbind(struct device *i915_kdev, struct intel_pxp *pxp = i915_dev_to_pxp(i915_kdev); intel_wakeref_t wakeref; - if (intel_pxp_is_enabled(pxp)) + if (intel_gtpxp_is_enabled(pxp)) with_intel_runtime_pm_if_in_use(&i915->runtime_pm, wakeref) intel_pxp_fini_hw(pxp); From patchwork Fri Oct 21 17:39:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Teres Alexis, Alan Previn" X-Patchwork-Id: 13015200 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 683D8C433FE for ; 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a="286781665" X-IronPort-AV: E=Sophos;i="5.95,202,1661842800"; d="scan'208";a="286781665" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Oct 2022 10:37:32 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10507"; a="755898788" X-IronPort-AV: E=Sophos;i="5.95,202,1661842800"; d="scan'208";a="755898788" Received: from aalteres-desk.fm.intel.com ([10.80.57.53]) by orsmga004.jf.intel.com with ESMTP; 21 Oct 2022 10:37:32 -0700 From: Alan Previn To: intel-gfx@lists.freedesktop.org Date: Fri, 21 Oct 2022 10:39:43 -0700 Message-Id: <20221021173946.366210-4-alan.previn.teres.alexis@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221021173946.366210-1-alan.previn.teres.alexis@intel.com> References: <20221021173946.366210-1-alan.previn.teres.alexis@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v3 3/6] drm/i915/pxp: Make intel_pxp_is_active implicitly sort PXP-owning-GT X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Make intel_pxp_is_active a global check and implicitly find the PXP-owning-GT. As per prior two patches, callers of this function shall now pass in i915 since PXP is a global GPU feature. Make intel_pxp_is_active implicitly find the right gt so it's transparent for global view callers (like display or gem-exec). However we also need to expose the per-gt variation of this for internal pxp files to use (like what intel_pxp_is_active was prior) so also expose a new intel_gtpxp_is_active function for replacement. Signed-off-by: Alan Previn --- drivers/gpu/drm/i915/gem/i915_gem_context.c | 2 +- drivers/gpu/drm/i915/pxp/intel_pxp.c | 14 ++++++++++++-- drivers/gpu/drm/i915/pxp/intel_pxp.h | 3 ++- drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c | 4 ++-- drivers/gpu/drm/i915/pxp/intel_pxp_irq.c | 2 +- 5 files changed, 18 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c index 72f47ebda75f..798e77398acc 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c @@ -271,7 +271,7 @@ static int proto_context_set_protected(struct drm_i915_private *i915, */ pc->pxp_wakeref = intel_runtime_pm_get(&i915->runtime_pm); - if (!intel_pxp_is_active(&to_gt(i915)->pxp)) + if (!intel_pxp_is_active(i915)) ret = intel_pxp_start(&to_gt(i915)->pxp); } diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c index f7c909fce97c..15f7983f6da8 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c @@ -97,11 +97,21 @@ bool intel_pxp_is_enabled(struct drm_i915_private *i915) return intel_gtpxp_is_enabled(>->pxp); } -bool intel_pxp_is_active(const struct intel_pxp *pxp) +bool intel_gtpxp_is_active(const struct intel_pxp *pxp) { return pxp->arb_is_valid; } +bool intel_pxp_is_active(struct drm_i915_private *i915) +{ + struct intel_gt *gt = _i915_to_pxp_gt(i915); + + if (!gt) + return false; + + return intel_gtpxp_is_active(>->pxp); +} + /* KCR register definitions */ #define KCR_INIT _MMIO(0x320f0) /* Setting KCR Init bit is required after system boot */ @@ -300,7 +310,7 @@ int intel_pxp_key_check(struct intel_pxp *pxp, struct drm_i915_gem_object *obj, bool assign) { - if (!intel_pxp_is_active(pxp)) + if (!intel_gtpxp_is_active(pxp)) return -ENODEV; if (!i915_gem_object_is_protected(obj)) diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h b/drivers/gpu/drm/i915/pxp/intel_pxp.h index 61472018bc45..70383394adb4 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp.h +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h @@ -16,9 +16,10 @@ struct drm_i915_private; struct intel_gt *pxp_to_gt(const struct intel_pxp *pxp); bool intel_gtpxp_is_supported(struct intel_pxp *pxp); bool intel_gtpxp_is_enabled(const struct intel_pxp *pxp); +bool intel_gtpxp_is_active(const struct intel_pxp *pxp); bool intel_pxp_is_enabled(struct drm_i915_private *i915); -bool intel_pxp_is_active(const struct intel_pxp *pxp); +bool intel_pxp_is_active(struct drm_i915_private *i915); void intel_pxp_init(struct intel_pxp *pxp); void intel_pxp_fini(struct intel_pxp *pxp); diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c b/drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c index 13f517f94bae..7f304b421633 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c @@ -25,7 +25,7 @@ static int pxp_info_show(struct seq_file *m, void *data) return 0; } - drm_printf(&p, "active: %s\n", str_yes_no(intel_pxp_is_active(pxp))); + drm_printf(&p, "active: %s\n", str_yes_no(intel_gtpxp_is_active(pxp))); drm_printf(&p, "instance counter: %u\n", pxp->key_instance); return 0; @@ -43,7 +43,7 @@ static int pxp_terminate_set(void *data, u64 val) struct intel_pxp *pxp = data; struct intel_gt *gt = pxp_to_gt(pxp); - if (!intel_pxp_is_active(pxp)) + if (!intel_gtpxp_is_active(pxp)) return -ENODEV; /* simulate a termination interrupt */ diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c b/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c index 8e8e5645e4fc..cd97f8d8cc10 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c @@ -86,7 +86,7 @@ void intel_pxp_irq_disable(struct intel_pxp *pxp) * called in a path were the driver consider the session as valid and * doesn't call a termination on restart. */ - GEM_WARN_ON(intel_pxp_is_active(pxp)); + GEM_WARN_ON(intel_gtpxp_is_active(pxp)); spin_lock_irq(gt->irq_lock); From patchwork Fri Oct 21 17:39:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Teres Alexis, Alan Previn" X-Patchwork-Id: 13015201 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CCBD3FA373D for ; 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a="286781667" X-IronPort-AV: E=Sophos;i="5.95,202,1661842800"; d="scan'208";a="286781667" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Oct 2022 10:37:32 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10507"; a="755898789" X-IronPort-AV: E=Sophos;i="5.95,202,1661842800"; d="scan'208";a="755898789" Received: from aalteres-desk.fm.intel.com ([10.80.57.53]) by orsmga004.jf.intel.com with ESMTP; 21 Oct 2022 10:37:32 -0700 From: Alan Previn To: intel-gfx@lists.freedesktop.org Date: Fri, 21 Oct 2022 10:39:44 -0700 Message-Id: <20221021173946.366210-5-alan.previn.teres.alexis@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221021173946.366210-1-alan.previn.teres.alexis@intel.com> References: <20221021173946.366210-1-alan.previn.teres.alexis@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v3 4/6] drm/i915/pxp: Make PXP tee component bind/unbind aware of PXP-owning-GT X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Ensure i915_pxp_tee_component_bind / unbind implicitly sorts out getting the correct per-GT PXP control-context from the PXP-owning-GT when establishing or ending connection. Thus, replace _i915_to_pxp_gt with intel_pxp_get_owning_gt (also takes in i915). Signed-off-by: Alan Previn Reviewed-by: Daniele Ceraolo Spurio --- drivers/gpu/drm/i915/pxp/intel_pxp.c | 6 +++--- drivers/gpu/drm/i915/pxp/intel_pxp.h | 2 ++ drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 14 ++++++++++++-- 3 files changed, 17 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c index 15f7983f6da8..2c835c38c527 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c @@ -74,7 +74,7 @@ bool intel_gtpxp_is_enabled(const struct intel_pxp *pxp) return pxp->ce; } -static struct intel_gt *_i915_to_pxp_gt(struct drm_i915_private *i915) +struct intel_gt *intel_pxp_get_owning_gt(struct drm_i915_private *i915) { struct intel_gt *gt = NULL; int i = 0; @@ -89,7 +89,7 @@ static struct intel_gt *_i915_to_pxp_gt(struct drm_i915_private *i915) bool intel_pxp_is_enabled(struct drm_i915_private *i915) { - struct intel_gt *gt = _i915_to_pxp_gt(i915); + struct intel_gt *gt = intel_pxp_get_owning_gt(i915); if (!gt) return false; @@ -104,7 +104,7 @@ bool intel_gtpxp_is_active(const struct intel_pxp *pxp) bool intel_pxp_is_active(struct drm_i915_private *i915) { - struct intel_gt *gt = _i915_to_pxp_gt(i915); + struct intel_gt *gt = intel_pxp_get_owning_gt(i915); if (!gt) return false; diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h b/drivers/gpu/drm/i915/pxp/intel_pxp.h index 70383394adb4..7d93055cdd6b 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp.h +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h @@ -13,6 +13,8 @@ struct intel_pxp; struct drm_i915_gem_object; struct drm_i915_private; +struct intel_gt *intel_pxp_get_owning_gt(struct drm_i915_private *i915); + struct intel_gt *pxp_to_gt(const struct intel_pxp *pxp); bool intel_gtpxp_is_supported(struct intel_pxp *pxp); bool intel_gtpxp_is_enabled(const struct intel_pxp *pxp); diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c index 1c6bc56391b7..eb7adb972610 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c @@ -20,8 +20,12 @@ static inline struct intel_pxp *i915_dev_to_pxp(struct device *i915_kdev) { struct drm_i915_private *i915 = kdev_to_i915(i915_kdev); + struct intel_gt *gt = intel_pxp_get_owning_gt(i915); - return &to_gt(i915)->pxp; + if (!gt) + return NULL; + + return >->pxp; } static int intel_pxp_tee_io_message(struct intel_pxp *pxp, @@ -128,10 +132,16 @@ static int i915_pxp_tee_component_bind(struct device *i915_kdev, { struct drm_i915_private *i915 = kdev_to_i915(i915_kdev); struct intel_pxp *pxp = i915_dev_to_pxp(i915_kdev); - struct intel_uc *uc = &pxp_to_gt(pxp)->uc; + struct intel_uc *uc; intel_wakeref_t wakeref; int ret = 0; + if (!pxp) { + drm_warn(&i915->drm, "tee comp binding without a PXP-owner GT\n"); + return -ENODEV; + } + uc = &pxp_to_gt(pxp)->uc; + mutex_lock(&pxp->tee_mutex); pxp->pxp_component = data; pxp->pxp_component->tee_dev = tee_kdev; From patchwork Fri Oct 21 17:39:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Teres Alexis, Alan Previn" X-Patchwork-Id: 13015203 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E26E0FA373E for ; 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a="286781668" X-IronPort-AV: E=Sophos;i="5.95,202,1661842800"; d="scan'208";a="286781668" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Oct 2022 10:37:32 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10507"; a="755898790" X-IronPort-AV: E=Sophos;i="5.95,202,1661842800"; d="scan'208";a="755898790" Received: from aalteres-desk.fm.intel.com ([10.80.57.53]) by orsmga004.jf.intel.com with ESMTP; 21 Oct 2022 10:37:32 -0700 From: Alan Previn To: intel-gfx@lists.freedesktop.org Date: Fri, 21 Oct 2022 10:39:45 -0700 Message-Id: <20221021173946.366210-6-alan.previn.teres.alexis@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221021173946.366210-1-alan.previn.teres.alexis@intel.com> References: <20221021173946.366210-1-alan.previn.teres.alexis@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v3 5/6] drm/i915/pxp: Make intel_pxp_start implicitly sort PXP-owning-GT X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Make intel_pxp_is_start implicitly find the PXP-owning-GT. Callers of this function shall now pass in i915 since PXP is a global GPU feature. Make intel_pxp_start implicitly find the right gt to start PXP arb session so it's transparent to the callers. Signed-off-by: Alan Previn Reviewed-by: Daniele Ceraolo Spurio --- drivers/gpu/drm/i915/gem/i915_gem_context.c | 2 +- drivers/gpu/drm/i915/pxp/intel_pxp.c | 9 ++++++++- drivers/gpu/drm/i915/pxp/intel_pxp.h | 2 +- 3 files changed, 10 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c index 798e77398acc..af60f6494947 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c @@ -272,7 +272,7 @@ static int proto_context_set_protected(struct drm_i915_private *i915, pc->pxp_wakeref = intel_runtime_pm_get(&i915->runtime_pm); if (!intel_pxp_is_active(i915)) - ret = intel_pxp_start(&to_gt(i915)->pxp); + ret = intel_pxp_start(i915); } return ret; diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c index 2c835c38c527..c87f812ba13a 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c @@ -259,10 +259,17 @@ static bool pxp_component_bound(struct intel_pxp *pxp) * the arb session is restarted from the irq work when we receive the * termination completion interrupt */ -int intel_pxp_start(struct intel_pxp *pxp) +int intel_pxp_start(struct drm_i915_private *i915) { + struct intel_gt *gt = intel_pxp_get_owning_gt(i915); + struct intel_pxp *pxp; int ret = 0; + if (!gt) + return -ENODEV; + + pxp = >->pxp; + if (!intel_gtpxp_is_enabled(pxp)) return -ENODEV; diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h b/drivers/gpu/drm/i915/pxp/intel_pxp.h index 7d93055cdd6b..c45949bb1f7b 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp.h +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h @@ -31,7 +31,7 @@ void intel_pxp_fini_hw(struct intel_pxp *pxp); void intel_pxp_mark_termination_in_progress(struct intel_pxp *pxp); -int intel_pxp_start(struct intel_pxp *pxp); +int intel_pxp_start(struct drm_i915_private *i915); int intel_pxp_key_check(struct intel_pxp *pxp, struct drm_i915_gem_object *obj, From patchwork Fri Oct 21 17:39:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Teres Alexis, Alan Previn" X-Patchwork-Id: 13015202 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2C030FA373D for ; Fri, 21 Oct 2022 17:38:11 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8B00910E608; Fri, 21 Oct 2022 17:38:08 +0000 (UTC) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id 49C9E10E608 for ; Fri, 21 Oct 2022 17:37:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1666373853; x=1697909853; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=rSprZE9eNs94Z3YcoX8Ho/Xh7ab7BHI2/oQC8tgG2EQ=; b=GjNexMtgTMjlV7/AjbRwM+C8JHIBg2rY/gXO892H5OXydvI2K5kvTiXa +bCMdV8TTZehnkDADL0P5kSSxFGWNBMzf0tkYHkKl4K4tWzCoyGLM35k9 fBfb9oSxdNNmf0fM/YCYpPtE7BTB5fY9E0mIqZAKqiFuPlCc90mestDds Orig/mTSiZEwrSQGdykXjyezbxuc7+sXyGpYcYg81KatVH2midaKvGS2b GnfKaHfHS6SuDNzFuySwTQQoFZFmMxH6eP8Lz8HoG+5+ZSR3QsxrXWfWY tEIEGRrqePPxX7oPXXqR/1JvjMQvUtaUba/oZhfS9gX+rYRIqaom70Izv w==; X-IronPort-AV: E=McAfee;i="6500,9779,10507"; a="286781669" X-IronPort-AV: E=Sophos;i="5.95,202,1661842800"; d="scan'208";a="286781669" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Oct 2022 10:37:32 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10507"; a="755898791" X-IronPort-AV: E=Sophos;i="5.95,202,1661842800"; d="scan'208";a="755898791" Received: from aalteres-desk.fm.intel.com ([10.80.57.53]) by orsmga004.jf.intel.com with ESMTP; 21 Oct 2022 10:37:32 -0700 From: Alan Previn To: intel-gfx@lists.freedesktop.org Date: Fri, 21 Oct 2022 10:39:46 -0700 Message-Id: <20221021173946.366210-7-alan.previn.teres.alexis@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221021173946.366210-1-alan.previn.teres.alexis@intel.com> References: <20221021173946.366210-1-alan.previn.teres.alexis@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v3 6/6] drm/i915/pxp: Make intel_pxp_key_check implicitly sort PXP-owning-GT X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Make intel_pxp_key_check implicitly find the PXP-owning-GT. Callers of this function shall now pass in i915 since PXP is a global GPU feature. Make intel_pxp_key_check implicitly find the right gt to verify pxp session key establishment count so it's transparent to the callers. Signed-off-by: Alan Previn Reviewed-by: Daniele Ceraolo Spurio --- drivers/gpu/drm/i915/display/skl_universal_plane.c | 2 +- drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 2 +- drivers/gpu/drm/i915/pxp/intel_pxp.c | 10 +++++++++- drivers/gpu/drm/i915/pxp/intel_pxp.h | 2 +- 4 files changed, 12 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c index 7cb713043408..04e78acbaf5f 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -1841,7 +1841,7 @@ static bool bo_has_valid_encryption(struct drm_i915_gem_object *obj) { struct drm_i915_private *i915 = to_i915(obj->base.dev); - return intel_pxp_key_check(&to_gt(i915)->pxp, obj, false) == 0; + return intel_pxp_key_check(i915, obj, false) == 0; } static bool pxp_is_borked(struct drm_i915_gem_object *obj) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c index 1160723c9d2d..23224977e003 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c @@ -868,7 +868,7 @@ static struct i915_vma *eb_lookup_vma(struct i915_execbuffer *eb, u32 handle) */ if (i915_gem_context_uses_protected_content(eb->gem_context) && i915_gem_object_is_protected(obj)) { - err = intel_pxp_key_check(&vm->gt->pxp, obj, true); + err = intel_pxp_key_check(vm->gt->i915, obj, true); if (err) { i915_gem_object_put(obj); return ERR_PTR(err); diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c index c87f812ba13a..5c9a4b2c9a75 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c @@ -313,10 +313,18 @@ void intel_pxp_fini_hw(struct intel_pxp *pxp) intel_pxp_irq_disable(pxp); } -int intel_pxp_key_check(struct intel_pxp *pxp, +int intel_pxp_key_check(struct drm_i915_private *i915, struct drm_i915_gem_object *obj, bool assign) { + struct intel_gt *gt = intel_pxp_get_owning_gt(i915); + struct intel_pxp *pxp; + + if (!gt) + return -ENODEV; + + pxp = >->pxp; + if (!intel_gtpxp_is_active(pxp)) return -ENODEV; diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h b/drivers/gpu/drm/i915/pxp/intel_pxp.h index c45949bb1f7b..85c5499daba5 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp.h +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h @@ -33,7 +33,7 @@ void intel_pxp_mark_termination_in_progress(struct intel_pxp *pxp); int intel_pxp_start(struct drm_i915_private *i915); -int intel_pxp_key_check(struct intel_pxp *pxp, +int intel_pxp_key_check(struct drm_i915_private *i915, struct drm_i915_gem_object *obj, bool assign);