From patchwork Sun Oct 23 14:56:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 13016297 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EE3BAECAAA1 for ; Sun, 23 Oct 2022 14:57:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230273AbiJWO5G (ORCPT ); Sun, 23 Oct 2022 10:57:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35648 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230251AbiJWO5G (ORCPT ); Sun, 23 Oct 2022 10:57:06 -0400 Received: from mail-wr1-x433.google.com (mail-wr1-x433.google.com [IPv6:2a00:1450:4864:20::433]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 348185C9C4; Sun, 23 Oct 2022 07:57:05 -0700 (PDT) Received: by mail-wr1-x433.google.com with SMTP id k8so3200143wrh.1; Sun, 23 Oct 2022 07:57:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=kj/OpguZjPKDUwIYpyWbwh1pY+n7iF9L6lxKcI6mhC0=; b=Q1Pvk3yc4qV0TxhrAP7miQlUWAmmJr6qwWmuFLZZsjy0F7nXkhy53QgtCdBeLcHZ5L IEkWt2Yhr3oQxdmcMJkMFOBkWP3j/A466/R6bLH/YmCiTY9pQc/2DTRigUbBNJ2tmIjv 3f/GwtSmf11x2SRBMTZtr+cXGOXzT4UvylbPPnvuKViBwJWuj3+XK8YmYPXBE2jJxTyn NxQBCoa6UerAiwd6mzLC2SPABFmXiovSHPSUwNrV8hLRfxb2vUszm10qI8lriTFNZJKe Wuv4qdi0oz0xNg4tfjX23VHmqEvtFvQ2b2Uk1ACJAhrnxs+trPH6JV0O8cacBXi8YPdD MhDA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kj/OpguZjPKDUwIYpyWbwh1pY+n7iF9L6lxKcI6mhC0=; b=MhgLf82HpqTewAH+IxSnKa2h57UWIoKn1iXC+nr2OPlOab0f8Zb1UYgsQqgUyGFmkQ moRDdLqzrmN6QKu2Dkyt4s2BknruLw+4oyWPKQqr/E9kXSaseYJ928n0tjZlLAQpCNam KjzRhDVG2EAgDNyB390SK0h2IVO8g4owLBa0cEcT6jbne7aIwHM4PS1sK8xF5nm/Cr6G IHva7btG5Aa0ntMeti42M3JuJiMwcgp36WirS18J41ydzFldxTQWwpB5WXz7ULjJKBQ5 hvs2NldyHePgf84I2LPzw1K1iYEhIAbQB4LsRLT89DE82H1hG56aIfxhaYz5TKFopfi3 tDVw== X-Gm-Message-State: ACrzQf0rgrBac8UykYrgQDzgF450YL9LEV8M2hsQbXs+P1v8k3rtJbIk clRIRPfN0ECQ1SgDBcP4N+s= X-Google-Smtp-Source: AMsMyM5ETqp1Bj57TU+4kYjUpQ3ScJ33WvuY7orTycMG9obvu4YGnUHkIJuyoi4RJwOUdCKeCFfOcw== X-Received: by 2002:adf:fb84:0:b0:21a:10f2:1661 with SMTP id a4-20020adffb84000000b0021a10f21661mr18224004wrr.2.1666537023782; Sun, 23 Oct 2022 07:57:03 -0700 (PDT) Received: from localhost (94.197.10.75.threembb.co.uk. [94.197.10.75]) by smtp.gmail.com with ESMTPSA id bg37-20020a05600c3ca500b003c706e177c1sm1758817wmb.14.2022.10.23.07.57.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Oct 2022 07:57:03 -0700 (PDT) From: Aidan MacDonald To: paul@crapouillou.net, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: zhouyu@wanyeetech.com, linux-mips@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 1/5] clk: ingenic: Make PLL clock "od" field optional Date: Sun, 23 Oct 2022 15:56:49 +0100 Message-Id: <20221023145653.177234-2-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20221023145653.177234-1-aidanmacdonald.0x0@gmail.com> References: <20221023145653.177234-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Add support for defining PLL clocks with od_bits = 0, meaning that OD is fixed to 1 and there is no OD field in the register. Signed-off-by: Aidan MacDonald --- drivers/clk/ingenic/cgu.c | 28 +++++++++++++++++++--------- drivers/clk/ingenic/cgu.h | 3 ++- 2 files changed, 21 insertions(+), 10 deletions(-) diff --git a/drivers/clk/ingenic/cgu.c b/drivers/clk/ingenic/cgu.c index 861c50d6cb24..7dc2e2567d53 100644 --- a/drivers/clk/ingenic/cgu.c +++ b/drivers/clk/ingenic/cgu.c @@ -96,8 +96,11 @@ ingenic_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) m += pll_info->m_offset; n = (ctl >> pll_info->n_shift) & GENMASK(pll_info->n_bits - 1, 0); n += pll_info->n_offset; - od_enc = ctl >> pll_info->od_shift; - od_enc &= GENMASK(pll_info->od_bits - 1, 0); + + if (pll_info->od_bits > 0) { + od_enc = ctl >> pll_info->od_shift; + od_enc &= GENMASK(pll_info->od_bits - 1, 0); + } if (pll_info->bypass_bit >= 0) { ctl = readl(cgu->base + pll_info->bypass_reg); @@ -108,12 +111,17 @@ ingenic_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) return parent_rate; } - for (od = 0; od < pll_info->od_max; od++) { - if (pll_info->od_encoding[od] == od_enc) - break; + if (pll_info->od_bits > 0) { + for (od = 0; od < pll_info->od_max; od++) { + if (pll_info->od_encoding[od] == od_enc) + break; + } + BUG_ON(od == pll_info->od_max); + od++; + } else { + /* OD is fixed to 1 if no OD field is present. */ + od = 1; } - BUG_ON(od == pll_info->od_max); - od++; return div_u64((u64)parent_rate * m * pll_info->rate_multiplier, n * od); @@ -215,8 +223,10 @@ ingenic_pll_set_rate(struct clk_hw *hw, unsigned long req_rate, ctl &= ~(GENMASK(pll_info->n_bits - 1, 0) << pll_info->n_shift); ctl |= (n - pll_info->n_offset) << pll_info->n_shift; - ctl &= ~(GENMASK(pll_info->od_bits - 1, 0) << pll_info->od_shift); - ctl |= pll_info->od_encoding[od - 1] << pll_info->od_shift; + if (pll_info->od_bits > 0) { + ctl &= ~(GENMASK(pll_info->od_bits - 1, 0) << pll_info->od_shift); + ctl |= pll_info->od_encoding[od - 1] << pll_info->od_shift; + } writel(ctl, cgu->base + pll_info->reg); diff --git a/drivers/clk/ingenic/cgu.h b/drivers/clk/ingenic/cgu.h index 147b7df0d657..567142b584bb 100644 --- a/drivers/clk/ingenic/cgu.h +++ b/drivers/clk/ingenic/cgu.h @@ -33,7 +33,8 @@ * @od_shift: the number of bits to shift the post-VCO divider value by (ie. * the index of the lowest bit of the post-VCO divider value in * the PLL's control register) - * @od_bits: the size of the post-VCO divider field in bits + * @od_bits: the size of the post-VCO divider field in bits, or 0 if no + * OD field exists (then the OD is fixed to 1) * @od_max: the maximum post-VCO divider value * @od_encoding: a pointer to an array mapping post-VCO divider values to * their encoded values in the PLL control register, or -1 for From patchwork Sun Oct 23 14:56:50 2022 Content-Type: text/plain; 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[94.197.10.75]) by smtp.gmail.com with ESMTPSA id b13-20020a5d4d8d000000b0023660f6cecfsm3747605wru.80.2022.10.23.07.57.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Oct 2022 07:57:04 -0700 (PDT) From: Aidan MacDonald To: paul@crapouillou.net, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: zhouyu@wanyeetech.com, linux-mips@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 2/5] clk: ingenic: Make PLL clock enable_bit and stable_bit optional Date: Sun, 23 Oct 2022 15:56:50 +0100 Message-Id: <20221023145653.177234-3-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20221023145653.177234-1-aidanmacdonald.0x0@gmail.com> References: <20221023145653.177234-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org When the enable bit is undefined, the clock is assumed to be always on and enable/disable is a no-op. When the stable bit is undefined, the PLL stable check is a no-op. Signed-off-by: Aidan MacDonald --- drivers/clk/ingenic/cgu.c | 14 +++++++++++++- drivers/clk/ingenic/cgu.h | 10 ++++++---- 2 files changed, 19 insertions(+), 5 deletions(-) diff --git a/drivers/clk/ingenic/cgu.c b/drivers/clk/ingenic/cgu.c index 7dc2e2567d53..bbb55e8d8b55 100644 --- a/drivers/clk/ingenic/cgu.c +++ b/drivers/clk/ingenic/cgu.c @@ -190,6 +190,9 @@ static inline int ingenic_pll_check_stable(struct ingenic_cgu *cgu, { u32 ctl; + if (pll_info->stable_bit < 0) + return 0; + return readl_poll_timeout(cgu->base + pll_info->reg, ctl, ctl & BIT(pll_info->stable_bit), 0, 100 * USEC_PER_MSEC); @@ -231,7 +234,7 @@ ingenic_pll_set_rate(struct clk_hw *hw, unsigned long req_rate, writel(ctl, cgu->base + pll_info->reg); /* If the PLL is enabled, verify that it's stable */ - if (ctl & BIT(pll_info->enable_bit)) + if (pll_info->enable_bit >= 0 && (ctl & BIT(pll_info->enable_bit))) ret = ingenic_pll_check_stable(cgu, pll_info); spin_unlock_irqrestore(&cgu->lock, flags); @@ -249,6 +252,9 @@ static int ingenic_pll_enable(struct clk_hw *hw) int ret; u32 ctl; + if (pll_info->enable_bit < 0) + return 0; + spin_lock_irqsave(&cgu->lock, flags); if (pll_info->bypass_bit >= 0) { ctl = readl(cgu->base + pll_info->bypass_reg); @@ -279,6 +285,9 @@ static void ingenic_pll_disable(struct clk_hw *hw) unsigned long flags; u32 ctl; + if (pll_info->enable_bit < 0) + return; + spin_lock_irqsave(&cgu->lock, flags); ctl = readl(cgu->base + pll_info->reg); @@ -296,6 +305,9 @@ static int ingenic_pll_is_enabled(struct clk_hw *hw) const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll; u32 ctl; + if (pll_info->enable_bit < 0) + return true; + ctl = readl(cgu->base + pll_info->reg); return !!(ctl & BIT(pll_info->enable_bit)); diff --git a/drivers/clk/ingenic/cgu.h b/drivers/clk/ingenic/cgu.h index 567142b584bb..a5e44ca7f969 100644 --- a/drivers/clk/ingenic/cgu.h +++ b/drivers/clk/ingenic/cgu.h @@ -42,8 +42,10 @@ * @bypass_reg: the offset of the bypass control register within the CGU * @bypass_bit: the index of the bypass bit in the PLL control register, or * -1 if there is no bypass bit - * @enable_bit: the index of the enable bit in the PLL control register - * @stable_bit: the index of the stable bit in the PLL control register + * @enable_bit: the index of the enable bit in the PLL control register, or + * -1 if there is no enable bit (ie, the PLL is always on) + * @stable_bit: the index of the stable bit in the PLL control register, or + * -1 if there is no stable bit */ struct ingenic_cgu_pll_info { unsigned reg; @@ -54,8 +56,8 @@ struct ingenic_cgu_pll_info { u8 od_shift, od_bits, od_max; unsigned bypass_reg; s8 bypass_bit; - u8 enable_bit; - u8 stable_bit; + s8 enable_bit; + s8 stable_bit; void (*calc_m_n_od)(const struct ingenic_cgu_pll_info *pll_info, unsigned long rate, unsigned long parent_rate, unsigned int *m, unsigned int *n, unsigned int *od); From patchwork Sun Oct 23 14:56:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 13016298 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 12F2AFA3742 for ; Sun, 23 Oct 2022 14:57:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230305AbiJWO5K (ORCPT ); Sun, 23 Oct 2022 10:57:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35666 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229515AbiJWO5J (ORCPT ); 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[94.197.10.75]) by smtp.gmail.com with ESMTPSA id r6-20020a5d52c6000000b00228dbf15072sm23603166wrv.62.2022.10.23.07.57.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Oct 2022 07:57:05 -0700 (PDT) From: Aidan MacDonald To: paul@crapouillou.net, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: zhouyu@wanyeetech.com, linux-mips@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 3/5] clk: ingenic: Add .set_rate_hook() for PLL clocks Date: Sun, 23 Oct 2022 15:56:51 +0100 Message-Id: <20221023145653.177234-4-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20221023145653.177234-1-aidanmacdonald.0x0@gmail.com> References: <20221023145653.177234-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org The set rate hook is called immediately after updating the clock register but before the spinlock is released. This allows another register to be updated alongside the main one, which is needed to handle the I2S divider on some SoCs. Signed-off-by: Aidan MacDonald --- drivers/clk/ingenic/cgu.c | 3 +++ drivers/clk/ingenic/cgu.h | 4 ++++ 2 files changed, 7 insertions(+) diff --git a/drivers/clk/ingenic/cgu.c b/drivers/clk/ingenic/cgu.c index bbb55e8d8b55..574d5fe10fdf 100644 --- a/drivers/clk/ingenic/cgu.c +++ b/drivers/clk/ingenic/cgu.c @@ -233,6 +233,9 @@ ingenic_pll_set_rate(struct clk_hw *hw, unsigned long req_rate, writel(ctl, cgu->base + pll_info->reg); + if (pll_info->set_rate_hook) + pll_info->set_rate_hook(pll_info, rate, parent_rate); + /* If the PLL is enabled, verify that it's stable */ if (pll_info->enable_bit >= 0 && (ctl & BIT(pll_info->enable_bit))) ret = ingenic_pll_check_stable(cgu, pll_info); diff --git a/drivers/clk/ingenic/cgu.h b/drivers/clk/ingenic/cgu.h index a5e44ca7f969..99da9bd86e63 100644 --- a/drivers/clk/ingenic/cgu.h +++ b/drivers/clk/ingenic/cgu.h @@ -46,6 +46,8 @@ * -1 if there is no enable bit (ie, the PLL is always on) * @stable_bit: the index of the stable bit in the PLL control register, or * -1 if there is no stable bit + * @set_rate_hook: hook called immediately after updating the CGU register, + * before releasing the spinlock */ struct ingenic_cgu_pll_info { unsigned reg; @@ -61,6 +63,8 @@ struct ingenic_cgu_pll_info { void (*calc_m_n_od)(const struct ingenic_cgu_pll_info *pll_info, unsigned long rate, unsigned long parent_rate, unsigned int *m, unsigned int *n, unsigned int *od); + void (*set_rate_hook)(const struct ingenic_cgu_pll_info *pll_info, + unsigned long rate, unsigned long parent_rate); }; /** From patchwork Sun Oct 23 14:56:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 13016300 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C8DFBFA373E for ; Sun, 23 Oct 2022 14:57:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230341AbiJWO5N (ORCPT ); Sun, 23 Oct 2022 10:57:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35676 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230320AbiJWO5K (ORCPT ); Sun, 23 Oct 2022 10:57:10 -0400 Received: from mail-wm1-x331.google.com (mail-wm1-x331.google.com [IPv6:2a00:1450:4864:20::331]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AD52A5C9D1; Sun, 23 Oct 2022 07:57:08 -0700 (PDT) Received: by mail-wm1-x331.google.com with SMTP id v11so5122096wmd.1; Sun, 23 Oct 2022 07:57:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ZNepXipGDeJQVdil2MM/OA4hZBASj3NiREHHvlf/RXY=; b=N5ocY8LPkrECmPbCUP5uVZnlbVjTNrJiVbq1owEIcKUOPsEgV7i/vjpUkPwiMMu1kW 5hSIikD1VO15M08WNrdtB9Ox98Y2PqOMsWeseV+HKgWVTv6U88wKfG537lKiJ3c/ptcZ Z9h8t2BDNEsruHh0hS1hgDARxbW8xuXpuZcWQsYYBrT1QR0E2uAtgM/7FiJudOGjlOxQ IX1WXxIA0oSdnDMCd26HLPFv2R1tDvWmatQ6chYyC6F18bMCzIHD/RUBuAfJAdceGtaf XDEiUs328+77QwjifszCig6RA8Sbk/n3NpjwN0LYUzUU4fWwUVdOSjv+G13PPHM9fqdQ TD0Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ZNepXipGDeJQVdil2MM/OA4hZBASj3NiREHHvlf/RXY=; b=bKEbQ1NM+nR0QzUmC+Vqzl0gmIZ1jgFzLkVUW5uG+9RoHNhM9az1atX3+vmEMztNrp DDQyDwDVcm4cb7gN96z2eKBkDCxNqlbzTf+Al6F/QWK8DV+NXoOrjP8znIooFQqtzJY5 CZ7I5/OFhgcX5ArGb7Ut2rWc+/Omik2Q7EpICn5tiQNzYolUL6Nl2Bgif0EXoHJLnisk 64RVMsBIR+LftVmLMnQ6Xb+0VvJ81ZlDqXTwOimsEYN4IRlZ5D5qnBTqn67tWsfa7pYx bHTYAsnGYQbUbEaYDoPfNLf6BBV8MaMgeTqdjLJax5T6KmpaExuQ7q2/J/qf3ECqqRF6 QkvA== X-Gm-Message-State: ACrzQf0lZ7Lcjw52oHnzTuPY8MDVQkCv7grXebh6GvuH7IZip4EDiGtD J63/BP0H7Vi4Ign9UqnZ32E= X-Google-Smtp-Source: AMsMyM6wytrKNgTyh7Lmv+UbUvZzrlOg+CLkYo1mM4UpmbcWQzOXUPWTAB5Kg/wtt2cWDBfVo/u/PQ== X-Received: by 2002:a1c:f008:0:b0:3b4:fd2e:3ede with SMTP id a8-20020a1cf008000000b003b4fd2e3edemr40780835wmb.133.1666537027289; Sun, 23 Oct 2022 07:57:07 -0700 (PDT) Received: from localhost (94.197.10.75.threembb.co.uk. [94.197.10.75]) by smtp.gmail.com with ESMTPSA id j8-20020adfd208000000b00235da296623sm9139763wrh.31.2022.10.23.07.57.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Oct 2022 07:57:06 -0700 (PDT) From: Aidan MacDonald To: paul@crapouillou.net, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: zhouyu@wanyeetech.com, linux-mips@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 4/5] dt-bindings: ingenic,x1000-cgu: Add audio clocks Date: Sun, 23 Oct 2022 15:56:52 +0100 Message-Id: <20221023145653.177234-5-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20221023145653.177234-1-aidanmacdonald.0x0@gmail.com> References: <20221023145653.177234-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Add bindings for audio-related clocks on the Ingenic X1000 SoC. Signed-off-by: Aidan MacDonald Acked-by: Krzysztof Kozlowski --- include/dt-bindings/clock/ingenic,x1000-cgu.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/dt-bindings/clock/ingenic,x1000-cgu.h b/include/dt-bindings/clock/ingenic,x1000-cgu.h index f187e0719fd3..78daf44b3514 100644 --- a/include/dt-bindings/clock/ingenic,x1000-cgu.h +++ b/include/dt-bindings/clock/ingenic,x1000-cgu.h @@ -50,5 +50,9 @@ #define X1000_CLK_PDMA 35 #define X1000_CLK_EXCLK_DIV512 36 #define X1000_CLK_RTC 37 +#define X1000_CLK_AIC 38 +#define X1000_CLK_I2SPLLMUX 39 +#define X1000_CLK_I2SPLL 40 +#define X1000_CLK_I2S 41 #endif /* __DT_BINDINGS_CLOCK_X1000_CGU_H__ */ From patchwork Sun Oct 23 14:56:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 13016302 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C2B5FECAAA1 for ; Sun, 23 Oct 2022 14:57:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230365AbiJWO5Q (ORCPT ); Sun, 23 Oct 2022 10:57:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35706 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229649AbiJWO5M (ORCPT ); Sun, 23 Oct 2022 10:57:12 -0400 Received: from mail-wm1-x32d.google.com (mail-wm1-x32d.google.com [IPv6:2a00:1450:4864:20::32d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E44B35C97B; Sun, 23 Oct 2022 07:57:09 -0700 (PDT) Received: by mail-wm1-x32d.google.com with SMTP id az22-20020a05600c601600b003c6b72797fdso5039358wmb.5; Sun, 23 Oct 2022 07:57:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=rFj+0g9zC945JfgR9vxO7Ms2xSVk7a3nRyoILt5SjhM=; b=HjAWWLBr2kEf7p1VaqiGbzqwOt0zJ6cdDBbwqgi7VVAnNs2J4k0wf7oVKh6hAFAGRP e0KQh+W/DzAfb4/8yyM3CEPegwqICG2RfnumnGcvadIWjucdvNBmEUOFKz/1qHXyuz6n siYeaEx0ijMQDm/XfFdQ9+6zj9jU7hq4g45OrgvY7iTVKznU+mesB1MKw7QwLxVza21C XG1zzw5H34g643YpeeIM/Lg12lGsS30Hyu6DmJ+aTZUUPdy3HMZqyNIVdn+G/HBUnMfW aLkPitcfjsbHboG5wQVHVnIiZ+s3rrliVKV6E2au2RA7RWOAyP2ypUICizEtHVWp3Pg+ 1WNw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rFj+0g9zC945JfgR9vxO7Ms2xSVk7a3nRyoILt5SjhM=; b=ocGHGmekFKUX2IKcKmuwCDrckEBMYaflPdbRQUfSO29ODwotmfX7K17M0MhfhqxYV3 TTvMpa3OUWNoaq9Ck/QuKJW5aRFI35IbcvKvTQWMuu9euajeqKopgFP2MbzJw/HAkh7z kPUpT0onV2cAHA2SRe+FPCakslb9lEWLiOzrpGgEUyppb/krNmTzMOkrvHWXL8nelQKQ 8E3MRgqsVddBLdV7b9ChTjsv/YCwHHCdQxG7KM0wL98mkfUvYtIcBJbFS62l0Z9Fv09Y CDPtaHzDb8q3vJtD5Azlz7V4NHZ3G+IF/ThRjtoWGi8Sqs/Jrl4y7qs6K2OIyVjIaEv5 lS6Q== X-Gm-Message-State: ACrzQf0zHLk6z+nR8p/6lcXUdHdXtVHstbNSWyzJg0ADWtgVDG3bp0XG WSNo6srU130ehvuqSsBsQMg= X-Google-Smtp-Source: AMsMyM6K+feSGR7UlA9AzzeCWHxBkSa7NMQLfVqzBsHLhj/RVhDQit81k3PILc6V2Yy+7qDYAXfDvg== X-Received: by 2002:a05:600c:1e89:b0:3c7:1e:acc2 with SMTP id be9-20020a05600c1e8900b003c7001eacc2mr18476310wmb.44.1666537028420; Sun, 23 Oct 2022 07:57:08 -0700 (PDT) Received: from localhost (94.197.10.75.threembb.co.uk. [94.197.10.75]) by smtp.gmail.com with ESMTPSA id hg16-20020a05600c539000b003c6b70a4d69sm8345331wmb.42.2022.10.23.07.57.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Oct 2022 07:57:08 -0700 (PDT) From: Aidan MacDonald To: paul@crapouillou.net, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: zhouyu@wanyeetech.com, linux-mips@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 5/5] clk: ingenic: Add X1000 audio clocks Date: Sun, 23 Oct 2022 15:56:53 +0100 Message-Id: <20221023145653.177234-6-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20221023145653.177234-1-aidanmacdonald.0x0@gmail.com> References: <20221023145653.177234-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org The X1000's CGU supplies the I2S system clock to the AIC module and ultimately the audio codec, represented by the "i2s" clock. It is a simple mux which can either pass through EXCLK or a PLL multiplied by a fractional divider (the "i2s_pll" clock). The AIC contains a separate 1/N divider controlled by the I2S driver, which generates the bit clock from the system clock. The frame clock is always fixed to 1/64th of the bit clock. Signed-off-by: Aidan MacDonald --- drivers/clk/ingenic/x1000-cgu.c | 69 +++++++++++++++++++++++++++++++++ 1 file changed, 69 insertions(+) diff --git a/drivers/clk/ingenic/x1000-cgu.c b/drivers/clk/ingenic/x1000-cgu.c index b2ce3fb83f54..341276e5e1ef 100644 --- a/drivers/clk/ingenic/x1000-cgu.c +++ b/drivers/clk/ingenic/x1000-cgu.c @@ -8,6 +8,7 @@ #include #include #include +#include #include @@ -168,6 +169,37 @@ static const struct clk_ops x1000_otg_phy_ops = { .is_enabled = x1000_usb_phy_is_enabled, }; +static void +x1000_i2spll_calc_m_n_od(const struct ingenic_cgu_pll_info *pll_info, + unsigned long rate, unsigned long parent_rate, + unsigned int *pm, unsigned int *pn, unsigned int *pod) +{ + const unsigned long m_max = GENMASK(pll_info->m_bits - 1, 0); + const unsigned long n_max = GENMASK(pll_info->n_bits - 1, 0); + unsigned long m, n; + + rational_best_approximation(rate, parent_rate, m_max, n_max, &m, &n); + + /* n should not be less than 2*m */ + if (n < 2 * m) + n = 2 * m; + + *pm = m; + *pn = n; + *pod = 1; +} + +static void +x1000_i2spll_set_rate_hook(const struct ingenic_cgu_pll_info *pll_info, + unsigned long rate, unsigned long parent_rate) +{ + /* + * For some reason, the I2S divider doesn't work properly after + * updating I2SCDR unless I2SCDR1 is read & written back. + */ + writel(readl(cgu->base + CGU_REG_I2SCDR1), cgu->base + CGU_REG_I2SCDR1); +} + static const s8 pll_od_encoding[8] = { 0x0, 0x1, -1, 0x2, -1, -1, -1, 0x3, }; @@ -319,6 +351,37 @@ static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = { .gate = { CGU_REG_CLKGR, 25 }, }, + [X1000_CLK_I2SPLLMUX] = { + "i2s_pll_mux", CGU_CLK_MUX, + .parents = { X1000_CLK_SCLKA, X1000_CLK_MPLL, -1, -1 }, + .mux = { CGU_REG_I2SCDR, 31, 1 }, + }, + + [X1000_CLK_I2SPLL] = { + "i2s_pll", CGU_CLK_PLL, + .parents = { X1000_CLK_I2SPLLMUX, -1, -1, -1 }, + .pll = { + .reg = CGU_REG_I2SCDR, + .rate_multiplier = 1, + .m_shift = 13, + .m_bits = 9, + .n_shift = 0, + .n_bits = 13, + .calc_m_n_od = x1000_i2spll_calc_m_n_od, + .set_rate_hook = x1000_i2spll_set_rate_hook, + }, + }, + + [X1000_CLK_I2S] = { + "i2s", CGU_CLK_MUX, + .parents = { X1000_CLK_EXCLK, -1, -1, X1000_CLK_I2SPLL }, + /* + * NOTE: the mux is at bit 30; bit 29 enables the M/N divider. + * Therefore, the divider is disabled when EXCLK is selected. + */ + .mux = { CGU_REG_I2SCDR, 29, 2 }, + }, + [X1000_CLK_LCD] = { "lcd", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE, .parents = { X1000_CLK_SCLKA, X1000_CLK_MPLL }, @@ -426,6 +489,12 @@ static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = { .gate = { CGU_REG_CLKGR, 9 }, }, + [X1000_CLK_AIC] = { + "aic", CGU_CLK_GATE, + .parents = { X1000_CLK_EXCLK, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR, 11 }, + }, + [X1000_CLK_UART0] = { "uart0", CGU_CLK_GATE, .parents = { X1000_CLK_EXCLK, -1, -1, -1 },