From patchwork Sat Oct 22 15:04:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 13016595 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9C46DC38A2D for ; Mon, 24 Oct 2022 04:30:01 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1omgeD-0001DB-0F for qemu-devel@archiver.kernel.org; Sun, 23 Oct 2022 15:28:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1omG4P-0006zC-Ec; Sat, 22 Oct 2022 11:05:53 -0400 Received: from mail-ed1-x533.google.com ([2a00:1450:4864:20::533]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1omG4N-00020s-NI; Sat, 22 Oct 2022 11:05:53 -0400 Received: by mail-ed1-x533.google.com with SMTP id m15so16048518edb.13; Sat, 22 Oct 2022 08:05:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=7NYjJAiwL3UkwUI5mA0F3Wlg5qiA3msCo54CbNGwBvU=; b=Y9BFyq6eC2hhZUACYAhhwfxetpXfaVv8xvz8h4fo37MaMENg2lSZgQyIJ/HO0TWWCN fT9ue+DGg8eYjazACEspN2nQsjFCpbsDJJS1QKvh4j6KowPjscBorUXEVk8Ct7D9B9Ss K4IR6pLjg70sS0L2eFXLBp8fawfENn1Dpi6/95PHg0Fb5WagUY/5moDhsmhPp8jdZFzx p5lPSqCHPr2feSxEd29xNi4/uW1lRr6n1IqD9jp+Sm2deUTW729EzOkOO6wUkDxvGCKU WmGwqVrWv8zFeHzKer/glsWxyA6z0ZcUMe0ehQkseMj6QIDa2sbO6T0vwtpYmgkY/Nyo KhEQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7NYjJAiwL3UkwUI5mA0F3Wlg5qiA3msCo54CbNGwBvU=; b=faCEjyBB8TqLr9RYy69+QPLuUJdj76SUTyq3+I5cX479a8gQo7T74ZHB5cv7C734bk 6/DevZqxY8kvVFf45Le5U/tVh7RsG5J+s9kV5qgodS2X+6xOMQp7+xeEhxjSEbwnmmBl xyUq9jxDE32ghYbM7ZcEyMcrR9MhzLXLtNsliRizqdk0rx2uMT4VB2ILAwhngdmcfkRK L2S7IkEZjzFUxZT0mOyrOYDL0YjrdY4B631voqSiABmWPoEU+XkNy68rc0d9yFGAXLGs suSzPXJVUY+A/KEkyiXxu2xw+OjdXWsjaN5glVVyW3bLga9hfZGIshkyLHj125FRqV6z ucoQ== X-Gm-Message-State: ACrzQf1eAUgNd+oUtOh5g4inzueQ3TVhfSuraMSONWPaL5f/3yWz1KOF BZBbYAOqCwgGrmGLBujo6SZ5dNQrLD1mYw== X-Google-Smtp-Source: AMsMyM4nXtChWRXkOU/AyiyUMhmhOFJaAeFiotW50Mq6NZZOv2EAUcV3ur0ZB35vrBXGojQv59hJ7Q== X-Received: by 2002:a17:907:d9e:b0:78e:2ff7:72f4 with SMTP id go30-20020a1709070d9e00b0078e2ff772f4mr19383740ejc.608.1666451148449; Sat, 22 Oct 2022 08:05:48 -0700 (PDT) Received: from localhost.localdomain (dynamic-077-191-171-138.77.191.pool.telefonica.de. [77.191.171.138]) by smtp.gmail.com with ESMTPSA id 4-20020a170906310400b00780ab5a9116sm13021558ejx.211.2022.10.22.08.05.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 22 Oct 2022 08:05:47 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Eduardo Habkost , =?utf-8?q?Herv=C3=A9_Poussineau?= , Aurelien Jarno , Igor Mammedov , Gerd Hoffmann , John Snow , Jiaxun Yang , Ani Sinha , Marcel Apfelbaum , qemu-block@nongnu.org, Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , "Michael S. Tsirkin" , Paolo Bonzini , Bernhard Beschow Subject: [PATCH v2 01/43] hw/i386/pc: Create DMA controllers in south bridges Date: Sat, 22 Oct 2022 17:04:26 +0200 Message-Id: <20221022150508.26830-2-shentey@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221022150508.26830-1-shentey@gmail.com> References: <20221022150508.26830-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::533; envelope-from=shentey@gmail.com; helo=mail-ed1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Just like in the real hardware (and in PIIX4), create the DMA controllers in the south bridges. Signed-off-by: Bernhard Beschow Reviewed-by: Philippe Mathieu-Daudé --- hw/i386/pc.c | 3 --- hw/i386/pc_piix.c | 2 ++ hw/isa/Kconfig | 2 ++ hw/isa/lpc_ich9.c | 3 +++ hw/isa/piix3.c | 9 +++++++-- 5 files changed, 14 insertions(+), 5 deletions(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 768982ae9a..b39ecd4d0c 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -47,7 +47,6 @@ #include "multiboot.h" #include "hw/rtc/mc146818rtc.h" #include "hw/intc/i8259.h" -#include "hw/dma/i8257.h" #include "hw/timer/i8254.h" #include "hw/input/i8042.h" #include "hw/irq.h" @@ -1320,8 +1319,6 @@ void pc_basic_device_init(struct PCMachineState *pcms, pcspk_init(pcms->pcspk, isa_bus, pit); } - i8257_dma_init(isa_bus, 0); - /* Super I/O */ pc_superio_init(isa_bus, create_fdctrl, pcms->i8042_enabled, pcms->vmport != ON_OFF_AUTO_ON); diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 0b1a79c0fa..7a55b9ca8e 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -26,6 +26,7 @@ #include CONFIG_DEVICES #include "qemu/units.h" +#include "hw/dma/i8257.h" #include "hw/loader.h" #include "hw/i386/x86.h" #include "hw/i386/pc.h" @@ -225,6 +226,7 @@ static void pc_init1(MachineState *machine, pci_bus = NULL; isa_bus = isa_bus_new(NULL, get_system_memory(), system_io, &error_abort); + i8257_dma_init(isa_bus, 0); pcms->hpet_enabled = false; } isa_bus_irqs(isa_bus, x86ms->gsi); diff --git a/hw/isa/Kconfig b/hw/isa/Kconfig index d42143a991..c65d2d2666 100644 --- a/hw/isa/Kconfig +++ b/hw/isa/Kconfig @@ -33,6 +33,7 @@ config PC87312 config PIIX3 bool + select I8257 select ISA_BUS config PIIX4 @@ -67,6 +68,7 @@ config LPC_ICH9 bool # For historical reasons, SuperIO devices are created in the board # for ICH9. + select I8257 select ISA_BUS select ACPI_SMBUS select ACPI_X86_ICH diff --git a/hw/isa/lpc_ich9.c b/hw/isa/lpc_ich9.c index 4553b5925b..8694e58b21 100644 --- a/hw/isa/lpc_ich9.c +++ b/hw/isa/lpc_ich9.c @@ -34,6 +34,7 @@ #include "qapi/error.h" #include "qapi/visitor.h" #include "qemu/range.h" +#include "hw/dma/i8257.h" #include "hw/isa/isa.h" #include "migration/vmstate.h" #include "hw/irq.h" @@ -722,6 +723,8 @@ static void ich9_lpc_realize(PCIDevice *d, Error **errp) qdev_init_gpio_out_named(dev, lpc->gsi, ICH9_GPIO_GSI, GSI_NUM_PINS); isa_bus_irqs(isa_bus, lpc->gsi); + + i8257_dma_init(isa_bus, 0); } static bool ich9_rst_cnt_needed(void *opaque) diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c index 48f9ab1096..44a9998752 100644 --- a/hw/isa/piix3.c +++ b/hw/isa/piix3.c @@ -25,6 +25,7 @@ #include "qemu/osdep.h" #include "qemu/range.h" #include "qapi/error.h" +#include "hw/dma/i8257.h" #include "hw/southbridge/piix.h" #include "hw/irq.h" #include "hw/isa/isa.h" @@ -295,9 +296,11 @@ static const MemoryRegionOps rcr_ops = { static void pci_piix3_realize(PCIDevice *dev, Error **errp) { PIIX3State *d = PIIX3_PCI_DEVICE(dev); + ISABus *isa_bus; - if (!isa_bus_new(DEVICE(d), get_system_memory(), - pci_address_space_io(dev), errp)) { + isa_bus = isa_bus_new(DEVICE(d), get_system_memory(), + pci_address_space_io(dev), errp); + if (!isa_bus) { return; } @@ -307,6 +310,8 @@ static void pci_piix3_realize(PCIDevice *dev, Error **errp) PIIX_RCR_IOPORT, &d->rcr_mem, 1); qemu_register_reset(piix3_reset, d); + + i8257_dma_init(isa_bus, 0); } static void build_pci_isa_aml(AcpiDevAmlIf *adev, Aml *scope) From patchwork Sat Oct 22 15:04:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 13016499 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5B141C3A59D for ; Mon, 24 Oct 2022 02:22:40 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1omghm-0001hq-Sj for qemu-devel@archiver.kernel.org; Sun, 23 Oct 2022 15:32:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1omG4S-00070c-Ty; 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[77.191.171.138]) by smtp.gmail.com with ESMTPSA id 4-20020a170906310400b00780ab5a9116sm13021558ejx.211.2022.10.22.08.05.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 22 Oct 2022 08:05:50 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Eduardo Habkost , =?utf-8?q?Herv=C3=A9_Poussineau?= , Aurelien Jarno , Igor Mammedov , Gerd Hoffmann , John Snow , Jiaxun Yang , Ani Sinha , Marcel Apfelbaum , qemu-block@nongnu.org, Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , "Michael S. Tsirkin" , Paolo Bonzini , Bernhard Beschow , Peter Maydell Subject: [PATCH v2 02/43] hw/i386/pc_piix: Allow for setting properties before realizing PIIX3 south bridge Date: Sat, 22 Oct 2022 17:04:27 +0200 Message-Id: <20221022150508.26830-3-shentey@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221022150508.26830-1-shentey@gmail.com> References: <20221022150508.26830-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::52c; envelope-from=shentey@gmail.com; helo=mail-ed1-x52c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" The next patches will need to take advantage of it. Signed-off-by: Bernhard Beschow Reviewed-by: Peter Maydell --- hw/i386/pc_piix.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 7a55b9ca8e..5caef9bfc9 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -217,7 +217,8 @@ static void pc_init1(MachineState *machine, pci_memory, ram_memory); pcms->bus = pci_bus; - pci_dev = pci_create_simple_multifunction(pci_bus, -1, true, type); + pci_dev = pci_new_multifunction(-1, true, type); + pci_realize_and_unref(pci_dev, pci_bus, &error_fatal); piix3 = PIIX3_PCI_DEVICE(pci_dev); piix3->pic = x86ms->gsi; piix3_devfn = piix3->dev.devfn; From patchwork Sat Oct 22 15:04:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 13016769 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B1D70C3A59D for ; Mon, 24 Oct 2022 07:08:40 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1omgjh-0001t2-Bc for qemu-devel@archiver.kernel.org; Sun, 23 Oct 2022 15:34:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1omG4U-00070e-5l; Sat, 22 Oct 2022 11:05:58 -0400 Received: from mail-ed1-x52d.google.com ([2a00:1450:4864:20::52d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1omG4S-00022R-NP; Sat, 22 Oct 2022 11:05:57 -0400 Received: by mail-ed1-x52d.google.com with SMTP id z97so16067004ede.8; Sat, 22 Oct 2022 08:05:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=YhL+s2XxnSnUyjtcmi53XqolC/lv7/2Xksgo6ny9BDs=; b=OvNyTTFpqelgJINOPLULD9ZVMb1A1t2ub/dpH80HNuFItQoolPgZgmKRhZbtY6GP/5 EsNf2c3Rps84Hd535VQOoBtlK0u6uHc3Fb+eHY/crl5rE3HDtSVD+gpU/Tqtm4C5gdFH Nt9Z4jcrounWxhozo8c5ZK+vnKdkQjsFnezmD+7Rlj8V58Kkue8GvUhUoGxp38tVJURp sWIPTpPROsGRos8SFT8ECIbdCSHdFijWx5QHSOzt6y5cJE4otrdDpBsi1jgxDwWq69Uy 3MHpzhRCTll7JiDM3SfqA4/G3RTZ0fPrbZ11+HRONhfS+bnlcg2RGa43z4nWR8/jAFn5 80KA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YhL+s2XxnSnUyjtcmi53XqolC/lv7/2Xksgo6ny9BDs=; b=Lz3Zsosw7H1B/yKLYf5vNO1GkrWrHi6jCkm9kG+UurOLq4kV/UkG/IpSm0Ztu/1TVL Bh9d/j6xfcEe97izKEu8TAi62qjG0VwMV7sYLnZfn8Tm7lxueSEEkWyblaNSpRt/f3eP OdZjnCc5v6a9fkGk774KbWr6rbYnYjndatfpmBJkdoR8gi4Vab+shlpYimLjkFDCqVd1 hUZitXClahgM+rlFTlc/5WUsSjlb2L09G7GAPJx0MowsrztJyHQJzU8rF20lYjMCId4v k/aerpKBii2KvGxJXtr1CizJRJ+TXTy28Ki+rU8/6CmTP/IkF6/yqbgplBSTOQuswAsW nITg== X-Gm-Message-State: ACrzQf1Qi2WIUDWam30SRF2KL/+cFKfNXLM9B91ws0rJEBwW2/SnpmVV N7NCPIgwxU/OPotX5mWsHgiwzExqcwomCw== X-Google-Smtp-Source: AMsMyM4DlHwCvP39dzlpqD3SYniNoUB/ufYhfXbrx15EezSKkQEsUXJ7ct6EOuIqQsXz68hwYGcWDQ== X-Received: by 2002:a17:906:7621:b0:750:c4a3:8fcd with SMTP id c1-20020a170906762100b00750c4a38fcdmr21274632ejn.180.1666451154636; Sat, 22 Oct 2022 08:05:54 -0700 (PDT) Received: from localhost.localdomain (dynamic-077-191-171-138.77.191.pool.telefonica.de. [77.191.171.138]) by smtp.gmail.com with ESMTPSA id 4-20020a170906310400b00780ab5a9116sm13021558ejx.211.2022.10.22.08.05.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 22 Oct 2022 08:05:53 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Eduardo Habkost , =?utf-8?q?Herv=C3=A9_Poussineau?= , Aurelien Jarno , Igor Mammedov , Gerd Hoffmann , John Snow , Jiaxun Yang , Ani Sinha , Marcel Apfelbaum , qemu-block@nongnu.org, Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , "Michael S. Tsirkin" , Paolo Bonzini , Bernhard Beschow , Peter Maydell Subject: [PATCH v2 03/43] hw/isa/piix3: Remove extra ';' outside of functions Date: Sat, 22 Oct 2022 17:04:28 +0200 Message-Id: <20221022150508.26830-4-shentey@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221022150508.26830-1-shentey@gmail.com> References: <20221022150508.26830-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::52d; envelope-from=shentey@gmail.com; helo=mail-ed1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Fixes the "extra-semi" clang-tidy check. Signed-off-by: Bernhard Beschow Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé --- hw/isa/piix3.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c index 44a9998752..04895ce2e5 100644 --- a/hw/isa/piix3.c +++ b/hw/isa/piix3.c @@ -375,7 +375,7 @@ static void piix3_realize(PCIDevice *dev, Error **errp) pci_bus_irqs(pci_bus, piix3_set_irq, pci_slot_get_pirq, piix3, PIIX_NUM_PIRQS); pci_bus_set_route_irq_fn(pci_bus, piix3_route_intx_pin_to_irq); -}; +} static void piix3_class_init(ObjectClass *klass, void *data) { @@ -410,7 +410,7 @@ static void piix3_xen_realize(PCIDevice *dev, Error **errp) */ pci_bus_irqs(pci_bus, xen_piix3_set_irq, xen_pci_slot_get_pirq, piix3, XEN_PIIX_NUM_PIRQS); -}; +} static void piix3_xen_class_init(ObjectClass *klass, void *data) { @@ -418,7 +418,7 @@ static void piix3_xen_class_init(ObjectClass *klass, void *data) k->config_write = piix3_write_config_xen; k->realize = piix3_xen_realize; -}; +} static const TypeInfo piix3_xen_info = { .name = TYPE_PIIX3_XEN_DEVICE, From patchwork Sat Oct 22 15:04:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 13016448 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 936E6C3A59D for ; Sun, 23 Oct 2022 21:03:12 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1omgmw-0002Fu-F5 for qemu-devel@archiver.kernel.org; Sun, 23 Oct 2022 15:37:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1omG4a-00072J-LT; Sat, 22 Oct 2022 11:06:04 -0400 Received: from mail-ed1-x534.google.com ([2a00:1450:4864:20::534]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1omG4Z-00023s-7D; Sat, 22 Oct 2022 11:06:04 -0400 Received: by mail-ed1-x534.google.com with SMTP id m16so15998494edc.4; Sat, 22 Oct 2022 08:06:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=uX6RSTfRaf07nsOqTQPiiSP6v8L6Z8I07u4DqsFmNRo=; b=Pq/Ui5/xxiWYGmeu0t8Poo/cyBkBU9UlhZlp7pMKnYYMIR/lHUpTPTjhqj6ElV6YZ7 eQ1s4rwvmdYuj6jw3dthaD7StB/McY7JJswaDq5wQxiLPlll/GNJ1oBuiWixCwdH7TWS PVAC6AnzoRp8vSbd+Tk5g6vfnybLk9Fh/RxUc2E5pp5vMwQhQjaUPFR2ee//4ludch39 3DgmNZZe/3g3xCC/cHYn65EGxKdzAh2ReMaWgGVryO9YS6F67NubPTvXu72omxtjIati Jpq3tfgdf/nVo21ddcoyOmpHpGpwN8Gbrzspe0bUc6ClJX2asMZ21h0N3cgqy1SEVX88 WvoA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=uX6RSTfRaf07nsOqTQPiiSP6v8L6Z8I07u4DqsFmNRo=; b=VfXRJLf4nW4UTmDTJ7x8N10lfAixIR6YQBp+WYpN7OUI2vss+pobDVd4OHyn/zYckZ 0rdIpLF57FyWmvRFL+2J6U4Fz6cgn7NPp6NQJ/GsDurwcleSwJvA33O+NfkE3SKH/XH/ 7t9a2I5SqdFPrLxqZWK9iXizHjTFHTbLte15sLZ7uX75nEj7qf3ymZaBxpBsdfZ0Vhyt u9IiEWt7ZyyHNKlPSgUkUDqgN8Hq2M4lDZCnzk7Ct3DmOI80ZgJiWnr6c7ITGMlZHvJL ZNg2ZkPXSAXByQtmD2CcqdE7VBNAvRUl7FiwlwaiuNBTS7CYo2XWsBwbfQxztksqRBh+ pqrw== X-Gm-Message-State: ACrzQf2mig9O+eEyhBl/v+mzk6dXpCmiuOdsjwajZOsEcAm00XmTd7ES xLo97MlFNt8jxgQC7oPpGon7N2SyovoPmA== X-Google-Smtp-Source: AMsMyM7NucFIJxQj9aYKz/jYjzNLaXVdA0Blj7bQBtRkkJCzF+DaDkYhxLCHP3+gAJuQ/05MvElJAw== X-Received: by 2002:a17:907:7e87:b0:78e:1a4:130 with SMTP id qb7-20020a1709077e8700b0078e01a40130mr20823066ejc.101.1666451158886; Sat, 22 Oct 2022 08:05:58 -0700 (PDT) Received: from localhost.localdomain (dynamic-077-191-171-138.77.191.pool.telefonica.de. [77.191.171.138]) by smtp.gmail.com with ESMTPSA id 4-20020a170906310400b00780ab5a9116sm13021558ejx.211.2022.10.22.08.05.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 22 Oct 2022 08:05:56 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Eduardo Habkost , =?utf-8?q?Herv=C3=A9_Poussineau?= , Aurelien Jarno , Igor Mammedov , Gerd Hoffmann , John Snow , Jiaxun Yang , Ani Sinha , Marcel Apfelbaum , qemu-block@nongnu.org, Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , "Michael S. Tsirkin" , Paolo Bonzini , Bernhard Beschow Subject: [PATCH v2 04/43] hw/isa/piix3: Add size constraints to rcr_ops Date: Sat, 22 Oct 2022 17:04:29 +0200 Message-Id: <20221022150508.26830-5-shentey@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221022150508.26830-1-shentey@gmail.com> References: <20221022150508.26830-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::534; envelope-from=shentey@gmail.com; helo=mail-ed1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" According to the PIIX3 datasheet, the reset control register is one byte in size. Moreover, PIIX4 has it, so add it to PIIX3 as well. Signed-off-by: Bernhard Beschow Reviewed-by: Philippe Mathieu-Daudé --- hw/isa/piix3.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c index 04895ce2e5..72dbf688d9 100644 --- a/hw/isa/piix3.c +++ b/hw/isa/piix3.c @@ -290,7 +290,11 @@ static uint64_t rcr_read(void *opaque, hwaddr addr, unsigned len) static const MemoryRegionOps rcr_ops = { .read = rcr_read, .write = rcr_write, - .endianness = DEVICE_LITTLE_ENDIAN + .endianness = DEVICE_LITTLE_ENDIAN, + .impl = { + .min_access_size = 1, + .max_access_size = 1, + }, }; static void pci_piix3_realize(PCIDevice *dev, Error **errp) From patchwork Sat Oct 22 15:04:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 13016464 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EF0A0C3A59D for ; Sun, 23 Oct 2022 22:38:15 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1omgo0-0002SH-Er for qemu-devel@archiver.kernel.org; Sun, 23 Oct 2022 15:38:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1omG4a-00072K-No; Sat, 22 Oct 2022 11:06:04 -0400 Received: from mail-ed1-x52d.google.com ([2a00:1450:4864:20::52d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1omG4Z-00022R-6f; Sat, 22 Oct 2022 11:06:04 -0400 Received: by mail-ed1-x52d.google.com with SMTP id z97so16067643ede.8; Sat, 22 Oct 2022 08:06:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=jA1SDPeK2ToD4+n7uN+7fLnNFWowNdP73qPzh6JImnI=; b=P4FNIyYoO6zLOLiLJgn+UP70kMfg7xJDAW2c53DZEo/7Ipcy5esMJL1mjeWZtHW2Tw 8Ot1yW+jeJUoXsdh4SBZJ1hqP+h5EZ8nqVabbnVpaP0wfDHjw3GJNVHUk9en1AxOPTjV OcKcoHwLSHWAj2q2qxAO6T/CK0q8vwuOyb7CkHuZcwk55kkBsekTSYG6hOqI931EzUv6 qmwNaXGqbmpjQIONpiGGMRzKMusOvcQ8d1ebgsM6GjOnCPFqy1jjJZ8EkRWoZbMg1pO3 OG/U0hqRPl4qiQ1mEt3/nUP5Nc8xof9Zx+xUUzFJxTsCpFWg4oeRFJR7lIKUj8kdqMgL ac3g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jA1SDPeK2ToD4+n7uN+7fLnNFWowNdP73qPzh6JImnI=; b=3KK5jRAoYDCGkH+q7BCPLwnUbJClxoEO3133IaS9Yg5LKXx5+zD45Vcwt7hmNXD5yN rPDT7cv5yInoxfJQkCbg8G7spNR4TvP5zv41cNfgBY7YzCvp0l8/Vvn47TmJLRQRin4H vrzQ4E4xLONZ0nt4UoSoR4AbHHigyRxjdabjke5j4MfEWT6gDAo4iIopd4bktx1G6/ZA PrKVH1jyrVdj1oArQ6uPtYs2C/KKxNgLRIwvKX//WbIzmaUorg8IcM/bUrD0C+NWp9dn zfFroQJ61kVpHabmPqefn4UXPzCJagKisTEuSzYiE2RGdrg8LMg2VDHJZU3ZnTqMetVU QP3Q== X-Gm-Message-State: ACrzQf0ex+nP3FryKZQu2aufDtI5pJTs5XIMs6h9iLV/71+nm46bz5wz L3jp+syBIY25NtdxFEUkSM3mOni8SEzpLQ== X-Google-Smtp-Source: AMsMyM5QGJ4AQYzVd/VymUA8lyKvM09RGq3PvIadpMhfdA7JMBMp2YMhnjRG6zVYULxzohn3DgvN1A== X-Received: by 2002:a17:906:ee8e:b0:730:3646:d178 with SMTP id wt14-20020a170906ee8e00b007303646d178mr20556686ejb.426.1666451161453; Sat, 22 Oct 2022 08:06:01 -0700 (PDT) Received: from localhost.localdomain (dynamic-077-191-171-138.77.191.pool.telefonica.de. [77.191.171.138]) by smtp.gmail.com with ESMTPSA id 4-20020a170906310400b00780ab5a9116sm13021558ejx.211.2022.10.22.08.05.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 22 Oct 2022 08:06:00 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Eduardo Habkost , =?utf-8?q?Herv=C3=A9_Poussineau?= , Aurelien Jarno , Igor Mammedov , Gerd Hoffmann , John Snow , Jiaxun Yang , Ani Sinha , Marcel Apfelbaum , qemu-block@nongnu.org, Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , "Michael S. Tsirkin" , Paolo Bonzini , Bernhard Beschow Subject: [PATCH v2 05/43] hw/isa/piix3: Modernize reset handling Date: Sat, 22 Oct 2022 17:04:30 +0200 Message-Id: <20221022150508.26830-6-shentey@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221022150508.26830-1-shentey@gmail.com> References: <20221022150508.26830-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::52d; envelope-from=shentey@gmail.com; helo=mail-ed1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Rather than registering the reset handler via a function which appends the handler to a global list, prefer to implement it as a virtual method - PIIX4 does the same already. Note that this means that piix3_reset can now also be called writing to the relevant configuration space register on a PCI bridge. Signed-off-by: Bernhard Beschow Reviewed-by: Philippe Mathieu-Daudé --- hw/isa/piix3.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c index 72dbf688d9..723ad0a896 100644 --- a/hw/isa/piix3.c +++ b/hw/isa/piix3.c @@ -31,7 +31,6 @@ #include "hw/isa/isa.h" #include "hw/xen/xen.h" #include "sysemu/xen.h" -#include "sysemu/reset.h" #include "sysemu/runstate.h" #include "migration/vmstate.h" #include "hw/acpi/acpi_aml_interface.h" @@ -156,9 +155,9 @@ static void piix3_write_config_xen(PCIDevice *dev, piix3_write_config(dev, address, val, len); } -static void piix3_reset(void *opaque) +static void piix3_reset(DeviceState *dev) { - PIIX3State *d = opaque; + PIIX3State *d = PIIX3_PCI_DEVICE(dev); uint8_t *pci_conf = d->dev.config; pci_conf[0x04] = 0x07; /* master, memory and I/O */ @@ -313,8 +312,6 @@ static void pci_piix3_realize(PCIDevice *dev, Error **errp) memory_region_add_subregion_overlap(pci_address_space_io(dev), PIIX_RCR_IOPORT, &d->rcr_mem, 1); - qemu_register_reset(piix3_reset, d); - i8257_dma_init(isa_bus, 0); } @@ -337,6 +334,7 @@ static void pci_piix3_class_init(ObjectClass *klass, void *data) PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); AcpiDevAmlIfClass *adevc = ACPI_DEV_AML_IF_CLASS(klass); + dc->reset = piix3_reset; dc->desc = "ISA bridge"; dc->vmsd = &vmstate_piix3; dc->hotpluggable = false; From patchwork Sat Oct 22 15:04:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 13016466 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7D09AC3A59D for ; Sun, 23 Oct 2022 23:36:32 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1omgpj-0002e2-48 for qemu-devel@archiver.kernel.org; Sun, 23 Oct 2022 15:40:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1omG4f-00074D-2y; Sat, 22 Oct 2022 11:06:09 -0400 Received: from mail-ed1-x534.google.com ([2a00:1450:4864:20::534]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1omG4d-00024P-Kk; Sat, 22 Oct 2022 11:06:08 -0400 Received: by mail-ed1-x534.google.com with SMTP id e18so16102332edj.3; Sat, 22 Oct 2022 08:06:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=HYMDu5mDtutX+XNVdVht0ydVyFdG15WL8sqXmNN4tBA=; b=HptB+jNrTG3gUDRS+yjnYBx9LlNe/Kni/LyiGjFBv/Pz6g4bbFD35oBF0lvpmBE0qB kXvdZSLDGbsebi9xAIWIMQlYFzhhjxXLFiU4nspKAWXcC/+0iAHTN6jaZ0SV77W3E44J 1lQt1iDe2Xzt6l+6sc1Em6T6M30UXZCKozcEz06WPA5p7kkDhvSpqZZ7eTGRlSFVFm66 1Zfcf/ZhuYCrxhrtFN6cCLF0jB0x0n31rKgels0BNjkeVzTr3EkEFwwetLKveYDHJyCb e8mOhhMsvxaIsXMbW3ODqpk+E3F+McOlwmukslABilxDl70C4rj1o4P10+8uTfJc7c78 NM0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HYMDu5mDtutX+XNVdVht0ydVyFdG15WL8sqXmNN4tBA=; b=juUTxlQEyFgwr1u+MDoUIi/8cKd+hDXlYroDCUSDP80jZbs3k03VGamInQzmTX1VmV BHdMd7lwxFVzvWc3vSSOFwd5uNG0vmuq69cj8VhlLe/THWlUrPRVq1SvOr1fBnI0tq0g DZ6CcmgaOb5gfIKovmv0jMh0MG+mip8ePToYFSgooA4kRvjfHT0cNG56fYujy12S1CBu Cvb/1nbFz7Ek2dT1vVGHwfsMHULwh8ehxUvaAiFE/eFyzkR97xku7EZPwmFXa+abhkbF 8cKg7RK/fvB4Wrjn05StgyRov85+WgAtuM9xgHVCuI9/78uZzl6MDo2zG6rNYRO7MCP5 Y8Eg== X-Gm-Message-State: ACrzQf2IChNL8lezmw9FfMOJzvCUccyQ6m/xeRoU9n+wo2DwRwbC6RoU y1Fq5jcp4mc/qLw4EbTDefwkKi8mzU+kyQ== X-Google-Smtp-Source: AMsMyM40/y0MNwVHIF20gdocya9iuXBTPTIihe/L3TaEATLx8J30/CnGZpfSMdfWACzPWx8FZBxSQw== X-Received: by 2002:a17:906:844f:b0:78d:8bd1:ee8c with SMTP id e15-20020a170906844f00b0078d8bd1ee8cmr21102605ejy.262.1666451164562; Sat, 22 Oct 2022 08:06:04 -0700 (PDT) Received: from localhost.localdomain (dynamic-077-191-171-138.77.191.pool.telefonica.de. [77.191.171.138]) by smtp.gmail.com with ESMTPSA id 4-20020a170906310400b00780ab5a9116sm13021558ejx.211.2022.10.22.08.06.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 22 Oct 2022 08:06:03 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Eduardo Habkost , =?utf-8?q?Herv=C3=A9_Poussineau?= , Aurelien Jarno , Igor Mammedov , Gerd Hoffmann , John Snow , Jiaxun Yang , Ani Sinha , Marcel Apfelbaum , qemu-block@nongnu.org, Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , "Michael S. Tsirkin" , Paolo Bonzini , Bernhard Beschow Subject: [PATCH v2 06/43] hw/isa/piix3: Prefer pci_address_space() over get_system_memory() Date: Sat, 22 Oct 2022 17:04:31 +0200 Message-Id: <20221022150508.26830-7-shentey@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221022150508.26830-1-shentey@gmail.com> References: <20221022150508.26830-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::534; envelope-from=shentey@gmail.com; helo=mail-ed1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" get_system_memory() accesses global state while pci_address_space() uses whatever has been passed to the device instance, so avoid the global. Moreover, PIIX4 uses pci_address_space() here as well. Signed-off-by: Bernhard Beschow Reviewed-by: Philippe Mathieu-Daudé --- hw/isa/piix3.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c index 723ad0a896..0bea4aefe7 100644 --- a/hw/isa/piix3.c +++ b/hw/isa/piix3.c @@ -301,7 +301,7 @@ static void pci_piix3_realize(PCIDevice *dev, Error **errp) PIIX3State *d = PIIX3_PCI_DEVICE(dev); ISABus *isa_bus; - isa_bus = isa_bus_new(DEVICE(d), get_system_memory(), + isa_bus = isa_bus_new(DEVICE(d), pci_address_space(dev), pci_address_space_io(dev), errp); if (!isa_bus) { return; From patchwork Sat Oct 22 15:04:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 13016582 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0AB3BC38A2D for ; Mon, 24 Oct 2022 03:48:13 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1omgrd-0002tH-QG for qemu-devel@archiver.kernel.org; Sun, 23 Oct 2022 15:42:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1omG4f-00074K-Nf; Sat, 22 Oct 2022 11:06:10 -0400 Received: from mail-ed1-x52b.google.com ([2a00:1450:4864:20::52b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1omG4e-00024Y-A9; Sat, 22 Oct 2022 11:06:09 -0400 Received: by mail-ed1-x52b.google.com with SMTP id e18so16102524edj.3; Sat, 22 Oct 2022 08:06:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=pGBR0uW70Gj4MBPT0PqLYE43W0BADt/1wu3qTUQp2Ok=; b=FO2D8Gc98+0Noj0XNb/sx+4HBI3LpQuMVLYkQ7ilhJnFcw1C0NaMGojx5lFqocguYp OP/ipdRo4K6rRVs6thRxXrdvYRJEgxFFY7ANpQG/sVoMZ1NktZFuD9ftJR788ku1pLq3 uuZw5PgV+S6jpVDnhPLadou5wWRm7D+sdEIl6CxJDOyJRxrlj0zr/5o5TKxbOaLC4Ios oFo5whdJy0nJ9xOgNTtE7kmn2/+KOc0Esmdqcedw2G3w8gUzO7uDl0bu4dcIettBO/x/ BkeIMX8Kd91epWwVg3N0lGRV1iLVPN21p5CIUyv7NIPrS/btMQoAHe/NF6rw2gd3H9l7 uaZQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=pGBR0uW70Gj4MBPT0PqLYE43W0BADt/1wu3qTUQp2Ok=; b=xDmjBtcGzGFxhDwKXUOP7o4ooZVLvuQukJra1eWOSmSfXakWXoJGcLjzl8pbEG0bx0 HETkdWVMYM0DDr3PMggnInICAzf0DzGaOdwcF1SwVX/w/eTNTObhodGshyeB+2wRrk6A MHd+ARqNH8Q7lWZYGTeOfh15vEVpWG9vDDcRK3hFSTF23XglM2U/tE0mnHOQnzHB8lIo 8TjImvC9ZzGHb6ROqNFsyVXrkXJVd5tLHsbdz0cJkbGjpkO1Um9c+WR7yXLbc9eHymru VqYJRV3CZ3Yn91qPkCkwKr1xNTXnB8cIfh8EanWW4k6MeWiucduDsRKHgJwVI9jqvBds zLnA== X-Gm-Message-State: ACrzQf0Fuhok4pQ7wQuoY3qXojwO2n6QyYh6iuejreEqh4N+gcyx97mz 2gzaWAQ9kEFwB6tntAsLLgNyiT5fe2TrvQ== X-Google-Smtp-Source: AMsMyM6xR80tNu2r6exAnMk0ECE4/rGQPgTOALlzPz66ajTiZBeFeD9u+PXAVDGvtdy3Li0v7YSUMA== X-Received: by 2002:a17:907:3f90:b0:78d:afad:2a78 with SMTP id hr16-20020a1709073f9000b0078dafad2a78mr20734013ejc.68.1666451166284; Sat, 22 Oct 2022 08:06:06 -0700 (PDT) Received: from localhost.localdomain (dynamic-077-191-171-138.77.191.pool.telefonica.de. [77.191.171.138]) by smtp.gmail.com with ESMTPSA id 4-20020a170906310400b00780ab5a9116sm13021558ejx.211.2022.10.22.08.06.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 22 Oct 2022 08:06:05 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Eduardo Habkost , =?utf-8?q?Herv=C3=A9_Poussineau?= , Aurelien Jarno , Igor Mammedov , Gerd Hoffmann , John Snow , Jiaxun Yang , Ani Sinha , Marcel Apfelbaum , qemu-block@nongnu.org, Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , "Michael S. Tsirkin" , Paolo Bonzini , Bernhard Beschow Subject: [PATCH v2 07/43] hw/isa/piix4: Rename wrongly named method Date: Sat, 22 Oct 2022 17:04:32 +0200 Message-Id: <20221022150508.26830-8-shentey@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221022150508.26830-1-shentey@gmail.com> References: <20221022150508.26830-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::52b; envelope-from=shentey@gmail.com; helo=mail-ed1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" This method post-loads the southbridge, not the IDE device. Signed-off-by: Bernhard Beschow Reviewed-by: Philippe Mathieu-Daudé --- hw/isa/piix4.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index 15f344dbb7..c88d3bf3bf 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -141,7 +141,7 @@ static void piix4_isa_reset(DeviceState *dev) pci_conf[0xae] = 0x00; } -static int piix4_ide_post_load(void *opaque, int version_id) +static int piix4_post_load(void *opaque, int version_id) { PIIX4State *s = opaque; @@ -156,7 +156,7 @@ static const VMStateDescription vmstate_piix4 = { .name = "PIIX4", .version_id = 3, .minimum_version_id = 2, - .post_load = piix4_ide_post_load, + .post_load = piix4_post_load, .fields = (VMStateField[]) { VMSTATE_PCI_DEVICE(dev, PIIX4State), VMSTATE_UINT8_V(rcr, PIIX4State, 3), From patchwork Sat Oct 22 15:04:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 13016502 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EAD99C433FE for ; Mon, 24 Oct 2022 02:31:26 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1omgsa-00032H-5g for qemu-devel@archiver.kernel.org; Sun, 23 Oct 2022 15:43:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1omG4i-00074q-4N; Sat, 22 Oct 2022 11:06:13 -0400 Received: from mail-ed1-x52f.google.com ([2a00:1450:4864:20::52f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1omG4g-00024q-DY; Sat, 22 Oct 2022 11:06:11 -0400 Received: by mail-ed1-x52f.google.com with SMTP id w8so13811160edc.1; Sat, 22 Oct 2022 08:06:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=cKZqib3fhm1kepMM6SwFFivJWeCKSjR8Aa5Vv4oIg6E=; b=R+8/rKBU7onKIoUJALsHXr7Ajv0uRGLYyXcL41twYvbvkKFB62s9DvdNB6arJlqDb7 i6FmJn5S1R1vq6YOd9VBKp5nE2693eeFvjppZ1fyvlKMdKukZcBx3LH8gOD8NREP7qY2 fb276KxhF/MCBmv+Cv+yf9eYk2ikgFdEMUbxmubHk83At7hYcLmM0cfgjiuUBFJryxpC 80/E/Sf/LQ84Cr61aRFz63nhOK1+7DoVQPMQdaRJMtZ0/cq6s0aRuPvX1cEyf9JUOR4g MKabEVUHxhumH6Fx8r+3kTa9D64bmN1AsgGsEYF7DoJ5RcgXaiaLuDfl4xsQ0k/N1pyw gvNw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=cKZqib3fhm1kepMM6SwFFivJWeCKSjR8Aa5Vv4oIg6E=; b=bHz2ytapiyCuvhj0rGUvKA0b2VRITeibAxh1sBDNmFJec3jUQi+dTaMLf424UCdkUf ++bAV0H8a1TJ0e5sAFPjegwWg4nmaGV3V/8pYWehfzSGSy1nWRX+XpzUDcFELq1iIgqy HrJkKUDCrIKlmjtFS20nGNHpPmlYej3GXKz4boXw4s+glcEz160JItRgb7yhzYDqpBru 9JZJ02OZgWg67zlufc+3QGJdtA1uMkmOzI38IEBfysRD04bqs1oZ3GP+0r/ETZvkQ8Y6 InRuKF0MKIaEXmcS0ejEbE/UWRdkDYXp9QZs6mcvYdrZI7/DadDmJ1iZa35ADCKuxAWc AmgQ== X-Gm-Message-State: ACrzQf180OgQakKdgSRmxtWB447ZBMOCzZ8JFpQtU9I5norYFdFAuQ4n DebzZ9Qe5FTJfrHnDiR82wsJ6vBfHHbUbw== X-Google-Smtp-Source: AMsMyM73l5JfljiaC/NoU+nOEOn+Ym82rHyXMEE6T+lrVf1d5uh7Ft+T8/sEpYqqECxOK1yHGr1ZLQ== X-Received: by 2002:a17:907:9495:b0:78e:1bee:5919 with SMTP id dm21-20020a170907949500b0078e1bee5919mr19914510ejc.701.1666451168466; Sat, 22 Oct 2022 08:06:08 -0700 (PDT) Received: from localhost.localdomain (dynamic-077-191-171-138.77.191.pool.telefonica.de. [77.191.171.138]) by smtp.gmail.com with ESMTPSA id 4-20020a170906310400b00780ab5a9116sm13021558ejx.211.2022.10.22.08.06.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 22 Oct 2022 08:06:07 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Eduardo Habkost , =?utf-8?q?Herv=C3=A9_Poussineau?= , Aurelien Jarno , Igor Mammedov , Gerd Hoffmann , John Snow , Jiaxun Yang , Ani Sinha , Marcel Apfelbaum , qemu-block@nongnu.org, Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , "Michael S. Tsirkin" , Paolo Bonzini , Bernhard Beschow , Mark Cave-Ayland Subject: [PATCH v2 08/43] hw/ide/piix: Introduce TYPE_ macros for PIIX IDE controllers Date: Sat, 22 Oct 2022 17:04:33 +0200 Message-Id: <20221022150508.26830-9-shentey@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221022150508.26830-1-shentey@gmail.com> References: <20221022150508.26830-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::52f; envelope-from=shentey@gmail.com; helo=mail-ed1-x52f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Suggested-by: Mark Cave-Ayland Signed-off-by: Bernhard Beschow Reviewed-by: Philippe Mathieu-Daudé --- hw/i386/pc_piix.c | 3 ++- hw/ide/piix.c | 5 +++-- hw/isa/piix4.c | 3 ++- include/hw/ide/piix.h | 7 +++++++ 4 files changed, 14 insertions(+), 4 deletions(-) create mode 100644 include/hw/ide/piix.h diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 5caef9bfc9..e26509a935 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -40,6 +40,7 @@ #include "hw/usb.h" #include "net/net.h" #include "hw/ide/pci.h" +#include "hw/ide/piix.h" #include "hw/irq.h" #include "sysemu/kvm.h" #include "hw/kvm/clock.h" @@ -260,7 +261,7 @@ static void pc_init1(MachineState *machine, if (pcmc->pci_enabled) { PCIDevice *dev; - dev = pci_create_simple(pci_bus, piix3_devfn + 1, "piix3-ide"); + dev = pci_create_simple(pci_bus, piix3_devfn + 1, TYPE_PIIX3_IDE); pci_ide_create_devs(dev); idebus[0] = qdev_get_child_bus(&dev->qdev, "ide.0"); idebus[1] = qdev_get_child_bus(&dev->qdev, "ide.1"); diff --git a/hw/ide/piix.c b/hw/ide/piix.c index de1f4f0efb..267dbf37db 100644 --- a/hw/ide/piix.c +++ b/hw/ide/piix.c @@ -36,6 +36,7 @@ #include "sysemu/blockdev.h" #include "sysemu/dma.h" +#include "hw/ide/piix.h" #include "hw/ide/pci.h" #include "trace.h" @@ -202,7 +203,7 @@ static void piix3_ide_class_init(ObjectClass *klass, void *data) } static const TypeInfo piix3_ide_info = { - .name = "piix3-ide", + .name = TYPE_PIIX3_IDE, .parent = TYPE_PCI_IDE, .class_init = piix3_ide_class_init, }; @@ -224,7 +225,7 @@ static void piix4_ide_class_init(ObjectClass *klass, void *data) } static const TypeInfo piix4_ide_info = { - .name = "piix4-ide", + .name = TYPE_PIIX4_IDE, .parent = TYPE_PCI_IDE, .class_init = piix4_ide_class_init, }; diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index c88d3bf3bf..e05e65d3bc 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -28,6 +28,7 @@ #include "hw/irq.h" #include "hw/southbridge/piix.h" #include "hw/pci/pci.h" +#include "hw/ide/piix.h" #include "hw/isa/isa.h" #include "hw/intc/i8259.h" #include "hw/dma/i8257.h" @@ -277,7 +278,7 @@ static void piix4_init(Object *obj) PIIX4State *s = PIIX4_PCI_DEVICE(obj); object_initialize_child(obj, "rtc", &s->rtc, TYPE_MC146818_RTC); - object_initialize_child(obj, "ide", &s->ide, "piix4-ide"); + object_initialize_child(obj, "ide", &s->ide, TYPE_PIIX4_IDE); object_initialize_child(obj, "uhci", &s->uhci, "piix4-usb-uhci"); object_initialize_child(obj, "pm", &s->pm, TYPE_PIIX4_PM); diff --git a/include/hw/ide/piix.h b/include/hw/ide/piix.h new file mode 100644 index 0000000000..ef3ef3d62d --- /dev/null +++ b/include/hw/ide/piix.h @@ -0,0 +1,7 @@ +#ifndef HW_IDE_PIIX_H +#define HW_IDE_PIIX_H + +#define TYPE_PIIX3_IDE "piix3-ide" +#define TYPE_PIIX4_IDE "piix4-ide" + +#endif /* HW_IDE_PIIX_H */ From patchwork Sat Oct 22 15:04:34 2022 Content-Type: text/plain; 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[77.191.171.138]) by smtp.gmail.com with ESMTPSA id 4-20020a170906310400b00780ab5a9116sm13021558ejx.211.2022.10.22.08.06.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 22 Oct 2022 08:06:10 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Eduardo Habkost , =?utf-8?q?Herv=C3=A9_Poussineau?= , Aurelien Jarno , Igor Mammedov , Gerd Hoffmann , John Snow , Jiaxun Yang , Ani Sinha , Marcel Apfelbaum , qemu-block@nongnu.org, Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , "Michael S. Tsirkin" , Paolo Bonzini , Bernhard Beschow , Mark Cave-Ayland Subject: [PATCH v2 09/43] hw/usb/hcd-uhci: Introduce TYPE_ defines for device models Date: Sat, 22 Oct 2022 17:04:34 +0200 Message-Id: <20221022150508.26830-10-shentey@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221022150508.26830-1-shentey@gmail.com> References: <20221022150508.26830-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::52d; envelope-from=shentey@gmail.com; helo=mail-ed1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Suggested-by: Mark Cave-Ayland Signed-off-by: Bernhard Beschow --- hw/i386/pc_piix.c | 3 ++- hw/i386/pc_q35.c | 13 +++++++------ hw/isa/piix4.c | 2 +- hw/usb/hcd-uhci.c | 16 ++++++++-------- hw/usb/hcd-uhci.h | 9 +++++++++ 5 files changed, 27 insertions(+), 16 deletions(-) diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index e26509a935..caa983d76e 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -50,6 +50,7 @@ #include "exec/memory.h" #include "hw/acpi/acpi.h" #include "hw/acpi/piix4.h" +#include "hw/usb/hcd-uhci.h" #include "qapi/error.h" #include "qemu/error-report.h" #include "sysemu/xen.h" @@ -291,7 +292,7 @@ static void pc_init1(MachineState *machine, #endif if (pcmc->pci_enabled && machine_usb(machine)) { - pci_create_simple(pci_bus, piix3_devfn + 2, "piix3-usb-uhci"); + pci_create_simple(pci_bus, piix3_devfn + 2, TYPE_PIIX3_USB_UHCI); } if (pcmc->pci_enabled && x86_machine_is_acpi_enabled(X86_MACHINE(pcms))) { diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index a496bd6e74..fa24b5ef66 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -48,6 +48,7 @@ #include "hw/ide/pci.h" #include "hw/ide/ahci.h" #include "hw/usb.h" +#include "hw/usb/hcd-uhci.h" #include "qapi/error.h" #include "qemu/error-report.h" #include "sysemu/numa.h" @@ -65,15 +66,15 @@ struct ehci_companions { }; static const struct ehci_companions ich9_1d[] = { - { .name = "ich9-usb-uhci1", .func = 0, .port = 0 }, - { .name = "ich9-usb-uhci2", .func = 1, .port = 2 }, - { .name = "ich9-usb-uhci3", .func = 2, .port = 4 }, + { .name = TYPE_ICH9_USB_UHCI1, .func = 0, .port = 0 }, + { .name = TYPE_ICH9_USB_UHCI2, .func = 1, .port = 2 }, + { .name = TYPE_ICH9_USB_UHCI3, .func = 2, .port = 4 }, }; static const struct ehci_companions ich9_1a[] = { - { .name = "ich9-usb-uhci4", .func = 0, .port = 0 }, - { .name = "ich9-usb-uhci5", .func = 1, .port = 2 }, - { .name = "ich9-usb-uhci6", .func = 2, .port = 4 }, + { .name = TYPE_ICH9_USB_UHCI4, .func = 0, .port = 0 }, + { .name = TYPE_ICH9_USB_UHCI5, .func = 1, .port = 2 }, + { .name = TYPE_ICH9_USB_UHCI6, .func = 2, .port = 4 }, }; static int ehci_create_ich9_with_companions(PCIBus *bus, int slot) diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index e05e65d3bc..83b50c3a9b 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -279,7 +279,7 @@ static void piix4_init(Object *obj) object_initialize_child(obj, "rtc", &s->rtc, TYPE_MC146818_RTC); object_initialize_child(obj, "ide", &s->ide, TYPE_PIIX4_IDE); - object_initialize_child(obj, "uhci", &s->uhci, "piix4-usb-uhci"); + object_initialize_child(obj, "uhci", &s->uhci, TYPE_PIIX4_USB_UHCI); object_initialize_child(obj, "pm", &s->pm, TYPE_PIIX4_PM); qdev_prop_set_uint32(DEVICE(&s->pm), "smb_io_base", 0x1100); diff --git a/hw/usb/hcd-uhci.c b/hw/usb/hcd-uhci.c index d1b5657d72..0ec4cfaa52 100644 --- a/hw/usb/hcd-uhci.c +++ b/hw/usb/hcd-uhci.c @@ -1292,56 +1292,56 @@ void uhci_data_class_init(ObjectClass *klass, void *data) static UHCIInfo uhci_info[] = { { - .name = "piix3-usb-uhci", + .name = TYPE_PIIX3_USB_UHCI, .vendor_id = PCI_VENDOR_ID_INTEL, .device_id = PCI_DEVICE_ID_INTEL_82371SB_2, .revision = 0x01, .irq_pin = 3, .unplug = true, },{ - .name = "piix4-usb-uhci", + .name = TYPE_PIIX4_USB_UHCI, .vendor_id = PCI_VENDOR_ID_INTEL, .device_id = PCI_DEVICE_ID_INTEL_82371AB_2, .revision = 0x01, .irq_pin = 3, .unplug = true, },{ - .name = "ich9-usb-uhci1", /* 00:1d.0 */ + .name = TYPE_ICH9_USB_UHCI1, /* 00:1d.0 */ .vendor_id = PCI_VENDOR_ID_INTEL, .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI1, .revision = 0x03, .irq_pin = 0, .unplug = false, },{ - .name = "ich9-usb-uhci2", /* 00:1d.1 */ + .name = TYPE_ICH9_USB_UHCI2, /* 00:1d.1 */ .vendor_id = PCI_VENDOR_ID_INTEL, .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI2, .revision = 0x03, .irq_pin = 1, .unplug = false, },{ - .name = "ich9-usb-uhci3", /* 00:1d.2 */ + .name = TYPE_ICH9_USB_UHCI3, /* 00:1d.2 */ .vendor_id = PCI_VENDOR_ID_INTEL, .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI3, .revision = 0x03, .irq_pin = 2, .unplug = false, },{ - .name = "ich9-usb-uhci4", /* 00:1a.0 */ + .name = TYPE_ICH9_USB_UHCI4, /* 00:1a.0 */ .vendor_id = PCI_VENDOR_ID_INTEL, .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI4, .revision = 0x03, .irq_pin = 0, .unplug = false, },{ - .name = "ich9-usb-uhci5", /* 00:1a.1 */ + .name = TYPE_ICH9_USB_UHCI5, /* 00:1a.1 */ .vendor_id = PCI_VENDOR_ID_INTEL, .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI5, .revision = 0x03, .irq_pin = 1, .unplug = false, },{ - .name = "ich9-usb-uhci6", /* 00:1a.2 */ + .name = TYPE_ICH9_USB_UHCI6, /* 00:1a.2 */ .vendor_id = PCI_VENDOR_ID_INTEL, .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI6, .revision = 0x03, diff --git a/hw/usb/hcd-uhci.h b/hw/usb/hcd-uhci.h index c85ab7868e..22f6e6fcfc 100644 --- a/hw/usb/hcd-uhci.h +++ b/hw/usb/hcd-uhci.h @@ -91,4 +91,13 @@ typedef struct UHCIInfo { void uhci_data_class_init(ObjectClass *klass, void *data); void usb_uhci_common_realize(PCIDevice *dev, Error **errp); +#define TYPE_PIIX3_USB_UHCI "piix3-usb-uhci" +#define TYPE_PIIX4_USB_UHCI "piix4-usb-uhci" +#define TYPE_ICH9_USB_UHCI1 "ich9-usb-uhci1" +#define TYPE_ICH9_USB_UHCI2 "ich9-usb-uhci2" +#define TYPE_ICH9_USB_UHCI3 "ich9-usb-uhci3" +#define TYPE_ICH9_USB_UHCI4 "ich9-usb-uhci4" +#define TYPE_ICH9_USB_UHCI5 "ich9-usb-uhci5" +#define TYPE_ICH9_USB_UHCI6 "ich9-usb-uhci6" + #endif From patchwork Sat Oct 22 15:04:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 13016450 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 97BE7C433FE for ; Sun, 23 Oct 2022 21:03:49 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1omgxS-0003dH-9d for qemu-devel@archiver.kernel.org; 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[77.191.171.138]) by smtp.gmail.com with ESMTPSA id 4-20020a170906310400b00780ab5a9116sm13021558ejx.211.2022.10.22.08.06.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 22 Oct 2022 08:06:12 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Eduardo Habkost , =?utf-8?q?Herv=C3=A9_Poussineau?= , Aurelien Jarno , Igor Mammedov , Gerd Hoffmann , John Snow , Jiaxun Yang , Ani Sinha , Marcel Apfelbaum , qemu-block@nongnu.org, Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , "Michael S. Tsirkin" , Paolo Bonzini , Bernhard Beschow Subject: [PATCH v2 10/43] hw/i386/pc: Create RTC controllers in south bridges Date: Sat, 22 Oct 2022 17:04:35 +0200 Message-Id: <20221022150508.26830-11-shentey@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221022150508.26830-1-shentey@gmail.com> References: <20221022150508.26830-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::530; envelope-from=shentey@gmail.com; helo=mail-ed1-x530.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Just like in the real hardware (and in PIIX4), create the RTC controllers in the south bridges. Signed-off-by: Bernhard Beschow --- hw/i386/pc.c | 12 +++++++++++- hw/i386/pc_piix.c | 8 ++++++++ hw/i386/pc_q35.c | 1 + hw/isa/Kconfig | 2 ++ hw/isa/lpc_ich9.c | 8 ++++++++ hw/isa/piix3.c | 15 +++++++++++++++ include/hw/i386/ich9.h | 2 ++ include/hw/southbridge/piix.h | 3 +++ 8 files changed, 50 insertions(+), 1 deletion(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index b39ecd4d0c..8f72aedea4 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -1301,7 +1301,17 @@ void pc_basic_device_init(struct PCMachineState *pcms, pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); } - *rtc_state = mc146818_rtc_init(isa_bus, 2000, rtc_irq); + + if (rtc_irq) { + qdev_connect_gpio_out(DEVICE(*rtc_state), 0, rtc_irq); + } else { + uint32_t irq = object_property_get_uint(OBJECT(*rtc_state), + "irq", + &error_fatal); + isa_connect_gpio_out(*rtc_state, 0, irq); + } + object_property_add_alias(OBJECT(pcms), "rtc-time", OBJECT(*rtc_state), + "date"); qemu_register_boot_set(pc_boot_set, *rtc_state); diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index caa983d76e..7de2f1092b 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -32,6 +32,7 @@ #include "hw/i386/pc.h" #include "hw/i386/apic.h" #include "hw/pci-host/i440fx.h" +#include "hw/rtc/mc146818rtc.h" #include "hw/southbridge/piix.h" #include "hw/display/ramfb.h" #include "hw/firmware/smbios.h" @@ -225,10 +226,17 @@ static void pc_init1(MachineState *machine, piix3->pic = x86ms->gsi; piix3_devfn = piix3->dev.devfn; isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0")); + rtc_state = ISA_DEVICE(object_resolve_path_component(OBJECT(pci_dev), + "rtc")); } else { pci_bus = NULL; isa_bus = isa_bus_new(NULL, get_system_memory(), system_io, &error_abort); + + rtc_state = isa_new(TYPE_MC146818_RTC); + qdev_prop_set_int32(DEVICE(rtc_state), "base_year", 2000); + isa_realize_and_unref(rtc_state, isa_bus, &error_fatal); + i8257_dma_init(isa_bus, 0); pcms->hpet_enabled = false; } diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index fa24b5ef66..bf0888db97 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -239,6 +239,7 @@ static void pc_q35_init(MachineState *machine) lpc = pci_create_simple_multifunction(host_bus, PCI_DEVFN(ICH9_LPC_DEV, ICH9_LPC_FUNC), true, TYPE_ICH9_LPC_DEVICE); + rtc_state = ISA_DEVICE(object_resolve_path_component(OBJECT(lpc), "rtc")); object_property_add_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP, TYPE_HOTPLUG_HANDLER, diff --git a/hw/isa/Kconfig b/hw/isa/Kconfig index c65d2d2666..6e8f9cac54 100644 --- a/hw/isa/Kconfig +++ b/hw/isa/Kconfig @@ -35,6 +35,7 @@ config PIIX3 bool select I8257 select ISA_BUS + select MC146818RTC config PIIX4 bool @@ -72,3 +73,4 @@ config LPC_ICH9 select ISA_BUS select ACPI_SMBUS select ACPI_X86_ICH + select MC146818RTC diff --git a/hw/isa/lpc_ich9.c b/hw/isa/lpc_ich9.c index 8694e58b21..0051fa66ab 100644 --- a/hw/isa/lpc_ich9.c +++ b/hw/isa/lpc_ich9.c @@ -660,6 +660,8 @@ static void ich9_lpc_initfn(Object *obj) static const uint8_t acpi_enable_cmd = ICH9_APM_ACPI_ENABLE; static const uint8_t acpi_disable_cmd = ICH9_APM_ACPI_DISABLE; + object_initialize_child(obj, "rtc", &lpc->rtc, TYPE_MC146818_RTC); + object_property_add_uint8_ptr(obj, ACPI_PM_PROP_SCI_INT, &lpc->sci_gsi, OBJ_PROP_FLAG_READ); object_property_add_uint8_ptr(OBJECT(lpc), ACPI_PM_PROP_ACPI_ENABLE_CMD, @@ -725,6 +727,12 @@ static void ich9_lpc_realize(PCIDevice *d, Error **errp) isa_bus_irqs(isa_bus, lpc->gsi); i8257_dma_init(isa_bus, 0); + + /* RTC */ + qdev_prop_set_int32(DEVICE(&lpc->rtc), "base_year", 2000); + if (!qdev_realize(DEVICE(&lpc->rtc), BUS(isa_bus), errp)) { + return; + } } static bool ich9_rst_cnt_needed(void *opaque) diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c index 0bea4aefe7..75c6370e33 100644 --- a/hw/isa/piix3.c +++ b/hw/isa/piix3.c @@ -28,6 +28,7 @@ #include "hw/dma/i8257.h" #include "hw/southbridge/piix.h" #include "hw/irq.h" +#include "hw/qdev-properties.h" #include "hw/isa/isa.h" #include "hw/xen/xen.h" #include "sysemu/xen.h" @@ -313,6 +314,12 @@ static void pci_piix3_realize(PCIDevice *dev, Error **errp) PIIX_RCR_IOPORT, &d->rcr_mem, 1); i8257_dma_init(isa_bus, 0); + + /* RTC */ + qdev_prop_set_int32(DEVICE(&d->rtc), "base_year", 2000); + if (!qdev_realize(DEVICE(&d->rtc), BUS(isa_bus), errp)) { + return; + } } static void build_pci_isa_aml(AcpiDevAmlIf *adev, Aml *scope) @@ -328,6 +335,13 @@ static void build_pci_isa_aml(AcpiDevAmlIf *adev, Aml *scope) } } +static void pci_piix3_init(Object *obj) +{ + PIIX3State *d = PIIX3_PCI_DEVICE(obj); + + object_initialize_child(obj, "rtc", &d->rtc, TYPE_MC146818_RTC); +} + static void pci_piix3_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); @@ -354,6 +368,7 @@ static const TypeInfo piix3_pci_type_info = { .name = TYPE_PIIX3_PCI_DEVICE, .parent = TYPE_PCI_DEVICE, .instance_size = sizeof(PIIX3State), + .instance_init = pci_piix3_init, .abstract = true, .class_init = pci_piix3_class_init, .interfaces = (InterfaceInfo[]) { diff --git a/include/hw/i386/ich9.h b/include/hw/i386/ich9.h index 23ee8e371b..672efc6bce 100644 --- a/include/hw/i386/ich9.h +++ b/include/hw/i386/ich9.h @@ -11,6 +11,7 @@ #include "hw/acpi/acpi.h" #include "hw/acpi/ich9.h" #include "hw/pci/pci_bus.h" +#include "hw/rtc/mc146818rtc.h" #include "qom/object.h" void ich9_lpc_set_irq(void *opaque, int irq_num, int level); @@ -39,6 +40,7 @@ struct ICH9LPCState { */ uint8_t irr[PCI_SLOT_MAX][PCI_NUM_PINS]; + RTCState rtc; APMState apm; ICH9LPCPMRegs pm; uint32_t sci_level; /* track sci level */ diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h index 2693778b23..b1fa08dd2b 100644 --- a/include/hw/southbridge/piix.h +++ b/include/hw/southbridge/piix.h @@ -14,6 +14,7 @@ #include "hw/pci/pci.h" #include "qom/object.h" +#include "hw/rtc/mc146818rtc.h" /* PIRQRC[A:D]: PIRQx Route Control Registers */ #define PIIX_PIRQCA 0x60 @@ -52,6 +53,8 @@ struct PIIXState { /* This member isn't used. Just for save/load compatibility */ int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS]; + RTCState rtc; + /* Reset Control Register contents */ uint8_t rcr; From patchwork Sat Oct 22 15:04:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 13016465 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D130BC433FE for ; Sun, 23 Oct 2022 22:41:40 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1omgyn-0003lH-Hf for qemu-devel@archiver.kernel.org; Sun, 23 Oct 2022 15:49:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1omG4s-00077p-6z; Sat, 22 Oct 2022 11:06:22 -0400 Received: from mail-ed1-x52d.google.com ([2a00:1450:4864:20::52d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1omG4q-00026R-Im; Sat, 22 Oct 2022 11:06:22 -0400 Received: by mail-ed1-x52d.google.com with SMTP id u21so16098625edi.9; Sat, 22 Oct 2022 08:06:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=GR9CJIBgt9N+B9FKDmAgyhzq/HDc453u4Nxt6YUO8PE=; b=KamZZ1ho3l94LDdtEhSATSyGjX2ZfouQ8d81CqLJQfqnerOcZ9Xr9hdPX9SjuHXW4N KqwVCcvCtY4VYSFoDobZTijPL6zLVIFvx0YNJmrlF+NFye5mrmVVrqcf/t/YysEt6aIx hgLbL6S+aCmJcS2Xiy7zBOSiHWih8SMymJSyvTrLxHqWsi3jf95ezLxRnTAQuQgqKxEY +0yTz57MhvPPhasWAgxNXyo82oaXF6o2hxoB93WXxXeKZ93/G6zPDTJMHJrK5ZwLBqz1 cuhZAHi7vIYTB3uazEb0RsEUAqZm37p+EESSrlfFxrPpf0+5ZTZX+8xG6FSXJ/4OBZ1D PlcA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=GR9CJIBgt9N+B9FKDmAgyhzq/HDc453u4Nxt6YUO8PE=; b=pbb95XAKwdcVsUe4PtVQsv/ZpiEEcl1VyAzYbwSii8tE5sjQ20QrGMjhHCorC460N7 W0GyvYBbabXkhQgbnxYRAJcjTQhHMK1dXwbAGP76G/l9Z08Qc94kH4YFo7AoehbzyY9X FRssjFWhf/dhyrUuI4ooxSHCpBOEVo1EXxnfaBAeQKvxTTWJV50kkj4khVBS1j5josY5 dEjrHiJ2ekxCzhdJ1wsJIfL6a53MBTJPI1tYIZy9HwCCfGPUlPlXNaZ3RIleqxgjYcX9 HiBkB24TLbaEp/+0X/qDPpsjEzNH3ebv/QLY+FEgv/peHmBv7ZiqcqHElx86iJojBegd gFhg== X-Gm-Message-State: ACrzQf2zKk5TKOTQKvOUtj1intZToCz/hlN7B2BfxQVpJJbuAnk76h9z QH1znkyOkcvTCueyqluIACoQ94KeTscmHg== X-Google-Smtp-Source: AMsMyM4oEg2uHL4mHdM4QRyNJz+lp8yva0HsPH/sYMEfGpCCnuqVpe2ZsyB+cXToV1xaJl3KzMuL0Q== X-Received: by 2002:a17:906:c152:b0:78d:9dbb:150b with SMTP id dp18-20020a170906c15200b0078d9dbb150bmr19347990ejc.542.1666451178595; Sat, 22 Oct 2022 08:06:18 -0700 (PDT) Received: from localhost.localdomain (dynamic-077-191-171-138.77.191.pool.telefonica.de. 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Tsirkin" , Paolo Bonzini , Bernhard Beschow , Peter Maydell Subject: [PATCH v2 11/43] hw/i386/pc: No need for rtc_state to be an out-parameter Date: Sat, 22 Oct 2022 17:04:36 +0200 Message-Id: <20221022150508.26830-12-shentey@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221022150508.26830-1-shentey@gmail.com> References: <20221022150508.26830-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::52d; envelope-from=shentey@gmail.com; helo=mail-ed1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Now that the RTC is created as part of the southbridges it doesn't need to be an out-parameter any longer. Signed-off-by: Bernhard Beschow Reviewed-by: Peter Maydell --- hw/i386/pc.c | 12 ++++++------ hw/i386/pc_piix.c | 2 +- hw/i386/pc_q35.c | 2 +- include/hw/i386/pc.h | 2 +- 4 files changed, 9 insertions(+), 9 deletions(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 8f72aedea4..8619a295f2 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -1248,7 +1248,7 @@ static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, void pc_basic_device_init(struct PCMachineState *pcms, ISABus *isa_bus, qemu_irq *gsi, - ISADevice **rtc_state, + ISADevice *rtc_state, bool create_fdctrl, uint32_t hpet_irqs) { @@ -1303,17 +1303,17 @@ void pc_basic_device_init(struct PCMachineState *pcms, } if (rtc_irq) { - qdev_connect_gpio_out(DEVICE(*rtc_state), 0, rtc_irq); + qdev_connect_gpio_out(DEVICE(rtc_state), 0, rtc_irq); } else { - uint32_t irq = object_property_get_uint(OBJECT(*rtc_state), + uint32_t irq = object_property_get_uint(OBJECT(rtc_state), "irq", &error_fatal); - isa_connect_gpio_out(*rtc_state, 0, irq); + isa_connect_gpio_out(rtc_state, 0, irq); } - object_property_add_alias(OBJECT(pcms), "rtc-time", OBJECT(*rtc_state), + object_property_add_alias(OBJECT(pcms), "rtc-time", OBJECT(rtc_state), "date"); - qemu_register_boot_set(pc_boot_set, *rtc_state); + qemu_register_boot_set(pc_boot_set, rtc_state); if (!xen_enabled() && (x86ms->pit == ON_OFF_AUTO_AUTO || x86ms->pit == ON_OFF_AUTO_ON)) { diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 7de2f1092b..b97bff5674 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -262,7 +262,7 @@ static void pc_init1(MachineState *machine, } /* init basic PC hardware */ - pc_basic_device_init(pcms, isa_bus, x86ms->gsi, &rtc_state, true, + pc_basic_device_init(pcms, isa_bus, x86ms->gsi, rtc_state, true, 0x4); pc_nic_init(pcmc, isa_bus, pci_bus); diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index bf0888db97..bee932fb8f 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -293,7 +293,7 @@ static void pc_q35_init(MachineState *machine) } /* init basic PC hardware */ - pc_basic_device_init(pcms, isa_bus, x86ms->gsi, &rtc_state, !mc->no_floppy, + pc_basic_device_init(pcms, isa_bus, x86ms->gsi, rtc_state, !mc->no_floppy, 0xff0104); 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[77.191.171.138]) by smtp.gmail.com with ESMTPSA id 4-20020a170906310400b00780ab5a9116sm13021558ejx.211.2022.10.22.08.06.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 22 Oct 2022 08:06:19 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Eduardo Habkost , =?utf-8?q?Herv=C3=A9_Poussineau?= , Aurelien Jarno , Igor Mammedov , Gerd Hoffmann , John Snow , Jiaxun Yang , Ani Sinha , Marcel Apfelbaum , qemu-block@nongnu.org, Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , "Michael S. Tsirkin" , Paolo Bonzini , Bernhard Beschow Subject: [PATCH v2 12/43] hw/isa/piix3: Create USB controller in host device Date: Sat, 22 Oct 2022 17:04:37 +0200 Message-Id: <20221022150508.26830-13-shentey@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221022150508.26830-1-shentey@gmail.com> References: <20221022150508.26830-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::52b; envelope-from=shentey@gmail.com; helo=mail-ed1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" The USB controller is an integral part of PIIX3 (function 2). So create it as part of the south bridge. Note that the USB function is optional in QEMU. This is why it gets object_initialize_child()'ed in realize rather than in instance_init. Signed-off-by: Bernhard Beschow --- hw/i386/pc_piix.c | 7 ++----- hw/isa/Kconfig | 1 + hw/isa/piix3.c | 17 +++++++++++++++++ include/hw/southbridge/piix.h | 4 ++++ 4 files changed, 24 insertions(+), 5 deletions(-) diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index b97bff5674..22c1c5404c 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -51,7 +51,6 @@ #include "exec/memory.h" #include "hw/acpi/acpi.h" #include "hw/acpi/piix4.h" -#include "hw/usb/hcd-uhci.h" #include "qapi/error.h" #include "qemu/error-report.h" #include "sysemu/xen.h" @@ -221,6 +220,8 @@ static void pc_init1(MachineState *machine, pcms->bus = pci_bus; pci_dev = pci_new_multifunction(-1, true, type); + object_property_set_bool(OBJECT(pci_dev), "has-usb", + machine_usb(machine), &error_abort); pci_realize_and_unref(pci_dev, pci_bus, &error_fatal); piix3 = PIIX3_PCI_DEVICE(pci_dev); piix3->pic = x86ms->gsi; @@ -299,10 +300,6 @@ static void pc_init1(MachineState *machine, } #endif - if (pcmc->pci_enabled && machine_usb(machine)) { - pci_create_simple(pci_bus, piix3_devfn + 2, TYPE_PIIX3_USB_UHCI); - } - if (pcmc->pci_enabled && x86_machine_is_acpi_enabled(X86_MACHINE(pcms))) { PCIDevice *piix4_pm; diff --git a/hw/isa/Kconfig b/hw/isa/Kconfig index 6e8f9cac54..f02eca3c3e 100644 --- a/hw/isa/Kconfig +++ b/hw/isa/Kconfig @@ -36,6 +36,7 @@ config PIIX3 select I8257 select ISA_BUS select MC146818RTC + select USB_UHCI config PIIX4 bool diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c index 75c6370e33..2f227fde0e 100644 --- a/hw/isa/piix3.c +++ b/hw/isa/piix3.c @@ -300,6 +300,7 @@ static const MemoryRegionOps rcr_ops = { static void pci_piix3_realize(PCIDevice *dev, Error **errp) { PIIX3State *d = PIIX3_PCI_DEVICE(dev); + PCIBus *pci_bus = pci_get_bus(dev); ISABus *isa_bus; isa_bus = isa_bus_new(DEVICE(d), pci_address_space(dev), @@ -320,6 +321,16 @@ static void pci_piix3_realize(PCIDevice *dev, Error **errp) if (!qdev_realize(DEVICE(&d->rtc), BUS(isa_bus), errp)) { return; } + + /* USB */ + if (d->has_usb) { + object_initialize_child(OBJECT(dev), "uhci", &d->uhci, + TYPE_PIIX3_USB_UHCI); + qdev_prop_set_int32(DEVICE(&d->uhci), "addr", dev->devfn + 2); + if (!qdev_realize(DEVICE(&d->uhci), BUS(pci_bus), errp)) { + return; + } + } } static void build_pci_isa_aml(AcpiDevAmlIf *adev, Aml *scope) @@ -342,6 +353,11 @@ static void pci_piix3_init(Object *obj) object_initialize_child(obj, "rtc", &d->rtc, TYPE_MC146818_RTC); } +static Property pci_piix3_props[] = { + DEFINE_PROP_BOOL("has-usb", PIIX3State, has_usb, true), + DEFINE_PROP_END_OF_LIST(), +}; + static void pci_piix3_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); @@ -361,6 +377,7 @@ static void pci_piix3_class_init(ObjectClass *klass, void *data) * pc_piix.c's pc_init1() */ dc->user_creatable = false; + device_class_set_props(dc, pci_piix3_props); adevc->build_dev_aml = build_pci_isa_aml; } diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h index b1fa08dd2b..5367917182 100644 --- a/include/hw/southbridge/piix.h +++ b/include/hw/southbridge/piix.h @@ -15,6 +15,7 @@ #include "hw/pci/pci.h" #include "qom/object.h" #include "hw/rtc/mc146818rtc.h" +#include "hw/usb/hcd-uhci.h" /* PIRQRC[A:D]: PIRQx Route Control Registers */ #define PIIX_PIRQCA 0x60 @@ -54,12 +55,15 @@ struct PIIXState { int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS]; RTCState rtc; + UHCIState uhci; /* Reset Control Register contents */ uint8_t rcr; /* IO memory region for Reset Control Register (PIIX_RCR_IOPORT) */ MemoryRegion rcr_mem; + + bool has_usb; }; typedef struct PIIXState PIIX3State; From patchwork Sat Oct 22 15:04:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 13016445 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9E8F3C433FE for ; Sun, 23 Oct 2022 20:53:00 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1omh29-0004J7-IN for qemu-devel@archiver.kernel.org; Sun, 23 Oct 2022 15:53:21 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1omG4z-000797-9h; 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[77.191.171.138]) by smtp.gmail.com with ESMTPSA id 4-20020a170906310400b00780ab5a9116sm13021558ejx.211.2022.10.22.08.06.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 22 Oct 2022 08:06:23 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Eduardo Habkost , =?utf-8?q?Herv=C3=A9_Poussineau?= , Aurelien Jarno , Igor Mammedov , Gerd Hoffmann , John Snow , Jiaxun Yang , Ani Sinha , Marcel Apfelbaum , qemu-block@nongnu.org, Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , "Michael S. Tsirkin" , Paolo Bonzini , Bernhard Beschow Subject: [PATCH v2 13/43] hw/isa/piix3: Create power management controller in host device Date: Sat, 22 Oct 2022 17:04:38 +0200 Message-Id: <20221022150508.26830-14-shentey@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221022150508.26830-1-shentey@gmail.com> References: <20221022150508.26830-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::534; envelope-from=shentey@gmail.com; helo=mail-ed1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" The power management controller is an integral part of PIIX3 (function 3). So create it as part of the south bridge. Note that the ACPI function is optional in QEMU. This is why it gets object_initialize_child()'ed in realize rather than in instance_init. Signed-off-by: Bernhard Beschow --- hw/i386/pc_piix.c | 23 +++++++++++++---------- hw/isa/Kconfig | 1 + hw/isa/piix3.c | 14 ++++++++++++++ include/hw/southbridge/piix.h | 6 ++++++ 4 files changed, 34 insertions(+), 10 deletions(-) diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 22c1c5404c..c96d989636 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -46,11 +46,11 @@ #include "sysemu/kvm.h" #include "hw/kvm/clock.h" #include "hw/sysbus.h" +#include "hw/i2c/i2c.h" #include "hw/i2c/smbus_eeprom.h" #include "hw/xen/xen-x86.h" #include "exec/memory.h" #include "hw/acpi/acpi.h" -#include "hw/acpi/piix4.h" #include "qapi/error.h" #include "qemu/error-report.h" #include "sysemu/xen.h" @@ -85,6 +85,7 @@ static void pc_init1(MachineState *machine, MemoryRegion *system_io = get_system_io(); PCIBus *pci_bus; ISABus *isa_bus; + Object *piix4_pm; int piix3_devfn = -1; qemu_irq smi_irq; GSIState *gsi_state; @@ -222,6 +223,13 @@ static void pc_init1(MachineState *machine, pci_dev = pci_new_multifunction(-1, true, type); object_property_set_bool(OBJECT(pci_dev), "has-usb", machine_usb(machine), &error_abort); + object_property_set_bool(OBJECT(pci_dev), "has-acpi", + x86_machine_is_acpi_enabled(x86ms), + &error_abort); + qdev_prop_set_uint32(DEVICE(pci_dev), "smb_io_base", 0xb100); + object_property_set_bool(OBJECT(pci_dev), "smm-enabled", + x86_machine_is_smm_enabled(x86ms), + &error_abort); pci_realize_and_unref(pci_dev, pci_bus, &error_fatal); piix3 = PIIX3_PCI_DEVICE(pci_dev); piix3->pic = x86ms->gsi; @@ -229,8 +237,10 @@ static void pc_init1(MachineState *machine, isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0")); rtc_state = ISA_DEVICE(object_resolve_path_component(OBJECT(pci_dev), "rtc")); + piix4_pm = object_resolve_path_component(OBJECT(pci_dev), "pm"); } else { pci_bus = NULL; + piix4_pm = NULL; isa_bus = isa_bus_new(NULL, get_system_memory(), system_io, &error_abort); @@ -300,15 +310,8 @@ static void pc_init1(MachineState *machine, } #endif - if (pcmc->pci_enabled && x86_machine_is_acpi_enabled(X86_MACHINE(pcms))) { - PCIDevice *piix4_pm; - + if (piix4_pm) { smi_irq = qemu_allocate_irq(pc_acpi_smi_interrupt, first_cpu, 0); - piix4_pm = pci_new(piix3_devfn + 3, TYPE_PIIX4_PM); - qdev_prop_set_uint32(DEVICE(piix4_pm), "smb_io_base", 0xb100); - qdev_prop_set_bit(DEVICE(piix4_pm), "smm-enabled", - x86_machine_is_smm_enabled(x86ms)); - pci_realize_and_unref(piix4_pm, pci_bus, &error_fatal); qdev_connect_gpio_out(DEVICE(piix4_pm), 0, x86ms->gsi[9]); qdev_connect_gpio_out_named(DEVICE(piix4_pm), "smi-irq", 0, smi_irq); @@ -322,7 +325,7 @@ static void pc_init1(MachineState *machine, object_property_allow_set_link, OBJ_PROP_LINK_STRONG); object_property_set_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP, - OBJECT(piix4_pm), &error_abort); + piix4_pm, &error_abort); } if (machine->nvdimms_state->is_enabled) { diff --git a/hw/isa/Kconfig b/hw/isa/Kconfig index f02eca3c3e..f10daa26bc 100644 --- a/hw/isa/Kconfig +++ b/hw/isa/Kconfig @@ -33,6 +33,7 @@ config PC87312 config PIIX3 bool + select ACPI_PIIX4 select I8257 select ISA_BUS select MC146818RTC diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c index 2f227fde0e..a4b8ebd5f5 100644 --- a/hw/isa/piix3.c +++ b/hw/isa/piix3.c @@ -331,6 +331,17 @@ static void pci_piix3_realize(PCIDevice *dev, Error **errp) return; } } + + /* Power Management */ + if (d->has_acpi) { + object_initialize_child(OBJECT(d), "pm", &d->pm, TYPE_PIIX4_PM); + qdev_prop_set_int32(DEVICE(&d->pm), "addr", dev->devfn + 3); + qdev_prop_set_uint32(DEVICE(&d->pm), "smb_io_base", d->smb_io_base); + qdev_prop_set_bit(DEVICE(&d->pm), "smm-enabled", d->smm_enabled); + if (!qdev_realize(DEVICE(&d->pm), BUS(pci_bus), errp)) { + return; + } + } } static void build_pci_isa_aml(AcpiDevAmlIf *adev, Aml *scope) @@ -354,7 +365,10 @@ static void pci_piix3_init(Object *obj) } static Property pci_piix3_props[] = { + DEFINE_PROP_UINT32("smb_io_base", PIIX3State, smb_io_base, 0), + DEFINE_PROP_BOOL("has-acpi", PIIX3State, has_acpi, true), DEFINE_PROP_BOOL("has-usb", PIIX3State, has_usb, true), + DEFINE_PROP_BOOL("smm-enabled", PIIX3State, smm_enabled, false), DEFINE_PROP_END_OF_LIST(), }; diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h index 5367917182..1c291cc954 100644 --- a/include/hw/southbridge/piix.h +++ b/include/hw/southbridge/piix.h @@ -14,6 +14,7 @@ #include "hw/pci/pci.h" #include "qom/object.h" +#include "hw/acpi/piix4.h" #include "hw/rtc/mc146818rtc.h" #include "hw/usb/hcd-uhci.h" @@ -56,6 +57,9 @@ struct PIIXState { RTCState rtc; UHCIState uhci; + PIIX4PMState pm; + + uint32_t smb_io_base; /* Reset Control Register contents */ uint8_t rcr; @@ -63,7 +67,9 @@ struct PIIXState { /* IO memory region for Reset Control Register (PIIX_RCR_IOPORT) */ MemoryRegion rcr_mem; + bool has_acpi; bool has_usb; + bool smm_enabled; }; typedef struct PIIXState PIIX3State; From patchwork Sat Oct 22 15:04:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 13016509 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 30A53C3A59D for ; Mon, 24 Oct 2022 03:04:36 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1omh4a-0004bK-9w for qemu-devel@archiver.kernel.org; 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[77.191.171.138]) by smtp.gmail.com with ESMTPSA id 4-20020a170906310400b00780ab5a9116sm13021558ejx.211.2022.10.22.08.06.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 22 Oct 2022 08:06:26 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Eduardo Habkost , =?utf-8?q?Herv=C3=A9_Poussineau?= , Aurelien Jarno , Igor Mammedov , Gerd Hoffmann , John Snow , Jiaxun Yang , Ani Sinha , Marcel Apfelbaum , qemu-block@nongnu.org, Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , "Michael S. Tsirkin" , Paolo Bonzini , Bernhard Beschow Subject: [PATCH v2 14/43] hw/intc/i8259: Introduce i8259 proxy "isa-pic" Date: Sat, 22 Oct 2022 17:04:39 +0200 Message-Id: <20221022150508.26830-15-shentey@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221022150508.26830-1-shentey@gmail.com> References: <20221022150508.26830-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::52d; envelope-from=shentey@gmail.com; helo=mail-ed1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Having an i8259 proxy allows for ISA PICs to be created and wired up in southbridges. This is especially interesting for PIIX3 for two reasons: First, the southbridge doesn't need to care about the virtualization technology used (KVM, TCG, Xen) due to in-IRQs (where devices get attached) and out-IRQs (which will trigger the IRQs of the respective virtzalization technology) are separated. Second, since the in-IRQs are populated with fully initialized qemu_irq's, they can already be wired up inside PIIX3. Signed-off-by: Bernhard Beschow --- hw/intc/i8259.c | 27 +++++++++++++++++++++++++++ include/hw/intc/i8259.h | 14 ++++++++++++++ 2 files changed, 41 insertions(+) diff --git a/hw/intc/i8259.c b/hw/intc/i8259.c index cc4e21ffec..531f6cca53 100644 --- a/hw/intc/i8259.c +++ b/hw/intc/i8259.c @@ -458,9 +458,36 @@ static const TypeInfo i8259_info = { .class_size = sizeof(PICClass), }; +static void isapic_set_irq(void *opaque, int irq, int level) +{ + ISAPICState *s = opaque; + + qemu_set_irq(s->out_irqs[irq], level); +} + +static void isapic_init(Object *obj) +{ + ISAPICState *s = ISA_PIC(obj); + + qdev_init_gpio_in(DEVICE(s), isapic_set_irq, ISA_NUM_IRQS); + qdev_init_gpio_out(DEVICE(s), s->out_irqs, ISA_NUM_IRQS); + + for (int i = 0; i < ISA_NUM_IRQS; ++i) { + s->in_irqs[i] = qdev_get_gpio_in(DEVICE(s), i); + } +} + +static const TypeInfo isapic_info = { + .name = TYPE_ISA_PIC, + .parent = TYPE_ISA_DEVICE, + .instance_size = sizeof(ISAPICState), + .instance_init = isapic_init, +}; + static void pic_register_types(void) { type_register_static(&i8259_info); + type_register_static(&isapic_info); } type_init(pic_register_types) diff --git a/include/hw/intc/i8259.h b/include/hw/intc/i8259.h index e2b1e8c59a..0246ab6ac6 100644 --- a/include/hw/intc/i8259.h +++ b/include/hw/intc/i8259.h @@ -1,6 +1,20 @@ #ifndef HW_I8259_H #define HW_I8259_H +#include "qom/object.h" +#include "hw/isa/isa.h" +#include "qemu/typedefs.h" + +#define TYPE_ISA_PIC "isa-pic" +OBJECT_DECLARE_SIMPLE_TYPE(ISAPICState, ISA_PIC) + +struct ISAPICState { + ISADevice parent_obj; + + qemu_irq in_irqs[ISA_NUM_IRQS]; + qemu_irq out_irqs[ISA_NUM_IRQS]; +}; + /* i8259.c */ extern DeviceState *isa_pic; From patchwork Sat Oct 22 15:04:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 13016427 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7E4E6C3A59D for ; Sun, 23 Oct 2022 20:23:35 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1omh6J-0004rd-P6 for qemu-devel@archiver.kernel.org; Sun, 23 Oct 2022 15:57:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1omG54-0007Ai-8Y; Sat, 22 Oct 2022 11:06:34 -0400 Received: from mail-ed1-x534.google.com ([2a00:1450:4864:20::534]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1omG52-00023s-Kc; Sat, 22 Oct 2022 11:06:34 -0400 Received: by mail-ed1-x534.google.com with SMTP id m16so16002005edc.4; Sat, 22 Oct 2022 08:06:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=G1vCU5NYptRGXLYMrv5TX0E2WjykERp7exAmrNpAikI=; b=XS1v+xktbbevQh/REAEW4SyDvQdqrY8JpuyysKzJGHfDrN1CZmGlSx01HYevxUCleq bv8L0oYVJGfA7PqKUCiM+agPdggSdMfZ9ygZGLMXm6ds3C/YN3wI2BPi9JPMYgCg1sHc vQdSKJdIXfSYsw/E1TFKmMXu56Joh/sjRbXYQfzTDF6g2QcZWTLXVUNCBHQR2w2w7hex 2gotCbKBGXL4+xZR+pbZpf15Rvpo7gAj7URtLn9Or9bjWuy3jTrvtVmcArKPg0iXPBnG gb+Dapy7yOKh7esuhl2BcsXXOb6in223k8PikajUqdT4z8uk8Nq6mHOQvBAVA72CGWmu 5ahg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=G1vCU5NYptRGXLYMrv5TX0E2WjykERp7exAmrNpAikI=; b=ddUk4UirEjqkuc9+zpxODaiZC9+5nJ87jk3hsRIBf8smqolVKhhbSeWtw6/+3tey/f 3HlKVz3l+6XC43gCIIX1gNU7N306mScwbAjTALgJwOAkyiMr96nC47xFiHS6qXgZPH3m Sz9NIHul2j1drXWF+lwlmd5Xczrfj+YFzpR+S4qG+gHQ44f4fCjonjfCBQLUibtHjSl2 zRh9ED5rmxNr0FfUD9agRq9OZ7bVJtHBXrunOB1trEfnrDE5DNf+cIAYGBinJPE+K3Ss nEH2zoN1ZNHZpPT7+BWbx0BCxh86NvV439YIq8Aj23sDDj+1QSPmrLdb4hH1w4vwipUI hJVg== X-Gm-Message-State: ACrzQf3IG1/V15FvbMbm1i5zJHCxnIMvoDQA0bbdXyrnBVhAHxxTjXFS +g8jLQ2F23ajZb9or2+VUT0KWiKcO8HbDg== X-Google-Smtp-Source: AMsMyM5UfyOw1iFkOwiq6Skq7zN0yDt3u/sHNc6WIqLsrRTt+/TC+TtJvlAjIBCIgsY3m2fegWzJXQ== X-Received: by 2002:a17:906:58c9:b0:78d:b042:eecc with SMTP id e9-20020a17090658c900b0078db042eeccmr20508267ejs.658.1666451191256; Sat, 22 Oct 2022 08:06:31 -0700 (PDT) Received: from localhost.localdomain (dynamic-077-191-171-138.77.191.pool.telefonica.de. [77.191.171.138]) by smtp.gmail.com with ESMTPSA id 4-20020a170906310400b00780ab5a9116sm13021558ejx.211.2022.10.22.08.06.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 22 Oct 2022 08:06:29 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Eduardo Habkost , =?utf-8?q?Herv=C3=A9_Poussineau?= , Aurelien Jarno , Igor Mammedov , Gerd Hoffmann , John Snow , Jiaxun Yang , Ani Sinha , Marcel Apfelbaum , qemu-block@nongnu.org, Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , "Michael S. Tsirkin" , Paolo Bonzini , Bernhard Beschow Subject: [PATCH v2 15/43] hw/isa/piix3: Create ISA PIC in host device Date: Sat, 22 Oct 2022 17:04:40 +0200 Message-Id: <20221022150508.26830-16-shentey@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221022150508.26830-1-shentey@gmail.com> References: <20221022150508.26830-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::534; envelope-from=shentey@gmail.com; helo=mail-ed1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Use the newly introduced i8259 proxy "isa-pic" which allows for wiring up devices in the southbridge where the virtualization technology used (KVM, TCG, Xen) is not yet known. Signed-off-by: Bernhard Beschow --- hw/i386/pc_piix.c | 15 +++++++++------ hw/isa/Kconfig | 1 + hw/isa/piix3.c | 10 +++++++++- include/hw/southbridge/piix.h | 4 ++-- 4 files changed, 21 insertions(+), 9 deletions(-) diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index c96d989636..f81e91220f 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -207,10 +207,11 @@ static void pc_init1(MachineState *machine, gsi_state = pc_gsi_create(&x86ms->gsi, pcmc->pci_enabled); if (pcmc->pci_enabled) { - PIIX3State *piix3; + DeviceState *dev; PCIDevice *pci_dev; const char *type = xen_enabled() ? TYPE_PIIX3_XEN_DEVICE : TYPE_PIIX3_DEVICE; + int i; pci_bus = i440fx_init(pci_type, i440fx_host, @@ -231,10 +232,12 @@ static void pc_init1(MachineState *machine, x86_machine_is_smm_enabled(x86ms), &error_abort); pci_realize_and_unref(pci_dev, pci_bus, &error_fatal); - piix3 = PIIX3_PCI_DEVICE(pci_dev); - piix3->pic = x86ms->gsi; - piix3_devfn = piix3->dev.devfn; - isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0")); + dev = DEVICE(object_resolve_path_component(OBJECT(pci_dev), "pic")); + for (i = 0; i < ISA_NUM_IRQS; i++) { + qdev_connect_gpio_out(dev, i, x86ms->gsi[i]); + } + piix3_devfn = pci_dev->devfn; + isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(pci_dev), "isa.0")); rtc_state = ISA_DEVICE(object_resolve_path_component(OBJECT(pci_dev), "rtc")); piix4_pm = object_resolve_path_component(OBJECT(pci_dev), "pm"); @@ -243,6 +246,7 @@ static void pc_init1(MachineState *machine, piix4_pm = NULL; isa_bus = isa_bus_new(NULL, get_system_memory(), system_io, &error_abort); + isa_bus_irqs(isa_bus, x86ms->gsi); rtc_state = isa_new(TYPE_MC146818_RTC); qdev_prop_set_int32(DEVICE(rtc_state), "base_year", 2000); @@ -251,7 +255,6 @@ static void pc_init1(MachineState *machine, i8257_dma_init(isa_bus, 0); pcms->hpet_enabled = false; } - isa_bus_irqs(isa_bus, x86ms->gsi); if (x86ms->pic == ON_OFF_AUTO_ON || x86ms->pic == ON_OFF_AUTO_AUTO) { pc_i8259_create(isa_bus, gsi_state->i8259_irq); diff --git a/hw/isa/Kconfig b/hw/isa/Kconfig index f10daa26bc..24e79a9a41 100644 --- a/hw/isa/Kconfig +++ b/hw/isa/Kconfig @@ -35,6 +35,7 @@ config PIIX3 bool select ACPI_PIIX4 select I8257 + select I8259 select ISA_BUS select MC146818RTC select USB_UHCI diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c index a4b8ebd5f5..ce3ec84e22 100644 --- a/hw/isa/piix3.c +++ b/hw/isa/piix3.c @@ -40,7 +40,7 @@ static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq) { - qemu_set_irq(piix3->pic[pic_irq], + qemu_set_irq(piix3->pic.in_irqs[pic_irq], !!(piix3->pic_levels & (((1ULL << PIIX_NUM_PIRQS) - 1) << (pic_irq * PIIX_NUM_PIRQS)))); @@ -309,6 +309,13 @@ static void pci_piix3_realize(PCIDevice *dev, Error **errp) return; } + /* PIC */ + if (!qdev_realize(DEVICE(&d->pic), BUS(isa_bus), errp)) { + return; + } + + isa_bus_irqs(isa_bus, d->pic.in_irqs); + memory_region_init_io(&d->rcr_mem, OBJECT(dev), &rcr_ops, d, "piix3-reset-control", 1); memory_region_add_subregion_overlap(pci_address_space_io(dev), @@ -361,6 +368,7 @@ static void pci_piix3_init(Object *obj) { PIIX3State *d = PIIX3_PCI_DEVICE(obj); + object_initialize_child(obj, "pic", &d->pic, TYPE_ISA_PIC); object_initialize_child(obj, "rtc", &d->rtc, TYPE_MC146818_RTC); } diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h index 1c291cc954..7178147b75 100644 --- a/include/hw/southbridge/piix.h +++ b/include/hw/southbridge/piix.h @@ -15,6 +15,7 @@ #include "hw/pci/pci.h" #include "qom/object.h" #include "hw/acpi/piix4.h" +#include "hw/intc/i8259.h" #include "hw/rtc/mc146818rtc.h" #include "hw/usb/hcd-uhci.h" @@ -50,11 +51,10 @@ struct PIIXState { #endif uint64_t pic_levels; - qemu_irq *pic; - /* This member isn't used. Just for save/load compatibility */ int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS]; + ISAPICState pic; RTCState rtc; UHCIState uhci; PIIX4PMState pm; From patchwork Sat Oct 22 15:04:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 13016588 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 22FEAC3A59D for ; Mon, 24 Oct 2022 04:04:40 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1omh92-0005Bj-4Z for qemu-devel@archiver.kernel.org; Sun, 23 Oct 2022 16:00:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1omG57-0007Bg-Hh; Sat, 22 Oct 2022 11:06:37 -0400 Received: from mail-ed1-x52e.google.com ([2a00:1450:4864:20::52e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1omG55-0002Cw-OD; Sat, 22 Oct 2022 11:06:37 -0400 Received: by mail-ed1-x52e.google.com with SMTP id a5so3028387edb.11; Sat, 22 Oct 2022 08:06:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=kYVfy9y1+h6JyR2m6Er7WWMrinNKJlNZKF1s+lQY25M=; b=ClnOJpQw7uNuC+2TT9kBGMM1m3ik+K5Zq+UC5U8/YjEGmEce+qQWOQ7iWXf27N6pum 3Hjs7oFNTycqOg9Vxct8eKhGBhEA+w+7uIdMDAzNIzbEuVo5zr19GHJSWUPvcQH667so Yz/f0rXVUsItXd5XSRVwcPztkGNGQrWjBaLEacwkyo5Kg6FVHUPkUcIWbhCTFjrvT9vz gA+UtRa+0Sgq+WQNQE2rZ0j/Ap5z9owksCRm3LCYWr4R7g8x+mK6xpJFk+gd9RqOswFT +fxBm8wMeFQnjOAsXixFY+r2GYFfkvUp0gtv9nAEgJ18W+vPsFTUzjClUuMQ5Tp1hfQh G0JQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kYVfy9y1+h6JyR2m6Er7WWMrinNKJlNZKF1s+lQY25M=; b=sg/QcWnp8mSCOhF2uxFAhajyFe48pRM3tGZEkKFQUGrLEkDw2aZ8OyPq/p9vL13Cb4 cu7x5qwQBeHxhhqKFHxjTY+hELjLjeZfHuhIdkKOMljjEgtWHnJJIkaghAiZYyEZ7crB GM9+SJDKBBP3w7lo1LvZuNsB/xfbE5R2iuuW5Hn/1cFlJt+5jioxd/+GvDd/Vs43vz8H 6vLnPk1mZF1mw8RDN+O3lv6ugrUSdXuW0m04RCX7YC7K85AXrT6kQUUCuymxR75ux0pX 7jsF8o5WBdTRgkvuxIxjBWl/0yHJcDT9nB+RPQNijBgRE1jwHXbnZxDvDnsoq9DQYpyk FhuQ== X-Gm-Message-State: ACrzQf2F5hDS/Ct6jpwFQpACgT0rLR3m1rAzMUEesd8rtFYxkVauBWEd rGcz4FR5/vIufdXDh1c4ZUJPP2l9yUARhg== X-Google-Smtp-Source: AMsMyM4GLIe5MzCDWztZIYY35QhbzFNIuMQXqOOjoRfXcpbZ5OnDYfitxLO01rfe6g+X6fqc/C4ZGw== X-Received: by 2002:a17:907:7215:b0:791:a61f:56b3 with SMTP id dr21-20020a170907721500b00791a61f56b3mr17409950ejc.331.1666451193453; Sat, 22 Oct 2022 08:06:33 -0700 (PDT) Received: from localhost.localdomain (dynamic-077-191-171-138.77.191.pool.telefonica.de. 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Tsirkin" , Paolo Bonzini , Bernhard Beschow Subject: [PATCH v2 16/43] hw/isa/piix3: Create IDE controller in host device Date: Sat, 22 Oct 2022 17:04:41 +0200 Message-Id: <20221022150508.26830-17-shentey@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221022150508.26830-1-shentey@gmail.com> References: <20221022150508.26830-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::52e; envelope-from=shentey@gmail.com; helo=mail-ed1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Now that PIIX3 contains the new isa-pic, it is possible to instantiate PIIX3 IDE in the PIIX3 southbridge. PIIX3 IDE wires up its interrupts to the ISA bus in its realize method which requires the interrupt controller to provide fully populated qemu_irqs. This is the case for isa-pic even though the virtualization technology not known yet. Signed-off-by: Bernhard Beschow --- hw/i386/Kconfig | 1 - hw/i386/pc_piix.c | 15 ++++++--------- hw/isa/Kconfig | 1 + hw/isa/piix3.c | 8 ++++++++ include/hw/southbridge/piix.h | 2 ++ 5 files changed, 17 insertions(+), 10 deletions(-) diff --git a/hw/i386/Kconfig b/hw/i386/Kconfig index d22ac4a4b9..dd247f215c 100644 --- a/hw/i386/Kconfig +++ b/hw/i386/Kconfig @@ -74,7 +74,6 @@ config I440FX select ACPI_SMBUS select PCI_I440FX select PIIX3 - select IDE_PIIX select DIMM select SMBIOS select FW_CFG_DMA diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index f81e91220f..19fe07a13b 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -41,7 +41,6 @@ #include "hw/usb.h" #include "net/net.h" #include "hw/ide/pci.h" -#include "hw/ide/piix.h" #include "hw/irq.h" #include "sysemu/kvm.h" #include "hw/kvm/clock.h" @@ -86,7 +85,6 @@ static void pc_init1(MachineState *machine, PCIBus *pci_bus; ISABus *isa_bus; Object *piix4_pm; - int piix3_devfn = -1; qemu_irq smi_irq; GSIState *gsi_state; BusState *idebus[MAX_IDE_BUS]; @@ -236,11 +234,14 @@ static void pc_init1(MachineState *machine, for (i = 0; i < ISA_NUM_IRQS; i++) { qdev_connect_gpio_out(dev, i, x86ms->gsi[i]); } - piix3_devfn = pci_dev->devfn; isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(pci_dev), "isa.0")); rtc_state = ISA_DEVICE(object_resolve_path_component(OBJECT(pci_dev), "rtc")); piix4_pm = object_resolve_path_component(OBJECT(pci_dev), "pm"); + dev = DEVICE(object_resolve_path_component(OBJECT(pci_dev), "ide")); + pci_ide_create_devs(PCI_DEVICE(dev)); + idebus[0] = qdev_get_child_bus(dev, "ide.0"); + idebus[1] = qdev_get_child_bus(dev, "ide.1"); } else { pci_bus = NULL; piix4_pm = NULL; @@ -254,6 +255,8 @@ static void pc_init1(MachineState *machine, i8257_dma_init(isa_bus, 0); pcms->hpet_enabled = false; + idebus[0] = NULL; + idebus[1] = NULL; } if (x86ms->pic == ON_OFF_AUTO_ON || x86ms->pic == ON_OFF_AUTO_AUTO) { @@ -282,12 +285,6 @@ static void pc_init1(MachineState *machine, pc_nic_init(pcmc, isa_bus, pci_bus); if (pcmc->pci_enabled) { - PCIDevice *dev; - - dev = pci_create_simple(pci_bus, piix3_devfn + 1, TYPE_PIIX3_IDE); - pci_ide_create_devs(dev); - idebus[0] = qdev_get_child_bus(&dev->qdev, "ide.0"); - idebus[1] = qdev_get_child_bus(&dev->qdev, "ide.1"); pc_cmos_init(pcms, idebus[0], idebus[1], rtc_state); } #ifdef CONFIG_IDE_ISA diff --git a/hw/isa/Kconfig b/hw/isa/Kconfig index 24e79a9a41..a021e1cbfc 100644 --- a/hw/isa/Kconfig +++ b/hw/isa/Kconfig @@ -36,6 +36,7 @@ config PIIX3 select ACPI_PIIX4 select I8257 select I8259 + select IDE_PIIX select ISA_BUS select MC146818RTC select USB_UHCI diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c index ce3ec84e22..bbd1dfc373 100644 --- a/hw/isa/piix3.c +++ b/hw/isa/piix3.c @@ -29,6 +29,7 @@ #include "hw/southbridge/piix.h" #include "hw/irq.h" #include "hw/qdev-properties.h" +#include "hw/ide/piix.h" #include "hw/isa/isa.h" #include "hw/xen/xen.h" #include "sysemu/xen.h" @@ -329,6 +330,12 @@ static void pci_piix3_realize(PCIDevice *dev, Error **errp) return; } + /* IDE */ + qdev_prop_set_int32(DEVICE(&d->ide), "addr", dev->devfn + 1); + if (!qdev_realize(DEVICE(&d->ide), BUS(pci_bus), errp)) { + return; + } + /* USB */ if (d->has_usb) { object_initialize_child(OBJECT(dev), "uhci", &d->uhci, @@ -370,6 +377,7 @@ static void pci_piix3_init(Object *obj) object_initialize_child(obj, "pic", &d->pic, TYPE_ISA_PIC); object_initialize_child(obj, "rtc", &d->rtc, TYPE_MC146818_RTC); + object_initialize_child(obj, "ide", &d->ide, TYPE_PIIX3_IDE); } static Property pci_piix3_props[] = { diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h index 7178147b75..1f22eb1444 100644 --- a/include/hw/southbridge/piix.h +++ b/include/hw/southbridge/piix.h @@ -15,6 +15,7 @@ #include "hw/pci/pci.h" #include "qom/object.h" #include "hw/acpi/piix4.h" +#include "hw/ide/pci.h" #include "hw/intc/i8259.h" #include "hw/rtc/mc146818rtc.h" #include "hw/usb/hcd-uhci.h" @@ -56,6 +57,7 @@ struct PIIXState { ISAPICState pic; RTCState rtc; + PCIIDEState ide; UHCIState uhci; PIIX4PMState pm; From patchwork Sat Oct 22 15:04:42 2022 Content-Type: text/plain; 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Tsirkin" , Paolo Bonzini , Bernhard Beschow Subject: [PATCH v2 17/43] hw/isa/piix3: Wire up ACPI interrupt internally Date: Sat, 22 Oct 2022 17:04:42 +0200 Message-Id: <20221022150508.26830-18-shentey@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221022150508.26830-1-shentey@gmail.com> References: <20221022150508.26830-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::52d; envelope-from=shentey@gmail.com; helo=mail-ed1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Now that PIIX3 has the PIC integrated, the ACPI controller can be wired up internally. Signed-off-by: Bernhard Beschow --- hw/i386/pc_piix.c | 1 - hw/isa/piix3.c | 2 ++ 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 19fe07a13b..dd4e89acf9 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -313,7 +313,6 @@ static void pc_init1(MachineState *machine, if (piix4_pm) { smi_irq = qemu_allocate_irq(pc_acpi_smi_interrupt, first_cpu, 0); - qdev_connect_gpio_out(DEVICE(piix4_pm), 0, x86ms->gsi[9]); qdev_connect_gpio_out_named(DEVICE(piix4_pm), "smi-irq", 0, smi_irq); pcms->smbus = I2C_BUS(qdev_get_child_bus(DEVICE(piix4_pm), "i2c")); /* TODO: Populate SPD eeprom data. */ diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c index bbd1dfc373..59599558a1 100644 --- a/hw/isa/piix3.c +++ b/hw/isa/piix3.c @@ -355,6 +355,8 @@ static void pci_piix3_realize(PCIDevice *dev, Error **errp) if (!qdev_realize(DEVICE(&d->pm), BUS(pci_bus), errp)) { return; } + qdev_connect_gpio_out(DEVICE(&d->pm), 0, + qdev_get_gpio_in(DEVICE(&d->pic), 9)); } } From patchwork Sat Oct 22 15:04:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 13016594 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4B376C38A2D for ; Mon, 24 Oct 2022 04:26:07 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1omhDu-0005pX-2a for qemu-devel@archiver.kernel.org; Sun, 23 Oct 2022 16:05:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1omG5A-0007Cv-DV; Sat, 22 Oct 2022 11:06:40 -0400 Received: from mail-ed1-x52e.google.com ([2a00:1450:4864:20::52e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1omG59-0002Cw-39; Sat, 22 Oct 2022 11:06:40 -0400 Received: by mail-ed1-x52e.google.com with SMTP id a5so3028811edb.11; Sat, 22 Oct 2022 08:06:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=yeRNXzVfr9gpAq+8v0gKJ81J3Pkz4jG0UR9VroPG7bk=; b=Lfse1QdzmEPqxWI3fbhTVUXaeXiYe/KqYZcN8/nnu6z+9+AKScHixih22nBaUasKn/ yIRY/u/KWil/g92JmXEgFrE23Xt+XJp0GZBjrunuwgzGYJa7lN8p+6XZQ+O7hfX3Rdon qG6Q/flxGc63MyEpSm41CCmSQA9lVHWP8BTKm0WRfWAjrN0FLXq/kxMxyLw+8Kt0fK/G 3GRdPK0TzZfZlGuISpAgXBXaWQaTGwqgZ/hmQVI9fX2ZTNH3HBYp7t1dfGG5YBgPvMgA xIqTUnr69fBaVV9KXuHnIeKIE6Qx4oP5o99QeQUUfIqfMsQq89vpbS1B4gSqLBY6S2zJ 3fEw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yeRNXzVfr9gpAq+8v0gKJ81J3Pkz4jG0UR9VroPG7bk=; b=dqMGuht7PEjpCHQvQnTcGOwjma47m+6CHD9TzP1cFjLUW+8Zq+iKRUttTsEz7Nxvw8 tSmiNOJ+McsVxEWNBgP2b0wnIVcyCBv/ZdICAZXkxYoiMEVOzQOnOPWIt33NxZzErhul 8VBck5n6uXV7Wx95bNr1mKCl74WnnmJ7C0z1j+ONGSiCgciv49xdE3TNu64ZgPfw88rl +aFZAFKsGYt1sQ6Fr+EiQ6zS/kFa7jfghpYOXo5acXMlcas2qw0odnz6phDf1B6Or726 Bm3GffU+hbYX/7FTgOv6+P9XvqlhOd7okmeKbMDbe0nqzI1k8taiEo/018rYUByS1479 OdKA== X-Gm-Message-State: ACrzQf2mfOWHJydHJxD+honykkeoFUt3qW0kjRGrA64cd9wuOJPcRZxD uFWyQWpgXKR5X7YnjF+WPJOBnU38q1zTAQ== X-Google-Smtp-Source: AMsMyM51PWFLcTgw/WgauwBwiTH9IlfkuWH7/nU1OPgBqYeys2wPYLQfGssLE7w0WXi5T3LCiwgzKA== X-Received: by 2002:a17:907:708:b0:77e:ff47:34b1 with SMTP id xb8-20020a170907070800b0077eff4734b1mr19316150ejb.493.1666451197840; Sat, 22 Oct 2022 08:06:37 -0700 (PDT) Received: from localhost.localdomain (dynamic-077-191-171-138.77.191.pool.telefonica.de. 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Tsirkin" , Paolo Bonzini , Bernhard Beschow Subject: [PATCH v2 18/43] hw/isa/piix3: Remove unused include Date: Sat, 22 Oct 2022 17:04:43 +0200 Message-Id: <20221022150508.26830-19-shentey@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221022150508.26830-1-shentey@gmail.com> References: <20221022150508.26830-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::52e; envelope-from=shentey@gmail.com; helo=mail-ed1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Ammends commit 988fb613215993dd0ce642b89ca8182c479d39dd. Signed-off-by: Bernhard Beschow --- hw/isa/piix3.c | 1 - 1 file changed, 1 deletion(-) diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c index 59599558a1..aa32f43e4a 100644 --- a/hw/isa/piix3.c +++ b/hw/isa/piix3.c @@ -32,7 +32,6 @@ #include "hw/ide/piix.h" #include "hw/isa/isa.h" #include "hw/xen/xen.h" -#include "sysemu/xen.h" #include "sysemu/runstate.h" #include "migration/vmstate.h" #include "hw/acpi/acpi_aml_interface.h" From patchwork Sat Oct 22 15:04:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 13016722 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 12FCAC38A2D for ; Mon, 24 Oct 2022 06:23:06 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1omhFZ-000669-Ds for qemu-devel@archiver.kernel.org; Sun, 23 Oct 2022 16:07:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1omG5D-0007DY-7P; Sat, 22 Oct 2022 11:06:43 -0400 Received: from mail-ed1-x52e.google.com ([2a00:1450:4864:20::52e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1omG5B-0002Cw-KY; Sat, 22 Oct 2022 11:06:43 -0400 Received: by mail-ed1-x52e.google.com with SMTP id a5so3029074edb.11; Sat, 22 Oct 2022 08:06:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=aPF9+HfmXGc/QS2MxhD55Mybo4zeq8/bfRvcchWncns=; b=I8OJ82nIGVhQNSgYz7xcBYcTBFq5IXI2DGCE3WEJX+AHYH4rUpLC1Is8PGpe9RK5ao irSjm3rBzz393bC/BRiGMpUZ82Zita6oGCF0CpZVjw8qTsyhLzVfHK7yb68+Ai745JGZ Gcgrh5tlAN0Tj3u5qRnuABpatvehjEOf6i3jG/AuEvBV+g/Ltq+iGTjIpzbsodajZVLn TuPZcctRUUXDZEhTwo6L7QoogZIj2qB6vfulmx40jjROKL4eT696NHI6ybgqYDL+j8sO e54tYRdarFsZRhu2IE5pwP+pU3eH02y3wgJfUVZybk7G5oSQNoxGJJVHeUhPYcQOjjAP ITwg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=aPF9+HfmXGc/QS2MxhD55Mybo4zeq8/bfRvcchWncns=; b=CQvf0XQ5lLSXrLaqcw5jTiRsXItVv5LB+EFjrWfEV36yDZ8Vjv3MBBcvP9fEf48xOe zVg9qakRj4A/W8yO+mnfiARv4ZRao+65+quaIke3NZW2y6RC8psxseC2P3Gis0h4kzmJ L07vjjHCFEInVlLSFCk8Y4Bh6LZfZhIusb1Sax10xppw+/zWO8zkitQ2HFoh7d4Vk2oa OS4FAGQJN49Vk6HicMWwb0xJqjoGHeQ3YxPsyYZNelqsTS5WR5BfLj600C43ttXO92kU H+xL8rP2u9ndBD5jhz/CXK3llzeN0sYqy37gjSBxA3yDlRIcxbKVni0JcaqY+QOMyqaf /0Fw== X-Gm-Message-State: ACrzQf3KTxbpfuba8/zVlCMJitMen/kilAlEl3qks2Gwqh0wOmCIw3r6 ZAMI21mxlELibvyoaPptvcMJaUy1SSfD8w== X-Google-Smtp-Source: AMsMyM41h1cDcBqTFIcHfWvZlyR+i+uyqV2T/jhcre+zeVZhQcf7YEC7XOJ1dUk/N9D9s4onR5MtMQ== X-Received: by 2002:a05:6402:3887:b0:458:289e:c9cc with SMTP id fd7-20020a056402388700b00458289ec9ccmr22456316edb.101.1666451200351; Sat, 22 Oct 2022 08:06:40 -0700 (PDT) Received: from localhost.localdomain (dynamic-077-191-171-138.77.191.pool.telefonica.de. [77.191.171.138]) by smtp.gmail.com with ESMTPSA id 4-20020a170906310400b00780ab5a9116sm13021558ejx.211.2022.10.22.08.06.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 22 Oct 2022 08:06:39 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Eduardo Habkost , =?utf-8?q?Herv=C3=A9_Poussineau?= , Aurelien Jarno , Igor Mammedov , Gerd Hoffmann , John Snow , Jiaxun Yang , Ani Sinha , Marcel Apfelbaum , qemu-block@nongnu.org, Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , "Michael S. Tsirkin" , Paolo Bonzini , Bernhard Beschow Subject: [PATCH v2 19/43] hw/isa/piix3: Allow board to provide PCI interrupt routes Date: Sat, 22 Oct 2022 17:04:44 +0200 Message-Id: <20221022150508.26830-20-shentey@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221022150508.26830-1-shentey@gmail.com> References: <20221022150508.26830-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::52e; envelope-from=shentey@gmail.com; helo=mail-ed1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" PIIX3 initializes the PIRQx route control registers to the default values as described in the 82371AB PCI-TO-ISA/IDE XCELERATOR (PIIX4) April 1997 manual. PIIX4, however, initializes the routes according to the Malta™ User’s Manual, ch 6.6, which are IRQs 10 and 11. In order to allow the reset methods to be consolidated, allow board code to specify the routes. Signed-off-by: Bernhard Beschow --- hw/isa/piix3.c | 12 ++++++++---- include/hw/southbridge/piix.h | 1 + 2 files changed, 9 insertions(+), 4 deletions(-) diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c index aa32f43e4a..c6a8f1f27d 100644 --- a/hw/isa/piix3.c +++ b/hw/isa/piix3.c @@ -168,10 +168,10 @@ static void piix3_reset(DeviceState *dev) pci_conf[0x4c] = 0x4d; pci_conf[0x4e] = 0x03; pci_conf[0x4f] = 0x00; - pci_conf[0x60] = 0x80; - pci_conf[0x61] = 0x80; - pci_conf[0x62] = 0x80; - pci_conf[0x63] = 0x80; + pci_conf[PIIX_PIRQCA] = d->pci_irq_reset_mappings[0]; + pci_conf[PIIX_PIRQCB] = d->pci_irq_reset_mappings[1]; + pci_conf[PIIX_PIRQCC] = d->pci_irq_reset_mappings[2]; + pci_conf[PIIX_PIRQCD] = d->pci_irq_reset_mappings[3]; pci_conf[0x69] = 0x02; pci_conf[0x70] = 0x80; pci_conf[0x76] = 0x0c; @@ -383,6 +383,10 @@ static void pci_piix3_init(Object *obj) static Property pci_piix3_props[] = { DEFINE_PROP_UINT32("smb_io_base", PIIX3State, smb_io_base, 0), + DEFINE_PROP_UINT8("pirqa", PIIX3State, pci_irq_reset_mappings[0], 0x80), + DEFINE_PROP_UINT8("pirqb", PIIX3State, pci_irq_reset_mappings[1], 0x80), + DEFINE_PROP_UINT8("pirqc", PIIX3State, pci_irq_reset_mappings[2], 0x80), + DEFINE_PROP_UINT8("pirqd", PIIX3State, pci_irq_reset_mappings[3], 0x80), DEFINE_PROP_BOOL("has-acpi", PIIX3State, has_acpi, true), DEFINE_PROP_BOOL("has-usb", PIIX3State, has_usb, true), DEFINE_PROP_BOOL("smm-enabled", PIIX3State, smm_enabled, false), diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h index 1f22eb1444..df3e0084c5 100644 --- a/include/hw/southbridge/piix.h +++ b/include/hw/southbridge/piix.h @@ -54,6 +54,7 @@ struct PIIXState { /* This member isn't used. Just for save/load compatibility */ int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS]; + uint8_t pci_irq_reset_mappings[PIIX_NUM_PIRQS]; ISAPICState pic; RTCState rtc; From patchwork Sat Oct 22 15:04:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 13016461 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E151FC3A59D for ; Sun, 23 Oct 2022 22:12:29 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1omhHn-0006LC-N3 for qemu-devel@archiver.kernel.org; Sun, 23 Oct 2022 16:09:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1omG5G-0007EF-5W; Sat, 22 Oct 2022 11:06:46 -0400 Received: from mail-ed1-x535.google.com ([2a00:1450:4864:20::535]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1omG5E-0002Ex-J3; Sat, 22 Oct 2022 11:06:45 -0400 Received: by mail-ed1-x535.google.com with SMTP id l22so16106274edj.5; Sat, 22 Oct 2022 08:06:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ABmoX0NxCwxVmKp1ogPkbw+xGj88SbGX6PhBV12lAkI=; b=Hj1r6vCYrRgRLGftTqdV8mqQ5+d8m3zR+8PFc0unkbeARj7GhTp7bxv//2xmxKHLsA GpEO61Z8cDjv5a46yKiB/P4BgbS2QR+QJL3DFfEZ+sFlJjE8JQqjwmSqfPP04CcNSGwI AZUGYQ4CqiBAQG+64/8MM493yG/KkqDj81+oHrxht7qhwdwMrelWf45XZojnsV+IfnYm PVrNI4EOqVj+bzWtLwQNO2Zw00iCMvn+jOx2j0DJKOBahJVpQ4szAc6yzc9ErSd06FM1 mgYTGht9WsyuoQT1W16xPBUYOX5xFqPsB8I++C/bsDemLcq5M7OCWsH0kRqKGVF53g5P sJ5w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ABmoX0NxCwxVmKp1ogPkbw+xGj88SbGX6PhBV12lAkI=; b=NnTwLkuEto2XufcutwdkhBbPL3hf5J/bsaHS5CJ9j+9UjyUv6tsURm5Lrvbq3H6uKE Q63gZoEFht6LGTye2wkL2tLyk7Y8mwP0u15ig7YQtSH6uhwuLQVcVA65AzGycm8TCABg FrRHaNGvP3lx6WA3+o/rgTy4OmWjmkWc4P1qJ2r49nij8z+pTXUpaiH1ns94KGslk49e kDz/OqoasFKot66Tc0glvXP8W5UMut8DgMK97x3RsGOi8R5dgsPpqrxMuNkgGgvgDWez mK8z0zEhJwwLXqtoebCytU2KKYo5Vj3tvs3yS1LMLP2JzMljI0jccXlJ9BxZZafYVQ0U w4Cw== X-Gm-Message-State: ACrzQf1XX5/qBGExVhKMBHiSi8D5TySHXeHGeHJR9KamlaHkevox5UGr YA4SyZKuocfXd7/7An8w5+G0nAXqlcAGwg== X-Google-Smtp-Source: AMsMyM6I/XKIOIh/lSprscY5F8mcom6fQ6I5XDltI1DCG7/9Ox8WcrcgiMy6+xFvm1zhYTLIyYCvOA== X-Received: by 2002:a05:6402:144a:b0:461:8e34:d07b with SMTP id d10-20020a056402144a00b004618e34d07bmr1390756edx.426.1666451202464; Sat, 22 Oct 2022 08:06:42 -0700 (PDT) Received: from localhost.localdomain (dynamic-077-191-171-138.77.191.pool.telefonica.de. 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Tsirkin" , Paolo Bonzini , Bernhard Beschow Subject: [PATCH v2 20/43] hw/isa/piix3: Resolve redundant PIIX_NUM_PIC_IRQS Date: Sat, 22 Oct 2022 17:04:45 +0200 Message-Id: <20221022150508.26830-21-shentey@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221022150508.26830-1-shentey@gmail.com> References: <20221022150508.26830-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::535; envelope-from=shentey@gmail.com; helo=mail-ed1-x535.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" PIIX_NUM_PIC_IRQS is assumed to be the same as ISA_NUM_IRQS, otherwise inconsistencies can occur. Signed-off-by: Bernhard Beschow --- hw/isa/piix3.c | 8 ++++---- include/hw/southbridge/piix.h | 5 ++--- 2 files changed, 6 insertions(+), 7 deletions(-) diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c index c6a8f1f27d..9de7287589 100644 --- a/hw/isa/piix3.c +++ b/hw/isa/piix3.c @@ -52,7 +52,7 @@ static void piix3_set_irq_level_internal(PIIX3State *piix3, int pirq, int level) uint64_t mask; pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq]; - if (pic_irq >= PIIX_NUM_PIC_IRQS) { + if (pic_irq >= ISA_NUM_IRQS) { return; } @@ -66,7 +66,7 @@ static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level) int pic_irq; pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq]; - if (pic_irq >= PIIX_NUM_PIC_IRQS) { + if (pic_irq >= ISA_NUM_IRQS) { return; } @@ -98,7 +98,7 @@ static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin) int irq = piix3->dev.config[PIIX_PIRQCA + pin]; PCIINTxRoute route; - if (irq < PIIX_NUM_PIC_IRQS) { + if (irq < ISA_NUM_IRQS) { route.mode = PCI_INTX_ENABLED; route.irq = irq; } else { @@ -130,7 +130,7 @@ static void piix3_write_config(PCIDevice *dev, pci_bus_fire_intx_routing_notifier(pci_get_bus(&piix3->dev)); piix3_update_irq_levels(piix3); - for (pic_irq = 0; pic_irq < PIIX_NUM_PIC_IRQS; pic_irq++) { + for (pic_irq = 0; pic_irq < ISA_NUM_IRQS; pic_irq++) { piix3_set_irq_pic(piix3, pic_irq); } } diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h index df3e0084c5..ae3b49fe93 100644 --- a/include/hw/southbridge/piix.h +++ b/include/hw/southbridge/piix.h @@ -32,7 +32,6 @@ */ #define PIIX_RCR_IOPORT 0xcf9 -#define PIIX_NUM_PIC_IRQS 16 /* i8259 * 2 */ #define PIIX_NUM_PIRQS 4ULL /* PIRQ[A-D] */ struct PIIXState { @@ -44,10 +43,10 @@ struct PIIXState { * So one PIC level is tracked by PIIX_NUM_PIRQS bits. * * PIRQ is mapped to PIC pins, we track it by - * PIIX_NUM_PIRQS * PIIX_NUM_PIC_IRQS = 64 bits with + * PIIX_NUM_PIRQS * ISA_NUM_IRQS = 64 bits with * pic_irq * PIIX_NUM_PIRQS + pirq */ -#if PIIX_NUM_PIC_IRQS * PIIX_NUM_PIRQS > 64 +#if ISA_NUM_IRQS * PIIX_NUM_PIRQS > 64 #error "unable to encode pic state in 64bit in pic_levels." #endif uint64_t pic_levels; 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Tsirkin" , Paolo Bonzini , Bernhard Beschow Subject: [PATCH v2 21/43] hw/isa/piix3: Rename pci_piix3_props for sharing with PIIX4 Date: Sat, 22 Oct 2022 17:04:46 +0200 Message-Id: <20221022150508.26830-22-shentey@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221022150508.26830-1-shentey@gmail.com> References: <20221022150508.26830-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::536; envelope-from=shentey@gmail.com; helo=mail-ed1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Bernhard Beschow Reviewed-by: Philippe Mathieu-Daudé --- hw/isa/piix3.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c index 9de7287589..8dbf22eaab 100644 --- a/hw/isa/piix3.c +++ b/hw/isa/piix3.c @@ -381,7 +381,7 @@ static void pci_piix3_init(Object *obj) object_initialize_child(obj, "ide", &d->ide, TYPE_PIIX3_IDE); } -static Property pci_piix3_props[] = { +static Property pci_piix_props[] = { DEFINE_PROP_UINT32("smb_io_base", PIIX3State, smb_io_base, 0), DEFINE_PROP_UINT8("pirqa", PIIX3State, pci_irq_reset_mappings[0], 0x80), DEFINE_PROP_UINT8("pirqb", PIIX3State, pci_irq_reset_mappings[1], 0x80), @@ -412,7 +412,7 @@ static void pci_piix3_class_init(ObjectClass *klass, void *data) * pc_piix.c's pc_init1() */ dc->user_creatable = false; - device_class_set_props(dc, pci_piix3_props); + device_class_set_props(dc, pci_piix_props); adevc->build_dev_aml = build_pci_isa_aml; } From patchwork Sat Oct 22 15:04:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 13016513 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 856A0C3A59D for ; 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Tsirkin" , Paolo Bonzini , Bernhard Beschow Subject: [PATCH v2 22/43] hw/isa/piix3: Rename piix3_reset() for sharing with PIIX4 Date: Sat, 22 Oct 2022 17:04:47 +0200 Message-Id: <20221022150508.26830-23-shentey@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221022150508.26830-1-shentey@gmail.com> References: <20221022150508.26830-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::531; envelope-from=shentey@gmail.com; helo=mail-ed1-x531.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Bernhard Beschow Reviewed-by: Philippe Mathieu-Daudé --- hw/isa/piix3.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c index 8dbf22eaab..5214a75891 100644 --- a/hw/isa/piix3.c +++ b/hw/isa/piix3.c @@ -156,7 +156,7 @@ static void piix3_write_config_xen(PCIDevice *dev, piix3_write_config(dev, address, val, len); } -static void piix3_reset(DeviceState *dev) +static void piix_reset(DeviceState *dev) { PIIX3State *d = PIIX3_PCI_DEVICE(dev); uint8_t *pci_conf = d->dev.config; @@ -399,7 +399,7 @@ static void pci_piix3_class_init(ObjectClass *klass, void *data) PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); AcpiDevAmlIfClass *adevc = ACPI_DEV_AML_IF_CLASS(klass); - dc->reset = piix3_reset; + dc->reset = piix_reset; dc->desc = "ISA bridge"; dc->vmsd = &vmstate_piix3; dc->hotpluggable = false; From patchwork Sat Oct 22 15:04:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 13016583 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7578BC38A2D for ; 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Tsirkin" , Paolo Bonzini , Bernhard Beschow Subject: [PATCH v2 23/43] hw/isa/piix3: Prefix pci_slot_get_pirq() with "piix3_" Date: Sat, 22 Oct 2022 17:04:48 +0200 Message-Id: <20221022150508.26830-24-shentey@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221022150508.26830-1-shentey@gmail.com> References: <20221022150508.26830-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::535; envelope-from=shentey@gmail.com; helo=mail-ed1-x535.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" The additional prefix aligns the function name with both other piix3-internal functions as well as QEMU conventions. Furthermore, it will help to distinguish the function from its PIIX4 counterpart once merged. Signed-off-by: Bernhard Beschow Reviewed-by: Philippe Mathieu-Daudé --- hw/isa/piix3.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c index 5214a75891..8878d71465 100644 --- a/hw/isa/piix3.c +++ b/hw/isa/piix3.c @@ -85,7 +85,7 @@ static void piix3_set_irq(void *opaque, int pirq, int level) * Return the global irq number corresponding to a given device irq * pin. We could also use the bus number to have a more precise mapping. */ -static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx) +static int piix3_pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx) { int slot_addend; slot_addend = PCI_SLOT(pci_dev->devfn) - 1; @@ -441,7 +441,7 @@ static void piix3_realize(PCIDevice *dev, Error **errp) return; } - pci_bus_irqs(pci_bus, piix3_set_irq, pci_slot_get_pirq, + pci_bus_irqs(pci_bus, piix3_set_irq, piix3_pci_slot_get_pirq, piix3, PIIX_NUM_PIRQS); pci_bus_set_route_irq_fn(pci_bus, piix3_route_intx_pin_to_irq); } From patchwork Sat Oct 22 15:04:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 13016648 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5B08DC38A2D for ; Mon, 24 Oct 2022 05:04:14 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1omhMv-00079t-Se for qemu-devel@archiver.kernel.org; Sun, 23 Oct 2022 16:14:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1omG5Q-0007I0-07; Sat, 22 Oct 2022 11:06:56 -0400 Received: from mail-ed1-x52d.google.com ([2a00:1450:4864:20::52d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1omG5N-00026R-TY; Sat, 22 Oct 2022 11:06:55 -0400 Received: by mail-ed1-x52d.google.com with SMTP id u21so16102131edi.9; Sat, 22 Oct 2022 08:06:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Eo8tfp6teNlFVPHAvi7UB79RgFfoqZm7PsttG4dSiug=; b=A5a3t0ACSVRrpf+oOdle3XMh+rf972J336+6e3YreyflSIu1K/zz9VHA88p8SeFSwD CbDbEcnzhizwNspCOxOHaB+veY6uUdReraC1ga5Mq7GUfWfzAEqiIFyBejIs2qGZR7OV BZ2ZJ7AJFt3x29gJR2v05KzkUgkE0UHdCTZpIefl+PFcnotZQ1A4eXctL6iUJe8c32c1 LIpA4kTT/+8vybVJ5hqcdEmmcCR0GvqMthJ6+9SziogDZYpO/sjUmS4UiARupH+EhqsI Ce9rbhT+Ac6rTjSGzGiQBAcsNKoZI7ASwmG/SKDrYQe5NcJlAvySQlbBdbN7bM0G1jZN Wr1A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Eo8tfp6teNlFVPHAvi7UB79RgFfoqZm7PsttG4dSiug=; b=HER7ZIYhfJvyrrADbF0Tb/iOSFigDkNomsW2rDyNrrTrgxWKRcMrUuY8TrL9nzrzDP 9WytB5Ugu8zgkSdM8yDGDKO/fOsCbds58WTNj6+N/6rCyKxUXmu4lkWvmc2c+gff0WpL g06V8MCO1x7w3bBMml74PisN31QcgrO3PLiMBjaLY1aSg56ABOVooXGblc2poI2p3xqY YTRGe+xNhq44nkJcO97Wcm/hpT4kOINx/WDj6rIM4jiJiX2CflAjrqJRoZd+MLKkuC6i 2IgfeaoYe3f//9tvAFd66o3J2rOJC7vFVvv/xAvMssWRNM82cD8XAPhheo2mSMQBrNJ2 8xHw== X-Gm-Message-State: ACrzQf2jY6V+ZveYx9dLEmjOZ0mlAR2TEiZo3FHpJkt2MSrU42GycYpo 1nAFIA/uM8AgV3+2BNBkPa4um7AqhVZflg== X-Google-Smtp-Source: AMsMyM4ohhKba+8lyJP0XbB9LggIszqK5LMfLsLmxIS20kDy65UUa5tVJojcAul3IdzBpiqr/fh1qg== X-Received: by 2002:a17:906:30c5:b0:782:707:9e2d with SMTP id b5-20020a17090630c500b0078207079e2dmr19779033ejb.286.1666451212388; Sat, 22 Oct 2022 08:06:52 -0700 (PDT) Received: from localhost.localdomain (dynamic-077-191-171-138.77.191.pool.telefonica.de. [77.191.171.138]) by smtp.gmail.com with ESMTPSA id 4-20020a170906310400b00780ab5a9116sm13021558ejx.211.2022.10.22.08.06.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 22 Oct 2022 08:06:51 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Eduardo Habkost , =?utf-8?q?Herv=C3=A9_Poussineau?= , Aurelien Jarno , Igor Mammedov , Gerd Hoffmann , John Snow , Jiaxun Yang , Ani Sinha , Marcel Apfelbaum , qemu-block@nongnu.org, Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , "Michael S. Tsirkin" , Paolo Bonzini , Bernhard Beschow Subject: [PATCH v2 24/43] hw/isa/piix3: Rename typedef PIIX3State to PIIXState Date: Sat, 22 Oct 2022 17:04:49 +0200 Message-Id: <20221022150508.26830-25-shentey@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221022150508.26830-1-shentey@gmail.com> References: <20221022150508.26830-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::52d; envelope-from=shentey@gmail.com; helo=mail-ed1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" This commit marks the finalization of the PIIX3 preparations to be merged with PIIX4. In particular, PIIXState is prepared to be reused in piix4.c. Signed-off-by: Bernhard Beschow Reviewed-by: Philippe Mathieu-Daudé --- hw/isa/piix3.c | 58 +++++++++++++++++------------------ include/hw/southbridge/piix.h | 4 +-- 2 files changed, 31 insertions(+), 31 deletions(-) diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c index 8878d71465..b02a91c8eb 100644 --- a/hw/isa/piix3.c +++ b/hw/isa/piix3.c @@ -38,7 +38,7 @@ #define XEN_PIIX_NUM_PIRQS 128ULL -static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq) +static void piix3_set_irq_pic(PIIXState *piix3, int pic_irq) { qemu_set_irq(piix3->pic.in_irqs[pic_irq], !!(piix3->pic_levels & @@ -46,7 +46,7 @@ static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq) (pic_irq * PIIX_NUM_PIRQS)))); } -static void piix3_set_irq_level_internal(PIIX3State *piix3, int pirq, int level) +static void piix3_set_irq_level_internal(PIIXState *piix3, int pirq, int level) { int pic_irq; uint64_t mask; @@ -61,7 +61,7 @@ static void piix3_set_irq_level_internal(PIIX3State *piix3, int pirq, int level) piix3->pic_levels |= mask * !!level; } -static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level) +static void piix3_set_irq_level(PIIXState *piix3, int pirq, int level) { int pic_irq; @@ -77,7 +77,7 @@ static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level) static void piix3_set_irq(void *opaque, int pirq, int level) { - PIIX3State *piix3 = opaque; + PIIXState *piix3 = opaque; piix3_set_irq_level(piix3, pirq, level); } @@ -94,7 +94,7 @@ static int piix3_pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx) static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin) { - PIIX3State *piix3 = opaque; + PIIXState *piix3 = opaque; int irq = piix3->dev.config[PIIX_PIRQCA + pin]; PCIINTxRoute route; @@ -109,7 +109,7 @@ static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin) } /* irq routing is changed. so rebuild bitmap */ -static void piix3_update_irq_levels(PIIX3State *piix3) +static void piix3_update_irq_levels(PIIXState *piix3) { PCIBus *bus = pci_get_bus(&piix3->dev); int pirq; @@ -125,7 +125,7 @@ static void piix3_write_config(PCIDevice *dev, { pci_default_write_config(dev, address, val, len); if (ranges_overlap(address, len, PIIX_PIRQCA, 4)) { - PIIX3State *piix3 = PIIX3_PCI_DEVICE(dev); + PIIXState *piix3 = PIIX_PCI_DEVICE(dev); int pic_irq; pci_bus_fire_intx_routing_notifier(pci_get_bus(&piix3->dev)); @@ -158,7 +158,7 @@ static void piix3_write_config_xen(PCIDevice *dev, static void piix_reset(DeviceState *dev) { - PIIX3State *d = PIIX3_PCI_DEVICE(dev); + PIIXState *d = PIIX_PCI_DEVICE(dev); uint8_t *pci_conf = d->dev.config; pci_conf[0x04] = 0x07; /* master, memory and I/O */ @@ -199,7 +199,7 @@ static void piix_reset(DeviceState *dev) static int piix3_post_load(void *opaque, int version_id) { - PIIX3State *piix3 = opaque; + PIIXState *piix3 = opaque; int pirq; /* @@ -222,7 +222,7 @@ static int piix3_post_load(void *opaque, int version_id) static int piix3_pre_save(void *opaque) { int i; - PIIX3State *piix3 = opaque; + PIIXState *piix3 = opaque; for (i = 0; i < ARRAY_SIZE(piix3->pci_irq_levels_vmstate); i++) { piix3->pci_irq_levels_vmstate[i] = @@ -234,7 +234,7 @@ static int piix3_pre_save(void *opaque) static bool piix3_rcr_needed(void *opaque) { - PIIX3State *piix3 = opaque; + PIIXState *piix3 = opaque; return (piix3->rcr != 0); } @@ -245,7 +245,7 @@ static const VMStateDescription vmstate_piix3_rcr = { .minimum_version_id = 1, .needed = piix3_rcr_needed, .fields = (VMStateField[]) { - VMSTATE_UINT8(rcr, PIIX3State), + VMSTATE_UINT8(rcr, PIIXState), VMSTATE_END_OF_LIST() } }; @@ -257,8 +257,8 @@ static const VMStateDescription vmstate_piix3 = { .post_load = piix3_post_load, .pre_save = piix3_pre_save, .fields = (VMStateField[]) { - VMSTATE_PCI_DEVICE(dev, PIIX3State), - VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIX3State, + VMSTATE_PCI_DEVICE(dev, PIIXState), + VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIXState, PIIX_NUM_PIRQS, 3), VMSTATE_END_OF_LIST() }, @@ -271,7 +271,7 @@ static const VMStateDescription vmstate_piix3 = { static void rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned len) { - PIIX3State *d = opaque; + PIIXState *d = opaque; if (val & 4) { qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); @@ -282,7 +282,7 @@ static void rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned len) static uint64_t rcr_read(void *opaque, hwaddr addr, unsigned len) { - PIIX3State *d = opaque; + PIIXState *d = opaque; return d->rcr; } @@ -299,7 +299,7 @@ static const MemoryRegionOps rcr_ops = { static void pci_piix3_realize(PCIDevice *dev, Error **errp) { - PIIX3State *d = PIIX3_PCI_DEVICE(dev); + PIIXState *d = PIIX_PCI_DEVICE(dev); PCIBus *pci_bus = pci_get_bus(dev); ISABus *isa_bus; @@ -374,7 +374,7 @@ static void build_pci_isa_aml(AcpiDevAmlIf *adev, Aml *scope) static void pci_piix3_init(Object *obj) { - PIIX3State *d = PIIX3_PCI_DEVICE(obj); + PIIXState *d = PIIX_PCI_DEVICE(obj); object_initialize_child(obj, "pic", &d->pic, TYPE_ISA_PIC); object_initialize_child(obj, "rtc", &d->rtc, TYPE_MC146818_RTC); @@ -382,14 +382,14 @@ static void pci_piix3_init(Object *obj) } static Property pci_piix_props[] = { - DEFINE_PROP_UINT32("smb_io_base", PIIX3State, smb_io_base, 0), - DEFINE_PROP_UINT8("pirqa", PIIX3State, pci_irq_reset_mappings[0], 0x80), - DEFINE_PROP_UINT8("pirqb", PIIX3State, pci_irq_reset_mappings[1], 0x80), - DEFINE_PROP_UINT8("pirqc", PIIX3State, pci_irq_reset_mappings[2], 0x80), - DEFINE_PROP_UINT8("pirqd", PIIX3State, pci_irq_reset_mappings[3], 0x80), - DEFINE_PROP_BOOL("has-acpi", PIIX3State, has_acpi, true), - DEFINE_PROP_BOOL("has-usb", PIIX3State, has_usb, true), - DEFINE_PROP_BOOL("smm-enabled", PIIX3State, smm_enabled, false), + DEFINE_PROP_UINT32("smb_io_base", PIIXState, smb_io_base, 0), + DEFINE_PROP_UINT8("pirqa", PIIXState, pci_irq_reset_mappings[0], 0x80), + DEFINE_PROP_UINT8("pirqb", PIIXState, pci_irq_reset_mappings[1], 0x80), + DEFINE_PROP_UINT8("pirqc", PIIXState, pci_irq_reset_mappings[2], 0x80), + DEFINE_PROP_UINT8("pirqd", PIIXState, pci_irq_reset_mappings[3], 0x80), + DEFINE_PROP_BOOL("has-acpi", PIIXState, has_acpi, true), + DEFINE_PROP_BOOL("has-usb", PIIXState, has_usb, true), + DEFINE_PROP_BOOL("smm-enabled", PIIXState, smm_enabled, false), DEFINE_PROP_END_OF_LIST(), }; @@ -419,7 +419,7 @@ static void pci_piix3_class_init(ObjectClass *klass, void *data) static const TypeInfo piix3_pci_type_info = { .name = TYPE_PIIX3_PCI_DEVICE, .parent = TYPE_PCI_DEVICE, - .instance_size = sizeof(PIIX3State), + .instance_size = sizeof(PIIXState), .instance_init = pci_piix3_init, .abstract = true, .class_init = pci_piix3_class_init, @@ -433,7 +433,7 @@ static const TypeInfo piix3_pci_type_info = { static void piix3_realize(PCIDevice *dev, Error **errp) { ERRP_GUARD(); - PIIX3State *piix3 = PIIX3_PCI_DEVICE(dev); + PIIXState *piix3 = PIIX_PCI_DEVICE(dev); PCIBus *pci_bus = pci_get_bus(dev); pci_piix3_realize(dev, errp); @@ -463,7 +463,7 @@ static const TypeInfo piix3_info = { static void piix3_xen_realize(PCIDevice *dev, Error **errp) { ERRP_GUARD(); - PIIX3State *piix3 = PIIX3_PCI_DEVICE(dev); + PIIXState *piix3 = PIIX_PCI_DEVICE(dev); PCIBus *pci_bus = pci_get_bus(dev); pci_piix3_realize(dev, errp); diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h index ae3b49fe93..c9fa0f1aa6 100644 --- a/include/hw/southbridge/piix.h +++ b/include/hw/southbridge/piix.h @@ -73,10 +73,10 @@ struct PIIXState { bool has_usb; bool smm_enabled; }; -typedef struct PIIXState PIIX3State; +typedef struct PIIXState PIIXState; #define TYPE_PIIX3_PCI_DEVICE "pci-piix3" -DECLARE_INSTANCE_CHECKER(PIIX3State, PIIX3_PCI_DEVICE, +DECLARE_INSTANCE_CHECKER(PIIXState, PIIX_PCI_DEVICE, TYPE_PIIX3_PCI_DEVICE) #define TYPE_PIIX3_DEVICE "PIIX3" From patchwork Sat Oct 22 15:04:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 13016447 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1D228C433FE for ; Sun, 23 Oct 2022 20:56:49 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1omhPL-0007TY-7J for qemu-devel@archiver.kernel.org; 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[77.191.171.138]) by smtp.gmail.com with ESMTPSA id 4-20020a170906310400b00780ab5a9116sm13021558ejx.211.2022.10.22.08.06.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 22 Oct 2022 08:06:53 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Eduardo Habkost , =?utf-8?q?Herv=C3=A9_Poussineau?= , Aurelien Jarno , Igor Mammedov , Gerd Hoffmann , John Snow , Jiaxun Yang , Ani Sinha , Marcel Apfelbaum , qemu-block@nongnu.org, Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , "Michael S. Tsirkin" , Paolo Bonzini , Bernhard Beschow Subject: [PATCH v2 25/43] hw/mips/malta: Reuse dev variable Date: Sat, 22 Oct 2022 17:04:50 +0200 Message-Id: <20221022150508.26830-26-shentey@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221022150508.26830-1-shentey@gmail.com> References: <20221022150508.26830-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::52d; envelope-from=shentey@gmail.com; helo=mail-ed1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" While at it, move the assignments closer to where they are used. Signed-off-by: Bernhard Beschow Reviewed-by: Philippe Mathieu-Daudé --- hw/mips/malta.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/hw/mips/malta.c b/hw/mips/malta.c index 0e932988e0..0ec2ac2eaf 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -1239,7 +1239,6 @@ void mips_malta_init(MachineState *machine) MaltaState *s; PCIDevice *piix4; DeviceState *dev; - DeviceState *pm_dev; s = MIPS_MALTA(qdev_new(TYPE_MIPS_MALTA)); sysbus_realize_and_unref(SYS_BUS_DEVICE(s), &error_fatal); @@ -1405,13 +1404,13 @@ void mips_malta_init(MachineState *machine) TYPE_PIIX4_PCI_DEVICE); dev = DEVICE(piix4); isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0")); - pm_dev = DEVICE(object_resolve_path_component(OBJECT(dev), "pm")); - smbus = I2C_BUS(qdev_get_child_bus(pm_dev, "i2c")); /* Interrupt controller */ qdev_connect_gpio_out_named(dev, "intr", 0, i8259_irq); /* generate SPD EEPROM data */ + dev = DEVICE(object_resolve_path_component(OBJECT(piix4), "pm")); + smbus = I2C_BUS(qdev_get_child_bus(dev, "i2c")); generate_eeprom_spd(&smbus_eeprom_buf[0 * 256], ram_size); generate_eeprom_serial(&smbus_eeprom_buf[6 * 256]); smbus_eeprom_init(smbus, 8, smbus_eeprom_buf, smbus_eeprom_size); From patchwork Sat Oct 22 15:04:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 13016705 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B2E23C38A2D for ; Mon, 24 Oct 2022 06:14:27 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1omhQT-0007dJ-Oj for qemu-devel@archiver.kernel.org; Sun, 23 Oct 2022 16:18:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1omG5V-0007JL-GN; Sat, 22 Oct 2022 11:07:01 -0400 Received: from mail-ed1-x536.google.com ([2a00:1450:4864:20::536]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1omG5T-0002JF-PZ; Sat, 22 Oct 2022 11:07:01 -0400 Received: by mail-ed1-x536.google.com with SMTP id m15so16055352edb.13; Sat, 22 Oct 2022 08:06:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=kBMXBig4HIyHAZz2Q59/QE778riCp4LtfSIp8xixZNk=; b=XEBKSGPsQcm68D/REGXURH4NCEol4q6Qa+SZB3i/tizPgUQVhd9FndAMqu9ZgMn4tF cXwdgiYfNCR6g/QpagRDe8o+/fVTWhyKEMJ9kuzEy9Ob7/uzFtMCHY1pZ0BUM0VwkBB2 9+DMcqGGDt1PjkmP3zXZRii04ZbNmLYcUWTldme1iow/oIMOCqLbkrBMROdZ7UvrCs2T XiS3LjUPN/2Ycn2lAJVRyzCT4lE8zRC4kuicj7Pot57Vevj1e4a2No8mLPIuuu9Eg4gN LxTsirw01zgKeuXEx2IBmg25UBrfDx3f7Vm4jFo7Kp7ULWjEL713oKXy/bSEVg9lwnOj Kb7Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kBMXBig4HIyHAZz2Q59/QE778riCp4LtfSIp8xixZNk=; b=BknNN5RHIAGKus6efGPsSgvjnUbhOMw49Q5edBAbPfym2kDPwm5DKePjpLkrBPvkEP p3uh0qwyuWSZNP+avAENLxdSqi9QItGjE7GdyZEbYRkHbBbgxnrEP1JIn+Us2bPFnmft FS7BX23xdnub4I3ST7sx7zjpz5WiX8eOHIhxdRHU3UZRXk/UBqTijyMRVxZfw10TQVhx zWzqbZP3YeKrRmYQDWkxzpKLTrZ2HFvzoadBm82A06B5q3oA78oB/TY4OpWonVJ2Wcoi kyqNvHdc3OsBLfoAPmVEzvpbOyFeKU9pQYAV1ZEtz6nM0cMuBFnZR08vL6jiQtClx/5s SPkw== X-Gm-Message-State: ACrzQf0/oJAiyDuZdd5CJy+A4H/s2xXBRJKY0VNKeYYcSKu//32QdZp0 YyKxVSvXHyiCj+Np+OMgA7XnDQ5acLzKyg== X-Google-Smtp-Source: AMsMyM7mc93qfJM4KgGzD1NWpwBnj8+FDKgDreBbM2INKTskSreVuTvLK2RRNNx0A3sCvvlkhkb+Yg== X-Received: by 2002:a05:6402:5253:b0:45d:5914:245b with SMTP id t19-20020a056402525300b0045d5914245bmr23129479edd.227.1666451217746; Sat, 22 Oct 2022 08:06:57 -0700 (PDT) Received: from localhost.localdomain (dynamic-077-191-171-138.77.191.pool.telefonica.de. [77.191.171.138]) by smtp.gmail.com with ESMTPSA id 4-20020a170906310400b00780ab5a9116sm13021558ejx.211.2022.10.22.08.06.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 22 Oct 2022 08:06:57 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Eduardo Habkost , =?utf-8?q?Herv=C3=A9_Poussineau?= , Aurelien Jarno , Igor Mammedov , Gerd Hoffmann , John Snow , Jiaxun Yang , Ani Sinha , Marcel Apfelbaum , qemu-block@nongnu.org, Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , "Michael S. Tsirkin" , Paolo Bonzini , Bernhard Beschow Subject: [PATCH v2 26/43] meson: Fix dependencies of piix4 southbridge Date: Sat, 22 Oct 2022 17:04:51 +0200 Message-Id: <20221022150508.26830-27-shentey@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221022150508.26830-1-shentey@gmail.com> References: <20221022150508.26830-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::536; envelope-from=shentey@gmail.com; helo=mail-ed1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Bernhard Beschow --- configs/devices/mips-softmmu/common.mak | 1 - hw/isa/Kconfig | 6 ++++++ 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/configs/devices/mips-softmmu/common.mak b/configs/devices/mips-softmmu/common.mak index d2202c839e..416161f833 100644 --- a/configs/devices/mips-softmmu/common.mak +++ b/configs/devices/mips-softmmu/common.mak @@ -23,7 +23,6 @@ CONFIG_APM=y CONFIG_I8257=y CONFIG_PIIX4=y CONFIG_IDE_ISA=y -CONFIG_IDE_PIIX=y CONFIG_PFLASH_CFI01=y CONFIG_I8259=y CONFIG_MC146818RTC=y diff --git a/hw/isa/Kconfig b/hw/isa/Kconfig index a021e1cbfc..1aa10f84f2 100644 --- a/hw/isa/Kconfig +++ b/hw/isa/Kconfig @@ -45,7 +45,13 @@ config PIIX4 bool # For historical reasons, SuperIO devices are created in the board # for PIIX4. + select ACPI_PIIX4 + select I8254 + select I8257 + select I8259 + select IDE_PIIX select ISA_BUS + select MC146818RTC select USB_UHCI config VT82C686 From patchwork Sat Oct 22 15:04:52 2022 Content-Type: text/plain; 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[77.191.171.138]) by smtp.gmail.com with ESMTPSA id 4-20020a170906310400b00780ab5a9116sm13021558ejx.211.2022.10.22.08.06.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 22 Oct 2022 08:06:59 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Eduardo Habkost , =?utf-8?q?Herv=C3=A9_Poussineau?= , Aurelien Jarno , Igor Mammedov , Gerd Hoffmann , John Snow , Jiaxun Yang , Ani Sinha , Marcel Apfelbaum , qemu-block@nongnu.org, Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , "Michael S. Tsirkin" , Paolo Bonzini , Bernhard Beschow Subject: [PATCH v2 27/43] hw/isa/piix4: Add missing initialization Date: Sat, 22 Oct 2022 17:04:52 +0200 Message-Id: <20221022150508.26830-28-shentey@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221022150508.26830-1-shentey@gmail.com> References: <20221022150508.26830-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::52b; envelope-from=shentey@gmail.com; helo=mail-ed1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" PIIX3 clears its reset control register, so do the same in PIIX4. Signed-off-by: Bernhard Beschow --- hw/isa/piix4.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index 83b50c3a9b..4b8dece257 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -140,6 +140,8 @@ static void piix4_isa_reset(DeviceState *dev) pci_conf[0xab] = 0x00; pci_conf[0xac] = 0x00; pci_conf[0xae] = 0x00; + + d->rcr = 0; } static int piix4_post_load(void *opaque, int version_id) From patchwork Sat Oct 22 15:04:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 13016451 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B07AEC433FE for ; Sun, 23 Oct 2022 21:06:15 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1omhTU-00081V-DS for qemu-devel@archiver.kernel.org; Sun, 23 Oct 2022 16:21:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1omG5Z-0007KZ-Ts; Sat, 22 Oct 2022 11:07:05 -0400 Received: from mail-ed1-x535.google.com ([2a00:1450:4864:20::535]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1omG5X-0002Ex-O8; Sat, 22 Oct 2022 11:07:05 -0400 Received: by mail-ed1-x535.google.com with SMTP id l22so16108163edj.5; Sat, 22 Oct 2022 08:07:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=EJFanPG6Dom+OOVnb+H9BrqEGSCa/O3aKDM5m7Y77qA=; b=qod+5162ymnRd2jvZL24H4AlE6V2Zuq87FLbA/gJ4y6xGP5OuBb8r+paHhhH9wTimS lTxgrIV5q6o80JLVdIKdB1UemAvCcq3ogg2RjROzxJJ9og2lPRJBtEXmC1oeZkZr/Aha TJQo1EsHBdZfXU7URhfRvzygeyc5PBKm2K3Ykj8M0MF/dUBY7j74ZeQ0Q8QcgN2Q4ux9 y0XH+KT5wNrQveNd00/pCdIsTBq8Jfe5+5AsPCHceOCqYZByO23G8txjGvh+ciDZcyau FW+EmWf0+I/jkz12ngeaGtTIz3ZWL6R4abc5WwePoL+hRp/crgtMncXVS4PnGg0rnzjB DTdQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=EJFanPG6Dom+OOVnb+H9BrqEGSCa/O3aKDM5m7Y77qA=; b=c4YQndfVx+m45zg6JVogIsJupjK0+8y2R5vNvwm3o5WfrAdePCPwajNREGjK6SweW7 gTF+2mJlxjOWxm1c49YaoepZ1ywi6GMGXXIjio+oZ5xCy6bAb4EW84sfj4v9hcAQrBSD S6zXL01fGc3v6h4pTAVRpB5iGOse6x2c0H4VPSZM156kkIO3e2ue45INJkYbxKDATgOE hCEycDPVlrLIIVYMttkdLm38zziztZZBy4AVZ2AuVU3zbqsj+3ubT92lFrZ9/cl0xdI5 6ETmxSdEjPXoaZeu5WvR2O93B1owPLhmarP30DhdLPuWSYkB4uMscsmT+SOtmsAPHj00 9p4A== X-Gm-Message-State: ACrzQf19p03Rw9h9SaDQlvJCRkiM0MGsjr/ei1LZlCDQotm7hlZVYpGY YL8bSsM7JPLWO7qV2SZ65gsS+frt2SHWmg== X-Google-Smtp-Source: AMsMyM4id+kj4HX88VqemgqLrHjsC1rJmuZUCRXj8rIXePeoeNKAqN/7TrF+EA0BGsjpw2vNtJWvsA== X-Received: by 2002:a17:907:7b86:b0:78d:cb21:da0c with SMTP id ne6-20020a1709077b8600b0078dcb21da0cmr20857331ejc.24.1666451222460; Sat, 22 Oct 2022 08:07:02 -0700 (PDT) Received: from localhost.localdomain (dynamic-077-191-171-138.77.191.pool.telefonica.de. [77.191.171.138]) by smtp.gmail.com with ESMTPSA id 4-20020a170906310400b00780ab5a9116sm13021558ejx.211.2022.10.22.08.07.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 22 Oct 2022 08:07:01 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Eduardo Habkost , =?utf-8?q?Herv=C3=A9_Poussineau?= , Aurelien Jarno , Igor Mammedov , Gerd Hoffmann , John Snow , Jiaxun Yang , Ani Sinha , Marcel Apfelbaum , qemu-block@nongnu.org, Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , "Michael S. Tsirkin" , Paolo Bonzini , Bernhard Beschow Subject: [PATCH v2 28/43] hw/isa/piix4: Move pci_ide_create_devs() call to board code Date: Sat, 22 Oct 2022 17:04:53 +0200 Message-Id: <20221022150508.26830-29-shentey@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221022150508.26830-1-shentey@gmail.com> References: <20221022150508.26830-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::535; envelope-from=shentey@gmail.com; helo=mail-ed1-x535.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" For the VIA south bridges there was a comment to have the call in board code. Move it there for PIIX4 as well for consistency. Signed-off-by: Bernhard Beschow Reviewed-by: Philippe Mathieu-Daudé --- hw/isa/piix4.c | 1 - hw/mips/malta.c | 10 ++++++---- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index 4b8dece257..a7389ff193 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -257,7 +257,6 @@ static void piix4_realize(PCIDevice *dev, Error **errp) if (!qdev_realize(DEVICE(&s->ide), BUS(pci_bus), errp)) { return; } - pci_ide_create_devs(PCI_DEVICE(&s->ide)); /* USB */ qdev_prop_set_int32(DEVICE(&s->uhci), "addr", dev->devfn + 2); diff --git a/hw/mips/malta.c b/hw/mips/malta.c index 0ec2ac2eaf..a4b866a2cf 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -39,7 +39,7 @@ #include "hw/pci/pci.h" #include "qemu/log.h" #include "hw/mips/bios.h" -#include "hw/ide.h" +#include "hw/ide/pci.h" #include "hw/irq.h" #include "hw/loader.h" #include "elf.h" @@ -1402,11 +1402,13 @@ void mips_malta_init(MachineState *machine) /* Southbridge */ piix4 = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0), true, TYPE_PIIX4_PCI_DEVICE); - dev = DEVICE(piix4); - isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0")); + isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix4), "isa.0")); + + dev = DEVICE(object_resolve_path_component(OBJECT(piix4), "ide")); + pci_ide_create_devs(PCI_DEVICE(dev)); /* Interrupt controller */ - qdev_connect_gpio_out_named(dev, "intr", 0, i8259_irq); + qdev_connect_gpio_out_named(DEVICE(piix4), "intr", 0, i8259_irq); /* generate SPD EEPROM data */ dev = DEVICE(object_resolve_path_component(OBJECT(piix4), "pm")); From patchwork Sat Oct 22 15:04:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 13016659 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7338CC38A2D for ; Mon, 24 Oct 2022 05:22:42 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1omhUv-0008Nm-IQ for qemu-devel@archiver.kernel.org; Sun, 23 Oct 2022 16:23:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1omG5c-0007Km-FZ; Sat, 22 Oct 2022 11:07:08 -0400 Received: from mail-ed1-x530.google.com ([2a00:1450:4864:20::530]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1omG5a-0002KU-Sh; Sat, 22 Oct 2022 11:07:08 -0400 Received: by mail-ed1-x530.google.com with SMTP id r14so16113023edc.7; Sat, 22 Oct 2022 08:07:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=RTpOClvzPkztIRM/jCrquvIhowaJtx1x6Tz2AKs9S08=; b=QtFDbeU2bIQTKLHhGIt2xG7WxEclU/xAgo0tHaWHYbOsx0/FwAWxuynwst6AUzUk4g Xgrdjd8xyEiXfFnMv0nHnGzkqvYUeIhRXz7zYAQEhCN63tGQ4pFRMbFDgm0T57ssssFk gLiQuZZcf2dGH1vXfrTAfagZ9xCxwdZxBVCUAZbNCu8Gu7D6+2w5yXUpNDDJObx7yYMI bQ6mCKLPd/5BNdLYp5pahFz96si9rKfBxlq+7XDlWhtP+kT0Y5boF6d9UPBpUN2GFhlB 0wVEKMCpXV3Q9wcLUd+NTPIGc7pNJDzZnzQcelp4wIcwMwNnjapaDyd2CvHFSIxVx7e5 DJsw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=RTpOClvzPkztIRM/jCrquvIhowaJtx1x6Tz2AKs9S08=; b=cXavJpLHE29KKPOujAR6JR9mBvLgZwsdWyKfqUUsUt9gJMFGnJsbnnF7ahXx+Q5CHS 3tMgFwQ+mn6zPOoH+Lb0ZNpWKY5tIkIe06vpl19qg8Yrs5XblPhBBefziU51iQacBvEY ixmwCv7wsqYcHBbjbeOY8b/Vc/hDicKwmALkLUDRZmd0zXoKqAXxFIVadskh0SK7zHW3 WvBnoSkWvGmEKFM/pA0FgUHjk0Ddsl2r+wUee+Yp2GXbLZsd2RK5sOyKJs8Y4aVv4qGR nJMIlx0rZ+d1c1UeZg2OHG/OQD3pnQpmS8TpWt0nG3XgQmiJw/BjGn9OYBci3vfyoAFQ miEQ== X-Gm-Message-State: ACrzQf1jXEojTEoAo9ePhNw8iGqUvkKOUkG1c6HqB/Ro1rxWAQyeogDL t+29eftxzODedUMfnzNYLLY5AYwmurUA+Q== X-Google-Smtp-Source: AMsMyM7o/B8hau+TbKqv08DNbI6Ka6naoRw/s118aNDHgFpLyFzzy5JQTSSEwvZN3mC3xScVgyBQEg== X-Received: by 2002:a17:907:3ea9:b0:78d:fdf0:88fe with SMTP id hs41-20020a1709073ea900b0078dfdf088femr21046792ejc.667.1666451224953; Sat, 22 Oct 2022 08:07:04 -0700 (PDT) Received: from localhost.localdomain (dynamic-077-191-171-138.77.191.pool.telefonica.de. [77.191.171.138]) by smtp.gmail.com with ESMTPSA id 4-20020a170906310400b00780ab5a9116sm13021558ejx.211.2022.10.22.08.07.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 22 Oct 2022 08:07:03 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Eduardo Habkost , =?utf-8?q?Herv=C3=A9_Poussineau?= , Aurelien Jarno , Igor Mammedov , Gerd Hoffmann , John Snow , Jiaxun Yang , Ani Sinha , Marcel Apfelbaum , qemu-block@nongnu.org, Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , "Michael S. Tsirkin" , Paolo Bonzini , Bernhard Beschow Subject: [PATCH v2 29/43] hw/isa/piix4: Make PIIX4's ACPI and USB functions optional Date: Sat, 22 Oct 2022 17:04:54 +0200 Message-Id: <20221022150508.26830-30-shentey@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221022150508.26830-1-shentey@gmail.com> References: <20221022150508.26830-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::530; envelope-from=shentey@gmail.com; helo=mail-ed1-x530.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" This aligns PIIX4 with PIIX3. Signed-off-by: Bernhard Beschow --- hw/isa/piix4.c | 44 ++++++++++++++++++++++++++++++++------------ hw/mips/malta.c | 6 ++++-- 2 files changed, 36 insertions(+), 14 deletions(-) diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index a7389ff193..fc698c23be 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -51,9 +51,16 @@ struct PIIX4State { PCIIDEState ide; UHCIState uhci; PIIX4PMState pm; + + uint32_t smb_io_base; + /* Reset Control Register */ MemoryRegion rcr_mem; uint8_t rcr; + + bool has_acpi; + bool has_usb; + bool smm_enabled; }; OBJECT_DECLARE_SIMPLE_TYPE(PIIX4State, PIIX4_PCI_DEVICE) @@ -259,17 +266,26 @@ static void piix4_realize(PCIDevice *dev, Error **errp) } /* USB */ - qdev_prop_set_int32(DEVICE(&s->uhci), "addr", dev->devfn + 2); - if (!qdev_realize(DEVICE(&s->uhci), BUS(pci_bus), errp)) { - return; + if (s->has_usb) { + object_initialize_child(OBJECT(dev), "uhci", &s->uhci, + TYPE_PIIX4_USB_UHCI); + qdev_prop_set_int32(DEVICE(&s->uhci), "addr", dev->devfn + 2); + if (!qdev_realize(DEVICE(&s->uhci), BUS(pci_bus), errp)) { + return; + } } /* ACPI controller */ - qdev_prop_set_int32(DEVICE(&s->pm), "addr", dev->devfn + 3); - if (!qdev_realize(DEVICE(&s->pm), BUS(pci_bus), errp)) { - return; + if (s->has_acpi) { + object_initialize_child(OBJECT(s), "pm", &s->pm, TYPE_PIIX4_PM); + qdev_prop_set_int32(DEVICE(&s->pm), "addr", dev->devfn + 3); + qdev_prop_set_uint32(DEVICE(&s->pm), "smb_io_base", s->smb_io_base); + qdev_prop_set_bit(DEVICE(&s->pm), "smm-enabled", s->smm_enabled); + if (!qdev_realize(DEVICE(&s->pm), BUS(pci_bus), errp)) { + return; + } + qdev_connect_gpio_out(DEVICE(&s->pm), 0, s->isa[9]); } - qdev_connect_gpio_out(DEVICE(&s->pm), 0, s->isa[9]); pci_bus_irqs(pci_bus, piix4_set_irq, pci_slot_get_pirq, s, PIIX_NUM_PIRQS); } @@ -280,13 +296,16 @@ static void piix4_init(Object *obj) object_initialize_child(obj, "rtc", &s->rtc, TYPE_MC146818_RTC); object_initialize_child(obj, "ide", &s->ide, TYPE_PIIX4_IDE); - object_initialize_child(obj, "uhci", &s->uhci, TYPE_PIIX4_USB_UHCI); - - object_initialize_child(obj, "pm", &s->pm, TYPE_PIIX4_PM); - qdev_prop_set_uint32(DEVICE(&s->pm), "smb_io_base", 0x1100); - qdev_prop_set_bit(DEVICE(&s->pm), "smm-enabled", 0); } +static Property piix4_props[] = { + DEFINE_PROP_UINT32("smb_io_base", PIIX4State, smb_io_base, 0), + DEFINE_PROP_BOOL("has-acpi", PIIX4State, has_acpi, true), + DEFINE_PROP_BOOL("has-usb", PIIX4State, has_usb, true), + DEFINE_PROP_BOOL("smm-enabled", PIIX4State, smm_enabled, false), + DEFINE_PROP_END_OF_LIST(), +}; + static void piix4_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); @@ -305,6 +324,7 @@ static void piix4_class_init(ObjectClass *klass, void *data) */ dc->user_creatable = false; dc->hotpluggable = false; + device_class_set_props(dc, piix4_props); } static const TypeInfo piix4_info = { diff --git a/hw/mips/malta.c b/hw/mips/malta.c index a4b866a2cf..6339b0d66c 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -1400,8 +1400,10 @@ void mips_malta_init(MachineState *machine) empty_slot_init("GT64120", 0, 0x20000000); /* Southbridge */ - piix4 = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0), true, - TYPE_PIIX4_PCI_DEVICE); + piix4 = pci_new_multifunction(PCI_DEVFN(10, 0), true, + TYPE_PIIX4_PCI_DEVICE); + qdev_prop_set_uint32(DEVICE(piix4), "smb_io_base", 0x1100); + pci_realize_and_unref(piix4, pci_bus, &error_fatal); isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix4), "isa.0")); dev = DEVICE(object_resolve_path_component(OBJECT(piix4), "ide")); From patchwork Sat Oct 22 15:04:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 13016752 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B522AFA373F for ; Mon, 24 Oct 2022 07:05:48 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1omhWh-0000D9-Qe for qemu-devel@archiver.kernel.org; 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Tsirkin" , Paolo Bonzini , Bernhard Beschow Subject: [PATCH v2 30/43] hw/isa/piix4: Allow board to provide PCI interrupt routes Date: Sat, 22 Oct 2022 17:04:55 +0200 Message-Id: <20221022150508.26830-31-shentey@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221022150508.26830-1-shentey@gmail.com> References: <20221022150508.26830-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::52d; envelope-from=shentey@gmail.com; helo=mail-ed1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" PIIX3 initializes the PIRQx route control registers to the default values as described in the 82371AB PCI-TO-ISA/IDE XCELERATOR (PIIX4) April 1997 manual. PIIX4, however, initializes the routes according to the Malta™ User’s Manual, ch 6.6, which are IRQs 10 and 11. In order to allow the reset methods to be consolidated, allow board code to specify the routes. Signed-off-by: Bernhard Beschow Reviewed-by: Philippe Mathieu-Daudé --- hw/isa/piix4.c | 14 ++++++++++---- hw/mips/malta.c | 4 ++++ 2 files changed, 14 insertions(+), 4 deletions(-) diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index fc698c23be..57b0b98bef 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -58,6 +58,8 @@ struct PIIX4State { MemoryRegion rcr_mem; uint8_t rcr; + uint8_t pci_irq_reset_mappings[PIIX_NUM_PIRQS]; + bool has_acpi; bool has_usb; bool smm_enabled; @@ -123,10 +125,10 @@ static void piix4_isa_reset(DeviceState *dev) pci_conf[0x4c] = 0x4d; pci_conf[0x4e] = 0x03; pci_conf[0x4f] = 0x00; - pci_conf[0x60] = 0x0a; // PCI A -> IRQ 10 - pci_conf[0x61] = 0x0a; // PCI B -> IRQ 10 - pci_conf[0x62] = 0x0b; // PCI C -> IRQ 11 - pci_conf[0x63] = 0x0b; // PCI D -> IRQ 11 + pci_conf[PIIX_PIRQCA] = d->pci_irq_reset_mappings[0]; + pci_conf[PIIX_PIRQCB] = d->pci_irq_reset_mappings[1]; + pci_conf[PIIX_PIRQCC] = d->pci_irq_reset_mappings[2]; + pci_conf[PIIX_PIRQCD] = d->pci_irq_reset_mappings[3]; pci_conf[0x69] = 0x02; pci_conf[0x70] = 0x80; pci_conf[0x76] = 0x0c; @@ -300,6 +302,10 @@ static void piix4_init(Object *obj) static Property piix4_props[] = { DEFINE_PROP_UINT32("smb_io_base", PIIX4State, smb_io_base, 0), + DEFINE_PROP_UINT8("pirqa", PIIX4State, pci_irq_reset_mappings[0], 0x80), + DEFINE_PROP_UINT8("pirqb", PIIX4State, pci_irq_reset_mappings[1], 0x80), + DEFINE_PROP_UINT8("pirqc", PIIX4State, pci_irq_reset_mappings[2], 0x80), + DEFINE_PROP_UINT8("pirqd", PIIX4State, pci_irq_reset_mappings[3], 0x80), DEFINE_PROP_BOOL("has-acpi", PIIX4State, has_acpi, true), DEFINE_PROP_BOOL("has-usb", PIIX4State, has_usb, true), DEFINE_PROP_BOOL("smm-enabled", PIIX4State, smm_enabled, false), diff --git a/hw/mips/malta.c b/hw/mips/malta.c index 6339b0d66c..44b6b14f3d 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -1403,6 +1403,10 @@ void mips_malta_init(MachineState *machine) piix4 = pci_new_multifunction(PCI_DEVFN(10, 0), true, TYPE_PIIX4_PCI_DEVICE); qdev_prop_set_uint32(DEVICE(piix4), "smb_io_base", 0x1100); + qdev_prop_set_uint8(DEVICE(piix4), "pirqa", 10); + qdev_prop_set_uint8(DEVICE(piix4), "pirqb", 10); + qdev_prop_set_uint8(DEVICE(piix4), "pirqc", 11); + qdev_prop_set_uint8(DEVICE(piix4), "pirqd", 11); pci_realize_and_unref(piix4, pci_bus, &error_fatal); isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix4), "isa.0")); From patchwork Sat Oct 22 15:04:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 13016475 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BEB8FC3A59D for ; Mon, 24 Oct 2022 01:13:37 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1omhYf-0000an-W3 for qemu-devel@archiver.kernel.org; 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[77.191.171.138]) by smtp.gmail.com with ESMTPSA id 4-20020a170906310400b00780ab5a9116sm13021558ejx.211.2022.10.22.08.07.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 22 Oct 2022 08:07:08 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Eduardo Habkost , =?utf-8?q?Herv=C3=A9_Poussineau?= , Aurelien Jarno , Igor Mammedov , Gerd Hoffmann , John Snow , Jiaxun Yang , Ani Sinha , Marcel Apfelbaum , qemu-block@nongnu.org, Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , "Michael S. Tsirkin" , Paolo Bonzini , Bernhard Beschow Subject: [PATCH v2 31/43] hw/isa/piix4: Remove unused code Date: Sat, 22 Oct 2022 17:04:56 +0200 Message-Id: <20221022150508.26830-32-shentey@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221022150508.26830-1-shentey@gmail.com> References: <20221022150508.26830-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::531; envelope-from=shentey@gmail.com; helo=mail-ed1-x531.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" The Malta board, which is the only user of PIIX4, doesn't connect to the exported interrupt lines. Signed-off-by: Bernhard Beschow --- hw/isa/piix4.c | 8 -------- 1 file changed, 8 deletions(-) diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index 57b0b98bef..d65f486008 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -182,12 +182,6 @@ static void piix4_request_i8259_irq(void *opaque, int irq, int level) qemu_set_irq(s->cpu_intr, level); } -static void piix4_set_i8259_irq(void *opaque, int irq, int level) -{ - PIIX4State *s = opaque; - qemu_set_irq(s->isa[irq], level); -} - static void piix4_rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned int len) { @@ -231,8 +225,6 @@ static void piix4_realize(PCIDevice *dev, Error **errp) return; } - qdev_init_gpio_in_named(DEVICE(dev), piix4_set_i8259_irq, - "isa", ISA_NUM_IRQS); qdev_init_gpio_out_named(DEVICE(dev), &s->cpu_intr, "intr", 1); From patchwork Sat Oct 22 15:04:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 13016446 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5343EECAAA1 for ; Sun, 23 Oct 2022 20:53:47 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1omhZw-0000nI-FV for qemu-devel@archiver.kernel.org; Sun, 23 Oct 2022 16:28:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1omG5j-0007N7-Nc; Sat, 22 Oct 2022 11:07:15 -0400 Received: from mail-ed1-x52e.google.com ([2a00:1450:4864:20::52e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1omG5i-0002Cw-3S; Sat, 22 Oct 2022 11:07:15 -0400 Received: by mail-ed1-x52e.google.com with SMTP id a5so3032202edb.11; Sat, 22 Oct 2022 08:07:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=isW16/8LHToB3dy7xbWfr+auf6dFNG472EkefD72SSM=; b=c+OXyRY/Q5lu3nwPNVAZWoOv89LRjN5KpVyoAExmL2mp0KJGJSq+VUUkzjjDGrsF9J 4dGma/mBBuC3N5YHN+78YXIDjWgFF3RjjSu8j7A+OIdGDj7jkBCQZGgSwtirbFo6YhMv Z8aii0ExBei+fshFvdPBI0BKx6Bz+pAXUIoQzBwBeSooPbQwHBRp9Rai/lTAVgM2uaCt TsPQbb+B9AIpkB3h3LaYjEMH0nES08L7wmu3EIw4lfTelO2ndXMpAjFvgehyK/V+xAQf 3Q+thrNlZavyCvcKjcI/hUaBzys9wQiW26ml0G4xyaXVXacVbUEYWIn8MTlV++1ImJ30 rqlg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=isW16/8LHToB3dy7xbWfr+auf6dFNG472EkefD72SSM=; b=RRPsvTbHysW0m9u5//tx/hPRJZMJyqLmp26cvSIQsFWEIXva1W7kVskG2WJ8Z2x9/K zLr87+l1oyHEhOUap/gJxLCN42wvw31VmPajsEOSyjTYqGDVS4N0iAgGJ4eYHdohC2k/ 97guW2MGgPwqpb9LcMd+UYNCD3zZaIsZ56TLobM/o1MrJQTkcwE8hePixnAQ4tO+uBnA 4z0wCf19z4BsWHtJxY6xVUQynr+vLZ6Uq0QlEVjw/LNY+9yQWOKbJbTo+I0dpbSMbTca NhVDQUnRWZ1B9X99N1+rps7Qw5oXdMH+lF4Qt4hG9uzdvKcPLmxTYbep6dE6H8auB4nr 7nZw== X-Gm-Message-State: ACrzQf1s768IYJf1+BThAl2WiqHj+vjJVNe1yA/KN7Ni+VFqvlvE0E7x 0w7ixSxp/blzx8K4QmqBgeuLFBxotZQkqA== X-Google-Smtp-Source: AMsMyM47W9C8uIoNFaVHwdgw6iemOfE03le0dSrzLCfhR+25qGPfDQJ0aB5/TCuK7zhF3hV6FiiH/g== X-Received: by 2002:a05:6402:3223:b0:461:8635:e5c with SMTP id g35-20020a056402322300b0046186350e5cmr2023320eda.303.1666451232843; Sat, 22 Oct 2022 08:07:12 -0700 (PDT) Received: from localhost.localdomain (dynamic-077-191-171-138.77.191.pool.telefonica.de. [77.191.171.138]) by smtp.gmail.com with ESMTPSA id 4-20020a170906310400b00780ab5a9116sm13021558ejx.211.2022.10.22.08.07.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 22 Oct 2022 08:07:11 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Eduardo Habkost , =?utf-8?q?Herv=C3=A9_Poussineau?= , Aurelien Jarno , Igor Mammedov , Gerd Hoffmann , John Snow , Jiaxun Yang , Ani Sinha , Marcel Apfelbaum , qemu-block@nongnu.org, Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , "Michael S. Tsirkin" , Paolo Bonzini , Bernhard Beschow Subject: [PATCH v2 32/43] hw/isa/piix4: Use ISA PIC device Date: Sat, 22 Oct 2022 17:04:57 +0200 Message-Id: <20221022150508.26830-33-shentey@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221022150508.26830-1-shentey@gmail.com> References: <20221022150508.26830-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::52e; envelope-from=shentey@gmail.com; helo=mail-ed1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Aligns the code with PIIX3 such that PIIXState can be used in PIIX4, too. Signed-off-by: Bernhard Beschow --- hw/isa/piix4.c | 28 ++++++++++------------------ hw/mips/malta.c | 11 +++++++++-- 2 files changed, 19 insertions(+), 20 deletions(-) diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index d65f486008..8ddff23116 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -44,9 +44,8 @@ struct PIIX4State { PCIDevice dev; - qemu_irq cpu_intr; - qemu_irq *isa; + ISAPICState pic; RTCState rtc; PCIIDEState ide; UHCIState uhci; @@ -84,7 +83,7 @@ static void piix4_set_irq(void *opaque, int irq_num, int level) pic_level |= pci_bus_get_irq_level(bus, i); } } - qemu_set_irq(s->isa[pic_irq], pic_level); + qemu_set_irq(s->pic.in_irqs[pic_irq], pic_level); } } @@ -176,12 +175,6 @@ static const VMStateDescription vmstate_piix4 = { } }; -static void piix4_request_i8259_irq(void *opaque, int irq, int level) -{ - PIIX4State *s = opaque; - qemu_set_irq(s->cpu_intr, level); -} - static void piix4_rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned int len) { @@ -217,7 +210,6 @@ static void piix4_realize(PCIDevice *dev, Error **errp) PIIX4State *s = PIIX4_PCI_DEVICE(dev); PCIBus *pci_bus = pci_get_bus(dev); ISABus *isa_bus; - qemu_irq *i8259_out_irq; isa_bus = isa_bus_new(DEVICE(dev), pci_address_space(dev), pci_address_space_io(dev), errp); @@ -225,20 +217,18 @@ static void piix4_realize(PCIDevice *dev, Error **errp) return; } - qdev_init_gpio_out_named(DEVICE(dev), &s->cpu_intr, - "intr", 1); - memory_region_init_io(&s->rcr_mem, OBJECT(dev), &piix4_rcr_ops, s, "reset-control", 1); memory_region_add_subregion_overlap(pci_address_space_io(dev), PIIX_RCR_IOPORT, &s->rcr_mem, 1); /* initialize i8259 pic */ - i8259_out_irq = qemu_allocate_irqs(piix4_request_i8259_irq, s, 1); - s->isa = i8259_init(isa_bus, *i8259_out_irq); + if (!qdev_realize(DEVICE(&s->pic), BUS(isa_bus), errp)) { + return; + } /* initialize ISA irqs */ - isa_bus_irqs(isa_bus, s->isa); + isa_bus_irqs(isa_bus, s->pic.in_irqs); /* initialize pit */ i8254_pit_init(isa_bus, 0x40, 0, NULL); @@ -251,7 +241,7 @@ static void piix4_realize(PCIDevice *dev, Error **errp) if (!qdev_realize(DEVICE(&s->rtc), BUS(isa_bus), errp)) { return; } - s->rtc.irq = isa_get_irq(ISA_DEVICE(&s->rtc), s->rtc.isairq); + s->rtc.irq = qdev_get_gpio_in(DEVICE(&s->pic), s->rtc.isairq); /* IDE */ qdev_prop_set_int32(DEVICE(&s->ide), "addr", dev->devfn + 1); @@ -278,7 +268,8 @@ static void piix4_realize(PCIDevice *dev, Error **errp) if (!qdev_realize(DEVICE(&s->pm), BUS(pci_bus), errp)) { return; } - qdev_connect_gpio_out(DEVICE(&s->pm), 0, s->isa[9]); + qdev_connect_gpio_out(DEVICE(&s->pm), 0, + qdev_get_gpio_in(DEVICE(&s->pic), 9)); } pci_bus_irqs(pci_bus, piix4_set_irq, pci_slot_get_pirq, s, PIIX_NUM_PIRQS); @@ -288,6 +279,7 @@ static void piix4_init(Object *obj) { PIIX4State *s = PIIX4_PCI_DEVICE(obj); + object_initialize_child(obj, "pic", &s->pic, TYPE_ISA_PIC); object_initialize_child(obj, "rtc", &s->rtc, TYPE_MC146818_RTC); object_initialize_child(obj, "ide", &s->ide, TYPE_PIIX4_IDE); } diff --git a/hw/mips/malta.c b/hw/mips/malta.c index 44b6b14f3d..68e800b00f 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -28,6 +28,7 @@ #include "qemu/datadir.h" #include "hw/clock.h" #include "hw/southbridge/piix.h" +#include "hw/intc/i8259.h" #include "hw/isa/superio.h" #include "hw/char/serial.h" #include "net/net.h" @@ -1232,10 +1233,11 @@ void mips_malta_init(MachineState *machine) PCIBus *pci_bus; ISABus *isa_bus; qemu_irq cbus_irq, i8259_irq; + qemu_irq *i8259; I2CBus *smbus; DriveInfo *dinfo; int fl_idx = 0; - int be; + int be, i; MaltaState *s; PCIDevice *piix4; DeviceState *dev; @@ -1414,7 +1416,12 @@ void mips_malta_init(MachineState *machine) pci_ide_create_devs(PCI_DEVICE(dev)); /* Interrupt controller */ - qdev_connect_gpio_out_named(DEVICE(piix4), "intr", 0, i8259_irq); + dev = DEVICE(object_resolve_path_component(OBJECT(piix4), "pic")); + i8259 = i8259_init(isa_bus, i8259_irq); + for (i = 0; i < ISA_NUM_IRQS; i++) { + qdev_connect_gpio_out(dev, i, i8259[i]); + } + g_free(i8259); /* generate SPD EEPROM data */ dev = DEVICE(object_resolve_path_component(OBJECT(piix4), "pm")); From patchwork Sat Oct 22 15:04:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 13016508 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 28CD0C3A59D for ; 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[77.191.171.138]) by smtp.gmail.com with ESMTPSA id 4-20020a170906310400b00780ab5a9116sm13021558ejx.211.2022.10.22.08.07.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 22 Oct 2022 08:07:14 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Eduardo Habkost , =?utf-8?q?Herv=C3=A9_Poussineau?= , Aurelien Jarno , Igor Mammedov , Gerd Hoffmann , John Snow , Jiaxun Yang , Ani Sinha , Marcel Apfelbaum , qemu-block@nongnu.org, Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , "Michael S. Tsirkin" , Paolo Bonzini , Bernhard Beschow Subject: [PATCH v2 33/43] hw/isa/piix4: Reuse struct PIIXState from PIIX3 Date: Sat, 22 Oct 2022 17:04:58 +0200 Message-Id: <20221022150508.26830-34-shentey@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221022150508.26830-1-shentey@gmail.com> References: <20221022150508.26830-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::530; envelope-from=shentey@gmail.com; helo=mail-ed1-x530.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Now that PIIX4 also uses the "isa-pic" proxy, both implementations can share the same struct. Signed-off-by: Bernhard Beschow --- hw/isa/piix4.c | 61 ++++++++++++++++---------------------------------- 1 file changed, 19 insertions(+), 42 deletions(-) diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index 8ddff23116..a7d52c5294 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -42,34 +42,10 @@ #include "sysemu/runstate.h" #include "qom/object.h" -struct PIIX4State { - PCIDevice dev; - - ISAPICState pic; - RTCState rtc; - PCIIDEState ide; - UHCIState uhci; - PIIX4PMState pm; - - uint32_t smb_io_base; - - /* Reset Control Register */ - MemoryRegion rcr_mem; - uint8_t rcr; - - uint8_t pci_irq_reset_mappings[PIIX_NUM_PIRQS]; - - bool has_acpi; - bool has_usb; - bool smm_enabled; -}; - -OBJECT_DECLARE_SIMPLE_TYPE(PIIX4State, PIIX4_PCI_DEVICE) - static void piix4_set_irq(void *opaque, int irq_num, int level) { int i, pic_irq, pic_level; - PIIX4State *s = opaque; + PIIXState *s = opaque; PCIBus *bus = pci_get_bus(&s->dev); /* now we change the pic irq level according to the piix irq mappings */ @@ -114,7 +90,7 @@ static int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num) static void piix4_isa_reset(DeviceState *dev) { - PIIX4State *d = PIIX4_PCI_DEVICE(dev); + PIIXState *d = PIIX_PCI_DEVICE(dev); uint8_t *pci_conf = d->dev.config; pci_conf[0x04] = 0x07; // master, memory and I/O @@ -149,12 +125,13 @@ static void piix4_isa_reset(DeviceState *dev) pci_conf[0xac] = 0x00; pci_conf[0xae] = 0x00; + d->pic_levels = 0; /* not used in PIIX4 */ d->rcr = 0; } static int piix4_post_load(void *opaque, int version_id) { - PIIX4State *s = opaque; + PIIXState *s = opaque; if (version_id == 2) { s->rcr = 0; @@ -169,8 +146,8 @@ static const VMStateDescription vmstate_piix4 = { .minimum_version_id = 2, .post_load = piix4_post_load, .fields = (VMStateField[]) { - VMSTATE_PCI_DEVICE(dev, PIIX4State), - VMSTATE_UINT8_V(rcr, PIIX4State, 3), + VMSTATE_PCI_DEVICE(dev, PIIXState), + VMSTATE_UINT8_V(rcr, PIIXState, 3), VMSTATE_END_OF_LIST() } }; @@ -178,7 +155,7 @@ static const VMStateDescription vmstate_piix4 = { static void piix4_rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned int len) { - PIIX4State *s = opaque; + PIIXState *s = opaque; if (val & 4) { qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); @@ -190,7 +167,7 @@ static void piix4_rcr_write(void *opaque, hwaddr addr, uint64_t val, static uint64_t piix4_rcr_read(void *opaque, hwaddr addr, unsigned int len) { - PIIX4State *s = opaque; + PIIXState *s = opaque; return s->rcr; } @@ -207,7 +184,7 @@ static const MemoryRegionOps piix4_rcr_ops = { static void piix4_realize(PCIDevice *dev, Error **errp) { - PIIX4State *s = PIIX4_PCI_DEVICE(dev); + PIIXState *s = PIIX_PCI_DEVICE(dev); PCIBus *pci_bus = pci_get_bus(dev); ISABus *isa_bus; @@ -277,7 +254,7 @@ static void piix4_realize(PCIDevice *dev, Error **errp) static void piix4_init(Object *obj) { - PIIX4State *s = PIIX4_PCI_DEVICE(obj); + PIIXState *s = PIIX_PCI_DEVICE(obj); object_initialize_child(obj, "pic", &s->pic, TYPE_ISA_PIC); object_initialize_child(obj, "rtc", &s->rtc, TYPE_MC146818_RTC); @@ -285,14 +262,14 @@ static void piix4_init(Object *obj) } static Property piix4_props[] = { - DEFINE_PROP_UINT32("smb_io_base", PIIX4State, smb_io_base, 0), - DEFINE_PROP_UINT8("pirqa", PIIX4State, pci_irq_reset_mappings[0], 0x80), - DEFINE_PROP_UINT8("pirqb", PIIX4State, pci_irq_reset_mappings[1], 0x80), - DEFINE_PROP_UINT8("pirqc", PIIX4State, pci_irq_reset_mappings[2], 0x80), - DEFINE_PROP_UINT8("pirqd", PIIX4State, pci_irq_reset_mappings[3], 0x80), - DEFINE_PROP_BOOL("has-acpi", PIIX4State, has_acpi, true), - DEFINE_PROP_BOOL("has-usb", PIIX4State, has_usb, true), - DEFINE_PROP_BOOL("smm-enabled", PIIX4State, smm_enabled, false), + DEFINE_PROP_UINT32("smb_io_base", PIIXState, smb_io_base, 0), + DEFINE_PROP_UINT8("pirqa", PIIXState, pci_irq_reset_mappings[0], 0x80), + DEFINE_PROP_UINT8("pirqb", PIIXState, pci_irq_reset_mappings[1], 0x80), + DEFINE_PROP_UINT8("pirqc", PIIXState, pci_irq_reset_mappings[2], 0x80), + DEFINE_PROP_UINT8("pirqd", PIIXState, pci_irq_reset_mappings[3], 0x80), + DEFINE_PROP_BOOL("has-acpi", PIIXState, has_acpi, true), + DEFINE_PROP_BOOL("has-usb", PIIXState, has_usb, true), + DEFINE_PROP_BOOL("smm-enabled", PIIXState, smm_enabled, false), DEFINE_PROP_END_OF_LIST(), }; @@ -320,7 +297,7 @@ static void piix4_class_init(ObjectClass *klass, void *data) static const TypeInfo piix4_info = { .name = TYPE_PIIX4_PCI_DEVICE, .parent = TYPE_PCI_DEVICE, - .instance_size = sizeof(PIIX4State), + .instance_size = sizeof(PIIXState), .instance_init = piix4_init, .class_init = piix4_class_init, .interfaces = (InterfaceInfo[]) { From patchwork Sat Oct 22 15:04:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 13016467 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0DCDDC3A59D for ; Sun, 23 Oct 2022 23:45:34 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1omhdj-0001HO-QN for qemu-devel@archiver.kernel.org; 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Tsirkin" , Paolo Bonzini , Bernhard Beschow Subject: [PATCH v2 34/43] hw/isa/piix4: Rename reset control operations to match PIIX3 Date: Sat, 22 Oct 2022 17:04:59 +0200 Message-Id: <20221022150508.26830-35-shentey@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221022150508.26830-1-shentey@gmail.com> References: <20221022150508.26830-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::535; envelope-from=shentey@gmail.com; helo=mail-ed1-x535.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Both implementations are the same and will be shared upon merging. Signed-off-by: Bernhard Beschow Reviewed-by: Philippe Mathieu-Daudé --- hw/isa/piix4.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index a7d52c5294..2f5b6fc934 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -152,7 +152,7 @@ static const VMStateDescription vmstate_piix4 = { } }; -static void piix4_rcr_write(void *opaque, hwaddr addr, uint64_t val, +static void rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned int len) { PIIXState *s = opaque; @@ -165,16 +165,16 @@ static void piix4_rcr_write(void *opaque, hwaddr addr, uint64_t val, s->rcr = val & 2; /* keep System Reset type only */ } -static uint64_t piix4_rcr_read(void *opaque, hwaddr addr, unsigned int len) +static uint64_t rcr_read(void *opaque, hwaddr addr, unsigned int len) { PIIXState *s = opaque; return s->rcr; } -static const MemoryRegionOps piix4_rcr_ops = { - .read = piix4_rcr_read, - .write = piix4_rcr_write, +static const MemoryRegionOps rcr_ops = { + .read = rcr_read, + .write = rcr_write, .endianness = DEVICE_LITTLE_ENDIAN, .impl = { .min_access_size = 1, @@ -194,7 +194,7 @@ static void piix4_realize(PCIDevice *dev, Error **errp) return; } - memory_region_init_io(&s->rcr_mem, OBJECT(dev), &piix4_rcr_ops, s, + memory_region_init_io(&s->rcr_mem, OBJECT(dev), &rcr_ops, s, "reset-control", 1); memory_region_add_subregion_overlap(pci_address_space_io(dev), PIIX_RCR_IOPORT, &s->rcr_mem, 1); From patchwork Sat Oct 22 15:05:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 13016459 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 49C38C3A59D for ; Sun, 23 Oct 2022 22:04:23 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1omheQ-0001cp-TR for qemu-devel@archiver.kernel.org; Sun, 23 Oct 2022 16:32:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1omG5q-0007Oa-5I; Sat, 22 Oct 2022 11:07:22 -0400 Received: from mail-ed1-x52b.google.com ([2a00:1450:4864:20::52b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1omG5o-0002Jg-Ng; Sat, 22 Oct 2022 11:07:21 -0400 Received: by mail-ed1-x52b.google.com with SMTP id b12so16126193edd.6; Sat, 22 Oct 2022 08:07:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=CodyFwMG0+XS3PFJi4K5DiBGFix1qYFLR29JzDvdEB4=; b=NnwDx2xS+Vv2f75q63viz/EOjZGNgV5p3fs4RzktUk7q9cAvoAkcCOjrvFk2OvcyNn LwGCh/7OG3tm7dYF48n7Q3IU7EOMP+RV3gGFu2uzxFFlMlbNHNdNdBD+t180SnRpMpCc N1iDYe/rCB3y9mcV1YeGJkiaPAW+9F1F1SB6nXjHSN7SGBUgmN4og7vnw8jAOUv2GaUl 95LXRw/5BERPbkBnPO+7k/z3WZCZcduP2nS4vjKvB4wZZfyNPMp5OwB8CHzO2hxu89Y+ 1OyFJ5+mcquJxvnkwo3jB9dyZLJcN4UwMZ35wj18PgGfCkBSzDcBCvOmDt9FDQGJXGgB py4g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=CodyFwMG0+XS3PFJi4K5DiBGFix1qYFLR29JzDvdEB4=; b=gaZaOTeB3Npvpug3tsLVF3WBMSEx4pgFbyu/wsugPI9+gvAf23UFYeiVqpCCGRe4qF 6S9YtcveWnLmaTYJd87tbqr3Ha2jCdynf3e1yEjczeC9usLWYSi9W5zhrcB4tDivg+8F rG0SKQgHIaMrljhBuftRSrrMzMlmX7sv7X/nbBzEfPpr4uFCe0aeQ/QeFVY9ivt+m2rt 6caoTxSwOsZtNBvuK8Uv2Xb3Ucph+zLpeC9zzBfwQZyNcZ1y2api8ExcqoX1lHrCYBbY VZlYDWZsZfYaCvI2x88vkCHX1Y8RVfwU1TGNPBlBZld5iOhPsecsQA0w/xRmzlGIOZQt fEeg== X-Gm-Message-State: ACrzQf0uVRbnmhgB2WST7UJOUfm/3LDZjhLmrsBCm4Rt6CoYggOQFXK6 RKeSOhYlzNEfCdeS6bIzCTzRSBn08MdVig== X-Google-Smtp-Source: AMsMyM6k18I2uPBk7EVjxPo0/as1WHSxOol4b68sFNkUtBn6HYC/o/nrPmjPI5My47pGc6CPNV7a+g== X-Received: by 2002:a17:906:5dda:b0:78d:e7d2:7499 with SMTP id p26-20020a1709065dda00b0078de7d27499mr20470091ejv.588.1666451239350; Sat, 22 Oct 2022 08:07:19 -0700 (PDT) Received: from localhost.localdomain (dynamic-077-191-171-138.77.191.pool.telefonica.de. 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Tsirkin" , Paolo Bonzini , Bernhard Beschow Subject: [PATCH v2 35/43] hw/isa/piix4: Prefix pci_slot_get_pirq() with "piix4_" Date: Sat, 22 Oct 2022 17:05:00 +0200 Message-Id: <20221022150508.26830-36-shentey@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221022150508.26830-1-shentey@gmail.com> References: <20221022150508.26830-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::52b; envelope-from=shentey@gmail.com; helo=mail-ed1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Prefixing with "piix4_" makes the method distinguishable from its PIIX3 counterpart upon merging and also complies more with QEMU conventions. Signed-off-by: Bernhard Beschow --- hw/isa/piix4.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index 2f5b6fc934..dd189fa594 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -63,7 +63,7 @@ static void piix4_set_irq(void *opaque, int irq_num, int level) } } -static int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num) +static int piix4_pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num) { int slot; @@ -249,7 +249,8 @@ static void piix4_realize(PCIDevice *dev, Error **errp) qdev_get_gpio_in(DEVICE(&s->pic), 9)); } - pci_bus_irqs(pci_bus, piix4_set_irq, pci_slot_get_pirq, s, PIIX_NUM_PIRQS); + pci_bus_irqs(pci_bus, piix4_set_irq, piix4_pci_slot_get_pirq, s, + PIIX_NUM_PIRQS); } static void piix4_init(Object *obj) From patchwork Sat Oct 22 15:05:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 13016473 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9748AC3A59D for ; Mon, 24 Oct 2022 00:48:57 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1omhiK-00024y-TL for qemu-devel@archiver.kernel.org; Sun, 23 Oct 2022 16:36:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1omG5u-0007Pp-Fy; Sat, 22 Oct 2022 11:07:26 -0400 Received: from mail-ed1-x533.google.com ([2a00:1450:4864:20::533]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1omG5r-0002Nu-OF; Sat, 22 Oct 2022 11:07:26 -0400 Received: by mail-ed1-x533.google.com with SMTP id w8so13818698edc.1; Sat, 22 Oct 2022 08:07:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=b85qsEMV/N3kNPdCtsSKNM47zqNqdh3ucQkb83uNYaw=; b=V9UtmQ3wMBqO1za1BT385VwOU2YYbITwXBuzeNrFDZPZUEwfS2pnOLNLH0Nw8701NF iPn84Px6orAViYSEppz3PZ0Ba8GqIZ3Rwpy55p+o6dU6rH5qEh0oC6qAidCH8IlcAMMk 1lCqeENgk2tUkonmqPeIo19NsbyLFfd66BSax6gC1U34pFAbujgAUwDfHLbeczi7wY0w +RD8CAi3Y7hJOsCr5shoFivkpPxJG6bGTMm3gjM77KSGXpZRnIJTjFspUP/bwB5WBS6k UPvSEqBtFYBnlvYsYLeyttIFYnTkRy5DFzy2dtRQcxeQ7szK3cZNiek6Mayr30lfBcX5 Af9Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=b85qsEMV/N3kNPdCtsSKNM47zqNqdh3ucQkb83uNYaw=; b=2Js/B3jvu+s1ELrkq21/zdraq3vhqc/UrB0q3n/ZY+bBnrt24MzIiA3qUO+vRrGAaW 1t8QdWg1PisqatgAehr5xHnOI0TR6FUUJPXp1L45+arbVvWKMcRXUNQ1YNzJ/VMhtqS0 31eqpAA6NITDVVmlCf8erRX3bXEy2UMDWNub6udkJ4jzQ48U7mXcDvX11du0ssK1u/Mz D21fhtCMo8LdPjzj1lWIpaU2ckQUvANC+Ru+s5VmuA+DkxBNf9Tqy5QBzknNV0mJVmoW 34Ia6O/imZotxib3pUNn2DLKbDKr0gKx+jw0MQNZm5pTo1PUhtHmqxFvHImRzXswE4md xdug== X-Gm-Message-State: ACrzQf0ZvK6aQryXVko9jZjqIzJj5zr90YAJbduV4IThAjppQFq4F9yJ 6oPnF4rAUYH1IZl3gD0Fcy9lmL1r4GEjuw== X-Google-Smtp-Source: AMsMyM6P65HbTz6l/KSUoOs9S809rQWzNpA7LKa6riwItoEvxFySy91XJEuemSQy57bZgDBIYHGr0Q== X-Received: by 2002:a17:907:3f90:b0:78d:afad:2a78 with SMTP id hr16-20020a1709073f9000b0078dafad2a78mr20738461ejc.68.1666451241542; Sat, 22 Oct 2022 08:07:21 -0700 (PDT) Received: from localhost.localdomain (dynamic-077-191-171-138.77.191.pool.telefonica.de. [77.191.171.138]) by smtp.gmail.com with ESMTPSA id 4-20020a170906310400b00780ab5a9116sm13021558ejx.211.2022.10.22.08.07.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 22 Oct 2022 08:07:20 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Eduardo Habkost , =?utf-8?q?Herv=C3=A9_Poussineau?= , Aurelien Jarno , Igor Mammedov , Gerd Hoffmann , John Snow , Jiaxun Yang , Ani Sinha , Marcel Apfelbaum , qemu-block@nongnu.org, Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , "Michael S. Tsirkin" , Paolo Bonzini , Bernhard Beschow Subject: [PATCH v2 36/43] hw/isa/piix3: Merge hw/isa/piix4.c Date: Sat, 22 Oct 2022 17:05:01 +0200 Message-Id: <20221022150508.26830-37-shentey@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221022150508.26830-1-shentey@gmail.com> References: <20221022150508.26830-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::533; envelope-from=shentey@gmail.com; helo=mail-ed1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Now that the PIIX3 and PIIX4 device models are sufficiently consolidated Signed-off-by: Bernhard Beschow --- MAINTAINERS | 6 +- configs/devices/mips-softmmu/common.mak | 2 +- hw/i386/Kconfig | 2 +- hw/isa/Kconfig | 12 +- hw/isa/meson.build | 3 +- hw/isa/{piix3.c => piix.c} | 185 ++++++++++++++ hw/isa/piix4.c | 315 ------------------------ 7 files changed, 192 insertions(+), 333 deletions(-) rename hw/isa/{piix3.c => piix.c} (73%) delete mode 100644 hw/isa/piix4.c diff --git a/MAINTAINERS b/MAINTAINERS index e3d5b7e09c..f08f095222 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1228,7 +1228,7 @@ Malta M: Philippe Mathieu-Daudé R: Aurelien Jarno S: Odd Fixes -F: hw/isa/piix4.c +F: hw/isa/piix.c F: hw/acpi/piix4.c F: hw/mips/malta.c F: hw/mips/gt64xxx_pci.c @@ -1643,7 +1643,7 @@ F: hw/pci-host/pam.c F: include/hw/pci-host/i440fx.h F: include/hw/pci-host/q35.h F: include/hw/pci-host/pam.h -F: hw/isa/piix3.c +F: hw/isa/piix.c F: hw/isa/lpc_ich9.c F: hw/i2c/smbus_ich9.c F: hw/acpi/piix4.c @@ -2314,7 +2314,7 @@ PIIX4 South Bridge (i82371AB) M: Hervé Poussineau M: Philippe Mathieu-Daudé S: Maintained -F: hw/isa/piix4.c +F: hw/isa/piix.c F: include/hw/southbridge/piix.h Firmware configuration (fw_cfg) diff --git a/configs/devices/mips-softmmu/common.mak b/configs/devices/mips-softmmu/common.mak index 416161f833..ef3b7390a6 100644 --- a/configs/devices/mips-softmmu/common.mak +++ b/configs/devices/mips-softmmu/common.mak @@ -21,7 +21,7 @@ CONFIG_ACPI=y CONFIG_ACPI_PIIX4=y CONFIG_APM=y CONFIG_I8257=y -CONFIG_PIIX4=y +CONFIG_PIIX=y CONFIG_IDE_ISA=y CONFIG_PFLASH_CFI01=y CONFIG_I8259=y diff --git a/hw/i386/Kconfig b/hw/i386/Kconfig index dd247f215c..295693b32b 100644 --- a/hw/i386/Kconfig +++ b/hw/i386/Kconfig @@ -73,7 +73,7 @@ config I440FX select PC_ACPI select ACPI_SMBUS select PCI_I440FX - select PIIX3 + select PIIX select DIMM select SMBIOS select FW_CFG_DMA diff --git a/hw/isa/Kconfig b/hw/isa/Kconfig index 1aa10f84f2..000c2312ab 100644 --- a/hw/isa/Kconfig +++ b/hw/isa/Kconfig @@ -31,17 +31,7 @@ config PC87312 select FDC_ISA select IDE_ISA -config PIIX3 - bool - select ACPI_PIIX4 - select I8257 - select I8259 - select IDE_PIIX - select ISA_BUS - select MC146818RTC - select USB_UHCI - -config PIIX4 +config PIIX bool # For historical reasons, SuperIO devices are created in the board # for PIIX4. diff --git a/hw/isa/meson.build b/hw/isa/meson.build index 8bf678ca0a..314bbd0860 100644 --- a/hw/isa/meson.build +++ b/hw/isa/meson.build @@ -3,8 +3,7 @@ softmmu_ss.add(when: 'CONFIG_I82378', if_true: files('i82378.c')) softmmu_ss.add(when: 'CONFIG_ISA_BUS', if_true: files('isa-bus.c')) softmmu_ss.add(when: 'CONFIG_ISA_SUPERIO', if_true: files('isa-superio.c')) softmmu_ss.add(when: 'CONFIG_PC87312', if_true: files('pc87312.c')) -softmmu_ss.add(when: 'CONFIG_PIIX3', if_true: files('piix3.c')) -softmmu_ss.add(when: 'CONFIG_PIIX4', if_true: files('piix4.c')) +softmmu_ss.add(when: 'CONFIG_PIIX', if_true: files('piix.c')) softmmu_ss.add(when: 'CONFIG_SMC37C669', if_true: files('smc37c669-superio.c')) softmmu_ss.add(when: 'CONFIG_VT82C686', if_true: files('vt82c686.c')) diff --git a/hw/isa/piix3.c b/hw/isa/piix.c similarity index 73% rename from hw/isa/piix3.c rename to hw/isa/piix.c index b02a91c8eb..5123474fab 100644 --- a/hw/isa/piix3.c +++ b/hw/isa/piix.c @@ -2,6 +2,7 @@ * QEMU PIIX PCI ISA Bridge Emulation * * Copyright (c) 2006 Fabrice Bellard + * Copyright (c) 2018 Hervé Poussineau * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -26,7 +27,9 @@ #include "qemu/range.h" #include "qapi/error.h" #include "hw/dma/i8257.h" +#include "hw/intc/i8259.h" #include "hw/southbridge/piix.h" +#include "hw/timer/i8254.h" #include "hw/irq.h" #include "hw/qdev-properties.h" #include "hw/ide/piix.h" @@ -81,6 +84,27 @@ static void piix3_set_irq(void *opaque, int pirq, int level) piix3_set_irq_level(piix3, pirq, level); } +static void piix4_set_irq(void *opaque, int irq_num, int level) +{ + int i, pic_irq, pic_level; + PIIXState *s = opaque; + PCIBus *bus = pci_get_bus(&s->dev); + + /* now we change the pic irq level according to the piix irq mappings */ + /* XXX: optimize */ + pic_irq = s->dev.config[PIIX_PIRQCA + irq_num]; + if (pic_irq < ISA_NUM_IRQS) { + /* The pic level is the logical OR of all the PCI irqs mapped to it. */ + pic_level = 0; + for (i = 0; i < PIIX_NUM_PIRQS; i++) { + if (pic_irq == s->dev.config[PIIX_PIRQCA + i]) { + pic_level |= pci_bus_get_irq_level(bus, i); + } + } + qemu_set_irq(s->pic.in_irqs[pic_irq], pic_level); + } +} + /* * Return the global irq number corresponding to a given device irq * pin. We could also use the bus number to have a more precise mapping. @@ -92,6 +116,31 @@ static int piix3_pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx) return (pci_intx + slot_addend) & 3; } +static int piix4_pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num) +{ + int slot; + + slot = PCI_SLOT(pci_dev->devfn); + + switch (slot) { + /* PIIX4 USB */ + case 10: + return 3; + /* AMD 79C973 Ethernet */ + case 11: + return 1; + /* Crystal 4281 Sound */ + case 12: + return 2; + /* PCI slot 1 to 4 */ + case 18 ... 21: + return ((slot - 18) + irq_num) & 0x03; + /* Unknown device, don't do any translation */ + default: + return irq_num; + } +} + static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin) { PIIXState *piix3 = opaque; @@ -219,6 +268,17 @@ static int piix3_post_load(void *opaque, int version_id) return 0; } +static int piix4_post_load(void *opaque, int version_id) +{ + PIIXState *s = opaque; + + if (version_id == 2) { + s->rcr = 0; + } + + return 0; +} + static int piix3_pre_save(void *opaque) { int i; @@ -268,6 +328,17 @@ static const VMStateDescription vmstate_piix3 = { } }; +static const VMStateDescription vmstate_piix4 = { + .name = "PIIX4", + .version_id = 3, + .minimum_version_id = 2, + .post_load = piix4_post_load, + .fields = (VMStateField[]) { + VMSTATE_PCI_DEVICE(dev, PIIXState), + VMSTATE_UINT8_V(rcr, PIIXState, 3), + VMSTATE_END_OF_LIST() + } +}; static void rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned len) { @@ -495,11 +566,125 @@ static const TypeInfo piix3_xen_info = { .class_init = piix3_xen_class_init, }; +static void piix4_realize(PCIDevice *dev, Error **errp) +{ + PIIXState *s = PIIX_PCI_DEVICE(dev); + PCIBus *pci_bus = pci_get_bus(dev); + ISABus *isa_bus; + + isa_bus = isa_bus_new(DEVICE(dev), pci_address_space(dev), + pci_address_space_io(dev), errp); + if (!isa_bus) { + return; + } + + memory_region_init_io(&s->rcr_mem, OBJECT(dev), &rcr_ops, s, + "reset-control", 1); + memory_region_add_subregion_overlap(pci_address_space_io(dev), + PIIX_RCR_IOPORT, &s->rcr_mem, 1); + + /* initialize i8259 pic */ + if (!qdev_realize(DEVICE(&s->pic), BUS(isa_bus), errp)) { + return; + } + + /* initialize ISA irqs */ + isa_bus_irqs(isa_bus, s->pic.in_irqs); + + /* initialize pit */ + i8254_pit_init(isa_bus, 0x40, 0, NULL); + + /* DMA */ + i8257_dma_init(isa_bus, 0); + + /* RTC */ + qdev_prop_set_int32(DEVICE(&s->rtc), "base_year", 2000); + if (!qdev_realize(DEVICE(&s->rtc), BUS(isa_bus), errp)) { + return; + } + s->rtc.irq = qdev_get_gpio_in(DEVICE(&s->pic), s->rtc.isairq); + + /* IDE */ + qdev_prop_set_int32(DEVICE(&s->ide), "addr", dev->devfn + 1); + if (!qdev_realize(DEVICE(&s->ide), BUS(pci_bus), errp)) { + return; + } + + /* USB */ + if (s->has_usb) { + object_initialize_child(OBJECT(dev), "uhci", &s->uhci, + TYPE_PIIX4_USB_UHCI); + qdev_prop_set_int32(DEVICE(&s->uhci), "addr", dev->devfn + 2); + if (!qdev_realize(DEVICE(&s->uhci), BUS(pci_bus), errp)) { + return; + } + } + + /* ACPI controller */ + if (s->has_acpi) { + object_initialize_child(OBJECT(s), "pm", &s->pm, TYPE_PIIX4_PM); + qdev_prop_set_int32(DEVICE(&s->pm), "addr", dev->devfn + 3); + qdev_prop_set_uint32(DEVICE(&s->pm), "smb_io_base", s->smb_io_base); + qdev_prop_set_bit(DEVICE(&s->pm), "smm-enabled", s->smm_enabled); + if (!qdev_realize(DEVICE(&s->pm), BUS(pci_bus), errp)) { + return; + } + qdev_connect_gpio_out(DEVICE(&s->pm), 0, + qdev_get_gpio_in(DEVICE(&s->pic), 9)); + } + + pci_bus_irqs(pci_bus, piix4_set_irq, piix4_pci_slot_get_pirq, s, + PIIX_NUM_PIRQS); +} + +static void piix4_init(Object *obj) +{ + PIIXState *s = PIIX_PCI_DEVICE(obj); + + object_initialize_child(obj, "pic", &s->pic, TYPE_ISA_PIC); + object_initialize_child(obj, "rtc", &s->rtc, TYPE_MC146818_RTC); + object_initialize_child(obj, "ide", &s->ide, TYPE_PIIX4_IDE); +} + +static void piix4_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); + + k->realize = piix4_realize; + k->vendor_id = PCI_VENDOR_ID_INTEL; + k->device_id = PCI_DEVICE_ID_INTEL_82371AB_0; + k->class_id = PCI_CLASS_BRIDGE_ISA; + dc->reset = piix_reset; + dc->desc = "ISA bridge"; + dc->vmsd = &vmstate_piix4; + /* + * Reason: part of PIIX4 southbridge, needs to be wired up, + * e.g. by mips_malta_init() + */ + dc->user_creatable = false; + dc->hotpluggable = false; + device_class_set_props(dc, pci_piix_props); +} + +static const TypeInfo piix4_info = { + .name = TYPE_PIIX4_PCI_DEVICE, + .parent = TYPE_PCI_DEVICE, + .instance_size = sizeof(PIIXState), + .instance_init = piix4_init, + .class_init = piix4_class_init, + .interfaces = (InterfaceInfo[]) { + { INTERFACE_CONVENTIONAL_PCI_DEVICE }, + { }, + }, +}; + static void piix3_register_types(void) { type_register_static(&piix3_pci_type_info); type_register_static(&piix3_info); type_register_static(&piix3_xen_info); + type_register_static(&piix4_info); } type_init(piix3_register_types) diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c deleted file mode 100644 index dd189fa594..0000000000 --- a/hw/isa/piix4.c +++ /dev/null @@ -1,315 +0,0 @@ -/* - * QEMU PIIX4 PCI Bridge Emulation - * - * Copyright (c) 2006 Fabrice Bellard - * Copyright (c) 2018 Hervé Poussineau - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include "qemu/osdep.h" -#include "qapi/error.h" -#include "hw/irq.h" -#include "hw/southbridge/piix.h" -#include "hw/pci/pci.h" -#include "hw/ide/piix.h" -#include "hw/isa/isa.h" -#include "hw/intc/i8259.h" -#include "hw/dma/i8257.h" -#include "hw/timer/i8254.h" -#include "hw/rtc/mc146818rtc.h" -#include "hw/ide/pci.h" -#include "hw/acpi/piix4.h" -#include "hw/usb/hcd-uhci.h" -#include "migration/vmstate.h" -#include "sysemu/reset.h" -#include "sysemu/runstate.h" -#include "qom/object.h" - -static void piix4_set_irq(void *opaque, int irq_num, int level) -{ - int i, pic_irq, pic_level; - PIIXState *s = opaque; - PCIBus *bus = pci_get_bus(&s->dev); - - /* now we change the pic irq level according to the piix irq mappings */ - /* XXX: optimize */ - pic_irq = s->dev.config[PIIX_PIRQCA + irq_num]; - if (pic_irq < ISA_NUM_IRQS) { - /* The pic level is the logical OR of all the PCI irqs mapped to it. */ - pic_level = 0; - for (i = 0; i < PIIX_NUM_PIRQS; i++) { - if (pic_irq == s->dev.config[PIIX_PIRQCA + i]) { - pic_level |= pci_bus_get_irq_level(bus, i); - } - } - qemu_set_irq(s->pic.in_irqs[pic_irq], pic_level); - } -} - -static int piix4_pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num) -{ - int slot; - - slot = PCI_SLOT(pci_dev->devfn); - - switch (slot) { - /* PIIX4 USB */ - case 10: - return 3; - /* AMD 79C973 Ethernet */ - case 11: - return 1; - /* Crystal 4281 Sound */ - case 12: - return 2; - /* PCI slot 1 to 4 */ - case 18 ... 21: - return ((slot - 18) + irq_num) & 0x03; - /* Unknown device, don't do any translation */ - default: - return irq_num; - } -} - -static void piix4_isa_reset(DeviceState *dev) -{ - PIIXState *d = PIIX_PCI_DEVICE(dev); - uint8_t *pci_conf = d->dev.config; - - pci_conf[0x04] = 0x07; // master, memory and I/O - pci_conf[0x05] = 0x00; - pci_conf[0x06] = 0x00; - pci_conf[0x07] = 0x02; // PCI_status_devsel_medium - pci_conf[0x4c] = 0x4d; - pci_conf[0x4e] = 0x03; - pci_conf[0x4f] = 0x00; - pci_conf[PIIX_PIRQCA] = d->pci_irq_reset_mappings[0]; - pci_conf[PIIX_PIRQCB] = d->pci_irq_reset_mappings[1]; - pci_conf[PIIX_PIRQCC] = d->pci_irq_reset_mappings[2]; - pci_conf[PIIX_PIRQCD] = d->pci_irq_reset_mappings[3]; - pci_conf[0x69] = 0x02; - pci_conf[0x70] = 0x80; - pci_conf[0x76] = 0x0c; - pci_conf[0x77] = 0x0c; - pci_conf[0x78] = 0x02; - pci_conf[0x79] = 0x00; - pci_conf[0x80] = 0x00; - pci_conf[0x82] = 0x00; - pci_conf[0xa0] = 0x08; - pci_conf[0xa2] = 0x00; - pci_conf[0xa3] = 0x00; - pci_conf[0xa4] = 0x00; - pci_conf[0xa5] = 0x00; - pci_conf[0xa6] = 0x00; - pci_conf[0xa7] = 0x00; - pci_conf[0xa8] = 0x0f; - pci_conf[0xaa] = 0x00; - pci_conf[0xab] = 0x00; - pci_conf[0xac] = 0x00; - pci_conf[0xae] = 0x00; - - d->pic_levels = 0; /* not used in PIIX4 */ - d->rcr = 0; -} - -static int piix4_post_load(void *opaque, int version_id) -{ - PIIXState *s = opaque; - - if (version_id == 2) { - s->rcr = 0; - } - - return 0; -} - -static const VMStateDescription vmstate_piix4 = { - .name = "PIIX4", - .version_id = 3, - .minimum_version_id = 2, - .post_load = piix4_post_load, - .fields = (VMStateField[]) { - VMSTATE_PCI_DEVICE(dev, PIIXState), - VMSTATE_UINT8_V(rcr, PIIXState, 3), - VMSTATE_END_OF_LIST() - } -}; - -static void rcr_write(void *opaque, hwaddr addr, uint64_t val, - unsigned int len) -{ - PIIXState *s = opaque; - - if (val & 4) { - qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); - return; - } - - s->rcr = val & 2; /* keep System Reset type only */ -} - -static uint64_t rcr_read(void *opaque, hwaddr addr, unsigned int len) -{ - PIIXState *s = opaque; - - return s->rcr; -} - -static const MemoryRegionOps rcr_ops = { - .read = rcr_read, - .write = rcr_write, - .endianness = DEVICE_LITTLE_ENDIAN, - .impl = { - .min_access_size = 1, - .max_access_size = 1, - }, -}; - -static void piix4_realize(PCIDevice *dev, Error **errp) -{ - PIIXState *s = PIIX_PCI_DEVICE(dev); - PCIBus *pci_bus = pci_get_bus(dev); - ISABus *isa_bus; - - isa_bus = isa_bus_new(DEVICE(dev), pci_address_space(dev), - pci_address_space_io(dev), errp); - if (!isa_bus) { - return; - } - - memory_region_init_io(&s->rcr_mem, OBJECT(dev), &rcr_ops, s, - "reset-control", 1); - memory_region_add_subregion_overlap(pci_address_space_io(dev), - PIIX_RCR_IOPORT, &s->rcr_mem, 1); - - /* initialize i8259 pic */ - if (!qdev_realize(DEVICE(&s->pic), BUS(isa_bus), errp)) { - return; - } - - /* initialize ISA irqs */ - isa_bus_irqs(isa_bus, s->pic.in_irqs); - - /* initialize pit */ - i8254_pit_init(isa_bus, 0x40, 0, NULL); - - /* DMA */ - i8257_dma_init(isa_bus, 0); - - /* RTC */ - qdev_prop_set_int32(DEVICE(&s->rtc), "base_year", 2000); - if (!qdev_realize(DEVICE(&s->rtc), BUS(isa_bus), errp)) { - return; - } - s->rtc.irq = qdev_get_gpio_in(DEVICE(&s->pic), s->rtc.isairq); - - /* IDE */ - qdev_prop_set_int32(DEVICE(&s->ide), "addr", dev->devfn + 1); - if (!qdev_realize(DEVICE(&s->ide), BUS(pci_bus), errp)) { - return; - } - - /* USB */ - if (s->has_usb) { - object_initialize_child(OBJECT(dev), "uhci", &s->uhci, - TYPE_PIIX4_USB_UHCI); - qdev_prop_set_int32(DEVICE(&s->uhci), "addr", dev->devfn + 2); - if (!qdev_realize(DEVICE(&s->uhci), BUS(pci_bus), errp)) { - return; - } - } - - /* ACPI controller */ - if (s->has_acpi) { - object_initialize_child(OBJECT(s), "pm", &s->pm, TYPE_PIIX4_PM); - qdev_prop_set_int32(DEVICE(&s->pm), "addr", dev->devfn + 3); - qdev_prop_set_uint32(DEVICE(&s->pm), "smb_io_base", s->smb_io_base); - qdev_prop_set_bit(DEVICE(&s->pm), "smm-enabled", s->smm_enabled); - if (!qdev_realize(DEVICE(&s->pm), BUS(pci_bus), errp)) { - return; - } - qdev_connect_gpio_out(DEVICE(&s->pm), 0, - qdev_get_gpio_in(DEVICE(&s->pic), 9)); - } - - pci_bus_irqs(pci_bus, piix4_set_irq, piix4_pci_slot_get_pirq, s, - PIIX_NUM_PIRQS); -} - -static void piix4_init(Object *obj) -{ - PIIXState *s = PIIX_PCI_DEVICE(obj); - - object_initialize_child(obj, "pic", &s->pic, TYPE_ISA_PIC); - object_initialize_child(obj, "rtc", &s->rtc, TYPE_MC146818_RTC); - object_initialize_child(obj, "ide", &s->ide, TYPE_PIIX4_IDE); -} - -static Property piix4_props[] = { - DEFINE_PROP_UINT32("smb_io_base", PIIXState, smb_io_base, 0), - DEFINE_PROP_UINT8("pirqa", PIIXState, pci_irq_reset_mappings[0], 0x80), - DEFINE_PROP_UINT8("pirqb", PIIXState, pci_irq_reset_mappings[1], 0x80), - DEFINE_PROP_UINT8("pirqc", PIIXState, pci_irq_reset_mappings[2], 0x80), - DEFINE_PROP_UINT8("pirqd", PIIXState, pci_irq_reset_mappings[3], 0x80), - DEFINE_PROP_BOOL("has-acpi", PIIXState, has_acpi, true), - DEFINE_PROP_BOOL("has-usb", PIIXState, has_usb, true), - DEFINE_PROP_BOOL("smm-enabled", PIIXState, smm_enabled, false), - DEFINE_PROP_END_OF_LIST(), -}; - -static void piix4_class_init(ObjectClass *klass, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(klass); - PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); - - k->realize = piix4_realize; - k->vendor_id = PCI_VENDOR_ID_INTEL; - k->device_id = PCI_DEVICE_ID_INTEL_82371AB_0; - k->class_id = PCI_CLASS_BRIDGE_ISA; - dc->reset = piix4_isa_reset; - dc->desc = "ISA bridge"; - dc->vmsd = &vmstate_piix4; - /* - * Reason: part of PIIX4 southbridge, needs to be wired up, - * e.g. by mips_malta_init() - */ - dc->user_creatable = false; - dc->hotpluggable = false; - device_class_set_props(dc, piix4_props); -} - -static const TypeInfo piix4_info = { - .name = TYPE_PIIX4_PCI_DEVICE, - .parent = TYPE_PCI_DEVICE, - .instance_size = sizeof(PIIXState), - .instance_init = piix4_init, - .class_init = piix4_class_init, - .interfaces = (InterfaceInfo[]) { - { INTERFACE_CONVENTIONAL_PCI_DEVICE }, - { }, - }, -}; - -static void piix4_register_types(void) -{ - type_register_static(&piix4_info); -} - -type_init(piix4_register_types) From patchwork Sat Oct 22 15:05:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 13016592 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EBECBC38A2D for ; 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[77.191.171.138]) by smtp.gmail.com with ESMTPSA id 4-20020a170906310400b00780ab5a9116sm13021558ejx.211.2022.10.22.08.07.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 22 Oct 2022 08:07:22 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Eduardo Habkost , =?utf-8?q?Herv=C3=A9_Poussineau?= , Aurelien Jarno , Igor Mammedov , Gerd Hoffmann , John Snow , Jiaxun Yang , Ani Sinha , Marcel Apfelbaum , qemu-block@nongnu.org, Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , "Michael S. Tsirkin" , Paolo Bonzini , Bernhard Beschow Subject: [PATCH v2 37/43] hw/isa/piix: Harmonize names of reset control memory regions Date: Sat, 22 Oct 2022 17:05:02 +0200 Message-Id: <20221022150508.26830-38-shentey@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221022150508.26830-1-shentey@gmail.com> References: <20221022150508.26830-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::530; envelope-from=shentey@gmail.com; helo=mail-ed1-x530.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" There is no need for having different names here. Having the same name further allows code to be shared between PIIX3 and PIIX4. Signed-off-by: Bernhard Beschow Reviewed-by: Philippe Mathieu-Daudé --- hw/isa/piix.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/isa/piix.c b/hw/isa/piix.c index 5123474fab..55ed997b2c 100644 --- a/hw/isa/piix.c +++ b/hw/isa/piix.c @@ -388,7 +388,7 @@ static void pci_piix3_realize(PCIDevice *dev, Error **errp) isa_bus_irqs(isa_bus, d->pic.in_irqs); memory_region_init_io(&d->rcr_mem, OBJECT(dev), &rcr_ops, d, - "piix3-reset-control", 1); + "piix-reset-control", 1); memory_region_add_subregion_overlap(pci_address_space_io(dev), PIIX_RCR_IOPORT, &d->rcr_mem, 1); @@ -579,7 +579,7 @@ static void piix4_realize(PCIDevice *dev, Error **errp) } memory_region_init_io(&s->rcr_mem, OBJECT(dev), &rcr_ops, s, - "reset-control", 1); + "piix-reset-control", 1); memory_region_add_subregion_overlap(pci_address_space_io(dev), PIIX_RCR_IOPORT, &s->rcr_mem, 1); From patchwork Sat Oct 22 15:05:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 13016457 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C6B19C433FE for ; Sun, 23 Oct 2022 22:00:18 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1omhkN-0002TP-GP for qemu-devel@archiver.kernel.org; Sun, 23 Oct 2022 16:39:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1omG5v-0007QQ-Rk; Sat, 22 Oct 2022 11:07:27 -0400 Received: from mail-ed1-x52e.google.com ([2a00:1450:4864:20::52e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1omG5u-0002Cw-8y; Sat, 22 Oct 2022 11:07:27 -0400 Received: by mail-ed1-x52e.google.com with SMTP id a5so3033479edb.11; Sat, 22 Oct 2022 08:07:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=G5VRKJ9oOgZLszvvmXXLT1GczcYM83JN+GujG1qoV1k=; b=EqXtpoQKO62m5E+TvkrH6zT/trq+JMWOV/NrOv+UdLSwrSKakekPHGSHSxBb/Sl9OD QZEAF6MqAeOGlAEINa+wfuNxaaPqnyd67TIboclITsaDs2WntK92lXH3OAkHRC1nw/Cp 3JC6rqZJYwtd2v8u06wwGrgO4DfUdUUIYjXXrdjhiMCh5CGOy+yLJ1c5AHLNjKucnqI/ ZocQoz6HaInlkT+23MN2U3O/Yv08QVBgwwBKV9fp1P4R70AiWEa1PgaTogk7Ey+Yrbfp 185Wb79/Mx5tMLmms/tVKuCsdE99OkPWg/jVG6bHiqnNabzqpTtZe4Dd9N4u7Mx8RYy5 dmiw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=G5VRKJ9oOgZLszvvmXXLT1GczcYM83JN+GujG1qoV1k=; b=pRTDPr9PITxD1vzIIDpMaMNXZs7jD/YdV+KK/9sJOcpXRGRQjrVrsIaftA3YAOMUi7 icJ/a1ckXLwcVcUpHGk6VRhY0BaiDt8Me5URUxAWcdt4wR9iCF9REtzTclimjKUJz+jP XX2mcSkTRnvJUD46jDGga7dDp5GgPFfudoLWe/a5dzo451VlstAURHAKAlGA5S20X9IW 8vqkxQZ4e/KJFBCnuFuWd7NySGAw5s+SvpVjNj4n+CCpMm1NB2TkSEh/FTCX9GPbsSrf rfbi89ciJNu4q+mJOprxn7d2PaI2MEwWGp+6+UXrmcsne+jR/nie9xS7u3DCecHo3P/I LaaQ== X-Gm-Message-State: ACrzQf0w5M5qOqABHjk+GJj/Bh4X9SMckax02EF2zxKAIyl8BJ/rXbOf /14WAt0LwC5LxngpdwITUxUs1Optq9Fbvw== X-Google-Smtp-Source: AMsMyM6bsvwIZfZME2wx3nodlxN6buZOVFvyB5wgj5ObVfJ8Np+fpdojRY7I4NDxLtj+lTAifFUCRA== X-Received: by 2002:a17:907:7286:b0:7a1:ba0:7d7a with SMTP id dt6-20020a170907728600b007a10ba07d7amr2844135ejc.227.1666451244895; Sat, 22 Oct 2022 08:07:24 -0700 (PDT) Received: from localhost.localdomain (dynamic-077-191-171-138.77.191.pool.telefonica.de. [77.191.171.138]) by smtp.gmail.com with ESMTPSA id 4-20020a170906310400b00780ab5a9116sm13021558ejx.211.2022.10.22.08.07.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 22 Oct 2022 08:07:24 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Eduardo Habkost , =?utf-8?q?Herv=C3=A9_Poussineau?= , Aurelien Jarno , Igor Mammedov , Gerd Hoffmann , John Snow , Jiaxun Yang , Ani Sinha , Marcel Apfelbaum , qemu-block@nongnu.org, Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , "Michael S. Tsirkin" , Paolo Bonzini , Bernhard Beschow Subject: [PATCH v2 38/43] hw/isa/piix: Reuse PIIX3 base class' realize method in PIIX4 Date: Sat, 22 Oct 2022 17:05:03 +0200 Message-Id: <20221022150508.26830-39-shentey@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221022150508.26830-1-shentey@gmail.com> References: <20221022150508.26830-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::52e; envelope-from=shentey@gmail.com; helo=mail-ed1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Resolves duplicate code. Signed-off-by: Bernhard Beschow --- hw/isa/piix.c | 65 +++++++-------------------------------------------- 1 file changed, 9 insertions(+), 56 deletions(-) diff --git a/hw/isa/piix.c b/hw/isa/piix.c index 55ed997b2c..9e7b11bcdd 100644 --- a/hw/isa/piix.c +++ b/hw/isa/piix.c @@ -368,7 +368,8 @@ static const MemoryRegionOps rcr_ops = { }, }; -static void pci_piix3_realize(PCIDevice *dev, Error **errp) +static void pci_piix_realize(PCIDevice *dev, const char *uhci_type, + Error **errp) { PIIXState *d = PIIX_PCI_DEVICE(dev); PCIBus *pci_bus = pci_get_bus(dev); @@ -408,8 +409,7 @@ static void pci_piix3_realize(PCIDevice *dev, Error **errp) /* USB */ if (d->has_usb) { - object_initialize_child(OBJECT(dev), "uhci", &d->uhci, - TYPE_PIIX3_USB_UHCI); + object_initialize_child(OBJECT(dev), "uhci", &d->uhci, uhci_type); qdev_prop_set_int32(DEVICE(&d->uhci), "addr", dev->devfn + 2); if (!qdev_realize(DEVICE(&d->uhci), BUS(pci_bus), errp)) { return; @@ -507,7 +507,7 @@ static void piix3_realize(PCIDevice *dev, Error **errp) PIIXState *piix3 = PIIX_PCI_DEVICE(dev); PCIBus *pci_bus = pci_get_bus(dev); - pci_piix3_realize(dev, errp); + pci_piix_realize(dev, TYPE_PIIX3_USB_UHCI, errp); if (*errp) { return; } @@ -537,7 +537,7 @@ static void piix3_xen_realize(PCIDevice *dev, Error **errp) PIIXState *piix3 = PIIX_PCI_DEVICE(dev); PCIBus *pci_bus = pci_get_bus(dev); - pci_piix3_realize(dev, errp); + pci_piix_realize(dev, TYPE_PIIX3_USB_UHCI, errp); if (*errp) { return; } @@ -568,71 +568,24 @@ static const TypeInfo piix3_xen_info = { static void piix4_realize(PCIDevice *dev, Error **errp) { + ERRP_GUARD(); PIIXState *s = PIIX_PCI_DEVICE(dev); PCIBus *pci_bus = pci_get_bus(dev); ISABus *isa_bus; - isa_bus = isa_bus_new(DEVICE(dev), pci_address_space(dev), - pci_address_space_io(dev), errp); - if (!isa_bus) { - return; - } - - memory_region_init_io(&s->rcr_mem, OBJECT(dev), &rcr_ops, s, - "piix-reset-control", 1); - memory_region_add_subregion_overlap(pci_address_space_io(dev), - PIIX_RCR_IOPORT, &s->rcr_mem, 1); - - /* initialize i8259 pic */ - if (!qdev_realize(DEVICE(&s->pic), BUS(isa_bus), errp)) { + pci_piix_realize(dev, TYPE_PIIX4_USB_UHCI, errp); + if (*errp) { return; } - /* initialize ISA irqs */ - isa_bus_irqs(isa_bus, s->pic.in_irqs); + isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(dev), "isa.0")); /* initialize pit */ i8254_pit_init(isa_bus, 0x40, 0, NULL); - /* DMA */ - i8257_dma_init(isa_bus, 0); - /* RTC */ - qdev_prop_set_int32(DEVICE(&s->rtc), "base_year", 2000); - if (!qdev_realize(DEVICE(&s->rtc), BUS(isa_bus), errp)) { - return; - } s->rtc.irq = qdev_get_gpio_in(DEVICE(&s->pic), s->rtc.isairq); - /* IDE */ - qdev_prop_set_int32(DEVICE(&s->ide), "addr", dev->devfn + 1); - if (!qdev_realize(DEVICE(&s->ide), BUS(pci_bus), errp)) { - return; - } - - /* USB */ - if (s->has_usb) { - object_initialize_child(OBJECT(dev), "uhci", &s->uhci, - TYPE_PIIX4_USB_UHCI); - qdev_prop_set_int32(DEVICE(&s->uhci), "addr", dev->devfn + 2); - if (!qdev_realize(DEVICE(&s->uhci), BUS(pci_bus), errp)) { - return; - } - } - - /* ACPI controller */ - if (s->has_acpi) { - object_initialize_child(OBJECT(s), "pm", &s->pm, TYPE_PIIX4_PM); - qdev_prop_set_int32(DEVICE(&s->pm), "addr", dev->devfn + 3); - qdev_prop_set_uint32(DEVICE(&s->pm), "smb_io_base", s->smb_io_base); - qdev_prop_set_bit(DEVICE(&s->pm), "smm-enabled", s->smm_enabled); - if (!qdev_realize(DEVICE(&s->pm), BUS(pci_bus), errp)) { - return; - } - qdev_connect_gpio_out(DEVICE(&s->pm), 0, - qdev_get_gpio_in(DEVICE(&s->pic), 9)); - } - pci_bus_irqs(pci_bus, piix4_set_irq, piix4_pci_slot_get_pirq, s, PIIX_NUM_PIRQS); } From patchwork Sat Oct 22 15:05:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 13016578 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BF788C3A59D for ; Mon, 24 Oct 2022 03:30:15 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1omhlM-0002d0-SF for qemu-devel@archiver.kernel.org; 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Tsirkin" , Paolo Bonzini , Bernhard Beschow Subject: [PATCH v2 39/43] hw/isa/piix: Rename functions to be shared for interrupt triggering Date: Sat, 22 Oct 2022 17:05:04 +0200 Message-Id: <20221022150508.26830-40-shentey@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221022150508.26830-1-shentey@gmail.com> References: <20221022150508.26830-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::535; envelope-from=shentey@gmail.com; helo=mail-ed1-x535.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" PIIX4 will get the same optimizations which are already implemented for PIIX3. Signed-off-by: Bernhard Beschow --- hw/isa/piix.c | 56 +++++++++++++++++++++++++-------------------------- 1 file changed, 28 insertions(+), 28 deletions(-) diff --git a/hw/isa/piix.c b/hw/isa/piix.c index 9e7b11bcdd..446105a7a1 100644 --- a/hw/isa/piix.c +++ b/hw/isa/piix.c @@ -41,47 +41,47 @@ #define XEN_PIIX_NUM_PIRQS 128ULL -static void piix3_set_irq_pic(PIIXState *piix3, int pic_irq) +static void piix_set_irq_pic(PIIXState *piix, int pic_irq) { - qemu_set_irq(piix3->pic.in_irqs[pic_irq], - !!(piix3->pic_levels & + qemu_set_irq(piix->pic.in_irqs[pic_irq], + !!(piix->pic_levels & (((1ULL << PIIX_NUM_PIRQS) - 1) << (pic_irq * PIIX_NUM_PIRQS)))); } -static void piix3_set_irq_level_internal(PIIXState *piix3, int pirq, int level) +static void piix_set_irq_level_internal(PIIXState *piix, int pirq, int level) { int pic_irq; uint64_t mask; - pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq]; + pic_irq = piix->dev.config[PIIX_PIRQCA + pirq]; if (pic_irq >= ISA_NUM_IRQS) { return; } mask = 1ULL << ((pic_irq * PIIX_NUM_PIRQS) + pirq); - piix3->pic_levels &= ~mask; - piix3->pic_levels |= mask * !!level; + piix->pic_levels &= ~mask; + piix->pic_levels |= mask * !!level; } -static void piix3_set_irq_level(PIIXState *piix3, int pirq, int level) +static void piix_set_irq_level(PIIXState *piix, int pirq, int level) { int pic_irq; - pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq]; + pic_irq = piix->dev.config[PIIX_PIRQCA + pirq]; if (pic_irq >= ISA_NUM_IRQS) { return; } - piix3_set_irq_level_internal(piix3, pirq, level); + piix_set_irq_level_internal(piix, pirq, level); - piix3_set_irq_pic(piix3, pic_irq); + piix_set_irq_pic(piix, pic_irq); } -static void piix3_set_irq(void *opaque, int pirq, int level) +static void piix_set_irq(void *opaque, int pirq, int level) { - PIIXState *piix3 = opaque; - piix3_set_irq_level(piix3, pirq, level); + PIIXState *piix = opaque; + piix_set_irq_level(piix, pirq, level); } static void piix4_set_irq(void *opaque, int irq_num, int level) @@ -158,29 +158,29 @@ static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin) } /* irq routing is changed. so rebuild bitmap */ -static void piix3_update_irq_levels(PIIXState *piix3) +static void piix_update_irq_levels(PIIXState *piix) { - PCIBus *bus = pci_get_bus(&piix3->dev); + PCIBus *bus = pci_get_bus(&piix->dev); int pirq; - piix3->pic_levels = 0; + piix->pic_levels = 0; for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) { - piix3_set_irq_level(piix3, pirq, pci_bus_get_irq_level(bus, pirq)); + piix_set_irq_level(piix, pirq, pci_bus_get_irq_level(bus, pirq)); } } -static void piix3_write_config(PCIDevice *dev, - uint32_t address, uint32_t val, int len) +static void piix_write_config(PCIDevice *dev, uint32_t address, uint32_t val, + int len) { pci_default_write_config(dev, address, val, len); if (ranges_overlap(address, len, PIIX_PIRQCA, 4)) { - PIIXState *piix3 = PIIX_PCI_DEVICE(dev); + PIIXState *piix = PIIX_PCI_DEVICE(dev); int pic_irq; - pci_bus_fire_intx_routing_notifier(pci_get_bus(&piix3->dev)); - piix3_update_irq_levels(piix3); + pci_bus_fire_intx_routing_notifier(pci_get_bus(&piix->dev)); + piix_update_irq_levels(piix); for (pic_irq = 0; pic_irq < ISA_NUM_IRQS; pic_irq++) { - piix3_set_irq_pic(piix3, pic_irq); + piix_set_irq_pic(piix, pic_irq); } } } @@ -202,7 +202,7 @@ static void piix3_write_config_xen(PCIDevice *dev, } } - piix3_write_config(dev, address, val, len); + piix_write_config(dev, address, val, len); } static void piix_reset(DeviceState *dev) @@ -262,7 +262,7 @@ static int piix3_post_load(void *opaque, int version_id) */ piix3->pic_levels = 0; for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) { - piix3_set_irq_level_internal(piix3, pirq, + piix_set_irq_level_internal(piix3, pirq, pci_bus_get_irq_level(pci_get_bus(&piix3->dev), pirq)); } return 0; @@ -512,7 +512,7 @@ static void piix3_realize(PCIDevice *dev, Error **errp) return; } - pci_bus_irqs(pci_bus, piix3_set_irq, piix3_pci_slot_get_pirq, + pci_bus_irqs(pci_bus, piix_set_irq, piix3_pci_slot_get_pirq, piix3, PIIX_NUM_PIRQS); pci_bus_set_route_irq_fn(pci_bus, piix3_route_intx_pin_to_irq); } @@ -521,7 +521,7 @@ static void piix3_class_init(ObjectClass *klass, void *data) { PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); - k->config_write = piix3_write_config; + k->config_write = piix_write_config; k->realize = piix3_realize; } From patchwork Sat Oct 22 15:05:05 2022 Content-Type: text/plain; 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[77.191.171.138]) by smtp.gmail.com with ESMTPSA id 4-20020a170906310400b00780ab5a9116sm13021558ejx.211.2022.10.22.08.07.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 22 Oct 2022 08:07:27 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Eduardo Habkost , =?utf-8?q?Herv=C3=A9_Poussineau?= , Aurelien Jarno , Igor Mammedov , Gerd Hoffmann , John Snow , Jiaxun Yang , Ani Sinha , Marcel Apfelbaum , qemu-block@nongnu.org, Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , "Michael S. Tsirkin" , Paolo Bonzini , Bernhard Beschow Subject: [PATCH v2 40/43] hw/isa/piix: Consolidate IRQ triggering Date: Sat, 22 Oct 2022 17:05:05 +0200 Message-Id: <20221022150508.26830-41-shentey@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221022150508.26830-1-shentey@gmail.com> References: <20221022150508.26830-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::52f; envelope-from=shentey@gmail.com; helo=mail-ed1-x52f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Speeds up PIIX4 which resolves an old TODO. Signed-off-by: Bernhard Beschow --- hw/isa/piix.c | 26 +++----------------------- 1 file changed, 3 insertions(+), 23 deletions(-) diff --git a/hw/isa/piix.c b/hw/isa/piix.c index 446105a7a1..4ced9995f9 100644 --- a/hw/isa/piix.c +++ b/hw/isa/piix.c @@ -84,27 +84,6 @@ static void piix_set_irq(void *opaque, int pirq, int level) piix_set_irq_level(piix, pirq, level); } -static void piix4_set_irq(void *opaque, int irq_num, int level) -{ - int i, pic_irq, pic_level; - PIIXState *s = opaque; - PCIBus *bus = pci_get_bus(&s->dev); - - /* now we change the pic irq level according to the piix irq mappings */ - /* XXX: optimize */ - pic_irq = s->dev.config[PIIX_PIRQCA + irq_num]; - if (pic_irq < ISA_NUM_IRQS) { - /* The pic level is the logical OR of all the PCI irqs mapped to it. */ - pic_level = 0; - for (i = 0; i < PIIX_NUM_PIRQS; i++) { - if (pic_irq == s->dev.config[PIIX_PIRQCA + i]) { - pic_level |= pci_bus_get_irq_level(bus, i); - } - } - qemu_set_irq(s->pic.in_irqs[pic_irq], pic_level); - } -} - /* * Return the global irq number corresponding to a given device irq * pin. We could also use the bus number to have a more precise mapping. @@ -276,7 +255,7 @@ static int piix4_post_load(void *opaque, int version_id) s->rcr = 0; } - return 0; + return piix3_post_load(opaque, version_id); } static int piix3_pre_save(void *opaque) @@ -586,7 +565,7 @@ static void piix4_realize(PCIDevice *dev, Error **errp) /* RTC */ s->rtc.irq = qdev_get_gpio_in(DEVICE(&s->pic), s->rtc.isairq); - pci_bus_irqs(pci_bus, piix4_set_irq, piix4_pci_slot_get_pirq, s, + pci_bus_irqs(pci_bus, piix_set_irq, piix4_pci_slot_get_pirq, s, PIIX_NUM_PIRQS); } @@ -604,6 +583,7 @@ static void piix4_class_init(ObjectClass *klass, void *data) DeviceClass *dc = DEVICE_CLASS(klass); PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); + k->config_write = piix_write_config; k->realize = piix4_realize; k->vendor_id = PCI_VENDOR_ID_INTEL; k->device_id = PCI_DEVICE_ID_INTEL_82371AB_0; From patchwork Sat Oct 22 15:05:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 13016507 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id ED0B0C433FE for ; Mon, 24 Oct 2022 02:42:40 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1omho3-00034I-L6 for qemu-devel@archiver.kernel.org; Sun, 23 Oct 2022 16:42:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1omG62-0007SQ-EZ; Sat, 22 Oct 2022 11:07:36 -0400 Received: from mail-ed1-x533.google.com ([2a00:1450:4864:20::533]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1omG60-0002Nu-Ny; Sat, 22 Oct 2022 11:07:34 -0400 Received: by mail-ed1-x533.google.com with SMTP id w8so13819712edc.1; Sat, 22 Oct 2022 08:07:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=dS8kM3DSSBc7NZLLCGrwBWo7nHrXayCI+lmThiiO5j4=; b=XcLQpUejmyyzv0DZCdR3ILoAOmfb+mHksgQeEtG6iej1Y8HAn7+RJcJr/XFhfX9ktg dZfFLcKE7aKfPfTiDb9/R4DwqxtNl4T67emxwhBN5aa2YrY20sEgj0wKxAyAeb1LZZBm JUW0gwDe6BzslHTUKODmi7rQUugGA+NnfnZPkvMywgJKwTg9mbS891YXY6efZhmC42mG Zh0yFIPQEscE24aAXw/Xzw71SJCI7PF+hFdf85Fwo37GlVZbDycfPgqPDmeTeZuhdNLH KRloBR01gUEEg/+VDa8ZnqFFfosy41hKva5ARfdO4KMU1GQmF7i6lQo2yjmxitRTTum1 vWnA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dS8kM3DSSBc7NZLLCGrwBWo7nHrXayCI+lmThiiO5j4=; b=QoX0rzBzykcDOWT1Z7V6VpuRs6cpF7u7GStqe9s+Pc2GWuHZ5X0o1k6PPVKuUGonvQ uZioCRela7mtHjmTDnXpOKgcJn8df6RuyVWRd1PkrXl9bb+O5bOVEOW2G2/nA+YkbvEi LEZ57CS3uOGQlILfW0AT5di8wZeb9ChlCkUVetut+6up5ELKETzChcLSTVifLDV5M107 p4f7JuE9EyYvzYAYuyfPqGXASlraGYMTnHijaa4ZysdkPqSeQyIGwZcSHWhLdqFB5MY2 Kep2xpVfZuiO+Wl9Io4Xshp6X+ABmrTfqfs1GRRGdLufDlHXxloTPnxouculVilk/oZB 2K3w== X-Gm-Message-State: ACrzQf2urYmEroDhIrgtnF/LMU3fUMUzPZIWiLiwyPkrkg+dAnWup/Is uaUI7rEET+T1pFdEQ+QBQK4mU2E3YG9Kbg== X-Google-Smtp-Source: AMsMyM5zgrMsA+ioPu45+XJXhZsgv+lPlYJv/NBXeJ1h+J6nUxmlYl1CF9c5mdwyzF4hAsSGxpl4gQ== X-Received: by 2002:a17:907:e93:b0:78d:b8ff:9b5f with SMTP id ho19-20020a1709070e9300b0078db8ff9b5fmr20523402ejc.12.1666451251440; Sat, 22 Oct 2022 08:07:31 -0700 (PDT) Received: from localhost.localdomain (dynamic-077-191-171-138.77.191.pool.telefonica.de. [77.191.171.138]) by smtp.gmail.com with ESMTPSA id 4-20020a170906310400b00780ab5a9116sm13021558ejx.211.2022.10.22.08.07.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 22 Oct 2022 08:07:29 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Eduardo Habkost , =?utf-8?q?Herv=C3=A9_Poussineau?= , Aurelien Jarno , Igor Mammedov , Gerd Hoffmann , John Snow , Jiaxun Yang , Ani Sinha , Marcel Apfelbaum , qemu-block@nongnu.org, Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , "Michael S. Tsirkin" , Paolo Bonzini , Bernhard Beschow Subject: [PATCH v2 41/43] hw/isa/piix: Share PIIX3 base class with PIIX4 Date: Sat, 22 Oct 2022 17:05:06 +0200 Message-Id: <20221022150508.26830-42-shentey@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221022150508.26830-1-shentey@gmail.com> References: <20221022150508.26830-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::533; envelope-from=shentey@gmail.com; helo=mail-ed1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Having a common base class allows for substituting PIIX3 with PIIX4 and vice versa. Moreover, it makes PIIX4 implement the acpi-dev-aml-interface. Signed-off-by: Bernhard Beschow --- hw/isa/piix.c | 53 +++++++++++++++++++++++---------------------------- 1 file changed, 24 insertions(+), 29 deletions(-) diff --git a/hw/isa/piix.c b/hw/isa/piix.c index 4ced9995f9..c8c1a99bf1 100644 --- a/hw/isa/piix.c +++ b/hw/isa/piix.c @@ -422,13 +422,12 @@ static void build_pci_isa_aml(AcpiDevAmlIf *adev, Aml *scope) } } -static void pci_piix3_init(Object *obj) +static void pci_piix_init(Object *obj) { PIIXState *d = PIIX_PCI_DEVICE(obj); object_initialize_child(obj, "pic", &d->pic, TYPE_ISA_PIC); object_initialize_child(obj, "rtc", &d->rtc, TYPE_MC146818_RTC); - object_initialize_child(obj, "ide", &d->ide, TYPE_PIIX3_IDE); } static Property pci_piix_props[] = { @@ -443,7 +442,7 @@ static Property pci_piix_props[] = { DEFINE_PROP_END_OF_LIST(), }; -static void pci_piix3_class_init(ObjectClass *klass, void *data) +static void pci_piix_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); @@ -451,11 +450,8 @@ static void pci_piix3_class_init(ObjectClass *klass, void *data) dc->reset = piix_reset; dc->desc = "ISA bridge"; - dc->vmsd = &vmstate_piix3; dc->hotpluggable = false; k->vendor_id = PCI_VENDOR_ID_INTEL; - /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */ - k->device_id = PCI_DEVICE_ID_INTEL_82371SB_0; k->class_id = PCI_CLASS_BRIDGE_ISA; /* * Reason: part of PIIX3 southbridge, needs to be wired up by @@ -466,13 +462,13 @@ static void pci_piix3_class_init(ObjectClass *klass, void *data) adevc->build_dev_aml = build_pci_isa_aml; } -static const TypeInfo piix3_pci_type_info = { +static const TypeInfo piix_pci_type_info = { .name = TYPE_PIIX3_PCI_DEVICE, .parent = TYPE_PCI_DEVICE, .instance_size = sizeof(PIIXState), - .instance_init = pci_piix3_init, + .instance_init = pci_piix_init, .abstract = true, - .class_init = pci_piix3_class_init, + .class_init = pci_piix_class_init, .interfaces = (InterfaceInfo[]) { { INTERFACE_CONVENTIONAL_PCI_DEVICE }, { TYPE_ACPI_DEV_AML_IF }, @@ -496,17 +492,29 @@ static void piix3_realize(PCIDevice *dev, Error **errp) pci_bus_set_route_irq_fn(pci_bus, piix3_route_intx_pin_to_irq); } +static void piix3_init(Object *obj) +{ + PIIXState *d = PIIX_PCI_DEVICE(obj); + + object_initialize_child(obj, "ide", &d->ide, TYPE_PIIX3_IDE); +} + static void piix3_class_init(ObjectClass *klass, void *data) { + DeviceClass *dc = DEVICE_CLASS(klass); PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); k->config_write = piix_write_config; k->realize = piix3_realize; + /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */ + k->device_id = PCI_DEVICE_ID_INTEL_82371SB_0; + dc->vmsd = &vmstate_piix3; } static const TypeInfo piix3_info = { .name = TYPE_PIIX3_DEVICE, .parent = TYPE_PIIX3_PCI_DEVICE, + .instance_init = piix3_init, .class_init = piix3_class_init, }; @@ -533,15 +541,20 @@ static void piix3_xen_realize(PCIDevice *dev, Error **errp) static void piix3_xen_class_init(ObjectClass *klass, void *data) { + DeviceClass *dc = DEVICE_CLASS(klass); PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); k->config_write = piix3_write_config_xen; k->realize = piix3_xen_realize; + /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */ + k->device_id = PCI_DEVICE_ID_INTEL_82371SB_0; + dc->vmsd = &vmstate_piix3; } static const TypeInfo piix3_xen_info = { .name = TYPE_PIIX3_XEN_DEVICE, .parent = TYPE_PIIX3_PCI_DEVICE, + .instance_init = piix3_init, .class_init = piix3_xen_class_init, }; @@ -573,8 +586,6 @@ static void piix4_init(Object *obj) { PIIXState *s = PIIX_PCI_DEVICE(obj); - object_initialize_child(obj, "pic", &s->pic, TYPE_ISA_PIC); - object_initialize_child(obj, "rtc", &s->rtc, TYPE_MC146818_RTC); object_initialize_child(obj, "ide", &s->ide, TYPE_PIIX4_IDE); } @@ -585,36 +596,20 @@ static void piix4_class_init(ObjectClass *klass, void *data) k->config_write = piix_write_config; k->realize = piix4_realize; - k->vendor_id = PCI_VENDOR_ID_INTEL; k->device_id = PCI_DEVICE_ID_INTEL_82371AB_0; - k->class_id = PCI_CLASS_BRIDGE_ISA; - dc->reset = piix_reset; - dc->desc = "ISA bridge"; dc->vmsd = &vmstate_piix4; - /* - * Reason: part of PIIX4 southbridge, needs to be wired up, - * e.g. by mips_malta_init() - */ - dc->user_creatable = false; - dc->hotpluggable = false; - device_class_set_props(dc, pci_piix_props); } static const TypeInfo piix4_info = { .name = TYPE_PIIX4_PCI_DEVICE, - .parent = TYPE_PCI_DEVICE, - .instance_size = sizeof(PIIXState), + .parent = TYPE_PIIX3_PCI_DEVICE, .instance_init = piix4_init, .class_init = piix4_class_init, - .interfaces = (InterfaceInfo[]) { - { INTERFACE_CONVENTIONAL_PCI_DEVICE }, - { }, - }, }; static void piix3_register_types(void) { - type_register_static(&piix3_pci_type_info); + type_register_static(&piix_pci_type_info); type_register_static(&piix3_info); type_register_static(&piix3_xen_info); type_register_static(&piix4_info); From patchwork Sat Oct 22 15:05:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 13016680 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 67792C38A2D for ; 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Tsirkin" , Paolo Bonzini , Bernhard Beschow Subject: [PATCH v2 42/43] hw/isa/piix: Drop the "3" from the PIIX base class Date: Sat, 22 Oct 2022 17:05:07 +0200 Message-Id: <20221022150508.26830-43-shentey@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221022150508.26830-1-shentey@gmail.com> References: <20221022150508.26830-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::52f; envelope-from=shentey@gmail.com; helo=mail-ed1-x52f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Now that the base class is used for both PIIX3 and PIIX4, the "3" became misleading. Signed-off-by: Bernhard Beschow --- hw/i386/acpi-build.c | 2 +- hw/isa/piix.c | 8 ++++---- include/hw/southbridge/piix.h | 4 ++-- 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index 4f54b61904..c006db72e8 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -1298,7 +1298,7 @@ static void build_piix4_isa_bridge(Aml *table) * once PCI is converted to AcpiDevAmlIf and would be ble to generate * AML for bridge itself */ - obj = object_resolve_path_type("", TYPE_PIIX3_PCI_DEVICE, &ambiguous); + obj = object_resolve_path_type("", TYPE_PIIX_PCI_DEVICE, &ambiguous); assert(obj && !ambiguous); scope = aml_scope("_SB.PCI0"); diff --git a/hw/isa/piix.c b/hw/isa/piix.c index c8c1a99bf1..a361261940 100644 --- a/hw/isa/piix.c +++ b/hw/isa/piix.c @@ -463,7 +463,7 @@ static void pci_piix_class_init(ObjectClass *klass, void *data) } static const TypeInfo piix_pci_type_info = { - .name = TYPE_PIIX3_PCI_DEVICE, + .name = TYPE_PIIX_PCI_DEVICE, .parent = TYPE_PCI_DEVICE, .instance_size = sizeof(PIIXState), .instance_init = pci_piix_init, @@ -513,7 +513,7 @@ static void piix3_class_init(ObjectClass *klass, void *data) static const TypeInfo piix3_info = { .name = TYPE_PIIX3_DEVICE, - .parent = TYPE_PIIX3_PCI_DEVICE, + .parent = TYPE_PIIX_PCI_DEVICE, .instance_init = piix3_init, .class_init = piix3_class_init, }; @@ -553,7 +553,7 @@ static void piix3_xen_class_init(ObjectClass *klass, void *data) static const TypeInfo piix3_xen_info = { .name = TYPE_PIIX3_XEN_DEVICE, - .parent = TYPE_PIIX3_PCI_DEVICE, + .parent = TYPE_PIIX_PCI_DEVICE, .instance_init = piix3_init, .class_init = piix3_xen_class_init, }; @@ -602,7 +602,7 @@ static void piix4_class_init(ObjectClass *klass, void *data) static const TypeInfo piix4_info = { .name = TYPE_PIIX4_PCI_DEVICE, - .parent = TYPE_PIIX3_PCI_DEVICE, + .parent = TYPE_PIIX_PCI_DEVICE, .instance_init = piix4_init, .class_init = piix4_class_init, }; diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h index c9fa0f1aa6..c21b69e2be 100644 --- a/include/hw/southbridge/piix.h +++ b/include/hw/southbridge/piix.h @@ -75,9 +75,9 @@ struct PIIXState { }; typedef struct PIIXState PIIXState; -#define TYPE_PIIX3_PCI_DEVICE "pci-piix3" +#define TYPE_PIIX_PCI_DEVICE "pci-piix" DECLARE_INSTANCE_CHECKER(PIIXState, PIIX_PCI_DEVICE, - TYPE_PIIX3_PCI_DEVICE) + TYPE_PIIX_PCI_DEVICE) #define TYPE_PIIX3_DEVICE "PIIX3" #define TYPE_PIIX3_XEN_DEVICE "PIIX3-xen" From patchwork Sat Oct 22 15:05:08 2022 Content-Type: text/plain; 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[77.191.171.138]) by smtp.gmail.com with ESMTPSA id 4-20020a170906310400b00780ab5a9116sm13021558ejx.211.2022.10.22.08.07.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 22 Oct 2022 08:07:34 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Eduardo Habkost , =?utf-8?q?Herv=C3=A9_Poussineau?= , Aurelien Jarno , Igor Mammedov , Gerd Hoffmann , John Snow , Jiaxun Yang , Ani Sinha , Marcel Apfelbaum , qemu-block@nongnu.org, Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , "Michael S. Tsirkin" , Paolo Bonzini , Bernhard Beschow Subject: [PATCH v2 43/43] hw/i386/acpi-build: Resolve PIIX ISA bridge rather than ACPI controller Date: Sat, 22 Oct 2022 17:05:08 +0200 Message-Id: <20221022150508.26830-44-shentey@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221022150508.26830-1-shentey@gmail.com> References: <20221022150508.26830-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::534; envelope-from=shentey@gmail.com; helo=mail-ed1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Resolving the PIIX ISA bridge rather than the PIIX ACPI controller mirrors the ICH9 code one line below. Signed-off-by: Bernhard Beschow --- hw/i386/acpi-build.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index c006db72e8..d705ff6f3d 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -288,7 +288,7 @@ static void acpi_get_pm_info(MachineState *machine, AcpiPmInfo *pm) static void acpi_get_misc_info(AcpiMiscInfo *info) { - Object *piix = object_resolve_type_unambiguous(TYPE_PIIX4_PM); + Object *piix = object_resolve_type_unambiguous(TYPE_PIIX_PCI_DEVICE); Object *lpc = object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE); assert(!!piix != !!lpc);