From patchwork Mon Oct 24 09:46:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lev Kujawski X-Patchwork-Id: 13017073 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 562BEC38A2D for ; Mon, 24 Oct 2022 10:29:48 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1omu3r-0002BU-GP; Mon, 24 Oct 2022 05:47:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1omu37-0001rQ-Te; Mon, 24 Oct 2022 05:47:16 -0400 Received: from mout-p-103.mailbox.org ([2001:67c:2050:0:465::103]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_CHACHA20_POLY1305:256) (Exim 4.90_1) (envelope-from ) id 1omu2Y-0002ZN-9e; Mon, 24 Oct 2022 05:47:13 -0400 Received: from smtp1.mailbox.org (smtp1.mailbox.org [IPv6:2001:67c:2050:b231:465::1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mout-p-103.mailbox.org (Postfix) with ESMTPS id 4Mwqw872bFz9sJ4; Mon, 24 Oct 2022 11:46:32 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mailbox.org; s=mail20150812; t=1666604793; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=uSci2HODWG9PjNVJx6Y+YEanIA2l0t9/txobPaXHSjg=; b=ecZ9gsHm2YONviEE2XjfZoO5U+c+Ek7uvM0RmmBeduDfYtfQp4ZZVh8ZC++sVy/morylPW 2G1/N6PdDAw4h1WyaRk5H7nUKu6Dd9MXnftr4hCmpC/mI1ZU4vmABtLCUnt9vmSJkRLABV EdA1AyLkAjVZqe/ub9ZCw9nY3FAHnQpz1v59hgxAsTQtKebTzMXSV4/aikNkvq27yALJhL D7cNypv8hDBFTGPNj6zhy18jnmf02lC1a8ZcLqZnqJwqHu1bZfRqjav5qIvdYXZWN1OBd1 0nwgGhi2yClDzSFWTPG+f/TtsAkUS69xcRQaYhC34Eiz17yc6V/i7yKbwGdfJQ== From: Lev Kujawski DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mailbox.org; s=mail20150812; t=1666604791; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=uSci2HODWG9PjNVJx6Y+YEanIA2l0t9/txobPaXHSjg=; b=TUdLQ4uLt4d8jrrzHtj0QNKwVOrydxBLs9QCzh/Xnn95Dz0gGxYFgaER7A4fr/R5AzpSyb X57SSQmSe6XhYbhGVuQADQiU0jOqWbizj9pzHQCkH7SDPrvWR4sY01zUqxmaQ3EFQLc/wT EA7doWdPjDXBhnM4xuVESpnuqhvga7v8+iEdJKyiQz3yfjcCG/ASpyyixt9z2+pWBahu9X XXfozmi0xQEPXoRXdWKtjif1KBerAhrWrqKKNmeZriEWyRYHfqXN4tPMLqAo10Zw81DRB8 K5VTHfUBt93roMFvihC59VN2tBDDo7iwVeeoZyHy26hPu+dc8ecBGTfyE4L1ng== To: qemu-devel@nongnu.org, mst@redhat.com Cc: Eduardo Habkost , John Snow , qemu-block@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Marcel Apfelbaum , Laurent Vivier , Yanan Wang , Paolo Bonzini , Thomas Huth , Lev Kujawski Subject: [PATCH 1/2] qpci_device_enable: Allow for command bits hardwired to 0 Date: Mon, 24 Oct 2022 09:46:20 +0000 Message-Id: <20221024094621.512806-2-lkujaw@mailbox.org> In-Reply-To: <20221024094621.512806-1-lkujaw@mailbox.org> References: <20221007095229-mutt-send-email-mst@kernel.org> <20221024094621.512806-1-lkujaw@mailbox.org> MIME-Version: 1.0 X-MBO-RS-ID: 19dec13ea3fa218dc78 X-MBO-RS-META: 5g5m87k4jhceg1ezzqgz1bh6tw7ces6h X-Rspamd-Queue-Id: 4Mwqw872bFz9sJ4 Received-SPF: pass client-ip=2001:67c:2050:0:465::103; envelope-from=lkujaw@mailbox.org; helo=mout-p-103.mailbox.org X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Devices like the PIIX3/4 IDE controller do not support certain modes of operation, such as memory space accesses, and indicate this lack of support by hardwiring the applicable bits to zero. Extend the QEMU PCI device testing framework to accommodate such devices. * tests/qtest/libqos/pci.h: Add the command_disabled word to indicate bits hardwired to 0. * tests/qtest/libqos/pci.c: Verify that hardwired bits are actually hardwired. Signed-off-by: Lev Kujawski --- tests/qtest/libqos/pci.c | 13 +++++++------ tests/qtest/libqos/pci.h | 1 + 2 files changed, 8 insertions(+), 6 deletions(-) diff --git a/tests/qtest/libqos/pci.c b/tests/qtest/libqos/pci.c index b23d72346b..4f3d28d8d9 100644 --- a/tests/qtest/libqos/pci.c +++ b/tests/qtest/libqos/pci.c @@ -220,18 +220,19 @@ int qpci_secondary_buses_init(QPCIBus *bus) void qpci_device_enable(QPCIDevice *dev) { - uint16_t cmd; + const uint16_t enable_bits = + PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; + uint16_t cmd, new_cmd; /* FIXME -- does this need to be a bus callout? */ cmd = qpci_config_readw(dev, PCI_COMMAND); - cmd |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; + cmd |= enable_bits; qpci_config_writew(dev, PCI_COMMAND, cmd); /* Verify the bits are now set. */ - cmd = qpci_config_readw(dev, PCI_COMMAND); - g_assert_cmphex(cmd & PCI_COMMAND_IO, ==, PCI_COMMAND_IO); - g_assert_cmphex(cmd & PCI_COMMAND_MEMORY, ==, PCI_COMMAND_MEMORY); - g_assert_cmphex(cmd & PCI_COMMAND_MASTER, ==, PCI_COMMAND_MASTER); + new_cmd = qpci_config_readw(dev, PCI_COMMAND); + new_cmd &= enable_bits; + g_assert_cmphex(new_cmd, ==, enable_bits & ~dev->command_disabled); } /** diff --git a/tests/qtest/libqos/pci.h b/tests/qtest/libqos/pci.h index 8389614523..eaedb98588 100644 --- a/tests/qtest/libqos/pci.h +++ b/tests/qtest/libqos/pci.h @@ -68,6 +68,7 @@ struct QPCIDevice bool msix_enabled; QPCIBar msix_table_bar, msix_pba_bar; uint64_t msix_table_off, msix_pba_off; + uint16_t command_disabled; }; struct QPCIAddress { From patchwork Mon Oct 24 09:46:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lev Kujawski X-Patchwork-Id: 13017001 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D99DBC38A2D for ; Mon, 24 Oct 2022 10:09:13 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1omu3m-00029O-3l; Mon, 24 Oct 2022 05:47:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1omu2y-0001mY-VG; Mon, 24 Oct 2022 05:47:05 -0400 Received: from mout-p-101.mailbox.org ([80.241.56.151]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_CHACHA20_POLY1305:256) (Exim 4.90_1) (envelope-from ) id 1omu2a-0002da-Nt; Mon, 24 Oct 2022 05:47:04 -0400 Received: from smtp102.mailbox.org (smtp102.mailbox.org [IPv6:2001:67c:2050:b231:465::102]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mout-p-101.mailbox.org (Postfix) with ESMTPS id 4MwqwF2f9Qz9sHC; Mon, 24 Oct 2022 11:46:37 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mailbox.org; s=mail20150812; t=1666604797; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=aKdaeuGHlJPfzfaLRMfa378kLqDoCKmJnyWKUAy12hQ=; b=eu+PMy6fm2oVVpAQlqywmF2yKcaa3NlDvfOBkVPYFJ00RUZXQi30UMir/4PgZmi+sNulkr m7btiwsJ2FlPQmzZjHdvjHu+DbD1Q7vZXDnaMwegyShh/Gt00zt6+yB8WmCjuPkFnEz2bE nUSZPTtve3bQRADUEN8t0rFL0y+oA11vqfHfs+WcnzserJAN3YgdxNq7gSICUCCebDPO4L TgGIBt8L07VjS7weGQXVq2nLtrS0pYeT19k8cz8UljEWmZkV3GAMGhIKHjda6ozOu3EU7O JKcOE7XK0C9MH4ySpcpvfV4pMbBmcab0u+kTEjuBGv1+o0RFyViFG7GxDxJIPw== From: Lev Kujawski DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mailbox.org; s=mail20150812; t=1666604795; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=aKdaeuGHlJPfzfaLRMfa378kLqDoCKmJnyWKUAy12hQ=; b=SvhYj2cEkcHH8Ui2wvZOFfhdgMi4U7pkkTlPX3X6kRvMAYu+866mMjWhx+X1KPZ7j/kLsP mpn/JQs10m5jP+huesR4/KKu2ACTzfZ5f9bTqPSZh7QE8pajy2oCgNwQKjC8nQNtXLhF1R yPZSi90aFQVf71iF2hrqjsSQ3iMJqxTWJ/W1E82IOe0v6zlQCh2v4k07wMDfARN9NSh1u1 rC6xQBMd3fceEmgjdN5dzAbP5SfcHk1vh2PPlbb83zGKi46Z8fhvlxjuaxVBnSgrl0cWX8 QD9fhiEXvnzIp6pQ2kZuip/PYyVL3865SJXPKF8lyHvCC+O0wY3LkagQG8PJ0g== To: qemu-devel@nongnu.org, mst@redhat.com Cc: Eduardo Habkost , John Snow , qemu-block@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Marcel Apfelbaum , Laurent Vivier , Yanan Wang , Paolo Bonzini , Thomas Huth , Lev Kujawski Subject: [PATCH 2/2] hw/ide/piix: Ignore writes of hardwired PCI command register bits Date: Mon, 24 Oct 2022 09:46:21 +0000 Message-Id: <20221024094621.512806-3-lkujaw@mailbox.org> In-Reply-To: <20221024094621.512806-1-lkujaw@mailbox.org> References: <20221007095229-mutt-send-email-mst@kernel.org> <20221024094621.512806-1-lkujaw@mailbox.org> MIME-Version: 1.0 X-MBO-RS-ID: 6866f68cd3856ad6fcb X-MBO-RS-META: xs8mhydbnmd1ydrh4aj7w4qo5jjjnhsn X-Rspamd-Queue-Id: 4MwqwF2f9Qz9sHC Received-SPF: pass client-ip=80.241.56.151; envelope-from=lkujaw@mailbox.org; helo=mout-p-101.mailbox.org X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org One method to enable PCI bus mastering for IDE controllers, often used by x86 firmware, is to write 0x7 to the PCI command register. Neither the PIIX 3/4 specifications nor actual PIIX 3 hardware (a Tyan S1686D system) permit setting the Memory Space Enable (MSE) bit, thus the command register would be left in an unspecified state without this patch. * hw/core/machine.c Facilitate migration by not masking writes to the PIIX 3/4 PCICMD register for machine states of QEMU versions prior to 7.2. * hw/ide/piix.c a) Add a reference to the PIIX 4 data sheet. b) Mask the MSE bit using the QEMU PCI device wmask field. c) Define a new boolean property, x-filter-pcicmd, to control whether the write mask is enabled and enable it by default for both the PIIX 3 and PIIX 4 IDE controllers. * include/hw/ide/pci.h Add the boolean filter_pcicmd field to the PCIIDEState structure, because the PIIX IDE controllers do not define their own state. * tests/qtest/ide-test.c Use the command_disabled field of the QPCIDevice testing model to indicate that PCI_COMMAND_MEMORY is hardwired within PIIX 3/4 IDE controllers. Signed-off-by: Lev Kujawski --- hw/core/machine.c | 5 ++++- hw/ide/piix.c | 24 ++++++++++++++++++++++++ include/hw/ide/pci.h | 1 + tests/qtest/ide-test.c | 1 + 4 files changed, 30 insertions(+), 1 deletion(-) diff --git a/hw/core/machine.c b/hw/core/machine.c index aa520e74a8..8e8e69c081 100644 --- a/hw/core/machine.c +++ b/hw/core/machine.c @@ -40,7 +40,10 @@ #include "hw/virtio/virtio-pci.h" #include "qom/object_interfaces.h" -GlobalProperty hw_compat_7_1[] = {}; +GlobalProperty hw_compat_7_1[] = { + { "piix3-ide", "x-filter-pcicmd", "false" }, + { "piix4-ide", "x-filter-pcicmd", "false" }, +}; const size_t hw_compat_7_1_len = G_N_ELEMENTS(hw_compat_7_1); GlobalProperty hw_compat_7_0[] = { diff --git a/hw/ide/piix.c b/hw/ide/piix.c index de1f4f0efb..a3af32e126 100644 --- a/hw/ide/piix.c +++ b/hw/ide/piix.c @@ -25,6 +25,8 @@ * References: * [1] 82371FB (PIIX) AND 82371SB (PIIX3) PCI ISA IDE XCELERATOR, * 290550-002, Intel Corporation, April 1997. + * [2] 82371AB PCI-TO-ISA / IDE XCELERATOR (PIIX4), 290562-001, + * Intel Corporation, April 1997. */ #include "qemu/osdep.h" @@ -160,6 +162,21 @@ static void pci_piix_ide_realize(PCIDevice *dev, Error **errp) uint8_t *pci_conf = dev->config; int rc; + /* + * Mask all IDE PCI command register bits except for Bus Master + * Function Enable (bit 2) and I/O Space Enable (bit 0), as the + * remainder are hardwired to 0 [1, p.48] [2, p.89-90]. + * + * NOTE: According to the PIIX3 datasheet [1], the Memory Space + * Enable (MSE, bit 1) is hardwired to 1, but this is contradicted + * by actual PIIX3 hardware, the datasheet itself (viz., Default + * Value: 0000h), and the PIIX4 datasheet [2]. + */ + if (d->filter_pcicmd) { + pci_set_word(dev->wmask + PCI_COMMAND, + PCI_COMMAND_MASTER | PCI_COMMAND_IO); + } + pci_conf[PCI_CLASS_PROG] = 0x80; // legacy ATA mode bmdma_setup_bar(d); @@ -185,6 +202,11 @@ static void pci_piix_ide_exitfn(PCIDevice *dev) } } +static Property pci_piix_ide_properties[] = { + DEFINE_PROP_BOOL("x-filter-pcicmd", PCIIDEState, filter_pcicmd, TRUE), + DEFINE_PROP_END_OF_LIST(), +}; + /* NOTE: for the PIIX3, the IRQs and IOports are hardcoded */ static void piix3_ide_class_init(ObjectClass *klass, void *data) { @@ -198,6 +220,7 @@ static void piix3_ide_class_init(ObjectClass *klass, void *data) k->device_id = PCI_DEVICE_ID_INTEL_82371SB_1; k->class_id = PCI_CLASS_STORAGE_IDE; set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); + device_class_set_props(dc, pci_piix_ide_properties); dc->hotpluggable = false; } @@ -220,6 +243,7 @@ static void piix4_ide_class_init(ObjectClass *klass, void *data) k->device_id = PCI_DEVICE_ID_INTEL_82371AB; k->class_id = PCI_CLASS_STORAGE_IDE; set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); + device_class_set_props(dc, pci_piix_ide_properties); dc->hotpluggable = false; } diff --git a/include/hw/ide/pci.h b/include/hw/ide/pci.h index d8384e1c42..5424b00a9e 100644 --- a/include/hw/ide/pci.h +++ b/include/hw/ide/pci.h @@ -53,6 +53,7 @@ struct PCIIDEState { MemoryRegion bmdma_bar; MemoryRegion cmd_bar[2]; MemoryRegion data_bar[2]; + bool filter_pcicmd; /* used only for piix3/4 */ }; static inline IDEState *bmdma_active_if(BMDMAState *bmdma) diff --git a/tests/qtest/ide-test.c b/tests/qtest/ide-test.c index dbe1563b23..d5cec7c14c 100644 --- a/tests/qtest/ide-test.c +++ b/tests/qtest/ide-test.c @@ -174,6 +174,7 @@ static QPCIDevice *get_pci_device(QTestState *qts, QPCIBar *bmdma_bar, *ide_bar = qpci_legacy_iomap(dev, IDE_BASE); + dev->command_disabled = PCI_COMMAND_MEMORY; qpci_device_enable(dev); return dev;