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pr=C From: Ayan Kumar Halder To: CC: , , , , , , Ayan Kumar Halder Subject: [XEN v3 01/13] GICv3: Emulate GICD_IGRPMODR as RAZ / WI Date: Mon, 24 Oct 2022 19:25:18 +0100 Message-ID: <20221024182518.65002-1-ayankuma@amd.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT079:EE_|PH0PR12MB7078:EE_ X-MS-Office365-Filtering-Correlation-Id: 2a2da696-f8e8-4e1a-5d68-08dab5ed20e8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: v8XQ8HA17MSaPNS3CXX+muZklSQuTNVzr9ug7J46vBVW/zYD+5hxpZRPYe8Sy3sMZJsjNnMivIDjJwiBIWPm8Gnm9DTfO8IIDZxoiPVGyEK+4WqwgOK2Gebl/Nw1U8otAo6oWDIQkrgG+BxL9OQVhLb5SnV3XYjfDeUROQ2IEJS7UNsdZV9BGry9N87VgcBuxariyD1E7VvuQQB5S9tvdi3pdo1KIszCn0WHBCFDM/cRXr9mTJmRwlbYYwzB9rUwo6kXEsG6Wgc8hJyui9EA+iROtX1mBwAnO37s80YoIlCDbpPs3k+FE3APf8bOkBDnjzf+Nig5TASWHTBOswFa+3PvR/yRwuEjjyLXflL+BOCpxcr0YzC0VXE8q340eeTSg0FOwWxo1v0n/HvrVp4NohP4mAuKZOQJe9dLUG83wctkyudDe+T30mcJyFAh+pv4YfXkD2j/R2exORsx16CqtoOyprx9jL9QouNvwOe57jUVtzyyN9wcFZ9Rzb7b96dNrCCVHjoX0cisvE93u013453B+r8GdWMqtpemgErPxHR1fEHkzXQdVOrW7WmxnfsSt7k0+bUTKLK8CxSZA54YGd009vEHCDML6RG4AMPULntBIwi1Zn3yMRQYcQ5R3eBfCWzfIBAPmEWPpyYd8bjTqWs96wQE4hgg8uWjTx0WXq/4jDFrYhKt3E7pCwIgBRBkaGPokzCBg/RCwL1ot3CnKe0Q5dEVs2QP2QPx53qvxaZxA7pe3Zv1Ax5VJmQIEAtcLOAv0CvS5ZqoLSA5CmENuOBqRn9lY6btyzt/UtXf38g= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(39860400002)(396003)(346002)(136003)(376002)(451199015)(36840700001)(46966006)(40470700004)(36860700001)(36756003)(1076003)(478600001)(83380400001)(6666004)(47076005)(81166007)(356005)(316002)(82740400003)(426003)(40480700001)(336012)(2906002)(2616005)(6916009)(8676002)(41300700001)(54906003)(5660300002)(26005)(4326008)(186003)(40460700003)(82310400005)(8936002)(70586007)(70206006)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Oct 2022 18:25:29.0009 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2a2da696-f8e8-4e1a-5d68-08dab5ed20e8 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT079.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB7078 Refer GIC v3 specification (Arm IHI 0069H ID020922), IGRPMODR is emulated as RAZ / WI for the guests as "GICD_CTLR.ARE_S==0" is true. Xen is currently supported to run in non-secure mode, so guests will run in non-secure mode only. Also, if Xen was supposed to run in secure mode with guests, the programming of the interrupts (ie whether it belongs to secure/non secure and group 0/1) will be done by Xen only. The guests will not be allowed to change this. Signed-off-by: Ayan Kumar Halder Reviewed-by: Bertrand Marquis --- Observed the issue while running Zephyr on R52. Also, found that KVM has similar behaviour. Changes from:- v1 - Moved the definitions of GICD_IGRPMODR, GICD_IGRPMODRN to gic_v3 specific header. v2 - Updated the commit message. xen/arch/arm/include/asm/gic_v3_defs.h | 2 ++ xen/arch/arm/vgic-v3.c | 4 ++++ 2 files changed, 6 insertions(+) diff --git a/xen/arch/arm/include/asm/gic_v3_defs.h b/xen/arch/arm/include/asm/gic_v3_defs.h index 34ed5f857d..728e28d5e5 100644 --- a/xen/arch/arm/include/asm/gic_v3_defs.h +++ b/xen/arch/arm/include/asm/gic_v3_defs.h @@ -30,6 +30,8 @@ #define GICD_CLRSPI_NSR (0x048) #define GICD_SETSPI_SR (0x050) #define GICD_CLRSPI_SR (0x058) +#define GICD_IGRPMODR (0xD00) +#define GICD_IGRPMODRN (0xD7C) #define GICD_IROUTER (0x6000) #define GICD_IROUTER32 (0x6100) #define GICD_IROUTER1019 (0x7FD8) diff --git a/xen/arch/arm/vgic-v3.c b/xen/arch/arm/vgic-v3.c index 7fb99a9ff2..0c23f6df9d 100644 --- a/xen/arch/arm/vgic-v3.c +++ b/xen/arch/arm/vgic-v3.c @@ -685,6 +685,7 @@ static int __vgic_v3_distr_common_mmio_read(const char *name, struct vcpu *v, switch ( reg ) { case VRANGE32(GICD_IGROUPR, GICD_IGROUPRN): + case VRANGE32(GICD_IGRPMODR, GICD_IGRPMODRN): /* We do not implement security extensions for guests, read zero */ if ( dabt.size != DABT_WORD ) goto bad_width; goto read_as_zero; @@ -781,6 +782,7 @@ static int __vgic_v3_distr_common_mmio_write(const char *name, struct vcpu *v, switch ( reg ) { case VRANGE32(GICD_IGROUPR, GICD_IGROUPRN): + case VRANGE32(GICD_IGRPMODR, GICD_IGRPMODRN): /* We do not implement security extensions for guests, write ignore */ goto write_ignore_32; @@ -1192,6 +1194,7 @@ static int vgic_v3_distr_mmio_read(struct vcpu *v, mmio_info_t *info, case VRANGE32(GICD_ICACTIVER, GICD_ICACTIVERN): case VRANGE32(GICD_IPRIORITYR, GICD_IPRIORITYRN): case VRANGE32(GICD_ICFGR, GICD_ICFGRN): + case VRANGE32(GICD_IGRPMODR, GICD_IGRPMODRN): /* * Above all register are common with GICR and GICD * Manage in common @@ -1379,6 +1382,7 @@ static int vgic_v3_distr_mmio_write(struct vcpu *v, mmio_info_t *info, case VRANGE32(GICD_ICACTIVER, GICD_ICACTIVERN): case VRANGE32(GICD_IPRIORITYR, GICD_IPRIORITYRN): case VRANGE32(GICD_ICFGR, GICD_ICFGRN): + case VRANGE32(GICD_IGRPMODR, GICD_IGRPMODRN): /* Above registers are common with GICR and GICD * Manage in common */ return __vgic_v3_distr_common_mmio_write("vGICD", v, info,