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pr=C From: Ayan Kumar Halder To: CC: , , , , , , Ayan Kumar Halder Subject: [XEN v2] GICv3: Emulate GICR_PENDBASER correctly for 32 bit guests Date: Mon, 24 Oct 2022 20:30:02 +0100 Message-ID: <20221024193002.57888-1-ayankuma@amd.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT094:EE_|SN7PR12MB7345:EE_ X-MS-Office365-Filtering-Correlation-Id: c8d63ace-0f62-4e09-d257-08dab5f62b6f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: hddS1p0hLRzbDq5y9rlodPwX5CWGReypLe02li/Q8vDh9NEebOJhezG8pcRBF3Y3zP0jNWb+71FB3IOzcGsb5kAGajIknCMfarIQoG9J9Fe0h9qXoqIA7sxlZ08Od+0GMERPJCFz8Sg5zy4/reZ6gNNBHPEXeCvCywuj9u+7KAD8ak97wnnvVwsgG66ju1PGgr/ulFJ0CWvqHvFItknxeZLftplri0LzfVswVg2XV3eMqoEMb0t/BU8TGAaY3UCnuYKKwIh2L8JDM6b+D96C/H6jf9mAzxPI7XbNj3ucgWSMlwf/sFv5ftSirMu7vE/57pF5wyH0U71TRdA6doXzZoQa2KYw3DnG9xbfl4hDW02MrA7lZIcafueLGNmWLc06cX6nh+qk0DoelNO7pENjhCStLODPNHfPmaaF1ME8fVqehS2FPA0xsSjmgiEisst426nJmAcmImUM9lQSeNCGNgeSu5quPXj0ZK5OUUVyAlKGjqznk6Uxm9JEJdY4wkPPTutGACgmF71kENeUSCVZKyssCcqYhpSTdc2kXBWWF44SG81fRbR6QFmRsNIqqR4cQ6yWvATfaumgNjZfFzwBOmEUXFumCESZih9vy0zS5/BS0Va7ii6+VIsH/bjax22C1Dr62BE/1z0fq2HhNIdCH4G3owoOEzqyN48MKgxT6oKVP24R8IWVs65p1A2WHy5ix1ilhQ6UOfzSSAJq/HX4m61QwvrnjtEgwXk6Ri1RlKoaxcdiHUKo9Iiksb3EL7rolaZNMIW1+GJn8ytHnwK0jCEVdggZxlmbhviNtBG36qzKe0MAKX8vf/A/kTbnQ2+l X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(39860400002)(136003)(396003)(346002)(376002)(451199015)(40470700004)(46966006)(36840700001)(426003)(36860700001)(40460700003)(47076005)(36756003)(356005)(82740400003)(82310400005)(6666004)(40480700001)(70586007)(70206006)(83380400001)(81166007)(8676002)(6916009)(5660300002)(54906003)(316002)(336012)(2616005)(2906002)(186003)(1076003)(8936002)(4326008)(478600001)(41300700001)(26005)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Oct 2022 19:30:12.0896 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c8d63ace-0f62-4e09-d257-08dab5f62b6f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT094.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB7345 If a guest is running in 32 bit mode and it tries to access "GICR_PENDBASER + 4" mmio reg, it will be trapped to Xen. vreg_reg64_extract() will return the value stored "v->arch.vgic.rdist_pendbase + 4". This will be stored in a 32bit register. The 32bit register is then modified bitwise with a mask (ie GICR_PENDBASER_PTZ, it clears the 62nd bit) which is greater than 32 bits. This will give an incorrect result. The correct thing to do here is to store the value of "v->arch.vgic.rdist_pendbase" in a temporary 64 bit variable. This variable is then modified bitwise with GICR_PENDBASER_PTZ mask. It is then passed to vreg_reg64_extract() which will extract 32 bits from the given offset. Fixes: fe7fa1332dabd9ce4 ("ARM: vGICv3: handle virtual LPI pending and property tables") Signed-off-by: Ayan Kumar Halder Reviewed-by: Andre Przywara Reviewed-by: Bertrand Marquis --- Changes from:- v1 - 1. Extracted this fix from "[RFC PATCH v1 05/12] Arm: GICv3: Emulate GICR_PENDBASER and GICR_PROPBASER on AArch32" into a separate patch with an appropriate commit message. xen/arch/arm/vgic-v3.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/xen/arch/arm/vgic-v3.c b/xen/arch/arm/vgic-v3.c index 0c23f6df9d..7930ab6330 100644 --- a/xen/arch/arm/vgic-v3.c +++ b/xen/arch/arm/vgic-v3.c @@ -250,14 +250,16 @@ static int __vgic_v3_rdistr_rd_mmio_read(struct vcpu *v, mmio_info_t *info, case VREG64(GICR_PENDBASER): { unsigned long flags; + uint64_t val; if ( !v->domain->arch.vgic.has_its ) goto read_as_zero_64; if ( !vgic_reg64_check_access(dabt) ) goto bad_width; spin_lock_irqsave(&v->arch.vgic.lock, flags); - *r = vreg_reg64_extract(v->arch.vgic.rdist_pendbase, info); - *r &= ~GICR_PENDBASER_PTZ; /* WO, reads as 0 */ + val = v->arch.vgic.rdist_pendbase; + val &= ~GICR_PENDBASER_PTZ; /* WO, reads as 0 */ + *r = vreg_reg64_extract(val, info); spin_unlock_irqrestore(&v->arch.vgic.lock, flags); return 1; }