From patchwork Tue Oct 25 07:32:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 13018645 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 939F2C04A95 for ; Tue, 25 Oct 2022 07:33:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231837AbiJYHde (ORCPT ); Tue, 25 Oct 2022 03:33:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59612 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231831AbiJYHdU (ORCPT ); Tue, 25 Oct 2022 03:33:20 -0400 Received: from mail-pl1-x62f.google.com (mail-pl1-x62f.google.com [IPv6:2607:f8b0:4864:20::62f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 72C991552E9 for ; Tue, 25 Oct 2022 00:33:14 -0700 (PDT) Received: by mail-pl1-x62f.google.com with SMTP id p3so9536323pld.10 for ; Tue, 25 Oct 2022 00:33:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=jQnAjVM8KfWMqcwU3yG9m91ABhfRemXy71C0Mul10HU=; b=e8JJy63K9LlYNjNRkaJF+MGYeZJonUWQVJAkpo8xchWw4xqq+Fz/VfKE0WeZOnJcax W/+u2b+ROsGpGNPd/DE4I8cnfzjyQcemBjwVd6BD/A9kAfUwVQn85iW/9L0l5Zrv4zCM ef8TJpZAURk1+ZfOPgLTRLdnjX779naxVajmLClgWpVrgJ9hs8obvZPZTLuDWiGfgZcG uw9rUYAGDdZkDH6bkSgeaTruKw9jQF+/ZVJedGY5bkhH802qBSBQWn/TP+85PbXG5Aa6 dDTEMcpkWdMwnSN8Wz8WR0PU1o8fRBMTkgnFrW40RVh3yrb4XT+sk61BwQyZxDx3fzFD +7DQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jQnAjVM8KfWMqcwU3yG9m91ABhfRemXy71C0Mul10HU=; b=mexX68fq5gU+ls0tSk050BzKv6QvSM1vOIUcJuWVGKLbqmlGI71Q1Bv3c03qefMb1J zaF+eVhhVi8G3MqdOzS7ev1fl5IqeYLhhPPCX8S6b3mXDGOXN2q0ZDfH83SW6QDw2Qgf U25A0mnhH+UhetDkzAqqW0Jtbr6PcaUdxU8pMCh3UvJneHdFo8i9ELAD2cFzFQEfgyUd 1qO7QXye0n+pyc7G/is85FtLMExtn5MqCT3P1H7RLR9tY+N57s89azXVPLZbSzuKivRb +L+w1o4oR6srbxxu+Ho9bpRRft0L/ZSFX7dSZ9P1UnQTBE3NVZDMrnyNkaEj9cygUeQI OKYg== X-Gm-Message-State: ACrzQf1sbTp+uMQAWFe8Am2fSJ16S4mhhhbPwXlBxncu7Ul/d4MOhFEH g9N9oZfJo/4MuUm28vNLuDZB X-Google-Smtp-Source: AMsMyM5Q6hyH/r3aMTe/oOPuJy8fJM9avInLR8qN1a8pB8WvQDd7f46uyeOJuTz7+IsPb8Uv/YtK6Q== X-Received: by 2002:a17:90a:e606:b0:212:f100:22e3 with SMTP id j6-20020a17090ae60600b00212f10022e3mr15802518pjy.83.1666683194461; Tue, 25 Oct 2022 00:33:14 -0700 (PDT) Received: from localhost.localdomain ([117.193.211.146]) by smtp.gmail.com with ESMTPSA id c1-20020a17090a4d0100b0020dda7efe61sm5048369pjg.5.2022.10.25.00.33.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Oct 2022 00:33:12 -0700 (PDT) From: Manivannan Sadhasivam To: andersson@kernel.org, viresh.kumar@linaro.org, krzysztof.kozlowski+dt@linaro.org, rafael@kernel.org, robh+dt@kernel.org Cc: johan@kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Manivannan Sadhasivam , Rob Herring Subject: [PATCH v2 1/7] dt-bindings: cpufreq: cpufreq-qcom-hw: Add cpufreq clock provider Date: Tue, 25 Oct 2022 13:02:48 +0530 Message-Id: <20221025073254.1564622-2-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221025073254.1564622-1-manivannan.sadhasivam@linaro.org> References: <20221025073254.1564622-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Qualcomm platforms making use of CPUFreq HW Engine (EPSS/OSM) supply clocks to the CPU cores. Document the same in the binding to reflect the actual implementation. CPUFreq HW will become the clock provider and CPU cores will become the clock consumers. The clock index for each CPU core is based on the frequency domain index. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Rob Herring --- .../devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml index cbba8979fe0e..2e0336163ffb 100644 --- a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml @@ -57,6 +57,9 @@ properties: '#freq-domain-cells': const: 1 + '#clock-cells': + const: 1 + required: - compatible - reg @@ -84,6 +87,7 @@ examples: enable-method = "psci"; next-level-cache = <&L2_0>; qcom,freq-domain = <&cpufreq_hw 0>; + clocks = <&cpufreq_hw 0>; L2_0: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -100,6 +104,7 @@ examples: enable-method = "psci"; next-level-cache = <&L2_100>; qcom,freq-domain = <&cpufreq_hw 0>; + clocks = <&cpufreq_hw 0>; L2_100: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -113,6 +118,7 @@ examples: enable-method = "psci"; next-level-cache = <&L2_200>; qcom,freq-domain = <&cpufreq_hw 0>; + clocks = <&cpufreq_hw 0>; L2_200: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -126,6 +132,7 @@ examples: enable-method = "psci"; next-level-cache = <&L2_300>; qcom,freq-domain = <&cpufreq_hw 0>; + clocks = <&cpufreq_hw 0>; L2_300: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -139,6 +146,7 @@ examples: enable-method = "psci"; next-level-cache = <&L2_400>; qcom,freq-domain = <&cpufreq_hw 1>; + clocks = <&cpufreq_hw 1>; L2_400: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -152,6 +160,7 @@ examples: enable-method = "psci"; next-level-cache = <&L2_500>; qcom,freq-domain = <&cpufreq_hw 1>; + clocks = <&cpufreq_hw 1>; L2_500: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -165,6 +174,7 @@ examples: enable-method = "psci"; next-level-cache = <&L2_600>; qcom,freq-domain = <&cpufreq_hw 1>; + clocks = <&cpufreq_hw 1>; L2_600: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -178,6 +188,7 @@ examples: enable-method = "psci"; next-level-cache = <&L2_700>; qcom,freq-domain = <&cpufreq_hw 1>; + clocks = <&cpufreq_hw 1>; L2_700: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -198,6 +209,7 @@ examples: clock-names = "xo", "alternate"; #freq-domain-cells = <1>; + #clock-cells = <1>; }; }; ... From patchwork Tue Oct 25 07:32:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 13018646 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 89D09C04A95 for ; Tue, 25 Oct 2022 07:33:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231867AbiJYHdn (ORCPT ); Tue, 25 Oct 2022 03:33:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60176 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229685AbiJYHdW (ORCPT ); Tue, 25 Oct 2022 03:33:22 -0400 Received: from mail-pl1-x62c.google.com (mail-pl1-x62c.google.com [IPv6:2607:f8b0:4864:20::62c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0DF3AEC1CE for ; Tue, 25 Oct 2022 00:33:19 -0700 (PDT) Received: by mail-pl1-x62c.google.com with SMTP id u6so10457606plq.12 for ; Tue, 25 Oct 2022 00:33:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=5vgVZXeinbhpnwzOcj3FGms9cM/M5Xj4R/cDa4Tk1cA=; b=TGd3emrQMlbojhGNu0dbqI9EDiqhKWR1EA1BCRn6M1s0Ek+26HO48OcJlHPHVt1fE9 /Aof45ri7isiNPBEN9JrAKWNGaZPm1qNpcskltAHsisRPHwXMy8eI2R4LZYvs7d6FDwU mdxHVABURTLM+5KDPFAA+dMpJekVIKOgZziKX0BbgHdcYRGJdv9CvQjwe8COtGS+HnEy YMtph4uwAirSrVctzXmQMvt3Y8g+C1S4DXDGHU6nL24itBj6yl4X5wbQV67StBJyCEFZ 003KeZIPHSs1WfdXw+9qmZh10uaAAkgqPtq58A+4czxUR769AqDbvnRSyF4dWzhu2CU7 xCEQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5vgVZXeinbhpnwzOcj3FGms9cM/M5Xj4R/cDa4Tk1cA=; b=GvWIJ4r1AcpGZ8IDuSYp3BN9qM7uTWlM1xSBjLPdTYtSg85WyWVSxnqZdgNt0YY6zD bNieAAeJ/S1y4gHxVjLLGaiQ1O0n6WgQLaYq5JUwsLY2WkvSW5pMUF0CWlc4w3E4OBwA tBCcCY/qTSUdTS1dRtSR4nNVd0Zgjdo4beKYUSUMoZJG3shLPCflIwwAjAFBnJ6UXpTi gHXeiToxQ6RxKTSYjkxEUAjSk0kcfaDuvbn9IsdzHxSeCkL2KntKYzhg8Nuxth5szY3R EsoCAQ8C1BtsLqOb4JRxjkt6Meao9dUjUZZPCaObzwVAj+Fj5ZKwJuJb4bIw1BRDdlMU IxLQ== X-Gm-Message-State: ACrzQf17hXDR6vY/0eHjMm9NZhug5F8Pzz6KejbN8JjRaHuoRq3cerK2 E+QXPNijDwsBpISJEujrMAkdkyxUxpx9t2IdVg== X-Google-Smtp-Source: AMsMyM4/P/QQnBjfl6VcKyYKrffX4U63x2omE5TKgDTUDBnLXh9PuJH/wMTl1tjNWqSO5bD9SeA/6g== X-Received: by 2002:a17:90b:4a84:b0:20d:8953:5ab0 with SMTP id lp4-20020a17090b4a8400b0020d89535ab0mr78384541pjb.48.1666683199432; Tue, 25 Oct 2022 00:33:19 -0700 (PDT) Received: from localhost.localdomain ([117.193.211.146]) by smtp.gmail.com with ESMTPSA id c1-20020a17090a4d0100b0020dda7efe61sm5048369pjg.5.2022.10.25.00.33.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Oct 2022 00:33:17 -0700 (PDT) From: Manivannan Sadhasivam To: andersson@kernel.org, viresh.kumar@linaro.org, krzysztof.kozlowski+dt@linaro.org, rafael@kernel.org, robh+dt@kernel.org Cc: johan@kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH v2 2/7] arm64: dts: qcom: sm8450: Supply clock from cpufreq node to CPUs Date: Tue, 25 Oct 2022 13:02:49 +0530 Message-Id: <20221025073254.1564622-3-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221025073254.1564622-1-manivannan.sadhasivam@linaro.org> References: <20221025073254.1564622-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Qualcomm platforms making use of CPUFreq HW Engine (EPSS/OSM) supply clocks to the CPU cores. But this relationship is not represented in DTS so far. So let's make cpufreq node as the clock provider and CPU nodes as the consumers. The clock index for each CPU node is based on the frequency domain index. Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 6c18cfca9a34..8f26cf9aad01 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -52,6 +52,7 @@ CPU0: cpu@0 { power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 0>; #cooling-cells = <2>; + clocks = <&cpufreq_hw 0>; L2_0: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -71,6 +72,7 @@ CPU1: cpu@100 { power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 0>; #cooling-cells = <2>; + clocks = <&cpufreq_hw 0>; L2_100: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -87,6 +89,7 @@ CPU2: cpu@200 { power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 0>; #cooling-cells = <2>; + clocks = <&cpufreq_hw 0>; L2_200: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -103,6 +106,7 @@ CPU3: cpu@300 { power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 0>; #cooling-cells = <2>; + clocks = <&cpufreq_hw 0>; L2_300: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -119,6 +123,7 @@ CPU4: cpu@400 { power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 1>; #cooling-cells = <2>; + clocks = <&cpufreq_hw 1>; L2_400: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -135,6 +140,7 @@ CPU5: cpu@500 { power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 1>; #cooling-cells = <2>; + clocks = <&cpufreq_hw 1>; L2_500: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -152,6 +158,7 @@ CPU6: cpu@600 { power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 1>; #cooling-cells = <2>; + clocks = <&cpufreq_hw 1>; L2_600: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -168,6 +175,7 @@ CPU7: cpu@700 { power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 2>; #cooling-cells = <2>; + clocks = <&cpufreq_hw 2>; L2_700: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -3804,6 +3812,7 @@ cpufreq_hw: cpufreq@17d91000 { ; interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2"; #freq-domain-cells = <1>; + #clock-cells = <1>; }; gem_noc: interconnect@19100000 { From patchwork Tue Oct 25 07:32:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 13018647 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7DDCBFA3740 for ; Tue, 25 Oct 2022 07:33:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231394AbiJYHdp (ORCPT ); Tue, 25 Oct 2022 03:33:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59088 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231795AbiJYHdZ (ORCPT ); Tue, 25 Oct 2022 03:33:25 -0400 Received: from mail-pj1-x1032.google.com (mail-pj1-x1032.google.com [IPv6:2607:f8b0:4864:20::1032]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0608015624B for ; Tue, 25 Oct 2022 00:33:25 -0700 (PDT) Received: by mail-pj1-x1032.google.com with SMTP id d59-20020a17090a6f4100b00213202d77e1so3754056pjk.2 for ; Tue, 25 Oct 2022 00:33:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=YBJNc8d1DN49dwvNIgcD6LtTNDN4+u1e0rvTArMbSRY=; b=NKtZ4/S+UJJX5l07YfNyJffaTjRg3x5gdXQAfp1hQjYamonsDlnRlVScMQpKuxUuPD YH8HOm3NA3whEWOSPxoCMiSBZmcSzP47sA3dxaxRqwtt4iT2RrGst6q8oF8xpfMphvti L4xnbJ5fggOICM+WWyZsf9U01siCUPrcA/dFZdZM6yhRWIVH5kyzncKzkb31c5fyJMIJ FH8MZ8824mHcT6q3HhP8Cbz32wtXD8GgJxrXxf4Bu7yqwstSFxG/VT5TruN/RUa+lmhP 8eAMqK+9z7F5TAIrPlpMzAXglgn9aS5hIhTm/X1R8B5d1ihaxSRWSOLgR/jmf73BEAv5 syqQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YBJNc8d1DN49dwvNIgcD6LtTNDN4+u1e0rvTArMbSRY=; b=KKEFEPR9CWJydfC6iUhDyLJi5lbn16OurnyQcpnYPaF27bB7WvSp2U6gMMZQCpTSFL BTRwRpNA2uJZ1FUKRj6aasjmjnUHnj9ygoNLrrOuVDQ/v0hD0IIfQLHc2cxF7CW6S8/6 2/K8r/Y4cgodbzoDSp4iFj1Wz+j9+RAd2seG+H3gfAVhSbctOPSLAMrr/D+ENGTAljds cGLJw6mWvMCNJSnP277rtZlW6oTx9gUL4CL+RChUlRVGall/jiiWasgV5YMqrzI0aUlp pMWR047uIYU/C12+w9mCCJdUMjdl71REebDFgKsMfTbT6ub/LJ4D9tKoqFOgnqwbe/n3 LCtw== X-Gm-Message-State: ACrzQf2qXNT5x0UbHn0AA5zN0ggGycFpFs9h3kHGj0ksFFbIb0Kp3JvX zzTRwvPtH9We6gxq6cH+FysR X-Google-Smtp-Source: AMsMyM5ebe21aJ/05A103NwimF4/lit+9de8xb0gRjapa87GIXBhmDcr9nCa4c19+EffxDcuh8iIAw== X-Received: by 2002:a17:902:a606:b0:178:57e4:a0c1 with SMTP id u6-20020a170902a60600b0017857e4a0c1mr36885582plq.83.1666683204458; Tue, 25 Oct 2022 00:33:24 -0700 (PDT) Received: from localhost.localdomain ([117.193.211.146]) by smtp.gmail.com with ESMTPSA id c1-20020a17090a4d0100b0020dda7efe61sm5048369pjg.5.2022.10.25.00.33.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Oct 2022 00:33:22 -0700 (PDT) From: Manivannan Sadhasivam To: andersson@kernel.org, viresh.kumar@linaro.org, krzysztof.kozlowski+dt@linaro.org, rafael@kernel.org, robh+dt@kernel.org Cc: johan@kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH v2 3/7] cpufreq: qcom-hw: Remove un-necessary cpumask_empty() check Date: Tue, 25 Oct 2022 13:02:50 +0530 Message-Id: <20221025073254.1564622-4-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221025073254.1564622-1-manivannan.sadhasivam@linaro.org> References: <20221025073254.1564622-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org CPUFreq core will always set the "policy->cpus" bitmask with the bitfield of the CPU that goes first per domain/policy. So there is no way the "policy->cpus" bitmask will be empty during qcom_cpufreq_hw_cpu_init(). Signed-off-by: Manivannan Sadhasivam --- drivers/cpufreq/qcom-cpufreq-hw.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/drivers/cpufreq/qcom-cpufreq-hw.c b/drivers/cpufreq/qcom-cpufreq-hw.c index d5ef3c66c762..a5b3b8d0e164 100644 --- a/drivers/cpufreq/qcom-cpufreq-hw.c +++ b/drivers/cpufreq/qcom-cpufreq-hw.c @@ -552,11 +552,6 @@ static int qcom_cpufreq_hw_cpu_init(struct cpufreq_policy *policy) data->per_core_dcvs = true; qcom_get_related_cpus(index, policy->cpus); - if (cpumask_empty(policy->cpus)) { - dev_err(dev, "Domain-%d failed to get related CPUs\n", index); - ret = -ENOENT; - goto error; - } policy->driver_data = data; policy->dvfs_possible_from_any_cpu = true; From patchwork Tue Oct 25 07:32:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 13018651 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 439FCFA3748 for ; Tue, 25 Oct 2022 07:34:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231783AbiJYHeY (ORCPT ); Tue, 25 Oct 2022 03:34:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60544 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231809AbiJYHda (ORCPT ); Tue, 25 Oct 2022 03:33:30 -0400 Received: from mail-pj1-x1034.google.com (mail-pj1-x1034.google.com [IPv6:2607:f8b0:4864:20::1034]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D8AE0158D70 for ; Tue, 25 Oct 2022 00:33:29 -0700 (PDT) Received: by mail-pj1-x1034.google.com with SMTP id v4-20020a17090a088400b00212cb0ed97eso10934756pjc.5 for ; Tue, 25 Oct 2022 00:33:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=q2nlS3XahONFZFIAHmPH/AavNAlCb2gKg69yTobdo08=; b=QCY1FpXs5WO6Zoq7B22DvZ1pZWwGCMuIxC+78tY69RBgPRC5LFHcu6q4WjcR4WPFlK t7kpFICtt4+YWJQwpBeWdZyX8VO73OnZMcX8VrQkKPkQe2JBNZuaaynnW6uMZ6IEV8WV E6kTvCg8jJreqbNhu5EXq92YSS0A8RBVWMvG9L2Q/k/+VE6M60+xRcEE6qYGT12oI7Sl GAwi0ZobnHBmv1QbZacs9IEUCTJY+sH0W50YGlg8okH9nQX2LxFMh2mve91qUDqIWXgg LLoaJTA0usHfCwDgaabp+9U4kjGhNhT27EtF3liLMnuyCab9tlaSN7mmam3XDqmRv8EU ZV6g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=q2nlS3XahONFZFIAHmPH/AavNAlCb2gKg69yTobdo08=; b=5zx+o6dnnu707yH9YrTrjmvVax2BkHHwyAsQXSIryxBm1s5GivCrW1+niXTpSCbbMj y7hJ0w62oS0aRey1LH1uxPn6AizU8MgPlZXdRhrrzmaVn9RwkA1YkY1cCbS++zCkUBq0 RbJdncF8KE3Zx0wjIbvGfqGHPyr/x9B+YjStVV4yzZLa3yLzrxIFSBeicImt5v8uujIy bMBksSErbMM/6e8TWMUgdz985XzVzTZI1oimMErp035WJeDAvZGXh2ePQJXAL2rLe0Ik jRBabDZPu0Dl71yObmyb8POlVX827JIxM05hGKMKCNZxEEO+LEOC2RnxMRZTu3uYkPyR DjLw== X-Gm-Message-State: ACrzQf1+QdYeMz/fwo3dGlHLt4+YMg4NpfNV+KFSULLrjuqvXVFjjQwa Ji+YP4QbHuXSz9dv1Vwgytom X-Google-Smtp-Source: AMsMyM6Lyxu4C8r07ItG9E0ag22O+BWY2awNjYOtomIMytiks/zHPyHKsDZcism4d8QEdth6YnFgdg== X-Received: by 2002:a17:902:7c97:b0:17f:5abf:9450 with SMTP id y23-20020a1709027c9700b0017f5abf9450mr36016087pll.19.1666683209309; Tue, 25 Oct 2022 00:33:29 -0700 (PDT) Received: from localhost.localdomain ([117.193.211.146]) by smtp.gmail.com with ESMTPSA id c1-20020a17090a4d0100b0020dda7efe61sm5048369pjg.5.2022.10.25.00.33.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Oct 2022 00:33:27 -0700 (PDT) From: Manivannan Sadhasivam To: andersson@kernel.org, viresh.kumar@linaro.org, krzysztof.kozlowski+dt@linaro.org, rafael@kernel.org, robh+dt@kernel.org Cc: johan@kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH v2 4/7] cpufreq: qcom-hw: Allocate qcom_cpufreq_data during probe Date: Tue, 25 Oct 2022 13:02:51 +0530 Message-Id: <20221025073254.1564622-5-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221025073254.1564622-1-manivannan.sadhasivam@linaro.org> References: <20221025073254.1564622-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org qcom_cpufreq_data is allocated based on the number of frequency domains defined in DT which is static and won't change during runtime. There is no real reason to allocate it during the CPU init() callback and deallocate it during exit(). Hence, move the allocation to probe() and use the allocated memory during init(). This also allows us to use devm_platform_get_and_ioremap_resource() helper for acquiring the freq-domain resources from DT. Signed-off-by: Manivannan Sadhasivam --- drivers/cpufreq/qcom-cpufreq-hw.c | 86 +++++++++++++------------------ 1 file changed, 37 insertions(+), 49 deletions(-) diff --git a/drivers/cpufreq/qcom-cpufreq-hw.c b/drivers/cpufreq/qcom-cpufreq-hw.c index a5b3b8d0e164..1842e9facaa1 100644 --- a/drivers/cpufreq/qcom-cpufreq-hw.c +++ b/drivers/cpufreq/qcom-cpufreq-hw.c @@ -58,6 +58,10 @@ struct qcom_cpufreq_data { bool per_core_dcvs; }; +static struct { + struct qcom_cpufreq_data *data; +} qcom_cpufreq; + static unsigned long cpu_hw_rate, xo_rate; static bool icc_scaling_enabled; @@ -489,8 +493,6 @@ static int qcom_cpufreq_hw_cpu_init(struct cpufreq_policy *policy) struct of_phandle_args args; struct device_node *cpu_np; struct device *cpu_dev; - struct resource *res; - void __iomem *base; struct qcom_cpufreq_data *data; int ret, index; @@ -512,43 +514,16 @@ static int qcom_cpufreq_hw_cpu_init(struct cpufreq_policy *policy) return ret; index = args.args[0]; - - res = platform_get_resource(pdev, IORESOURCE_MEM, index); - if (!res) { - dev_err(dev, "failed to get mem resource %d\n", index); - return -ENODEV; - } - - if (!request_mem_region(res->start, resource_size(res), res->name)) { - dev_err(dev, "failed to request resource %pR\n", res); - return -EBUSY; - } - - base = ioremap(res->start, resource_size(res)); - if (!base) { - dev_err(dev, "failed to map resource %pR\n", res); - ret = -ENOMEM; - goto release_region; - } - - data = kzalloc(sizeof(*data), GFP_KERNEL); - if (!data) { - ret = -ENOMEM; - goto unmap_base; - } - data->soc_data = of_device_get_match_data(&pdev->dev); - data->base = base; - data->res = res; + data = &qcom_cpufreq.data[index]; /* HW should be in enabled state to proceed */ - if (!(readl_relaxed(base + data->soc_data->reg_enable) & 0x1)) { + if (!(readl_relaxed(data->base + data->soc_data->reg_enable) & 0x1)) { dev_err(dev, "Domain-%d cpufreq hardware not enabled\n", index); - ret = -ENODEV; - goto error; + return -ENODEV; } - if (readl_relaxed(base + data->soc_data->reg_dcvs_ctrl) & 0x1) + if (readl_relaxed(data->base + data->soc_data->reg_dcvs_ctrl) & 0x1) data->per_core_dcvs = true; qcom_get_related_cpus(index, policy->cpus); @@ -559,14 +534,13 @@ static int qcom_cpufreq_hw_cpu_init(struct cpufreq_policy *policy) ret = qcom_cpufreq_hw_read_lut(cpu_dev, policy); if (ret) { dev_err(dev, "Domain-%d failed to read LUT\n", index); - goto error; + return ret; } ret = dev_pm_opp_get_opp_count(cpu_dev); if (ret <= 0) { dev_err(cpu_dev, "Failed to add OPPs\n"); - ret = -ENODEV; - goto error; + return -ENODEV; } if (policy_has_boost_freq(policy)) { @@ -575,18 +549,7 @@ static int qcom_cpufreq_hw_cpu_init(struct cpufreq_policy *policy) dev_warn(cpu_dev, "failed to enable boost: %d\n", ret); } - ret = qcom_cpufreq_hw_lmh_init(policy, index); - if (ret) - goto error; - - return 0; -error: - kfree(data); -unmap_base: - iounmap(base); -release_region: - release_mem_region(res->start, resource_size(res)); - return ret; + return qcom_cpufreq_hw_lmh_init(policy, index); } static int qcom_cpufreq_hw_cpu_exit(struct cpufreq_policy *policy) @@ -643,7 +606,7 @@ static int qcom_cpufreq_hw_driver_probe(struct platform_device *pdev) { struct device *cpu_dev; struct clk *clk; - int ret; + int ret, i, num_domains; clk = clk_get(&pdev->dev, "xo"); if (IS_ERR(clk)) @@ -670,6 +633,31 @@ static int qcom_cpufreq_hw_driver_probe(struct platform_device *pdev) if (ret) return ret; + /* Allocate qcom_cpufreq_data based on the available frequency domains in DT */ + num_domains = of_property_count_elems_of_size(pdev->dev.of_node, "reg", sizeof(u32) * 4); + if (num_domains <= 0) + return num_domains; + + qcom_cpufreq.data = devm_kzalloc(&pdev->dev, sizeof(struct qcom_cpufreq_data) * num_domains, + GFP_KERNEL); + if (!qcom_cpufreq.data) + return -ENOMEM; + + for (i = 0; i < num_domains; i++) { + struct qcom_cpufreq_data *data = &qcom_cpufreq.data[i]; + struct resource *res; + void __iomem *base; + + base = devm_platform_get_and_ioremap_resource(pdev, i, &res); + if (IS_ERR(base)) { + dev_err(&pdev->dev, "Failed to map resource %pR\n", res); + return PTR_ERR(base); + } + + data->base = base; + data->res = res; + } + ret = cpufreq_register_driver(&cpufreq_qcom_hw_driver); if (ret) dev_err(&pdev->dev, "CPUFreq HW driver failed to register\n"); From patchwork Tue Oct 25 07:32:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 13018650 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 28714C04A95 for ; Tue, 25 Oct 2022 07:34:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231755AbiJYHeX (ORCPT ); Tue, 25 Oct 2022 03:34:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60854 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231831AbiJYHdg (ORCPT ); Tue, 25 Oct 2022 03:33:36 -0400 Received: from mail-pf1-x434.google.com (mail-pf1-x434.google.com [IPv6:2607:f8b0:4864:20::434]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BDEC415746A for ; Tue, 25 Oct 2022 00:33:34 -0700 (PDT) Received: by mail-pf1-x434.google.com with SMTP id 192so3910478pfx.5 for ; Tue, 25 Oct 2022 00:33:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=3UeGRLt0I6Ca0YYYt9StoKBqh2LnPMLZ6623L26cNAw=; b=X0RL/rMFeNQR0WlRbmLCElOKWXzvpdlLvDkjR4YTO7u8TR4XMeO2egtQYx8G/jG5qe Wwz3GBRVRRS9nmz47gxJTR96yUXyD6Cd2gy4jCSHBB5RW2/j0sralt9LqxBu7qxPaxfy lGRQw5xJXlCUN60USUCLU0Ktmn0e/YcDqhTsNBNH3ovUkH5ooHLe9cQ2TZMaMIojLlpJ 1ytohEqsESYOtThDKvxNer4zMK9Z8+UA8/P1CD2Lkm34l9Ie+cYYAI//1N/bDxqpbLpc o16rasF6aua2DiHsO348m9fI0oif7ZymhXfonnK13z5c9SvceN/jYgrqRYxuTM3opm7m KSNw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3UeGRLt0I6Ca0YYYt9StoKBqh2LnPMLZ6623L26cNAw=; b=hepXopkjbrOH8WQBE99PIg+96k1RLqCOCI/VZMzGLyYy2NsqQ2xfcdg9OYI7X2U/Ce 99LTWimmEWADa8ukk/QXiCqTk71lwIdfkAiCVb778ZlLA2bGHOQdxrCw5LsXrgDPeZRh R4Z70JzYcJBiQVRw2oM4tmb+rGVRyiazejQYt83S7js3ZDtiOiCXRU7yxNF96xPVGN7e 7AwqSw4KeCBcUNWZLTBDtj8rouQvjBhovdwh7aoSJVXM/ykXSN0AdTD8lVeFBNFMosmq Srr42N1xsTEvayOAOJZVK2E3kfMLn0NH6n86AfjDHo2t+hdXPKe3FLR36XbH7y2wiTa0 81Ew== X-Gm-Message-State: ACrzQf189KHBadsMG2rqSIYxhYyvKFGEEHrDHFBzh6MZQ7y3TYY8lDnU puSEqj0fhIZmSg3nWrB7xQqY X-Google-Smtp-Source: AMsMyM5j6iqRSkisi9RIe+WFzEnKm4yugU7gx9b0CI4vdgNgxWZeFWN4UlaLWpYSFevvPnXAFOEqaA== X-Received: by 2002:a63:5164:0:b0:43b:e57c:a15f with SMTP id r36-20020a635164000000b0043be57ca15fmr31182269pgl.586.1666683214172; Tue, 25 Oct 2022 00:33:34 -0700 (PDT) Received: from localhost.localdomain ([117.193.211.146]) by smtp.gmail.com with ESMTPSA id c1-20020a17090a4d0100b0020dda7efe61sm5048369pjg.5.2022.10.25.00.33.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Oct 2022 00:33:32 -0700 (PDT) From: Manivannan Sadhasivam To: andersson@kernel.org, viresh.kumar@linaro.org, krzysztof.kozlowski+dt@linaro.org, rafael@kernel.org, robh+dt@kernel.org Cc: johan@kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH v2 5/7] cpufreq: qcom-hw: Use cached dev pointer in probe() Date: Tue, 25 Oct 2022 13:02:52 +0530 Message-Id: <20221025073254.1564622-6-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221025073254.1564622-1-manivannan.sadhasivam@linaro.org> References: <20221025073254.1564622-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org There are multiple instances of dev pointer used in the probe() function. Instead of referencing pdev->dev all the time, let's use a cached dev pointer to simplify the code. Signed-off-by: Manivannan Sadhasivam --- drivers/cpufreq/qcom-cpufreq-hw.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/drivers/cpufreq/qcom-cpufreq-hw.c b/drivers/cpufreq/qcom-cpufreq-hw.c index 1842e9facaa1..bc991ef10c05 100644 --- a/drivers/cpufreq/qcom-cpufreq-hw.c +++ b/drivers/cpufreq/qcom-cpufreq-hw.c @@ -604,18 +604,19 @@ static struct cpufreq_driver cpufreq_qcom_hw_driver = { static int qcom_cpufreq_hw_driver_probe(struct platform_device *pdev) { + struct device *dev = &pdev->dev; struct device *cpu_dev; struct clk *clk; int ret, i, num_domains; - clk = clk_get(&pdev->dev, "xo"); + clk = clk_get(dev, "xo"); if (IS_ERR(clk)) return PTR_ERR(clk); xo_rate = clk_get_rate(clk); clk_put(clk); - clk = clk_get(&pdev->dev, "alternate"); + clk = clk_get(dev, "alternate"); if (IS_ERR(clk)) return PTR_ERR(clk); @@ -634,11 +635,11 @@ static int qcom_cpufreq_hw_driver_probe(struct platform_device *pdev) return ret; /* Allocate qcom_cpufreq_data based on the available frequency domains in DT */ - num_domains = of_property_count_elems_of_size(pdev->dev.of_node, "reg", sizeof(u32) * 4); + num_domains = of_property_count_elems_of_size(dev->of_node, "reg", sizeof(u32) * 4); if (num_domains <= 0) return num_domains; - qcom_cpufreq.data = devm_kzalloc(&pdev->dev, sizeof(struct qcom_cpufreq_data) * num_domains, + qcom_cpufreq.data = devm_kzalloc(dev, sizeof(struct qcom_cpufreq_data) * num_domains, GFP_KERNEL); if (!qcom_cpufreq.data) return -ENOMEM; @@ -650,7 +651,7 @@ static int qcom_cpufreq_hw_driver_probe(struct platform_device *pdev) base = devm_platform_get_and_ioremap_resource(pdev, i, &res); if (IS_ERR(base)) { - dev_err(&pdev->dev, "Failed to map resource %pR\n", res); + dev_err(dev, "Failed to map resource %pR\n", res); return PTR_ERR(base); } @@ -660,9 +661,9 @@ static int qcom_cpufreq_hw_driver_probe(struct platform_device *pdev) ret = cpufreq_register_driver(&cpufreq_qcom_hw_driver); if (ret) - dev_err(&pdev->dev, "CPUFreq HW driver failed to register\n"); + dev_err(dev, "CPUFreq HW driver failed to register\n"); else - dev_dbg(&pdev->dev, "QCOM CPUFreq HW driver initialized\n"); + dev_dbg(dev, "QCOM CPUFreq HW driver initialized\n"); return ret; } From patchwork Tue Oct 25 07:32:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 13018649 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4B1C1FA3742 for ; Tue, 25 Oct 2022 07:34:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231659AbiJYHeW (ORCPT ); Tue, 25 Oct 2022 03:34:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:32868 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231784AbiJYHdn (ORCPT ); Tue, 25 Oct 2022 03:33:43 -0400 Received: from mail-pj1-x102a.google.com (mail-pj1-x102a.google.com [IPv6:2607:f8b0:4864:20::102a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9EAD51581BA for ; Tue, 25 Oct 2022 00:33:39 -0700 (PDT) Received: by mail-pj1-x102a.google.com with SMTP id r61-20020a17090a43c300b00212f4e9cccdso6243414pjg.5 for ; Tue, 25 Oct 2022 00:33:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=947eFVQOjYHgL69E/eIjVgvNC7z93QCjfG2CSFXyEag=; b=rpLJ6UQtAPwIpX/vSn6NBqFp7r9mxD4dNkqOGChOIy1x+6RAQjtKqce54O9LM33EVP 0KYjdWSz5fy3SUW3TTfPV0D9jsyIl6zkSU121AGp5AASPl0OA4GvDPJD4/yMkhtZKyYY MPguHWDVDpRegL6EdwNJ4o4fKzxYUfajd+H4WSnre6zeHEGda0Ri8XkxXwDGROpOKtv7 BuK9WVolLJ5AEcuI2KtIwRDnW5BB4ed1RGmQkF7tsuINngiv7uRv6mYSDf3IlhmUtIGI xd8aOXLyJ5/ooL+CDFus/q5D2Jd9zMVLj+9nhsWNMyWhs6gpvIyRxBCzUcZl0yFIL7Hr 4NUA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=947eFVQOjYHgL69E/eIjVgvNC7z93QCjfG2CSFXyEag=; b=HMObZxdIdaoqRAEcvHSHhid4KJLBzzqeArXtNKhGD4nbKI1i99m3fbs31lGeX3JN5Z VFQ9R2FXBEN4djDbEjyMa5OrkeNsb071S9YDtJWO6hF2xZBmzexTCIPUjHPN9upv4k4Y fx+SF1HwYM1EN4rFNPAV2iOPEYCHNBFfZk8keZ4tSADmKdgLot8dRfrtan5I8tpsHrga J30fJDaueYMoG2vZt4BP0IPu9pZijvUC048uhyQdtwShJy0zE9+tpdoI/v+PeMAG6B8q +biibiYQP0AHdOEfKqp44SyhDYIadRkMrXLldwfuvXKza5KpYUHKS2WfQLhBv5jdjr10 UYFQ== X-Gm-Message-State: ACrzQf0GtXVdGLNXBEI7nlbkXp3kclnHtIIXW0G2odrl448isSBqZ04U Maz+x8zVWTrYWryMKpfri7vY X-Google-Smtp-Source: AMsMyM4a6vUHbgqeKEegoymZD8RDm1GIEbQ8fhCoqggXkXBOJV1Hpmn/CQumeig285Ga9Ch7elnS6A== X-Received: by 2002:a17:902:f78b:b0:17f:9c94:b247 with SMTP id q11-20020a170902f78b00b0017f9c94b247mr36034344pln.137.1666683219074; Tue, 25 Oct 2022 00:33:39 -0700 (PDT) Received: from localhost.localdomain ([117.193.211.146]) by smtp.gmail.com with ESMTPSA id c1-20020a17090a4d0100b0020dda7efe61sm5048369pjg.5.2022.10.25.00.33.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Oct 2022 00:33:37 -0700 (PDT) From: Manivannan Sadhasivam To: andersson@kernel.org, viresh.kumar@linaro.org, krzysztof.kozlowski+dt@linaro.org, rafael@kernel.org, robh+dt@kernel.org Cc: johan@kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH v2 6/7] cpufreq: qcom-hw: Move soc_data to struct qcom_cpufreq Date: Tue, 25 Oct 2022 13:02:53 +0530 Message-Id: <20221025073254.1564622-7-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221025073254.1564622-1-manivannan.sadhasivam@linaro.org> References: <20221025073254.1564622-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org soc_data is a static info of the driver and thus no need to cache it inside the qcom_cpufreq_data struct which is allocated per frequency domain. So, move it inside qcom_cpufreq struct. Signed-off-by: Manivannan Sadhasivam --- drivers/cpufreq/qcom-cpufreq-hw.c | 27 ++++++++++++++------------- 1 file changed, 14 insertions(+), 13 deletions(-) diff --git a/drivers/cpufreq/qcom-cpufreq-hw.c b/drivers/cpufreq/qcom-cpufreq-hw.c index bc991ef10c05..76f840636828 100644 --- a/drivers/cpufreq/qcom-cpufreq-hw.c +++ b/drivers/cpufreq/qcom-cpufreq-hw.c @@ -42,7 +42,6 @@ struct qcom_cpufreq_soc_data { struct qcom_cpufreq_data { void __iomem *base; struct resource *res; - const struct qcom_cpufreq_soc_data *soc_data; /* * Mutex to synchronize between de-init sequence and re-starting LMh @@ -60,6 +59,7 @@ struct qcom_cpufreq_data { static struct { struct qcom_cpufreq_data *data; + const struct qcom_cpufreq_soc_data *soc_data; } qcom_cpufreq; static unsigned long cpu_hw_rate, xo_rate; @@ -110,7 +110,7 @@ static int qcom_cpufreq_hw_target_index(struct cpufreq_policy *policy, unsigned int index) { struct qcom_cpufreq_data *data = policy->driver_data; - const struct qcom_cpufreq_soc_data *soc_data = data->soc_data; + const struct qcom_cpufreq_soc_data *soc_data = qcom_cpufreq.soc_data; unsigned long freq = policy->freq_table[index].frequency; unsigned int i; @@ -138,7 +138,7 @@ static unsigned int qcom_cpufreq_hw_get(unsigned int cpu) return 0; data = policy->driver_data; - soc_data = data->soc_data; + soc_data = qcom_cpufreq.soc_data; index = readl_relaxed(data->base + soc_data->reg_perf_state); index = min(index, LUT_MAX_ENTRIES - 1); @@ -150,7 +150,7 @@ static unsigned int qcom_cpufreq_hw_fast_switch(struct cpufreq_policy *policy, unsigned int target_freq) { struct qcom_cpufreq_data *data = policy->driver_data; - const struct qcom_cpufreq_soc_data *soc_data = data->soc_data; + const struct qcom_cpufreq_soc_data *soc_data = qcom_cpufreq.soc_data; unsigned int index; unsigned int i; @@ -174,7 +174,7 @@ static int qcom_cpufreq_hw_read_lut(struct device *cpu_dev, unsigned long rate; int ret; struct qcom_cpufreq_data *drv_data = policy->driver_data; - const struct qcom_cpufreq_soc_data *soc_data = drv_data->soc_data; + const struct qcom_cpufreq_soc_data *soc_data = qcom_cpufreq.soc_data; table = kcalloc(LUT_MAX_ENTRIES + 1, sizeof(*table), GFP_KERNEL); if (!table) @@ -291,10 +291,10 @@ static unsigned long qcom_lmh_get_throttle_freq(struct qcom_cpufreq_data *data) { unsigned int lval; - if (data->soc_data->reg_current_vote) - lval = readl_relaxed(data->base + data->soc_data->reg_current_vote) & 0x3ff; + if (qcom_cpufreq.soc_data->reg_current_vote) + lval = readl_relaxed(data->base + qcom_cpufreq.soc_data->reg_current_vote) & 0x3ff; else - lval = readl_relaxed(data->base + data->soc_data->reg_domain_state) & 0xff; + lval = readl_relaxed(data->base + qcom_cpufreq.soc_data->reg_domain_state) & 0xff; return lval * xo_rate; } @@ -366,9 +366,9 @@ static irqreturn_t qcom_lmh_dcvs_handle_irq(int irq, void *data) disable_irq_nosync(c_data->throttle_irq); schedule_delayed_work(&c_data->throttle_work, 0); - if (c_data->soc_data->reg_intr_clr) + if (qcom_cpufreq.soc_data->reg_intr_clr) writel_relaxed(GT_IRQ_STATUS, - c_data->base + c_data->soc_data->reg_intr_clr); + c_data->base + qcom_cpufreq.soc_data->reg_intr_clr); return IRQ_HANDLED; } @@ -514,16 +514,15 @@ static int qcom_cpufreq_hw_cpu_init(struct cpufreq_policy *policy) return ret; index = args.args[0]; - data->soc_data = of_device_get_match_data(&pdev->dev); data = &qcom_cpufreq.data[index]; /* HW should be in enabled state to proceed */ - if (!(readl_relaxed(data->base + data->soc_data->reg_enable) & 0x1)) { + if (!(readl_relaxed(data->base + qcom_cpufreq.soc_data->reg_enable) & 0x1)) { dev_err(dev, "Domain-%d cpufreq hardware not enabled\n", index); return -ENODEV; } - if (readl_relaxed(data->base + data->soc_data->reg_dcvs_ctrl) & 0x1) + if (readl_relaxed(data->base + qcom_cpufreq.soc_data->reg_dcvs_ctrl) & 0x1) data->per_core_dcvs = true; qcom_get_related_cpus(index, policy->cpus); @@ -644,6 +643,8 @@ static int qcom_cpufreq_hw_driver_probe(struct platform_device *pdev) if (!qcom_cpufreq.data) return -ENOMEM; + qcom_cpufreq.soc_data = of_device_get_match_data(dev); + for (i = 0; i < num_domains; i++) { struct qcom_cpufreq_data *data = &qcom_cpufreq.data[i]; struct resource *res; From patchwork Tue Oct 25 07:32:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 13018648 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 96758FA373F for ; Tue, 25 Oct 2022 07:34:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229907AbiJYHeV (ORCPT ); Tue, 25 Oct 2022 03:34:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59616 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231909AbiJYHeF (ORCPT ); Tue, 25 Oct 2022 03:34:05 -0400 Received: from mail-pj1-x1042.google.com (mail-pj1-x1042.google.com [IPv6:2607:f8b0:4864:20::1042]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C77C81552F8 for ; Tue, 25 Oct 2022 00:33:44 -0700 (PDT) Received: by mail-pj1-x1042.google.com with SMTP id pb15so9992576pjb.5 for ; Tue, 25 Oct 2022 00:33:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=XNFZLWBDpEQVVP8PITjRVb+C8Kzi0WYhsCO8eonBgh0=; b=QsWpwnJULajs9HDqiZmXgkvTZGZkYUVcrZ3B7G7duiqEitktj9vkDQ/g75wHP7rLUf Y3LQKXcUxrmrcTzZApvHSGRd8WDKxJl9BFS9YeQiQcopN147yzmCmsbwfVwQ74Cuf4L2 t6CsM7bnebtyY0C+qYldRH6J+y7Ie3OM/phjKEuQ8PpE2kMUEcwqpwEvi8QWsVca1d9F qeqMrcfJHFDjWyDBS6zLxeUfs4BG+K7Jx85MsYbjBWRCwUhEvznPHZtGZrkNkeITMnsP MZAph4ZsdQmxqbeYbzw4waTcN8bE5p+L9Bexg9B2yhAH0liE2Mh33RrsCYUIVpwE8XQM N0AQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=XNFZLWBDpEQVVP8PITjRVb+C8Kzi0WYhsCO8eonBgh0=; b=xd4bSCvFTz+FS086j3g77bOhSUxHDZ0NxIEj26Js9Y6minJwndpEzvGVXFn6CqIQuh aJ3f8lLI6cqWad2+oR0M/l+fcTZ71VELq3OTp81ydlq+EaRYV5RBIGu/DYxCHzyCko6q noOqJFrmahAeIdV37HF7E4Xdz+5UA7JjtKjF5IotmM7ys1DEsTCS0Mp9zZvK2UF+pmgi nJTj6vSK1LHiyOvP+IMzEIA3YlzZYWmnwVy9ek4Kn/zuhuvKzn5KuATwe2mGMFrpWMe4 4sfzQj4Qvr4jDLuoCr/7v88Xw/VlIhCaFrJmoB0NqbS5Q/C278lKzaewGd9O5HoOWA/E S9JQ== X-Gm-Message-State: ACrzQf31W3AYEJWFqNIXeNZRbs58U22hdS16Sp+1UCSVZ01PmFvMbBSE DZ+ISjkse6JoZsRgMp3msnCC X-Google-Smtp-Source: AMsMyM6+ep5OX6LFLnBIpKwOJqjTdnabuv3UlmkbhDRgTYaCRuGzjWjDmrmMeJFhb7UIoHNASgukig== X-Received: by 2002:a17:902:ce09:b0:178:bb78:49a5 with SMTP id k9-20020a170902ce0900b00178bb7849a5mr37984224plg.100.1666683223934; Tue, 25 Oct 2022 00:33:43 -0700 (PDT) Received: from localhost.localdomain ([117.193.211.146]) by smtp.gmail.com with ESMTPSA id c1-20020a17090a4d0100b0020dda7efe61sm5048369pjg.5.2022.10.25.00.33.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Oct 2022 00:33:42 -0700 (PDT) From: Manivannan Sadhasivam To: andersson@kernel.org, viresh.kumar@linaro.org, krzysztof.kozlowski+dt@linaro.org, rafael@kernel.org, robh+dt@kernel.org Cc: johan@kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH v2 7/7] cpufreq: qcom-hw: Add CPU clock provider support Date: Tue, 25 Oct 2022 13:02:54 +0530 Message-Id: <20221025073254.1564622-8-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221025073254.1564622-1-manivannan.sadhasivam@linaro.org> References: <20221025073254.1564622-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Qcom CPUFreq hardware (EPSS/OSM) controls clock and voltage to the CPU cores. But this relationship is not represented with the clk framework so far. So, let's make the qcom-cpufreq-hw driver a clock provider. This makes the clock producer/consumer relationship cleaner and is also useful for CPU related frameworks like OPP to know the frequency at which the CPUs are running. The clock frequency provided by the driver is for each frequency domain. We cannot get the frequency of each CPU core because, not all platforms support per-core DCVS feature. Also the frequency supplied by the driver is the actual frequency that comes out of the EPSS/OSM block after the DCVS operation. This frequency is not same as what the CPUFreq framework has set but it is the one that gets supplied to the CPUs after throttling by LMh. Signed-off-by: Manivannan Sadhasivam --- drivers/cpufreq/qcom-cpufreq-hw.c | 43 +++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/drivers/cpufreq/qcom-cpufreq-hw.c b/drivers/cpufreq/qcom-cpufreq-hw.c index 76f840636828..66677db3e267 100644 --- a/drivers/cpufreq/qcom-cpufreq-hw.c +++ b/drivers/cpufreq/qcom-cpufreq-hw.c @@ -4,6 +4,7 @@ */ #include +#include #include #include #include @@ -53,6 +54,7 @@ struct qcom_cpufreq_data { bool cancel_throttle; struct delayed_work throttle_work; struct cpufreq_policy *policy; + struct clk_hw cpu_clk; bool per_core_dcvs; }; @@ -601,8 +603,20 @@ static struct cpufreq_driver cpufreq_qcom_hw_driver = { .ready = qcom_cpufreq_ready, }; +static unsigned long qcom_cpufreq_hw_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) +{ + struct qcom_cpufreq_data *data = container_of(hw, struct qcom_cpufreq_data, cpu_clk); + + return qcom_lmh_get_throttle_freq(data) / HZ_PER_KHZ; +} + +static const struct clk_ops qcom_cpufreq_hw_clk_ops = { + .recalc_rate = qcom_cpufreq_hw_recalc_rate, +}; + static int qcom_cpufreq_hw_driver_probe(struct platform_device *pdev) { + struct clk_hw_onecell_data *clk_data; struct device *dev = &pdev->dev; struct device *cpu_dev; struct clk *clk; @@ -645,8 +659,16 @@ static int qcom_cpufreq_hw_driver_probe(struct platform_device *pdev) qcom_cpufreq.soc_data = of_device_get_match_data(dev); + clk_data = devm_kzalloc(dev, struct_size(clk_data, hws, num_domains), GFP_KERNEL); + if (!clk_data) + return -ENOMEM; + + clk_data->num = num_domains; + for (i = 0; i < num_domains; i++) { struct qcom_cpufreq_data *data = &qcom_cpufreq.data[i]; + static struct clk_init_data init = {}; + const char *clk_name; struct resource *res; void __iomem *base; @@ -658,6 +680,27 @@ static int qcom_cpufreq_hw_driver_probe(struct platform_device *pdev) data->base = base; data->res = res; + + /* Register CPU clock for each frequency domain */ + clk_name = devm_kasprintf(dev, GFP_KERNEL, "qcom_cpufreq%d", i); + init.name = clk_name; + init.flags = CLK_GET_RATE_NOCACHE; + init.ops = &qcom_cpufreq_hw_clk_ops; + data->cpu_clk.init = &init; + + ret = devm_clk_hw_register(dev, &data->cpu_clk); + if (ret < 0) { + dev_err(dev, "Failed to register Qcom CPUFreq clock\n"); + return ret; + } + + clk_data->hws[i] = &data->cpu_clk; + } + + ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clk_data); + if (ret < 0) { + dev_err(dev, "Failed to add Qcom CPUFreq clock provider\n"); + return ret; } ret = cpufreq_register_driver(&cpufreq_qcom_hw_driver);