From patchwork Wed Oct 26 05:59:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Raju Lakkaraju - I30499 X-Patchwork-Id: 13020172 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 56EE7C433FE for ; Wed, 26 Oct 2022 05:59:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233022AbiJZF7g (ORCPT ); Wed, 26 Oct 2022 01:59:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58100 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233007AbiJZF7d (ORCPT ); Wed, 26 Oct 2022 01:59:33 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8C2AABC9E; Tue, 25 Oct 2022 22:59:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1666763972; x=1698299972; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=g49TENwrwgphz8+ho5iXZTZ4lIXRuj0bNxSD+27xs5E=; b=Pqch0BTWPKg8jHpUkl2YNabneLd6UamsVCMxtXiKR5Si/DCGpVosk/OL P4rNkssI4qUgT1cliIYm0zBqSL7tHNkqWHCRxhV1k/VWOTj9fAqrW0Gi9 9cxvPySbzxUYDmz+x7e9+oiE4zARLsq1ztG6NVxAVBScOZhpjm9fWQ8xz Mu03DAkLS8miEMDmepYlKhF7ugxhWTGuQKRS8jLVg9Dz1Op6UCV7vZ/a+ yttXXG34zT1O1uoE6McJ9A1hg9k00JGssIb3sPIjeFaEsabcbOZAzkvnD WCRz7wlZhpSy9tJkahv1vF9uocKh6AMIrl2MI7/Rn4VuvkeCehxLS3MED w==; X-IronPort-AV: E=Sophos;i="5.95,213,1661842800"; d="scan'208";a="180546094" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 25 Oct 2022 22:59:31 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Tue, 25 Oct 2022 22:59:31 -0700 Received: from localhost.localdomain (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Tue, 25 Oct 2022 22:59:27 -0700 From: Raju Lakkaraju To: CC: , , , , , , , , , , Subject: [PATCH net-next V1 1/2] net: phy: mxl-gpy: Change gpy_update_interface() function return type Date: Wed, 26 Oct 2022 11:29:17 +0530 Message-ID: <20221026055918.4225-2-Raju.Lakkaraju@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221026055918.4225-1-Raju.Lakkaraju@microchip.com> References: <20221026055918.4225-1-Raju.Lakkaraju@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org gpy_update_interface() is called from gpy_read_status() which does return error codes. gpy_read_status() would benefit from returning -EINVAL, etc. Signed-off-by: Raju Lakkaraju --- drivers/net/phy/mxl-gpy.c | 28 ++++++++++++++++++++-------- 1 file changed, 20 insertions(+), 8 deletions(-) diff --git a/drivers/net/phy/mxl-gpy.c b/drivers/net/phy/mxl-gpy.c index 24bae27eedef..1383af3c2677 100644 --- a/drivers/net/phy/mxl-gpy.c +++ b/drivers/net/phy/mxl-gpy.c @@ -370,14 +370,14 @@ static int gpy_config_aneg(struct phy_device *phydev) VSPEC1_SGMII_CTRL_ANRS, VSPEC1_SGMII_CTRL_ANRS); } -static void gpy_update_interface(struct phy_device *phydev) +static int gpy_update_interface(struct phy_device *phydev) { int ret; /* Interface mode is fixed for USXGMII and integrated PHY */ if (phydev->interface == PHY_INTERFACE_MODE_USXGMII || phydev->interface == PHY_INTERFACE_MODE_INTERNAL) - return; + return -EINVAL; /* Automatically switch SERDES interface between SGMII and 2500-BaseX * according to speed. Disable ANEG in 2500-BaseX mode. @@ -387,10 +387,12 @@ static void gpy_update_interface(struct phy_device *phydev) phydev->interface = PHY_INTERFACE_MODE_2500BASEX; ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL, VSPEC1_SGMII_CTRL_ANEN, 0); - if (ret < 0) + if (ret < 0) { phydev_err(phydev, "Error: Disable of SGMII ANEG failed: %d\n", ret); + return ret; + } break; case SPEED_1000: case SPEED_100: @@ -404,15 +406,22 @@ static void gpy_update_interface(struct phy_device *phydev) ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL, VSPEC1_SGMII_ANEN_ANRS, VSPEC1_SGMII_ANEN_ANRS); - if (ret < 0) + if (ret < 0) { phydev_err(phydev, "Error: Enable of SGMII ANEG failed: %d\n", ret); + return ret; + } break; } - if (phydev->speed == SPEED_2500 || phydev->speed == SPEED_1000) - genphy_read_master_slave(phydev); + if (phydev->speed == SPEED_2500 || phydev->speed == SPEED_1000) { + ret = genphy_read_master_slave(phydev); + if (ret < 0) + return ret; + } + + return 0; } static int gpy_read_status(struct phy_device *phydev) @@ -463,8 +472,11 @@ static int gpy_read_status(struct phy_device *phydev) break; } - if (phydev->link) - gpy_update_interface(phydev); + if (phydev->link) { + ret = gpy_update_interface(phydev); + if (ret < 0) + return ret; + } return 0; } From patchwork Wed Oct 26 05:59:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Raju Lakkaraju - I30499 X-Patchwork-Id: 13020173 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 02F82C433FE for ; Wed, 26 Oct 2022 06:00:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233058AbiJZGAC (ORCPT ); Wed, 26 Oct 2022 02:00:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60206 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233062AbiJZF7y (ORCPT ); Wed, 26 Oct 2022 01:59:54 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 88AB326485; Tue, 25 Oct 2022 22:59:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1666763983; x=1698299983; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=e5Kq3BI41zG7Mb7tUnxFyLEKFKAvkFrcPX3TCynoDug=; b=1NTGSoUoTgc0P3zIT18AIK/Q/eIKC0w8z8sbAp6ifiWgKTuvCGgPmmS4 OudV9n+vF0yCRnUo3yZ3irYizTwqPAuF1PsDmc7juikMmLoQDEMEP0zUd E25GerY1FvClNzCZ4IsZ3t4qVaui6gQM0yXc2UJLyyHdh6XfuWImt+Afg RTx0g9IFRvfUIunJUMzF8lAPNtzykm6ORJu8ApXoHY4uz6LnnVibRog8N 8oN+nJu+1NG1V1ZsmjYNB1b+uW+XVmlgHYTI2OZnFekfooL7FkZCnND7X pqWh6wPJLw4M5W0Q0fqhSwGOoyO/a9LI4igQhR+0460zyMoB5lyVvpe4V A==; X-IronPort-AV: E=Sophos;i="5.95,213,1661842800"; d="scan'208";a="197064979" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 25 Oct 2022 22:59:38 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Tue, 25 Oct 2022 22:59:35 -0700 Received: from localhost.localdomain (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Tue, 25 Oct 2022 22:59:31 -0700 From: Raju Lakkaraju To: CC: , , , , , , , , , , Subject: [PATCH net-next V1 2/2] net: phy: mxl-gpy: Add PHY Auto/MDI/MDI-X set driver for GPY211 chips Date: Wed, 26 Oct 2022 11:29:18 +0530 Message-ID: <20221026055918.4225-3-Raju.Lakkaraju@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221026055918.4225-1-Raju.Lakkaraju@microchip.com> References: <20221026055918.4225-1-Raju.Lakkaraju@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org Add support for MDI-X status and configuration for GPY211 chips Signed-off-by: Raju Lakkaraju --- Change List: ============ V0 -> V1: - Remove the error prints in driver functions - Change the gpy_update_interface() return type drivers/net/phy/mxl-gpy.c | 72 ++++++++++++++++++++++++++++++++++++++- 1 file changed, 71 insertions(+), 1 deletion(-) diff --git a/drivers/net/phy/mxl-gpy.c b/drivers/net/phy/mxl-gpy.c index 1383af3c2677..27c0f161623e 100644 --- a/drivers/net/phy/mxl-gpy.c +++ b/drivers/net/phy/mxl-gpy.c @@ -29,6 +29,10 @@ #define PHY_ID_GPY241BM 0x67C9DE80 #define PHY_ID_GPY245B 0x67C9DEC0 +#define PHY_CTL1 0x13 +#define PHY_CTL1_MDICD BIT(3) +#define PHY_CTL1_MDIAB BIT(2) +#define PHY_CTL1_AMDIX BIT(0) #define PHY_MIISTAT 0x18 /* MII state */ #define PHY_IMASK 0x19 /* interrupt mask */ #define PHY_ISTAT 0x1A /* interrupt status */ @@ -59,6 +63,13 @@ #define PHY_FWV_MAJOR_MASK GENMASK(11, 8) #define PHY_FWV_MINOR_MASK GENMASK(7, 0) +#define PHY_PMA_MGBT_POLARITY 0x82 +#define PHY_MDI_MDI_X_MASK GENMASK(1, 0) +#define PHY_MDI_MDI_X_NORMAL 0x3 +#define PHY_MDI_MDI_X_AB 0x2 +#define PHY_MDI_MDI_X_CD 0x1 +#define PHY_MDI_MDI_X_CROSS 0x0 + /* SGMII */ #define VSPEC1_SGMII_CTRL 0x08 #define VSPEC1_SGMII_CTRL_ANEN BIT(12) /* Aneg enable */ @@ -289,6 +300,33 @@ static bool gpy_sgmii_aneg_en(struct phy_device *phydev) return (ret & VSPEC1_SGMII_CTRL_ANEN) ? true : false; } +static int gpy_config_mdix(struct phy_device *phydev, u8 ctrl) +{ + int ret; + u16 val; + + switch (ctrl) { + case ETH_TP_MDI_AUTO: + val = PHY_CTL1_AMDIX; + break; + case ETH_TP_MDI_X: + val = (PHY_CTL1_MDIAB | PHY_CTL1_MDICD); + break; + case ETH_TP_MDI: + val = 0; + break; + default: + return 0; + } + + ret = phy_modify(phydev, PHY_CTL1, PHY_CTL1_AMDIX | PHY_CTL1_MDIAB | + PHY_CTL1_MDICD, val); + if (ret < 0) + return ret; + + return genphy_c45_restart_aneg(phydev); +} + static int gpy_config_aneg(struct phy_device *phydev) { bool changed = false; @@ -304,6 +342,10 @@ static int gpy_config_aneg(struct phy_device *phydev) : genphy_c45_pma_setup_forced(phydev); } + ret = gpy_config_mdix(phydev, phydev->mdix_ctrl); + if (ret < 0) + return ret; + ret = genphy_c45_an_config_aneg(phydev); if (ret < 0) return ret; @@ -370,6 +412,34 @@ static int gpy_config_aneg(struct phy_device *phydev) VSPEC1_SGMII_CTRL_ANRS, VSPEC1_SGMII_CTRL_ANRS); } +static int gpy_update_mdix(struct phy_device *phydev) +{ + int ret; + + ret = phy_read(phydev, PHY_CTL1); + if (ret < 0) + return ret; + + if (ret & PHY_CTL1_AMDIX) + phydev->mdix_ctrl = ETH_TP_MDI_AUTO; + else + if (ret & PHY_CTL1_MDICD || ret & PHY_CTL1_MDIAB) + phydev->mdix_ctrl = ETH_TP_MDI_X; + else + phydev->mdix_ctrl = ETH_TP_MDI; + + ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, PHY_PMA_MGBT_POLARITY); + if (ret < 0) + return ret; + + if ((ret & PHY_MDI_MDI_X_MASK) < PHY_MDI_MDI_X_NORMAL) + phydev->mdix = ETH_TP_MDI_X; + else + phydev->mdix = ETH_TP_MDI; + + return 0; +} + static int gpy_update_interface(struct phy_device *phydev) { int ret; @@ -421,7 +491,7 @@ static int gpy_update_interface(struct phy_device *phydev) return ret; } - return 0; + return gpy_update_mdix(phydev); } static int gpy_read_status(struct phy_device *phydev)