From patchwork Wed Oct 26 07:58:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 13020288 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C36F0C38A2D for ; Wed, 26 Oct 2022 07:59:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:Message-Id:MIME-Version:Subject: Date:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=sbXdtInBXOb+2zNyAG3qAXHcwwSuzAi/HZObFGRzzL0=; b=30Ds3X3orvpTje P8yrx6IRlmQ8822Kn6fBix53xlQS6jUii+F8ozXmfVFGlai9SilLWeJHxAYP9fGPMnZK3Z3eMHTEr sAbbz7LjXhwsHktQL6vPY1UbDTt/vza7i5x6OS4Pj/T4FWAhF7c6O+uViIrs3c4eapx/W5kgAMsLH dHpIyjYeNATtfgBYeMXaJMtBnl1q8T7UsrsGIcmLfecgP7umfd04gLKEtCtYicaG5uuGnz3qOZKrS Cng/GtTa3Cygxxa5zL1SFnGYaRkpZZmj3A6afw3Vd6HlFyBVPngMKWtqntDnft9xnmKvFAlTK5Ym1 StkWOGunM9wBXfXG8/0g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1onbJ9-008TCI-L0; Wed, 26 Oct 2022 07:58:39 +0000 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1onbJ5-008TBU-UH for linux-arm-kernel@lists.infradead.org; Wed, 26 Oct 2022 07:58:37 +0000 Received: by mail-wm1-x32e.google.com with SMTP id y10so9675909wma.0 for ; Wed, 26 Oct 2022 00:58:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=cc:to:message-id:content-transfer-encoding:mime-version:subject :date:from:from:to:cc:subject:date:message-id:reply-to; bh=+jyjrbZo+ELkTQHp1UO8qB1tgFnSatDzGs6yA5dAalk=; b=D+lIzuFmmhNmptsvaY8BGQUNGKXCtzv9MHCJaBqvK9nBESL8oazEgpAqhXJVAJywpB i0qxXytK2Dwz3lYx3b2byIBa7MjTi4+3R/V3Jt+8aDopFCPUPRQVDBddysrWAA0Phax+ GsYYY4ORqfBeJ0gh58fwYn4mOe9jZKXpaONekw+G4azlTm6jgFc3k+AqCucxptEumHuc liQt7PiNML/sEXGIyXfUbanAFC9/tbEOA3DkJTRlKddeRB5fVya50nxVvbfV6LinPlC1 h3/iWju6Wi1Po0962nuxTwR6MKDELIciU2qzNQA7vRW34v/ASomx6+uoD/vRzRiOITSX RO0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:message-id:content-transfer-encoding:mime-version:subject :date:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=+jyjrbZo+ELkTQHp1UO8qB1tgFnSatDzGs6yA5dAalk=; b=4A0dgD6rO6+zISo9INAsojkHa2q2L1jo9euW/1szCuQkzMK4FfhYuMgXphrxgNKi+J WUw3/XJjbNcdhxuxJGJ3SKjB5cmvauMcUFbj/EECwa4RCRos7+5AhYLw5SmnFtrHv1aX /kZ57GeE8XbErLE8EOZXEHf2vrRyWy+E2AKBH+0lrc4OjeX4aPFdmKo181M9uMAiVZk+ m1s6kvQ4UELLfM4vc8V/Ec+uXyJFtf1qzHGyEc/v6j+siCTvRjeaBaqlkadmHlO2orRt UNKkQgwdcP/t2qtD1uJD+b4vdoord/kX3GfHitliN7PY8Q7yUl64GNtV1/DayAoD42Fq jNKA== X-Gm-Message-State: ACrzQf1CK5BMF2zpZLgl0A6RuRGhVI2GveBK3Q78zt5kCBEzm9fBnunm sZ8vgKuG2371U1yCVddMJdGjzA== X-Google-Smtp-Source: AMsMyM6biL997EUrBv+5AmVPUHlDggoRWcpPcDDG67spwOF+g8th63MEzdahrujErNWbC8OUcQgQOw== X-Received: by 2002:a05:600c:1e28:b0:3c6:e046:9da7 with SMTP id ay40-20020a05600c1e2800b003c6e0469da7mr1497424wmb.43.1666771113122; Wed, 26 Oct 2022 00:58:33 -0700 (PDT) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:8261:5fff:fe11:bdda]) by smtp.gmail.com with ESMTPSA id k1-20020a5d6e81000000b0022cc3e67fc5sm4562593wrz.65.2022.10.26.00.58.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Oct 2022 00:58:32 -0700 (PDT) From: Neil Armstrong Date: Wed, 26 Oct 2022 09:58:28 +0200 Subject: [PATCH] spi: meson-spicc: move wait completion in driver to take bursts delay in account MIME-Version: 1.0 Message-Id: <20221026-spicc-burst-delay-v1-0-1be5ffb7051a@linaro.org> To: Jerome Brunet , Martin Blumenstingl , Mark Brown , Kevin Hilman Cc: linux-arm-kernel@lists.infradead.org, Da Xue , linux-kernel@vger.kernel.org, linux-amlogic@lists.infradead.org, Neil Armstrong , linux-spi@vger.kernel.org X-Mailer: b4 0.10.1 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221026_005835_982015_E40299A0 X-CRM114-Status: GOOD ( 17.26 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Some delay occurs between each bursts, thus the default delay is wrong and a timeout will occur with big enough transfers. The solution is to handle the timeout management in the driver and add some delay for each bursts in the timeout calculation. Reported-by: Da Xue Signed-off-by: Neil Armstrong --- To: Mark Brown To: Kevin Hilman To: Jerome Brunet To: Martin Blumenstingl Cc: linux-spi@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-amlogic@lists.infradead.org Cc: linux-kernel@vger.kernel.org --- drivers/spi/spi-meson-spicc.c | 24 ++++++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) --- base-commit: 247f34f7b80357943234f93f247a1ae6b6c3a740 change-id: 20221026-spicc-burst-delay-ea0526602760 Best regards, diff --git a/drivers/spi/spi-meson-spicc.c b/drivers/spi/spi-meson-spicc.c index bad201510a99..52bffab18329 100644 --- a/drivers/spi/spi-meson-spicc.c +++ b/drivers/spi/spi-meson-spicc.c @@ -160,6 +160,7 @@ struct meson_spicc_device { struct clk *clk; struct spi_message *message; struct spi_transfer *xfer; + struct completion done; const struct meson_spicc_data *data; u8 *tx_buf; u8 *rx_buf; @@ -282,7 +283,7 @@ static irqreturn_t meson_spicc_irq(int irq, void *data) /* Disable all IRQs */ writel(0, spicc->base + SPICC_INTREG); - spi_finalize_current_transfer(spicc->master); + complete(&spicc->done); return IRQ_HANDLED; } @@ -386,6 +387,7 @@ static int meson_spicc_transfer_one(struct spi_master *master, struct spi_transfer *xfer) { struct meson_spicc_device *spicc = spi_master_get_devdata(master); + unsigned long timeout; /* Store current transfer */ spicc->xfer = xfer; @@ -410,13 +412,29 @@ static int meson_spicc_transfer_one(struct spi_master *master, /* Setup burst */ meson_spicc_setup_burst(spicc); + /* Setup wait for completion */ + reinit_completion(&spicc->done); + + /* For each byte we wait for 8 cycles of the SPI clock */ + timeout = 8LL * MSEC_PER_SEC * xfer->len; + do_div(timeout, xfer->speed_hz); + + /* Add 10us delay between each fifo bursts */ + timeout += ((xfer->len >> 4) * 10) / MSEC_PER_SEC; + + /* Increase it twice and add 200 ms tolerance */ + timeout += timeout + 200; + /* Start burst */ writel_bits_relaxed(SPICC_XCH, SPICC_XCH, spicc->base + SPICC_CONREG); /* Enable interrupts */ writel_relaxed(SPICC_TC_EN, spicc->base + SPICC_INTREG); - return 1; + if (!wait_for_completion_timeout(&spicc->done, msecs_to_jiffies(timeout))) + return -ETIMEDOUT; + + return 0; } static int meson_spicc_prepare_message(struct spi_master *master, @@ -743,6 +761,8 @@ static int meson_spicc_probe(struct platform_device *pdev) spicc->pdev = pdev; platform_set_drvdata(pdev, spicc); + init_completion(&spicc->done); + spicc->base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(spicc->base)) { dev_err(&pdev->dev, "io resource mapping failed\n");