From patchwork Thu Oct 27 16:47:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 13022394 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 65F6AECAAA1 for ; Thu, 27 Oct 2022 16:55:34 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oo64a-0001rt-2C; Thu, 27 Oct 2022 12:49:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oo64Z-0001rY-7P for qemu-devel@nongnu.org; Thu, 27 Oct 2022 12:49:39 -0400 Received: from mail-vs1-xe2b.google.com ([2607:f8b0:4864:20::e2b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oo64X-0002WQ-SB for qemu-devel@nongnu.org; Thu, 27 Oct 2022 12:49:39 -0400 Received: by mail-vs1-xe2b.google.com with SMTP id z189so1694029vsb.4 for ; Thu, 27 Oct 2022 09:49:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=6iyPZgBe1iNrOkj3Tn5anzDtlrl3yPzW0hHihe0EGPM=; b=ECxWNsV0FtSHhvz6c0DnFrVuUI9MOzC8aDQY1tWUGjLhux5X7CTMq3Jlz3QbWsb1Uz 5a44Bd+9mk93CGX0SrO3GyRYU4zf8gtgvCZr4dT/ApzBDdfbWzzPt9n/xOv2BPQXssDi +GMNWClzglZmDG/r7+FNSi8BUV9iZaHyL/QmvcGxciq7ruAzy/9Cq+VtjOAYK3sqSbFH QYMXBL5zY6L/0OGd5of6CGuxKkpGUTrMKUp0A6ib54G9ByCM5IQbCU151SXPjrG3Cd9r aj6JOAFVmqTHbQuB6QwwkWmrIHM7tahvYHJ/vYXSlCqMLzGt/TdkPbWZplRAanMFo//t wXGQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6iyPZgBe1iNrOkj3Tn5anzDtlrl3yPzW0hHihe0EGPM=; b=rL7Hdu4BWsnAYV728keqUyqocG6Py3o8/osVgbUmy9f+zQ5NdVau8D7ZqUPrp/aKhw SnKDZv8Ltqm75JnJqpnQybtMnP1tmQP+F8xKFWbhINoKEErULS4wL9V1clSDKm67/tor dffjviWH6uDs07dcZmRdBZ+rFv+3MoZvYXkVBlK4+83Vy6HiFG8ileM8A4DYmoapCl/t FhOcQOsrAsmk/7Ff56ZyIxqSkCCAyV/VE2ema0pLmeo2HTdcmHTQg8nvgiJpjT0N2GKS whH6gz0zxXa27vP8ZAyMEASpofFAtzHSdAz4zhMUXmguxdVy+qiLImGN4xQkCNNV0MhP FmZg== X-Gm-Message-State: ACrzQf2DSHLcs3Rg+6yPL3R0yX2M2IhX66O4KY69gzvoP+s3L0SiqeRG J8LDJQSJlXoC7vCg66rFm75UYmUBF3ZkMA== X-Google-Smtp-Source: AMsMyM4yMzwuZ8mGv2RdzC1qMz7NIaG6yHQGOes7mYpraDGEIDV+zyNhyVLSJszOYT5T4wAGpLZ1qA== X-Received: by 2002:a17:902:e888:b0:186:a6be:1106 with SMTP id w8-20020a170902e88800b00186a6be1106mr22114793plg.150.1666889286771; Thu, 27 Oct 2022 09:48:06 -0700 (PDT) Received: from anup-ubuntu64-vm.. ([103.97.165.210]) by smtp.gmail.com with ESMTPSA id b8-20020a17090a9bc800b00212e5fe09d7sm1212543pjw.10.2022.10.27.09.48.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Oct 2022 09:48:06 -0700 (PDT) From: Anup Patel To: Peter Maydell , Palmer Dabbelt , Alistair Francis , Sagar Karandikar Cc: Atish Patra , Richard Henderson , Anup Patel , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Anup Patel Subject: [PATCH 1/5] target/riscv: Typo fix in sstc() predicate Date: Thu, 27 Oct 2022 22:17:39 +0530 Message-Id: <20221027164743.194265-2-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221027164743.194265-1-apatel@ventanamicro.com> References: <20221027164743.194265-1-apatel@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::e2b; envelope-from=apatel@ventanamicro.com; helo=mail-vs1-xe2b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org We should use "&&" instead of "&" when checking hcounteren.TM and henvcfg.STCE bits. Fixes: 3ec0fe18a31f ("target/riscv: Add vstimecmp suppor") Signed-off-by: Anup Patel Reviewed-by: Alistair Francis --- target/riscv/csr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 5c9a7ee287..716f9d960e 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -838,7 +838,7 @@ static RISCVException sstc(CPURISCVState *env, int csrno) } if (riscv_cpu_virt_enabled(env)) { - if (!(get_field(env->hcounteren, COUNTEREN_TM) & + if (!(get_field(env->hcounteren, COUNTEREN_TM) && get_field(env->henvcfg, HENVCFG_STCE))) { return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; } From patchwork Thu Oct 27 16:47:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 13022391 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AD1D2FA3740 for ; Thu, 27 Oct 2022 16:52:45 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oo63g-0000jF-Vi; Thu, 27 Oct 2022 12:48:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oo63I-0006y5-1B for qemu-devel@nongnu.org; Thu, 27 Oct 2022 12:48:28 -0400 Received: from mail-pl1-x636.google.com ([2607:f8b0:4864:20::636]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oo63D-0002PF-5R for qemu-devel@nongnu.org; Thu, 27 Oct 2022 12:48:19 -0400 Received: by mail-pl1-x636.google.com with SMTP id y4so2136801plb.2 for ; Thu, 27 Oct 2022 09:48:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=qs0X8zxgyj3M+ThrhWzA5l1+0EjQf/1I4S4JsajyPOI=; b=eo9KncHjTiK2grvCzyv91erlxKz6R6qsV6kaBo61xPvTCVrWiGsjofvwYEG6wKDJcN +4Pac3UQwRgAR8Jp+/cd9s/cPErJ9oiCBm9HsirYNUIZqhXiEsw4zfmtVyH91P7w3DFO foWkJvQhShlX7/S5XAirshiwdK+xojewLu50czyPlFsePFls7uN1bipMxsAn1W58ibgh e1fS8pG3Vq45cjrjZcmPguHLCWwxXlU0yhaAFhPKtOyxmkFt0xeT+O9BrS6GZmSHFQT8 m7HkXUGblYKeIOYCN1xxA/0u7AdesGhfTwoeRjdOnCf0KCBM9ctirnvgHmvKjnKnZWi0 vROQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qs0X8zxgyj3M+ThrhWzA5l1+0EjQf/1I4S4JsajyPOI=; b=usZbIob0dEMxw3HNONUT4W5ZuvixDAwvRJaClMCUCcR/Cw8vj8hUipMqGeFeLksPR8 6nBufxhXPAVfm8LDfDTmoIlcZ8BK39d4Hm9jDyjDWhArUnjWW7fOSzPE7cfzt9wksZJq HYcmn025bCdHERLEnDK+jxn1CSjQ9nzBBAoQvN50FEru5QwEiQhOW9ljHWodtVYo6qAx 94YvwOSFntLhhFfC+knOqjE2MY32fax8cCY9higqQCF1oVfWkIFkef/W4xYkvN/h+Oyr QrYYTiTXqY2j2ViikD3cM7j5G42rCUx13ZAEkrGNV6PJb/5q5rhNVY1Yt5ykSZu5XutV +JDw== X-Gm-Message-State: ACrzQf1jiGuho6s84CyoaOUalKa6wXkFBi2GeJpg4f1C21M02+ZBHSSO H6tbvaOAUB8WjPZRC0CSx+07MQ== X-Google-Smtp-Source: AMsMyM5dJKqlpdcGnrgJIQSxX/PUXVsyhVfg8IguBgqgDTNQCEOT0tOLdLN0ZsWrMh3iI3wDWxNuNA== X-Received: by 2002:a17:90b:4d0d:b0:20d:6fc0:51 with SMTP id mw13-20020a17090b4d0d00b0020d6fc00051mr11000066pjb.10.1666889291345; Thu, 27 Oct 2022 09:48:11 -0700 (PDT) Received: from anup-ubuntu64-vm.. ([103.97.165.210]) by smtp.gmail.com with ESMTPSA id b8-20020a17090a9bc800b00212e5fe09d7sm1212543pjw.10.2022.10.27.09.48.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Oct 2022 09:48:10 -0700 (PDT) From: Anup Patel To: Peter Maydell , Palmer Dabbelt , Alistair Francis , Sagar Karandikar Cc: Atish Patra , Richard Henderson , Anup Patel , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Anup Patel Subject: [PATCH 2/5] target/riscv: Update VS timer whenever htimedelta changes Date: Thu, 27 Oct 2022 22:17:40 +0530 Message-Id: <20221027164743.194265-3-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221027164743.194265-1-apatel@ventanamicro.com> References: <20221027164743.194265-1-apatel@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=apatel@ventanamicro.com; helo=mail-pl1-x636.google.com X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1, DKIM_SIGNED=0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The htimedelta[h] CSR has impact on the VS timer comparison so we should call riscv_timer_write_timecmp() whenever htimedelta changes. Fixes: 3ec0fe18a31f ("target/riscv: Add vstimecmp suppor") Signed-off-by: Anup Patel Reviewed-by: Alistair Francis --- target/riscv/csr.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 716f9d960e..4b1a608260 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -2722,6 +2722,8 @@ static RISCVException read_htimedelta(CPURISCVState *env, int csrno, static RISCVException write_htimedelta(CPURISCVState *env, int csrno, target_ulong val) { + RISCVCPU *cpu = env_archcpu(env); + if (!env->rdtime_fn) { return RISCV_EXCP_ILLEGAL_INST; } @@ -2731,6 +2733,12 @@ static RISCVException write_htimedelta(CPURISCVState *env, int csrno, } else { env->htimedelta = val; } + + if (cpu->cfg.ext_sstc && env->rdtime_fn) { + riscv_timer_write_timecmp(cpu, env->vstimer, env->vstimecmp, + env->htimedelta, MIP_VSTIP); + } + return RISCV_EXCP_NONE; } @@ -2748,11 +2756,19 @@ static RISCVException read_htimedeltah(CPURISCVState *env, int csrno, static RISCVException write_htimedeltah(CPURISCVState *env, int csrno, target_ulong val) { + RISCVCPU *cpu = env_archcpu(env); + if (!env->rdtime_fn) { return RISCV_EXCP_ILLEGAL_INST; } env->htimedelta = deposit64(env->htimedelta, 32, 32, (uint64_t)val); + + if (cpu->cfg.ext_sstc && env->rdtime_fn) { + riscv_timer_write_timecmp(cpu, env->vstimer, env->vstimecmp, + env->htimedelta, MIP_VSTIP); + } + return RISCV_EXCP_NONE; } From patchwork Thu Oct 27 16:47:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 13022390 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id ABE89FA3740 for ; Thu, 27 Oct 2022 16:52:29 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oo63g-0000LQ-C6; Thu, 27 Oct 2022 12:48:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oo63O-0007IT-Lu for qemu-devel@nongnu.org; Thu, 27 Oct 2022 12:48:28 -0400 Received: from mail-pg1-x529.google.com ([2607:f8b0:4864:20::529]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oo63F-0002Pv-IJ for qemu-devel@nongnu.org; Thu, 27 Oct 2022 12:48:21 -0400 Received: by mail-pg1-x529.google.com with SMTP id h185so2032705pgc.10 for ; Thu, 27 Oct 2022 09:48:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=dPNKG9h2hj94wjs8mxSr/AkuBfy4MSWYkNKhqXWd3yQ=; b=ZcjxpFP3V3mA0RDpgk8XWDnvbu1Zpb0LBmNRI5D+RRitcrooQ2mhPqUL5i3C0u4a0d LtprEnUerKAhavxn8f1GCCC3g3B1oNvPTPSKo/gOVesU5pUDAygZRFwZBiV1TgVaVdwc Zz1D6gZBn+RZKFEMy5dPf7+tlzTY2J+ISx7HNIoptp404IpfhzpJSimzRs/hLxO5Rl4B LiKWjYJ+p6z/+4VeXWmjgbFQJ+b9xmmUyA5phbWrgrYNTgSFLW/2nTnQgKtrGwBqa/ke jPd/Xeogl3bX7DGVOTAVlnq+E1AUvnhXpbKXj2nSK3hcIeXTi0p0npFB5csv8+qeRHym X97A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dPNKG9h2hj94wjs8mxSr/AkuBfy4MSWYkNKhqXWd3yQ=; b=iudci8LmVBnFi2X9LmOqQNxXL4JwAr4G9cIIfNu8umkhTVjKy9J916s0XHHQJNEkSA Y4BLzVGwBCKDmcDpyM85a+7tB7k/jTN6G6GkfYBLjNSls9HVprBnpx0Z1a10nUPhf+bc o1WVNarACc+cI6ngB/Ey7XBZrLC5OLd0T8t7JkzaXEzm22A/ItVl9gS3TPq2SFbdNY0r wUVNlTcxS/s4ryYoY2dQFluTxHfs7EySHZdmJvmYlfo6FwWWWHWZbiU502nR1zfTtOl4 9jjah7GWba/1uVERaXjHe6hpwgVoay13EaxHRp+po8/m3WhrAJh7c6CsZ83ArnmifbQy PNbQ== X-Gm-Message-State: ACrzQf1nmtn+v2eWWrY+rjqZhdSoGqFKdvpQ5ZLX4mQFYCg0sWNv7Uy2 ziY/K47NqXhwypCg1YU/a4HL5A== X-Google-Smtp-Source: AMsMyM5DotugxLhi22bo7QnHr5/87zGiaBFYnEwPyaUvFjfkHpAuDWIT3/WSaGHZM8Td4nGpXXLo3w== X-Received: by 2002:a05:6a00:23d3:b0:56c:9f62:3369 with SMTP id g19-20020a056a0023d300b0056c9f623369mr3392957pfc.22.1666889295959; Thu, 27 Oct 2022 09:48:15 -0700 (PDT) Received: from anup-ubuntu64-vm.. ([103.97.165.210]) by smtp.gmail.com with ESMTPSA id b8-20020a17090a9bc800b00212e5fe09d7sm1212543pjw.10.2022.10.27.09.48.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Oct 2022 09:48:15 -0700 (PDT) From: Anup Patel To: Peter Maydell , Palmer Dabbelt , Alistair Francis , Sagar Karandikar Cc: Atish Patra , Richard Henderson , Anup Patel , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Anup Patel Subject: [PATCH 3/5] target/riscv: Don't clear mask in riscv_cpu_update_mip() for VSTIP Date: Thu, 27 Oct 2022 22:17:41 +0530 Message-Id: <20221027164743.194265-4-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221027164743.194265-1-apatel@ventanamicro.com> References: <20221027164743.194265-1-apatel@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::529; envelope-from=apatel@ventanamicro.com; helo=mail-pg1-x529.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Instead of clearing mask in riscv_cpu_update_mip() for VSTIP, we should call riscv_cpu_update_mip() with mask == 0 from timer_helper.c for VSTIP. Fixes: 3ec0fe18a31f ("target/riscv: Add vstimecmp suppor") Signed-off-by: Anup Patel Reviewed-by: Alistair Francis --- target/riscv/cpu_helper.c | 2 -- target/riscv/time_helper.c | 12 ++++++++---- 2 files changed, 8 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 5d66246c2c..a403825e49 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -617,8 +617,6 @@ uint64_t riscv_cpu_update_mip(RISCVCPU *cpu, uint64_t mask, uint64_t value) vsgein = (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0; } - /* No need to update mip for VSTIP */ - mask = ((mask == MIP_VSTIP) && env->vstime_irq) ? 0 : mask; vstip = env->vstime_irq ? MIP_VSTIP : 0; if (!qemu_mutex_iothread_locked()) { diff --git a/target/riscv/time_helper.c b/target/riscv/time_helper.c index 8cce667dfd..4fb2a471a9 100644 --- a/target/riscv/time_helper.c +++ b/target/riscv/time_helper.c @@ -27,7 +27,7 @@ static void riscv_vstimer_cb(void *opaque) RISCVCPU *cpu = opaque; CPURISCVState *env = &cpu->env; env->vstime_irq = 1; - riscv_cpu_update_mip(cpu, MIP_VSTIP, BOOL_TO_MASK(1)); + riscv_cpu_update_mip(cpu, 0, BOOL_TO_MASK(1)); } static void riscv_stimer_cb(void *opaque) @@ -57,16 +57,20 @@ void riscv_timer_write_timecmp(RISCVCPU *cpu, QEMUTimer *timer, */ if (timer_irq == MIP_VSTIP) { env->vstime_irq = 1; + riscv_cpu_update_mip(cpu, 0, BOOL_TO_MASK(1)); + } else { + riscv_cpu_update_mip(cpu, MIP_STIP, BOOL_TO_MASK(1)); } - riscv_cpu_update_mip(cpu, timer_irq, BOOL_TO_MASK(1)); return; } + /* Clear the [VS|S]TIP bit in mip */ if (timer_irq == MIP_VSTIP) { env->vstime_irq = 0; + riscv_cpu_update_mip(cpu, 0, BOOL_TO_MASK(0)); + } else { + riscv_cpu_update_mip(cpu, timer_irq, BOOL_TO_MASK(0)); } - /* Clear the [V]STIP bit in mip */ - riscv_cpu_update_mip(cpu, timer_irq, BOOL_TO_MASK(0)); /* otherwise, set up the future timer interrupt */ diff = timecmp - rtc_r; From patchwork Thu Oct 27 16:47:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 13022392 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 31177FA3741 for ; Thu, 27 Oct 2022 16:52:46 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oo64J-00018M-2y; Thu, 27 Oct 2022 12:49:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oo63Q-0007Ib-7x for qemu-devel@nongnu.org; Thu, 27 Oct 2022 12:48:28 -0400 Received: from mail-pl1-x62f.google.com ([2607:f8b0:4864:20::62f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oo63N-0002Qg-Ht for qemu-devel@nongnu.org; Thu, 27 Oct 2022 12:48:26 -0400 Received: by mail-pl1-x62f.google.com with SMTP id d9so2118636pll.7 for ; Thu, 27 Oct 2022 09:48:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=r25VipQj5iv3sDMX8KrTJiiJWqt3kWaLtBvAXK9jQF4=; b=n5Q5eE7SKQPqJey69xXVyc+//AD3n+0ZiK5rtTK9S+HAbpfxl5fs15dgYAeqmw8e0R SUI8wXvQomR5Bf2bD1X+2SC4/BZO4WQfUWg3PgMkUntCZK9R8N4N4yRkILE7pRF6/9K0 o7ikikQtuehPb0he70SzzvRK5Dpn9CSrQPQslG3XC+C4UKLbj4r9MvnjXeoXaXdlqFeg F0flZ1a5beB0voyi0ndZVRsj8XpZRECNKQFafyOfRY7P/eV7x3GMWg+EFWFRg+oKos3Z 1WB/cU38JEvBqDwqZzhpSoYc8jmmRailR1wOFxMqiNmRyguEK/HYlxAXH8294D6N4X9m nWJw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=r25VipQj5iv3sDMX8KrTJiiJWqt3kWaLtBvAXK9jQF4=; b=qg9YdB8eZY+DCv7YxJxl0LFVwsc/ndSqt6DyqTVKcB3zaK5jVDQn2qqOBMo4n8X2Re h+jsqLtafcSMXhOIKtPyu8e3mqCHCrCLs+ATw4lsTBCMU7OdsINjmbi4kiR7TW/h+7pp 0pfnWFz46QmvXLDZxa3oywxfVJHIqPdFXt5c1AV4VcJ986zThNOMdvK+NlPz0fn/jaun 3JNcV7WHxQUyPAqnvjP7gy1f+7MG5nLH+V3poz9p2hRfK7RTqqqSUJkSdn5CzYUqgGLi uYUe5UySdUXnCzSk7uzsPv6EqL+X//z+DHIf+vb5M0i75KBkn9yT+VyleANwG9V6t5t/ tuCA== X-Gm-Message-State: ACrzQf11NB5RNE2KhDD9lisEvRkJOmR5xSt9a6bYprov2zTIys5ewWfw +O+/sehfvz2x6/9Ec03Nl3v7yQ== X-Google-Smtp-Source: AMsMyM6avW1Z37vV1LY2XHMpf7pcpTBFao/yq25Liu1RE7Vlg6gf5+XT2p5ehF+LrcLuuAMjzvFEgw== X-Received: by 2002:a17:90a:65c7:b0:20f:8385:cc18 with SMTP id i7-20020a17090a65c700b0020f8385cc18mr11253052pjs.235.1666889301232; Thu, 27 Oct 2022 09:48:21 -0700 (PDT) Received: from anup-ubuntu64-vm.. ([103.97.165.210]) by smtp.gmail.com with ESMTPSA id b8-20020a17090a9bc800b00212e5fe09d7sm1212543pjw.10.2022.10.27.09.48.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Oct 2022 09:48:20 -0700 (PDT) From: Anup Patel To: Peter Maydell , Palmer Dabbelt , Alistair Francis , Sagar Karandikar Cc: Atish Patra , Richard Henderson , Anup Patel , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Anup Patel Subject: [PATCH 4/5] target/riscv: No need to re-start QEMU timer when timecmp == UINT64_MAX Date: Thu, 27 Oct 2022 22:17:42 +0530 Message-Id: <20221027164743.194265-5-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221027164743.194265-1-apatel@ventanamicro.com> References: <20221027164743.194265-1-apatel@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=apatel@ventanamicro.com; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The time CSR will wrap-around immediately after reaching UINT64_MAX so we don't need to re-start QEMU timer when timecmp == UINT64_MAX in riscv_timer_write_timecmp(). Signed-off-by: Anup Patel Reviewed-by: Alistair Francis --- target/riscv/time_helper.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/target/riscv/time_helper.c b/target/riscv/time_helper.c index 4fb2a471a9..1ee9f94813 100644 --- a/target/riscv/time_helper.c +++ b/target/riscv/time_helper.c @@ -72,6 +72,14 @@ void riscv_timer_write_timecmp(RISCVCPU *cpu, QEMUTimer *timer, riscv_cpu_update_mip(cpu, timer_irq, BOOL_TO_MASK(0)); } + /* + * Don't re-start the QEMU timer when timecmp == UINT64_MAX because + * time CSR will wrap-around immediately after reaching UINT64_MAX. + */ + if (timecmp == UINT64_MAX) { + return; + } + /* otherwise, set up the future timer interrupt */ diff = timecmp - rtc_r; /* back to ns (note args switched in muldiv64) */ From patchwork Thu Oct 27 16:47:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 13022393 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0C6D3FA3740 for ; Thu, 27 Oct 2022 16:53:20 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oo64J-0001Fn-RJ; Thu, 27 Oct 2022 12:49:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oo63S-0007pb-RV for qemu-devel@nongnu.org; Thu, 27 Oct 2022 12:48:30 -0400 Received: from mail-pf1-x434.google.com ([2607:f8b0:4864:20::434]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oo63Q-0002R9-JW for qemu-devel@nongnu.org; Thu, 27 Oct 2022 12:48:30 -0400 Received: by mail-pf1-x434.google.com with SMTP id y13so2133002pfp.7 for ; Thu, 27 Oct 2022 09:48:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=SFXOtEFct7aZBn9qsLOf6vADmM9nDSRAlMOl6gM3bOU=; b=NgM3usz7gaZwahJwl7XaEMDjn9O+nOnWVafU7CTkss0He3rapu0w7ETyvr+CghP95a Qtnmckg0CZGlItPGyQrO/+17M2jOA8RG+VrOhomlfbrgV4RgoCpomz1erm7FtthaiG30 ED9mpStEkbGhxLD/eh9HcMYVEtFUpcHMcHLZA92M/Hm3Ip6mNrWzUqvHMcmxX4w0n0O+ HLiKyPpxUy4+xh7LG1jV7AZv32S/lWvqAHGwsQEB47emShiFAF8svcPlwPscGlnVG77Q oSEiNUjMrUPAzPXavd3rePL01Or82+TbAveqIcFSCKoNLayht0YqckZmZUO8gPWCJbtM tQ+A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=SFXOtEFct7aZBn9qsLOf6vADmM9nDSRAlMOl6gM3bOU=; b=z8mmd4l+EOLcpMa5iILCsYWufc21bc/TPA6iRAVjJW89hf3BVrjzlWmAmrC4g+Nr1L WhwEBhZUhgymDYi3r/2AyEUXD+4MP9e5dQbHaiuXCbjfZMngrIu795Xb4iQgJC3qfkeB C6xXT+jtL8SBfUyL72zJfRM77OxGjzOUNyyZtf6X0OpaoglZ5a6gM4g+pxd1sknwKntP ItU/tXmNRLSU5UFYJ48AO+R8zzIjQ5Bzhj+2HF1onOxEPa1qFb//0/x9q5N2j5dMB6PI 0qcZWBYCgoB74iafPzHjeNZKtvDMtIoVvtHBZ04/wDsWrv2890m/GmHugb3WfZ+0O/2k ZZ1w== X-Gm-Message-State: ACrzQf108vV/LCVs7jeW4SmIju/crrwCjhVJTOJCYKAzFYLC8X6ppSE0 TkgxeC9HcFlZh2pDc9xlvSIKEA== X-Google-Smtp-Source: AMsMyM4KHOqpJw3kbTDRPLN5EmHcktY8uvzNP69XS7bp4+uNSL+TRKf4u4nGjxdawcmmuoMyWt9GmA== X-Received: by 2002:a05:6a00:16c4:b0:535:890:d4a with SMTP id l4-20020a056a0016c400b0053508900d4amr50513833pfc.0.1666889306091; Thu, 27 Oct 2022 09:48:26 -0700 (PDT) Received: from anup-ubuntu64-vm.. ([103.97.165.210]) by smtp.gmail.com with ESMTPSA id b8-20020a17090a9bc800b00212e5fe09d7sm1212543pjw.10.2022.10.27.09.48.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Oct 2022 09:48:25 -0700 (PDT) From: Anup Patel To: Peter Maydell , Palmer Dabbelt , Alistair Francis , Sagar Karandikar Cc: Atish Patra , Richard Henderson , Anup Patel , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Anup Patel Subject: [PATCH 5/5] target/riscv: Ensure opcode is saved for all relevant instructions Date: Thu, 27 Oct 2022 22:17:43 +0530 Message-Id: <20221027164743.194265-6-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221027164743.194265-1-apatel@ventanamicro.com> References: <20221027164743.194265-1-apatel@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=apatel@ventanamicro.com; helo=mail-pf1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org We should call decode_save_opc() for all relevant instructions which can potentially generate a virtual instruction fault or a guest page fault because generating transformed instruction upon guest page fault expects opcode to be available. Without this, hypervisor will see transformed instruction as zero in htinst CSR for guest MMIO emulation which makes MMIO emulation in hypervisor slow and also breaks nested virtualization. Fixes: a9814e3e08d2 ("target/riscv: Minimize the calls to decode_save_opc") Signed-off-by: Anup Patel --- target/riscv/insn_trans/trans_rva.c.inc | 10 +++++++--- target/riscv/insn_trans/trans_rvd.c.inc | 2 ++ target/riscv/insn_trans/trans_rvf.c.inc | 2 ++ target/riscv/insn_trans/trans_rvh.c.inc | 3 +++ target/riscv/insn_trans/trans_rvi.c.inc | 2 ++ target/riscv/insn_trans/trans_rvzfh.c.inc | 2 ++ target/riscv/insn_trans/trans_svinval.c.inc | 3 +++ 7 files changed, 21 insertions(+), 3 deletions(-) diff --git a/target/riscv/insn_trans/trans_rva.c.inc b/target/riscv/insn_trans/trans_rva.c.inc index 45db82c9be..5f194a447b 100644 --- a/target/riscv/insn_trans/trans_rva.c.inc +++ b/target/riscv/insn_trans/trans_rva.c.inc @@ -20,8 +20,10 @@ static bool gen_lr(DisasContext *ctx, arg_atomic *a, MemOp mop) { - TCGv src1 = get_address(ctx, a->rs1, 0); + TCGv src1; + decode_save_opc(ctx); + src1 = get_address(ctx, a->rs1, 0); if (a->rl) { tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); } @@ -43,6 +45,7 @@ static bool gen_sc(DisasContext *ctx, arg_atomic *a, MemOp mop) TCGLabel *l1 = gen_new_label(); TCGLabel *l2 = gen_new_label(); + decode_save_opc(ctx); src1 = get_address(ctx, a->rs1, 0); tcg_gen_brcond_tl(TCG_COND_NE, load_res, src1, l1); @@ -81,9 +84,10 @@ static bool gen_amo(DisasContext *ctx, arg_atomic *a, MemOp mop) { TCGv dest = dest_gpr(ctx, a->rd); - TCGv src1 = get_address(ctx, a->rs1, 0); - TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); + TCGv src1, src2 = get_gpr(ctx, a->rs2, EXT_NONE); + decode_save_opc(ctx); + src1 = get_address(ctx, a->rs1, 0); func(dest, src1, src2, ctx->mem_idx, mop); gen_set_gpr(ctx, a->rd, dest); diff --git a/target/riscv/insn_trans/trans_rvd.c.inc b/target/riscv/insn_trans/trans_rvd.c.inc index 1397c1ce1c..6e3159b797 100644 --- a/target/riscv/insn_trans/trans_rvd.c.inc +++ b/target/riscv/insn_trans/trans_rvd.c.inc @@ -38,6 +38,7 @@ static bool trans_fld(DisasContext *ctx, arg_fld *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVD); + decode_save_opc(ctx); addr = get_address(ctx, a->rs1, a->imm); tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], addr, ctx->mem_idx, MO_TEUQ); @@ -52,6 +53,7 @@ static bool trans_fsd(DisasContext *ctx, arg_fsd *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVD); + decode_save_opc(ctx); addr = get_address(ctx, a->rs1, a->imm); tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], addr, ctx->mem_idx, MO_TEUQ); return true; diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_trans/trans_rvf.c.inc index a1d3eb52ad..965e1f8d11 100644 --- a/target/riscv/insn_trans/trans_rvf.c.inc +++ b/target/riscv/insn_trans/trans_rvf.c.inc @@ -38,6 +38,7 @@ static bool trans_flw(DisasContext *ctx, arg_flw *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); + decode_save_opc(ctx); addr = get_address(ctx, a->rs1, a->imm); dest = cpu_fpr[a->rd]; tcg_gen_qemu_ld_i64(dest, addr, ctx->mem_idx, MO_TEUL); @@ -54,6 +55,7 @@ static bool trans_fsw(DisasContext *ctx, arg_fsw *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); + decode_save_opc(ctx); addr = get_address(ctx, a->rs1, a->imm); tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], addr, ctx->mem_idx, MO_TEUL); return true; diff --git a/target/riscv/insn_trans/trans_rvh.c.inc b/target/riscv/insn_trans/trans_rvh.c.inc index 4f8aecddc7..9248b48c36 100644 --- a/target/riscv/insn_trans/trans_rvh.c.inc +++ b/target/riscv/insn_trans/trans_rvh.c.inc @@ -36,6 +36,7 @@ static bool do_hlv(DisasContext *ctx, arg_r2 *a, MemOp mop) #ifdef CONFIG_USER_ONLY return false; #else + decode_save_opc(ctx); if (check_access(ctx)) { TCGv dest = dest_gpr(ctx, a->rd); TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE); @@ -82,6 +83,7 @@ static bool do_hsv(DisasContext *ctx, arg_r2_s *a, MemOp mop) #ifdef CONFIG_USER_ONLY return false; #else + decode_save_opc(ctx); if (check_access(ctx)) { TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE); TCGv data = get_gpr(ctx, a->rs2, EXT_NONE); @@ -135,6 +137,7 @@ static bool trans_hsv_d(DisasContext *ctx, arg_hsv_d *a) static bool do_hlvx(DisasContext *ctx, arg_r2 *a, void (*func)(TCGv, TCGv_env, TCGv)) { + decode_save_opc(ctx); if (check_access(ctx)) { TCGv dest = dest_gpr(ctx, a->rd); TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE); diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc index c49dbec0eb..1665efb639 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -261,6 +261,7 @@ static bool gen_load_i128(DisasContext *ctx, arg_lb *a, MemOp memop) static bool gen_load(DisasContext *ctx, arg_lb *a, MemOp memop) { + decode_save_opc(ctx); if (get_xl(ctx) == MXL_RV128) { return gen_load_i128(ctx, a, memop); } else { @@ -350,6 +351,7 @@ static bool gen_store_i128(DisasContext *ctx, arg_sb *a, MemOp memop) static bool gen_store(DisasContext *ctx, arg_sb *a, MemOp memop) { + decode_save_opc(ctx); if (get_xl(ctx) == MXL_RV128) { return gen_store_i128(ctx, a, memop); } else { diff --git a/target/riscv/insn_trans/trans_rvzfh.c.inc b/target/riscv/insn_trans/trans_rvzfh.c.inc index 5d07150cd0..2ad5716312 100644 --- a/target/riscv/insn_trans/trans_rvzfh.c.inc +++ b/target/riscv/insn_trans/trans_rvzfh.c.inc @@ -49,6 +49,7 @@ static bool trans_flh(DisasContext *ctx, arg_flh *a) REQUIRE_FPU; REQUIRE_ZFH_OR_ZFHMIN(ctx); + decode_save_opc(ctx); t0 = get_gpr(ctx, a->rs1, EXT_NONE); if (a->imm) { TCGv temp = temp_new(ctx); @@ -71,6 +72,7 @@ static bool trans_fsh(DisasContext *ctx, arg_fsh *a) REQUIRE_FPU; REQUIRE_ZFH_OR_ZFHMIN(ctx); + decode_save_opc(ctx); t0 = get_gpr(ctx, a->rs1, EXT_NONE); if (a->imm) { TCGv temp = tcg_temp_new(); diff --git a/target/riscv/insn_trans/trans_svinval.c.inc b/target/riscv/insn_trans/trans_svinval.c.inc index 2682bd969f..f3cd7d5c0b 100644 --- a/target/riscv/insn_trans/trans_svinval.c.inc +++ b/target/riscv/insn_trans/trans_svinval.c.inc @@ -28,6 +28,7 @@ static bool trans_sinval_vma(DisasContext *ctx, arg_sinval_vma *a) /* Do the same as sfence.vma currently */ REQUIRE_EXT(ctx, RVS); #ifndef CONFIG_USER_ONLY + decode_save_opc(ctx); gen_helper_tlb_flush(cpu_env); return true; #endif @@ -56,6 +57,7 @@ static bool trans_hinval_vvma(DisasContext *ctx, arg_hinval_vvma *a) /* Do the same as hfence.vvma currently */ REQUIRE_EXT(ctx, RVH); #ifndef CONFIG_USER_ONLY + decode_save_opc(ctx); gen_helper_hyp_tlb_flush(cpu_env); return true; #endif @@ -68,6 +70,7 @@ static bool trans_hinval_gvma(DisasContext *ctx, arg_hinval_gvma *a) /* Do the same as hfence.gvma currently */ REQUIRE_EXT(ctx, RVH); #ifndef CONFIG_USER_ONLY + decode_save_opc(ctx); gen_helper_hyp_gvma_tlb_flush(cpu_env); return true; #endif