From patchwork Fri Oct 28 03:41:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 13023032 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DEE87FA3745 for ; Fri, 28 Oct 2022 03:42:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236177AbiJ1DmV (ORCPT ); Thu, 27 Oct 2022 23:42:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56572 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235976AbiJ1DmQ (ORCPT ); Thu, 27 Oct 2022 23:42:16 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C2838D18C1; Thu, 27 Oct 2022 20:42:15 -0700 (PDT) Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 29S2Y0ma029946; Fri, 28 Oct 2022 03:42:04 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=eRmAl7BnMhR0tqcXfdbXtulC+rC9JOnkuGMe01W4BCc=; b=X+hOOeTpygaK0z9dIkw0NHFZTI+vR9lDhaCSsmv58+hJPQK0I4PVeA5sHdfzpvKLZe9t NAVdKsMbCpOEzXYEOjjn1n2QL8W8329T8RMalPf+C5sBIEzuP60MgfZg9XnbEMxlt3Vu FYTGGINGNuPZFsz70d6VoSF2EHgAfBB1olr6B1iwPVwJxeOk3p4BNBHrdvmp9MV7NPxG oU3jUCnly/qRjYBxz1dDKj0TDp52O1+18soyyTP+d+mEtm2DHVYaEgbjHF4OPVYT/m4U ps121E41FD3lsLO7YS7ocKxa8W8UZtkD2+wSDr8Jer5MAL9xf9s/BYLaT9bIiv9EGDJj Wg== Received: from nalasppmta02.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3kfahubye4-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 28 Oct 2022 03:42:03 +0000 Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 29S3g2Ia001380 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 28 Oct 2022 03:42:02 GMT Received: from th-lint-050.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Thu, 27 Oct 2022 20:42:01 -0700 From: Bjorn Andersson To: Georgi Djakov , Sibi Sankar CC: Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , "Rob Herring" , Mike Tipton , "Johan Hovold" , , , , Subject: [PATCH 01/10] interconnect: qcom: osm-l3: Use platform-independent node ids Date: Thu, 27 Oct 2022 20:41:46 -0700 Message-ID: <20221028034155.5580-2-quic_bjorande@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221028034155.5580-1-quic_bjorande@quicinc.com> References: <20221028034155.5580-1-quic_bjorande@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: fFWfN06SxWJUNPYlzMMOnoFQbPWFVS_B X-Proofpoint-ORIG-GUID: fFWfN06SxWJUNPYlzMMOnoFQbPWFVS_B X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-10-27_07,2022-10-27_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 phishscore=0 malwarescore=0 suspectscore=0 bulkscore=0 impostorscore=0 mlxlogscore=999 mlxscore=0 lowpriorityscore=0 priorityscore=1501 clxscore=1015 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2210170000 definitions=main-2210280022 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org The identifiers used for nodes needs to be unique in the running system, but defining them per platform results in a lot of duplicated definitions and prevents us from using generic compatibles. As these identifiers are not exposed outside the kernel, change to use driver-local numbers, picked completely at random. Signed-off-by: Bjorn Andersson --- drivers/interconnect/qcom/osm-l3.c | 87 +++++++++++------------------- 1 file changed, 30 insertions(+), 57 deletions(-) diff --git a/drivers/interconnect/qcom/osm-l3.c b/drivers/interconnect/qcom/osm-l3.c index ddbdf0943f94..d23769844419 100644 --- a/drivers/interconnect/qcom/osm-l3.c +++ b/drivers/interconnect/qcom/osm-l3.c @@ -74,6 +74,11 @@ struct qcom_osm_l3_desc { unsigned int reg_perf_state; }; +enum { + OSM_L3_MASTER_NODE = 10000, + OSM_L3_SLAVE_NODE, +}; + #define DEFINE_QNODE(_name, _id, _buswidth, ...) \ static const struct qcom_osm_l3_node _name = { \ .name = #_name, \ @@ -83,97 +88,65 @@ struct qcom_osm_l3_desc { .links = { __VA_ARGS__ }, \ } -DEFINE_QNODE(sdm845_osm_apps_l3, SDM845_MASTER_OSM_L3_APPS, 16, SDM845_SLAVE_OSM_L3); -DEFINE_QNODE(sdm845_osm_l3, SDM845_SLAVE_OSM_L3, 16); +DEFINE_QNODE(osm_l3_master, OSM_L3_MASTER_NODE, 16, OSM_L3_SLAVE_NODE); +DEFINE_QNODE(osm_l3_slave, OSM_L3_SLAVE_NODE, 16); + +static const struct qcom_osm_l3_node * const osm_l3_nodes[] = { + [MASTER_OSM_L3_APPS] = &osm_l3_master, + [SLAVE_OSM_L3] = &osm_l3_slave, +}; + +DEFINE_QNODE(epss_l3_master, OSM_L3_MASTER_NODE, 32, OSM_L3_SLAVE_NODE); +DEFINE_QNODE(epss_l3_slave, OSM_L3_SLAVE_NODE, 32); -static const struct qcom_osm_l3_node * const sdm845_osm_l3_nodes[] = { - [MASTER_OSM_L3_APPS] = &sdm845_osm_apps_l3, - [SLAVE_OSM_L3] = &sdm845_osm_l3, +static const struct qcom_osm_l3_node * const epss_l3_nodes[] = { + [MASTER_EPSS_L3_APPS] = &epss_l3_master, + [SLAVE_EPSS_L3_SHARED] = &epss_l3_slave, }; static const struct qcom_osm_l3_desc sdm845_icc_osm_l3 = { - .nodes = sdm845_osm_l3_nodes, - .num_nodes = ARRAY_SIZE(sdm845_osm_l3_nodes), + .nodes = osm_l3_nodes, + .num_nodes = ARRAY_SIZE(osm_l3_nodes), .lut_row_size = OSM_LUT_ROW_SIZE, .reg_freq_lut = OSM_REG_FREQ_LUT, .reg_perf_state = OSM_REG_PERF_STATE, }; -DEFINE_QNODE(sc7180_osm_apps_l3, SC7180_MASTER_OSM_L3_APPS, 16, SC7180_SLAVE_OSM_L3); -DEFINE_QNODE(sc7180_osm_l3, SC7180_SLAVE_OSM_L3, 16); - -static const struct qcom_osm_l3_node * const sc7180_osm_l3_nodes[] = { - [MASTER_OSM_L3_APPS] = &sc7180_osm_apps_l3, - [SLAVE_OSM_L3] = &sc7180_osm_l3, -}; - static const struct qcom_osm_l3_desc sc7180_icc_osm_l3 = { - .nodes = sc7180_osm_l3_nodes, - .num_nodes = ARRAY_SIZE(sc7180_osm_l3_nodes), + .nodes = osm_l3_nodes, + .num_nodes = ARRAY_SIZE(osm_l3_nodes), .lut_row_size = OSM_LUT_ROW_SIZE, .reg_freq_lut = OSM_REG_FREQ_LUT, .reg_perf_state = OSM_REG_PERF_STATE, }; -DEFINE_QNODE(sc7280_epss_apps_l3, SC7280_MASTER_EPSS_L3_APPS, 32, SC7280_SLAVE_EPSS_L3); -DEFINE_QNODE(sc7280_epss_l3, SC7280_SLAVE_EPSS_L3, 32); - -static const struct qcom_osm_l3_node * const sc7280_epss_l3_nodes[] = { - [MASTER_EPSS_L3_APPS] = &sc7280_epss_apps_l3, - [SLAVE_EPSS_L3_SHARED] = &sc7280_epss_l3, -}; - static const struct qcom_osm_l3_desc sc7280_icc_epss_l3 = { - .nodes = sc7280_epss_l3_nodes, - .num_nodes = ARRAY_SIZE(sc7280_epss_l3_nodes), + .nodes = epss_l3_nodes, + .num_nodes = ARRAY_SIZE(epss_l3_nodes), .lut_row_size = EPSS_LUT_ROW_SIZE, .reg_freq_lut = EPSS_REG_FREQ_LUT, .reg_perf_state = EPSS_REG_PERF_STATE, }; -DEFINE_QNODE(sc8180x_osm_apps_l3, SC8180X_MASTER_OSM_L3_APPS, 32, SC8180X_SLAVE_OSM_L3); -DEFINE_QNODE(sc8180x_osm_l3, SC8180X_SLAVE_OSM_L3, 32); - -static const struct qcom_osm_l3_node * const sc8180x_osm_l3_nodes[] = { - [MASTER_OSM_L3_APPS] = &sc8180x_osm_apps_l3, - [SLAVE_OSM_L3] = &sc8180x_osm_l3, -}; - static const struct qcom_osm_l3_desc sc8180x_icc_osm_l3 = { - .nodes = sc8180x_osm_l3_nodes, - .num_nodes = ARRAY_SIZE(sc8180x_osm_l3_nodes), + .nodes = osm_l3_nodes, + .num_nodes = ARRAY_SIZE(osm_l3_nodes), .lut_row_size = OSM_LUT_ROW_SIZE, .reg_freq_lut = OSM_REG_FREQ_LUT, .reg_perf_state = OSM_REG_PERF_STATE, }; -DEFINE_QNODE(sm8150_osm_apps_l3, SM8150_MASTER_OSM_L3_APPS, 32, SM8150_SLAVE_OSM_L3); -DEFINE_QNODE(sm8150_osm_l3, SM8150_SLAVE_OSM_L3, 32); - -static const struct qcom_osm_l3_node * const sm8150_osm_l3_nodes[] = { - [MASTER_OSM_L3_APPS] = &sm8150_osm_apps_l3, - [SLAVE_OSM_L3] = &sm8150_osm_l3, -}; - static const struct qcom_osm_l3_desc sm8150_icc_osm_l3 = { - .nodes = sm8150_osm_l3_nodes, - .num_nodes = ARRAY_SIZE(sm8150_osm_l3_nodes), + .nodes = osm_l3_nodes, + .num_nodes = ARRAY_SIZE(osm_l3_nodes), .lut_row_size = OSM_LUT_ROW_SIZE, .reg_freq_lut = OSM_REG_FREQ_LUT, .reg_perf_state = OSM_REG_PERF_STATE, }; -DEFINE_QNODE(sm8250_epss_apps_l3, SM8250_MASTER_EPSS_L3_APPS, 32, SM8250_SLAVE_EPSS_L3); -DEFINE_QNODE(sm8250_epss_l3, SM8250_SLAVE_EPSS_L3, 32); - -static const struct qcom_osm_l3_node * const sm8250_epss_l3_nodes[] = { - [MASTER_EPSS_L3_APPS] = &sm8250_epss_apps_l3, - [SLAVE_EPSS_L3_SHARED] = &sm8250_epss_l3, -}; - static const struct qcom_osm_l3_desc sm8250_icc_epss_l3 = { - .nodes = sm8250_epss_l3_nodes, - .num_nodes = ARRAY_SIZE(sm8250_epss_l3_nodes), + .nodes = epss_l3_nodes, + .num_nodes = ARRAY_SIZE(epss_l3_nodes), .lut_row_size = EPSS_LUT_ROW_SIZE, .reg_freq_lut = EPSS_REG_FREQ_LUT, .reg_perf_state = EPSS_REG_PERF_STATE, From patchwork Fri Oct 28 03:41:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 13023029 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3E077FA3747 for ; Fri, 28 Oct 2022 03:42:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234802AbiJ1DmS (ORCPT ); Thu, 27 Oct 2022 23:42:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56554 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234467AbiJ1DmP (ORCPT ); Thu, 27 Oct 2022 23:42:15 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BA088D0CEE; Thu, 27 Oct 2022 20:42:14 -0700 (PDT) Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 29S2o5fI026807; Fri, 28 Oct 2022 03:42:03 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=zQITVjOMu36nG2pgpk3PWbR8z3tJSa1zpAQs+GL2+DQ=; b=KCzQlkVmoDuFXf1OjiipwRf9QJ6q6y2hkxeB6HLdAs7uR6hbJs+2QSjzX81xb29OegBo GPGR4kKbjXK4dLDysK43P2peqnIfdPqcqCjnXq3UkK+k48V0BPUS7C2eLPBxHysHF5l/ u2CCdAJ+4bbsqpsjDhf+V9ZpHAK/1oaqksVBEBm4RNkzz+i87Dfi09IV5RmsJMZxygwH bQncYZAKbxpX+pWMuRG7H3Z/HOrHniBGpZI3mXmzOFjjEvBttvDe4P7kIxaQGDxqYi35 TfK+zVqCWqPnVjyDwR3sO7zuixOvYw66psdtjlw8rXV2mCTW/QNKUlFNes54/tZi6INH GQ== Received: from nalasppmta02.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3kg59ag9bq-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 28 Oct 2022 03:42:03 +0000 Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 29S3g2Ib001380 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 28 Oct 2022 03:42:02 GMT Received: from th-lint-050.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Thu, 27 Oct 2022 20:42:02 -0700 From: Bjorn Andersson To: Georgi Djakov , Sibi Sankar CC: Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , "Rob Herring" , Mike Tipton , "Johan Hovold" , , , , Subject: [PATCH 02/10] interconnect: qcom: osm-l3: Squash common descriptors Date: Thu, 27 Oct 2022 20:41:47 -0700 Message-ID: <20221028034155.5580-3-quic_bjorande@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221028034155.5580-1-quic_bjorande@quicinc.com> References: <20221028034155.5580-1-quic_bjorande@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: fhD7k9tAvN8qFkCyoiKpXXB_CsRrvu2B X-Proofpoint-ORIG-GUID: fhD7k9tAvN8qFkCyoiKpXXB_CsRrvu2B X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-10-27_07,2022-10-27_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 malwarescore=0 clxscore=1015 mlxscore=0 suspectscore=0 mlxlogscore=999 bulkscore=0 priorityscore=1501 spamscore=0 impostorscore=0 phishscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2210170000 definitions=main-2210280022 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Each platform defines their own OSM L3 descriptor, but in practice there's only two: one for OSM and one for EPSS. Remove the duplicated definitions. Signed-off-by: Bjorn Andersson --- drivers/interconnect/qcom/osm-l3.c | 48 +++++------------------------- 1 file changed, 8 insertions(+), 40 deletions(-) diff --git a/drivers/interconnect/qcom/osm-l3.c b/drivers/interconnect/qcom/osm-l3.c index d23769844419..7d6844253241 100644 --- a/drivers/interconnect/qcom/osm-l3.c +++ b/drivers/interconnect/qcom/osm-l3.c @@ -104,7 +104,7 @@ static const struct qcom_osm_l3_node * const epss_l3_nodes[] = { [SLAVE_EPSS_L3_SHARED] = &epss_l3_slave, }; -static const struct qcom_osm_l3_desc sdm845_icc_osm_l3 = { +static const struct qcom_osm_l3_desc osm_l3 = { .nodes = osm_l3_nodes, .num_nodes = ARRAY_SIZE(osm_l3_nodes), .lut_row_size = OSM_LUT_ROW_SIZE, @@ -112,39 +112,7 @@ static const struct qcom_osm_l3_desc sdm845_icc_osm_l3 = { .reg_perf_state = OSM_REG_PERF_STATE, }; -static const struct qcom_osm_l3_desc sc7180_icc_osm_l3 = { - .nodes = osm_l3_nodes, - .num_nodes = ARRAY_SIZE(osm_l3_nodes), - .lut_row_size = OSM_LUT_ROW_SIZE, - .reg_freq_lut = OSM_REG_FREQ_LUT, - .reg_perf_state = OSM_REG_PERF_STATE, -}; - -static const struct qcom_osm_l3_desc sc7280_icc_epss_l3 = { - .nodes = epss_l3_nodes, - .num_nodes = ARRAY_SIZE(epss_l3_nodes), - .lut_row_size = EPSS_LUT_ROW_SIZE, - .reg_freq_lut = EPSS_REG_FREQ_LUT, - .reg_perf_state = EPSS_REG_PERF_STATE, -}; - -static const struct qcom_osm_l3_desc sc8180x_icc_osm_l3 = { - .nodes = osm_l3_nodes, - .num_nodes = ARRAY_SIZE(osm_l3_nodes), - .lut_row_size = OSM_LUT_ROW_SIZE, - .reg_freq_lut = OSM_REG_FREQ_LUT, - .reg_perf_state = OSM_REG_PERF_STATE, -}; - -static const struct qcom_osm_l3_desc sm8150_icc_osm_l3 = { - .nodes = osm_l3_nodes, - .num_nodes = ARRAY_SIZE(osm_l3_nodes), - .lut_row_size = OSM_LUT_ROW_SIZE, - .reg_freq_lut = OSM_REG_FREQ_LUT, - .reg_perf_state = OSM_REG_PERF_STATE, -}; - -static const struct qcom_osm_l3_desc sm8250_icc_epss_l3 = { +static const struct qcom_osm_l3_desc epss_l3 = { .nodes = epss_l3_nodes, .num_nodes = ARRAY_SIZE(epss_l3_nodes), .lut_row_size = EPSS_LUT_ROW_SIZE, @@ -317,12 +285,12 @@ static int qcom_osm_l3_probe(struct platform_device *pdev) } static const struct of_device_id osm_l3_of_match[] = { - { .compatible = "qcom,sc7180-osm-l3", .data = &sc7180_icc_osm_l3 }, - { .compatible = "qcom,sc7280-epss-l3", .data = &sc7280_icc_epss_l3 }, - { .compatible = "qcom,sdm845-osm-l3", .data = &sdm845_icc_osm_l3 }, - { .compatible = "qcom,sm8150-osm-l3", .data = &sm8150_icc_osm_l3 }, - { .compatible = "qcom,sc8180x-osm-l3", .data = &sc8180x_icc_osm_l3 }, - { .compatible = "qcom,sm8250-epss-l3", .data = &sm8250_icc_epss_l3 }, + { .compatible = "qcom,sc7180-osm-l3", .data = &osm_l3 }, + { .compatible = "qcom,sc7280-epss-l3", .data = &epss_l3 }, + { .compatible = "qcom,sdm845-osm-l3", .data = &osm_l3 }, + { .compatible = "qcom,sm8150-osm-l3", .data = &osm_l3 }, + { .compatible = "qcom,sc8180x-osm-l3", .data = &osm_l3 }, + { .compatible = "qcom,sm8250-epss-l3", .data = &epss_l3 }, { } }; MODULE_DEVICE_TABLE(of, osm_l3_of_match); From patchwork Fri Oct 28 03:41:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 13023030 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 34CA8FA374C for ; Fri, 28 Oct 2022 03:42:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236139AbiJ1DmV (ORCPT ); Thu, 27 Oct 2022 23:42:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56570 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235990AbiJ1DmQ (ORCPT ); Thu, 27 Oct 2022 23:42:16 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B2686D0CFE; Thu, 27 Oct 2022 20:42:15 -0700 (PDT) Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 29S2pLiT000932; Fri, 28 Oct 2022 03:42:04 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=X9wfV/UctWWoKLEcIq+bmims0/mEAkeq/OCKUib/uaY=; b=EzeJlY6ig3nFTG4USCSozYjNA/dAYEELRFkbphn/i88/QEIWxhlOVWRsSm9QK0BF+WJE ilotIILq3HOrV6J15vTDuNAvJgXx2Td+9aICZJz0uWNWzJia8DxM37nv+s/AIeT05mM5 nCjIkqfsWYitRdd4Hoc5jwyZXo3hBEnaCV+CE3ib/81xOKVTRZnP9iAOy1UpihU5waSz KbOegSUDlfh4PO5GIt0fo4fDV7QUPcZyQZXE8eb+XVaH7yeB0UVrubpZorE3LtEw5pYN lervCliiXVjBD+ivetlrgxjguuRkYJ7c+HH44xAGpLmfPS3aEy5K9PDXyO6a10lwn4zH GA== Received: from nalasppmta01.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3kfahwbxt1-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 28 Oct 2022 03:42:04 +0000 Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 29S3g30U009901 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 28 Oct 2022 03:42:03 GMT Received: from th-lint-050.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Thu, 27 Oct 2022 20:42:02 -0700 From: Bjorn Andersson To: Georgi Djakov , Sibi Sankar CC: Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , "Rob Herring" , Mike Tipton , "Johan Hovold" , , , , Subject: [PATCH 03/10] interconnect: qcom: osm-l3: Add per-core EPSS L3 support Date: Thu, 27 Oct 2022 20:41:48 -0700 Message-ID: <20221028034155.5580-4-quic_bjorande@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221028034155.5580-1-quic_bjorande@quicinc.com> References: <20221028034155.5580-1-quic_bjorande@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: m15ls0RJkq_tpc5ruFwJvgpSRVKOwgb- X-Proofpoint-ORIG-GUID: m15ls0RJkq_tpc5ruFwJvgpSRVKOwgb- X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-10-27_07,2022-10-27_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 impostorscore=0 phishscore=0 bulkscore=0 suspectscore=0 adultscore=0 lowpriorityscore=0 priorityscore=1501 mlxscore=0 malwarescore=0 spamscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2210170000 definitions=main-2210280022 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org The EPSS instance in e.g. SM8350 and SC8280XP has per-core L3 voting enabled. In this configuration, the "shared" vote is done using the REG_L3_VOTE register instead of PERF_STATE. Rename epss_l3 to clarify that it's affecting the PERF_STATE register and add a new L3_VOTE description. Given platform lineage it's assumed that the L3_VOTE-based case will be the predominant one, so use this for a new generic qcom,epss-l3 compatible. While adding the EPSS generic, also add qcom,osm-l3. Signed-off-by: Bjorn Andersson --- drivers/interconnect/qcom/osm-l3.c | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/drivers/interconnect/qcom/osm-l3.c b/drivers/interconnect/qcom/osm-l3.c index 7d6844253241..469be732a00b 100644 --- a/drivers/interconnect/qcom/osm-l3.c +++ b/drivers/interconnect/qcom/osm-l3.c @@ -34,6 +34,7 @@ /* EPSS Register offsets */ #define EPSS_LUT_ROW_SIZE 4 +#define EPSS_REG_L3_VOTE 0x90 #define EPSS_REG_FREQ_LUT 0x100 #define EPSS_REG_PERF_STATE 0x320 @@ -112,7 +113,7 @@ static const struct qcom_osm_l3_desc osm_l3 = { .reg_perf_state = OSM_REG_PERF_STATE, }; -static const struct qcom_osm_l3_desc epss_l3 = { +static const struct qcom_osm_l3_desc epss_l3_perf_state = { .nodes = epss_l3_nodes, .num_nodes = ARRAY_SIZE(epss_l3_nodes), .lut_row_size = EPSS_LUT_ROW_SIZE, @@ -120,6 +121,14 @@ static const struct qcom_osm_l3_desc epss_l3 = { .reg_perf_state = EPSS_REG_PERF_STATE, }; +static const struct qcom_osm_l3_desc epss_l3_l3_vote = { + .nodes = epss_l3_nodes, + .num_nodes = ARRAY_SIZE(epss_l3_nodes), + .lut_row_size = EPSS_LUT_ROW_SIZE, + .reg_freq_lut = EPSS_REG_FREQ_LUT, + .reg_perf_state = EPSS_REG_L3_VOTE, +}; + static int qcom_osm_l3_set(struct icc_node *src, struct icc_node *dst) { struct qcom_osm_l3_icc_provider *qp; @@ -285,12 +294,14 @@ static int qcom_osm_l3_probe(struct platform_device *pdev) } static const struct of_device_id osm_l3_of_match[] = { + { .compatible = "qcom,epss-l3", .data = &epss_l3_l3_vote }, + { .compatible = "qcom,osm-l3", .data = &osm_l3 }, { .compatible = "qcom,sc7180-osm-l3", .data = &osm_l3 }, - { .compatible = "qcom,sc7280-epss-l3", .data = &epss_l3 }, + { .compatible = "qcom,sc7280-epss-l3", .data = &epss_l3_perf_state }, { .compatible = "qcom,sdm845-osm-l3", .data = &osm_l3 }, { .compatible = "qcom,sm8150-osm-l3", .data = &osm_l3 }, { .compatible = "qcom,sc8180x-osm-l3", .data = &osm_l3 }, - { .compatible = "qcom,sm8250-epss-l3", .data = &epss_l3 }, + { .compatible = "qcom,sm8250-epss-l3", .data = &epss_l3_perf_state }, { } }; MODULE_DEVICE_TABLE(of, osm_l3_of_match); From patchwork Fri Oct 28 03:41:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 13023027 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5BBBFC38A02 for ; Fri, 28 Oct 2022 03:42:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236021AbiJ1DmR (ORCPT ); Thu, 27 Oct 2022 23:42:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56544 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234693AbiJ1DmP (ORCPT ); Thu, 27 Oct 2022 23:42:15 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AE946D0CEC; Thu, 27 Oct 2022 20:42:14 -0700 (PDT) Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 29S1j6DU001501; Fri, 28 Oct 2022 03:42:04 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=ljwIYDmtXdUHA7IxdT6F5j2COIUJnQYPZUcPwQawneE=; b=WjXVqGJX/AwG51ifoYc0dvpBArFuxTBoesa+n6DRdNysQ6t/UsQXXHX0RRarG2zAMEKW DNis5W8G9YrmtXybpl2+CGjMzcSWtG2lVocZfCV2UX5Szmqu8gBGoOuaMqJWGXH6JCXW X25JmPSQ02tjozl3QzGUgNogQflD/LoT4VDFNjEKbBaJWbK9is3rov9SP5vsg9eLA7o3 LIvhfq9AdbsKPsAxFpQ3hpst9uf20mTC81W8ZGQ/8EXTDJ5g3iXzg+bKSb1scNcewXCN TYv1ChUWfODNFndcBQqQYbLV61ZrAPU8P4gNRUbfLuvvoR8uxrp700c4eP5wE49xP7Gi nw== Received: from nalasppmta02.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3kfyf7h3fg-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 28 Oct 2022 03:42:04 +0000 Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 29S3g35b001400 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 28 Oct 2022 03:42:03 GMT Received: from th-lint-050.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Thu, 27 Oct 2022 20:42:03 -0700 From: Bjorn Andersson To: Georgi Djakov , Sibi Sankar CC: Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , "Rob Herring" , Mike Tipton , "Johan Hovold" , , , , Subject: [PATCH 04/10] interconnect: qcom: osm-l3: Simplify osm_l3_set() Date: Thu, 27 Oct 2022 20:41:49 -0700 Message-ID: <20221028034155.5580-5-quic_bjorande@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221028034155.5580-1-quic_bjorande@quicinc.com> References: <20221028034155.5580-1-quic_bjorande@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: OQfNPHyCpKZOby8IWgexqsRN2f0KzCw0 X-Proofpoint-GUID: OQfNPHyCpKZOby8IWgexqsRN2f0KzCw0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-10-27_07,2022-10-27_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 phishscore=0 spamscore=0 malwarescore=0 clxscore=1015 lowpriorityscore=0 suspectscore=0 priorityscore=1501 mlxscore=0 bulkscore=0 adultscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2210170000 definitions=main-2210280022 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org The aggregation over votes for all nodes in the provider will always only find the bandwidth votes for the destination side of the path. Further more, the average kBps value will always be 0. Simplify the logic by directly looking at the destination node's peak bandwidth request. Signed-off-by: Bjorn Andersson --- drivers/interconnect/qcom/osm-l3.c | 10 +--------- 1 file changed, 1 insertion(+), 9 deletions(-) diff --git a/drivers/interconnect/qcom/osm-l3.c b/drivers/interconnect/qcom/osm-l3.c index 469be732a00b..5fa171087425 100644 --- a/drivers/interconnect/qcom/osm-l3.c +++ b/drivers/interconnect/qcom/osm-l3.c @@ -134,22 +134,14 @@ static int qcom_osm_l3_set(struct icc_node *src, struct icc_node *dst) struct qcom_osm_l3_icc_provider *qp; struct icc_provider *provider; const struct qcom_osm_l3_node *qn; - struct icc_node *n; unsigned int index; - u32 agg_peak = 0; - u32 agg_avg = 0; u64 rate; qn = src->data; provider = src->provider; qp = to_osm_l3_provider(provider); - list_for_each_entry(n, &provider->nodes, node_list) - provider->aggregate(n, 0, n->avg_bw, n->peak_bw, - &agg_avg, &agg_peak); - - rate = max(agg_avg, agg_peak); - rate = icc_units_to_bps(rate); + rate = icc_units_to_bps(dst->peak_bw); do_div(rate, qn->buswidth); for (index = 0; index < qp->max_state - 1; index++) { From patchwork Fri Oct 28 03:41:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 13023031 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F1F43FA3749 for ; Fri, 28 Oct 2022 03:42:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236059AbiJ1DmT (ORCPT ); Thu, 27 Oct 2022 23:42:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56568 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236002AbiJ1DmQ (ORCPT ); Thu, 27 Oct 2022 23:42:16 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ABE9FD0CC0; Thu, 27 Oct 2022 20:42:15 -0700 (PDT) Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 29S2o1OV026286; Fri, 28 Oct 2022 03:42:05 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=im6yITI1531e3Mh3hR1LfHjB0NtsCe0RG1IWCtmk4iY=; b=iwTont8evdsUviVhgp9O75tYPdiyTpn1kZrOae1lXRD7WHicr4U+FYyd38mKB1STUpld 8akzpRmedS5PIS4L+92RDmFWqFbEf0gDpx2Urt4mKKvdDe+rwbIv2kscH9vE3I4k+Yqq /CreEPPkf6n0WiDmezvpZjnS5VtpqnU9vGzf7ADETJlLYwJODA+AhN+pwNLxqxSM9i+G pzItdQ96hHPCLvw8zv4XZxcKKl8bNmn9ajQZ4Dq82et5gWoJEH062dlRl6I0GRWi4BD3 TFJ0mTyy0jaGquq6AHLt7lvQHCqcjrRk3ketyxUMyrV3iQHE0OABNcXCAK9OsZZljipM 1g== Received: from nalasppmta02.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3kfahwbxt2-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 28 Oct 2022 03:42:05 +0000 Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 29S3g41c001405 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 28 Oct 2022 03:42:04 GMT Received: from th-lint-050.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Thu, 27 Oct 2022 20:42:03 -0700 From: Bjorn Andersson To: Krzysztof Kozlowski , Georgi Djakov , Rob Herring , Sibi Sankar CC: Bjorn Andersson , Konrad Dybcio , Mike Tipton , Johan Hovold , , , , Subject: [PATCH 05/10] dt-bindings: interconnect: Add sm8350, sc8280xp and generic OSM L3 compatibles Date: Thu, 27 Oct 2022 20:41:50 -0700 Message-ID: <20221028034155.5580-6-quic_bjorande@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221028034155.5580-1-quic_bjorande@quicinc.com> References: <20221028034155.5580-1-quic_bjorande@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: SR_D6yQBde2Tvf8ljaRrri17d423xc6k X-Proofpoint-ORIG-GUID: SR_D6yQBde2Tvf8ljaRrri17d423xc6k X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-10-27_07,2022-10-27_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 impostorscore=0 phishscore=0 bulkscore=0 suspectscore=0 adultscore=0 lowpriorityscore=0 priorityscore=1501 mlxscore=0 malwarescore=0 spamscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2210170000 definitions=main-2210280022 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Add EPSS L3 compatibles for sm8350 and sc8280xp, but while at it also introduce generic compatible for both qcom,osm-l3 and qcom,epss-l3. Signed-off-by: Bjorn Andersson --- .../bindings/interconnect/qcom,osm-l3.yaml | 22 +++++++++++++------ 1 file changed, 15 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml index bf538c0c5a81..ae0995341a78 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml @@ -16,13 +16,21 @@ description: properties: compatible: - enum: - - qcom,sc7180-osm-l3 - - qcom,sc7280-epss-l3 - - qcom,sc8180x-osm-l3 - - qcom,sdm845-osm-l3 - - qcom,sm8150-osm-l3 - - qcom,sm8250-epss-l3 + oneOf: + items: + - enum: + - qcom,sc7180-osm-l3 + - qcom,sc8180x-osm-l3 + - qcom,sdm845-osm-l3 + - qcom,sm8150-osm-l3 + - const: qcom,osm-l3 + items: + - enum: + - qcom,sc7280-epss-l3 + - qcom,sc8280xp-epss-l3 + - qcom,sm8250-epss-l3 + - qcom,sm8350-epss-l3 + - const: qcom,epss-l3 reg: maxItems: 1 From patchwork Fri Oct 28 03:41:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 13023034 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4A435FA3749 for ; Fri, 28 Oct 2022 03:42:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236193AbiJ1DmX (ORCPT ); Thu, 27 Oct 2022 23:42:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56568 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236040AbiJ1DmR (ORCPT ); Thu, 27 Oct 2022 23:42:17 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B42D9D18C3; Thu, 27 Oct 2022 20:42:16 -0700 (PDT) Received: from pps.filterd (m0279868.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 29S2Y8k3018103; Fri, 28 Oct 2022 03:42:06 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=H3IiDcxNcmeVkbj/gkkfb82ZpzTE2PRvGEsi7tXavzM=; b=SHzQ8VwjR//xsgcb1oiW1Vzr3BmVENSA/Mjh3wlBdpyPBZB+LsZxS1bqJs39FsQWJUag GohiuILP2Szy2y0WBWZd2gRE8hGQn91kXMjrDP8SkHGd12S3U8d6KlB2bTQ2fTzJQuKE 2kzHg4pXI+YxsSp6WJQMm/La0LUqy3z9kdRVQvMH9gmk0ynf4JYzoUjflcPYRm3S2AMf b/L1DsUHIMkcQT6wvMpMFpeUKzYGqnVtlh14a7ltFceZCmKjibwQEj9Ym5owcaXiMo2W asJIRO8xgoLlkLaoKzwHefCN2T5p1lc0/pPO7odoKKVFhR0Iiy1JxDhQix5yPuxIVxe/ KA== Received: from nalasppmta01.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3kfaj1bwfm-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 28 Oct 2022 03:42:05 +0000 Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 29S3g4Sw009930 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 28 Oct 2022 03:42:04 GMT Received: from th-lint-050.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Thu, 27 Oct 2022 20:42:04 -0700 From: Bjorn Andersson To: Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , "Rob Herring" , Sibi Sankar CC: Georgi Djakov , Mike Tipton , Johan Hovold , , , , Subject: [PATCH 06/10] arm64: dts: qcom: Align with generic osm-l3/epss-l3 Date: Thu, 27 Oct 2022 20:41:51 -0700 Message-ID: <20221028034155.5580-7-quic_bjorande@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221028034155.5580-1-quic_bjorande@quicinc.com> References: <20221028034155.5580-1-quic_bjorande@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: aWwSxdAIgR6zcX5lsRP6uXick-EMUyLY X-Proofpoint-ORIG-GUID: aWwSxdAIgR6zcX5lsRP6uXick-EMUyLY X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-10-27_07,2022-10-27_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 mlxscore=0 suspectscore=0 adultscore=0 bulkscore=0 mlxlogscore=845 lowpriorityscore=0 phishscore=0 clxscore=1015 malwarescore=0 impostorscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2210170000 definitions=main-2210280022 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Update all references to OSM or EPSS L3 compatibles, to include the generic compatible, as defined by the updated binding. Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 2 +- arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 +- arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +- arch/arm64/boot/dts/qcom/sm8150.dtsi | 2 +- arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index f1482675610a..a6542b4d5bf5 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -3525,7 +3525,7 @@ apps_bcm_voter: bcm-voter { }; osm_l3: interconnect@18321000 { - compatible = "qcom,sc7180-osm-l3"; + compatible = "qcom,sc7180-osm-l3", "qcom,osm-l3"; reg = <0 0x18321000 0 0x1400>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 748eef6f5281..43da98f1ad98 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -5348,7 +5348,7 @@ rpmhcc: clock-controller { }; epss_l3: interconnect@18590000 { - compatible = "qcom,sc7280-epss-l3"; + compatible = "qcom,sc7280-epss-l3", "qcom,epss-l3"; reg = <0 0x18590000 0 0x1000>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; clock-names = "xo", "alternate"; diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 1a257f672887..9c7d484ce72f 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -5302,7 +5302,7 @@ frame@17d10000 { }; osm_l3: interconnect@17d41000 { - compatible = "qcom,sdm845-osm-l3"; + compatible = "qcom,sdm845-osm-l3", "qcom,osm-l3"; reg = <0 0x17d41000 0 0x1400>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index 5fa575e4425a..fe1abf9cb0ff 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -3958,7 +3958,7 @@ apps_bcm_voter: bcm-voter { }; osm_l3: interconnect@18321000 { - compatible = "qcom,sm8150-osm-l3"; + compatible = "qcom,sm8150-osm-l3", "qcom,osm-l3"; reg = <0 0x18321000 0 0x1400>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index eb5a10cbcd71..1b88da7be921 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -4885,7 +4885,7 @@ apps_bcm_voter: bcm-voter { }; epss_l3: interconnect@18590000 { - compatible = "qcom,sm8250-epss-l3"; + compatible = "qcom,sm8250-epss-l3", "qcom,epss-l3"; reg = <0 0x18590000 0 0x1000>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; From patchwork Fri Oct 28 03:41:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 13023033 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2E0A6ECAAA1 for ; Fri, 28 Oct 2022 03:42:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235953AbiJ1DmW (ORCPT ); Thu, 27 Oct 2022 23:42:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56574 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236003AbiJ1DmQ (ORCPT ); Thu, 27 Oct 2022 23:42:16 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6D3F8D0CEC; Thu, 27 Oct 2022 20:42:16 -0700 (PDT) Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 29S3Hlb2007982; Fri, 28 Oct 2022 03:42:06 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=qs7675PRZSUlrcVa9vdjZfR4fSJ2F9TinTifGqcbbKA=; b=VLl0Yn58MCPXFvTcg1dauZnmZwm37JY2ReFOvu7Ck8yKlviiAqOvSiJYxXMHaQio6WVH o7NCiRAai3tMv9cAI03lv8A6ijdLevDe0ys+eufkstzlm1RTucacv6RKRHxhCtI+80Z3 YE/gz43Rxcb1AJlvie3b7pXMUFU0n1MWYN8nj0O+vbgIs7mInoFmDYUCsGfbWToTqoLc DscNoO8sxbTsDboYGTpQRGFP3cSO2p94JMbXbxR0rVDh9LrRSUPRJlR1URmduZpo6YZ2 g32yZWS4e0VI5IIdK5S4BQTUrM3Mih5DpTA8e5Ku00O9ka8EgBqvXKquJoBi14V65em/ Bw== Received: from nalasppmta05.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3kfahen8rw-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 28 Oct 2022 03:42:05 +0000 Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 29S3g5Vp005704 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 28 Oct 2022 03:42:05 GMT Received: from th-lint-050.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Thu, 27 Oct 2022 20:42:04 -0700 From: Bjorn Andersson To: Bjorn Andersson , Konrad Dybcio , Sibi Sankar CC: Krzysztof Kozlowski , Georgi Djakov , Rob Herring , Mike Tipton , Johan Hovold , , , , Subject: [PATCH 07/10] arm64: dts: qcom: sc8280xp: Add epss_l3 node Date: Thu, 27 Oct 2022 20:41:52 -0700 Message-ID: <20221028034155.5580-8-quic_bjorande@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221028034155.5580-1-quic_bjorande@quicinc.com> References: <20221028034155.5580-1-quic_bjorande@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: xtC2tHw9CCvkyuWPnsMg1Mgi_uxxIrl2 X-Proofpoint-ORIG-GUID: xtC2tHw9CCvkyuWPnsMg1Mgi_uxxIrl2 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-10-27_07,2022-10-27_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 impostorscore=0 clxscore=1015 malwarescore=0 spamscore=0 phishscore=0 adultscore=0 mlxscore=0 bulkscore=0 mlxlogscore=999 priorityscore=1501 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2210170000 definitions=main-2210280022 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Add a device node for the EPSS L3 frequency domain. Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index ed806a6e20f6..ba404a31206e 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -1791,6 +1791,16 @@ rpmhpd_opp_turbo_l1: opp10 { }; }; + epss_l3: interconnect@18590000 { + compatible = "qcom,sc8280xp-epss-l3", "qcom,epss-l3"; + reg = <0 0x18590000 0 0x1000>; + + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; + clock-names = "xo", "alternate"; + + #interconnect-cells = <1>; + }; + cpufreq_hw: cpufreq@18591000 { compatible = "qcom,sc8280xp-cpufreq-epss", "qcom,cpufreq-epss"; reg = <0 0x18591000 0 0x1000>, From patchwork Fri Oct 28 03:41:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 13023037 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E2F56FA374F for ; Fri, 28 Oct 2022 03:42:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236281AbiJ1Dm1 (ORCPT ); Thu, 27 Oct 2022 23:42:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56604 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235114AbiJ1DmT (ORCPT ); Thu, 27 Oct 2022 23:42:19 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C1FF3D0CEB; Thu, 27 Oct 2022 20:42:17 -0700 (PDT) Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 29S1hWvC030749; Fri, 28 Oct 2022 03:42:06 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=W+Br6GRh8zbWIwctcQycUyDzHP6dGDS4vhJzi36bkZE=; b=bc+Rl+2TWvrq7QZfn725CmXpS2Dtj1eKVpDhDTSaG4z57DQp2GMV5M6YbbhIG0mvlGkM 80oF9GoYtOkb0DTNeK9HMtaqPRoo+VnM5VDCs7wCVbjdYvDK6I2pLHEylNiM7IfKLbWR OdZ+2myXyGc6iPfsDBc3LMczoMYMKoRhsPJWwRvXQhKRkWq1xJq/8QI2AYKjZmJu0NjN mqm4BscKOo6LEVCfoXhgYIu2cJBj0nVFAhg/DlwV2j1NUjxb0WPrLXS7eWhMvqDOXwyz nXKHLDlT0nj7U/iAOV9TzxFRMJZMZiN2aYqcJ40YmYDDQODUOyyRAKk2w6X4jsZXmOh1 EQ== Received: from nalasppmta04.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3kfyf7h3fh-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 28 Oct 2022 03:42:06 +0000 Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 29S3g55q003744 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 28 Oct 2022 03:42:05 GMT Received: from th-lint-050.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Thu, 27 Oct 2022 20:42:05 -0700 From: Bjorn Andersson To: Bjorn Andersson , Konrad Dybcio , Sibi Sankar CC: Krzysztof Kozlowski , Georgi Djakov , Rob Herring , Mike Tipton , Johan Hovold , , , , Subject: [PATCH 08/10] arm64: dts: qcom: sc8280xp: Set up L3 scaling Date: Thu, 27 Oct 2022 20:41:53 -0700 Message-ID: <20221028034155.5580-9-quic_bjorande@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221028034155.5580-1-quic_bjorande@quicinc.com> References: <20221028034155.5580-1-quic_bjorande@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: Hwsnt8oUWtkgZnJoACOh8FHVVwSMOEEI X-Proofpoint-GUID: Hwsnt8oUWtkgZnJoACOh8FHVVwSMOEEI X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-10-27_07,2022-10-27_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 phishscore=0 spamscore=0 malwarescore=0 clxscore=1015 lowpriorityscore=0 suspectscore=0 priorityscore=1501 mlxscore=0 bulkscore=0 adultscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2210170000 definitions=main-2210280022 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Add the L3 interconnect path to all CPUs and define the bandwidth requirements for all opp entries across sc8280xp and sa8540p. The values are based on the tables reported by the hardware, distributed such that each value is the largest value, lower than the cluster frequency. Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sa8540p.dtsi | 39 ++++++++++++++++++++ arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 51 ++++++++++++++++++++++++++ 2 files changed, 90 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8540p.dtsi b/arch/arm64/boot/dts/qcom/sa8540p.dtsi index 8ea2886fbab2..fd36800a7578 100644 --- a/arch/arm64/boot/dts/qcom/sa8540p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8540p.dtsi @@ -14,59 +14,81 @@ cpu0_opp_table: cpu0-opp-table { compatible = "operating-points-v2"; opp-shared; + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-peak-kBps = <(300000 * 32)>; + }; opp-403200000 { opp-hz = /bits/ 64 <403200000>; + opp-peak-kBps = <(384000 * 32)>; }; opp-499200000 { opp-hz = /bits/ 64 <499200000>; + opp-peak-kBps = <(480000 * 32)>; }; opp-595200000 { opp-hz = /bits/ 64 <595200000>; + opp-peak-kBps = <(576000 * 32)>; }; opp-710400000 { opp-hz = /bits/ 64 <710400000>; + opp-peak-kBps = <(672000 * 32)>; }; opp-806400000 { opp-hz = /bits/ 64 <806400000>; + opp-peak-kBps = <(768000 * 32)>; }; opp-902400000 { opp-hz = /bits/ 64 <902400000>; + opp-peak-kBps = <(864000 * 32)>; }; opp-1017600000 { opp-hz = /bits/ 64 <1017600000>; + opp-peak-kBps = <(960000 * 32)>; }; opp-1113600000 { opp-hz = /bits/ 64 <1113600000>; + opp-peak-kBps = <(1075200 * 32)>; }; opp-1209600000 { opp-hz = /bits/ 64 <1209600000>; + opp-peak-kBps = <(1171200 * 32)>; }; opp-1324800000 { opp-hz = /bits/ 64 <1324800000>; + opp-peak-kBps = <(1286400 * 32)>; }; opp-1440000000 { opp-hz = /bits/ 64 <1440000000>; + opp-peak-kBps = <(1382400 * 32)>; }; opp-1555200000 { opp-hz = /bits/ 64 <1555200000>; + opp-peak-kBps = <(1497600 * 32)>; }; opp-1670400000 { opp-hz = /bits/ 64 <1670400000>; + opp-peak-kBps = <(1593600 * 32)>; }; opp-1785600000 { opp-hz = /bits/ 64 <1785600000>; + opp-peak-kBps = <(1708800 * 32)>; }; opp-1881600000 { opp-hz = /bits/ 64 <1881600000>; + opp-peak-kBps = <(1708800 * 32)>; }; opp-2016000000 { opp-hz = /bits/ 64 <2016000000>; + opp-peak-kBps = <(1708800 * 32)>; }; opp-2131200000 { opp-hz = /bits/ 64 <2131200000>; + opp-peak-kBps = <(1708800 * 32)>; }; opp-2246400000 { opp-hz = /bits/ 64 <2246400000>; + opp-peak-kBps = <(1708800 * 32)>; }; }; @@ -76,54 +98,71 @@ cpu4_opp_table: cpu4-opp-table { opp-825600000 { opp-hz = /bits/ 64 <825600000>; + opp-peak-kBps = <(300000 * 32)>; }; opp-940800000 { opp-hz = /bits/ 64 <940800000>; + opp-peak-kBps = <(864000 * 32)>; }; opp-1056000000 { opp-hz = /bits/ 64 <1056000000>; + opp-peak-kBps = <(960000 * 32)>; }; opp-1171200000 { opp-hz = /bits/ 64 <1171200000>; + opp-peak-kBps = <(1171200 * 32)>; }; opp-1286400000 { opp-hz = /bits/ 64 <1286400000>; + opp-peak-kBps = <(1286400 * 32)>; }; opp-1401600000 { opp-hz = /bits/ 64 <1401600000>; + opp-peak-kBps = <(1382400 * 32)>; }; opp-1516800000 { opp-hz = /bits/ 64 <1516800000>; + opp-peak-kBps = <(1497600 * 32)>; }; opp-1632000000 { opp-hz = /bits/ 64 <1632000000>; + opp-peak-kBps = <(1593600 * 32)>; }; opp-1747200000 { opp-hz = /bits/ 64 <1747200000>; + opp-peak-kBps = <(1593600 * 32)>; }; opp-1862400000 { opp-hz = /bits/ 64 <1862400000>; + opp-peak-kBps = <(1708800 * 32)>; }; opp-1977600000 { opp-hz = /bits/ 64 <1977600000>; + opp-peak-kBps = <(1708800 * 32)>; }; opp-2073600000 { opp-hz = /bits/ 64 <2073600000>; + opp-peak-kBps = <(1708800 * 32)>; }; opp-2169600000 { opp-hz = /bits/ 64 <2169600000>; + opp-peak-kBps = <(1708800 * 32)>; }; opp-2284800000 { opp-hz = /bits/ 64 <2284800000>; + opp-peak-kBps = <(1708800 * 32)>; }; opp-2380800000 { opp-hz = /bits/ 64 <2380800000>; + opp-peak-kBps = <(1708800 * 32)>; }; opp-2496000000 { opp-hz = /bits/ 64 <2496000000>; + opp-peak-kBps = <(1708800 * 32)>; }; opp-2592000000 { opp-hz = /bits/ 64 <2592000000>; + opp-peak-kBps = <(1708800 * 32)>; }; }; }; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index ba404a31206e..e62245e37a61 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -6,6 +6,7 @@ #include #include +#include #include #include #include @@ -38,66 +39,87 @@ cpu0_opp_table: cpu0-opp-table { opp-300000000 { opp-hz = /bits/ 64 <300000000>; + opp-peak-kBps = <(300000 * 32)>; }; opp-403200000 { opp-hz = /bits/ 64 <403200000>; + opp-peak-kBps = <(384000 * 32)>; }; opp-499200000 { opp-hz = /bits/ 64 <499200000>; + opp-peak-kBps = <(480000 * 32)>; }; opp-595200000 { opp-hz = /bits/ 64 <595200000>; + opp-peak-kBps = <(576000 * 32)>; }; opp-691200000 { opp-hz = /bits/ 64 <691200000>; + opp-peak-kBps = <(672000 * 32)>; }; opp-806400000 { opp-hz = /bits/ 64 <806400000>; + opp-peak-kBps = <(768000 * 32)>; }; opp-902400000 { opp-hz = /bits/ 64 <902400000>; + opp-peak-kBps = <(864000 * 32)>; }; opp-1017600000 { opp-hz = /bits/ 64 <1017600000>; + opp-peak-kBps = <(960000 * 32)>; }; opp-1113600000 { opp-hz = /bits/ 64 <1113600000>; + opp-peak-kBps = <(1075200 * 32)>; }; opp-1209600000 { opp-hz = /bits/ 64 <1209600000>; + opp-peak-kBps = <(1171200 * 32)>; }; opp-1324800000 { opp-hz = /bits/ 64 <1324800000>; + opp-peak-kBps = <(1267200 * 32)>; }; opp-1440000000 { opp-hz = /bits/ 64 <1440000000>; + opp-peak-kBps = <(1363200 * 32)>; }; opp-1555200000 { opp-hz = /bits/ 64 <1555200000>; + opp-peak-kBps = <(1536000 * 32)>; }; opp-1670400000 { opp-hz = /bits/ 64 <1670400000>; + opp-peak-kBps = <(1612800 * 32)>; }; opp-1785600000 { opp-hz = /bits/ 64 <1785600000>; + opp-peak-kBps = <(1689600 * 32)>; }; opp-1881600000 { opp-hz = /bits/ 64 <1881600000>; + opp-peak-kBps = <(1689600 * 32)>; }; opp-1996800000 { opp-hz = /bits/ 64 <1996800000>; + opp-peak-kBps = <(1689600 * 32)>; }; opp-2112000000 { opp-hz = /bits/ 64 <2112000000>; + opp-peak-kBps = <(1689600 * 32)>; }; opp-2227200000 { opp-hz = /bits/ 64 <2227200000>; + opp-peak-kBps = <(1689600 * 32)>; }; opp-2342400000 { opp-hz = /bits/ 64 <2342400000>; + opp-peak-kBps = <(1689600 * 32)>; }; opp-2438400000 { opp-hz = /bits/ 64 <2438400000>; + opp-peak-kBps = <(1689600 * 32)>; }; }; @@ -107,66 +129,87 @@ cpu4_opp_table: cpu4-opp-table { opp-825600000 { opp-hz = /bits/ 64 <825600000>; + opp-peak-kBps = <(768000 * 32)>; }; opp-940800000 { opp-hz = /bits/ 64 <940800000>; + opp-peak-kBps = <(864000 * 32)>; }; opp-1056000000 { opp-hz = /bits/ 64 <1056000000>; + opp-peak-kBps = <(960000 * 32)>; }; opp-1171200000 { opp-hz = /bits/ 64 <1171200000>; + opp-peak-kBps = <(1171200 * 32)>; }; opp-1286400000 { opp-hz = /bits/ 64 <1286400000>; + opp-peak-kBps = <(1267200 * 32)>; }; opp-1401600000 { opp-hz = /bits/ 64 <1401600000>; + opp-peak-kBps = <(1363200 * 32)>; }; opp-1516800000 { opp-hz = /bits/ 64 <1516800000>; + opp-peak-kBps = <(1459200 * 32)>; }; opp-1632000000 { opp-hz = /bits/ 64 <1632000000>; + opp-peak-kBps = <(1612800 * 32)>; }; opp-1747200000 { opp-hz = /bits/ 64 <1747200000>; + opp-peak-kBps = <(1689600 * 32)>; }; opp-1862400000 { opp-hz = /bits/ 64 <1862400000>; + opp-peak-kBps = <(1689600 * 32)>; }; opp-1977600000 { opp-hz = /bits/ 64 <1977600000>; + opp-peak-kBps = <(1689600 * 32)>; }; opp-2073600000 { opp-hz = /bits/ 64 <2073600000>; + opp-peak-kBps = <(1689600 * 32)>; }; opp-2169600000 { opp-hz = /bits/ 64 <2169600000>; + opp-peak-kBps = <(1689600 * 32)>; }; opp-2284800000 { opp-hz = /bits/ 64 <2284800000>; + opp-peak-kBps = <(1689600 * 32)>; }; opp-2400000000 { opp-hz = /bits/ 64 <2400000000>; + opp-peak-kBps = <(1689600 * 32)>; }; opp-2496000000 { opp-hz = /bits/ 64 <2496000000>; + opp-peak-kBps = <(1689600 * 32)>; }; opp-2592000000 { opp-hz = /bits/ 64 <2592000000>; + opp-peak-kBps = <(1689600 * 32)>; }; opp-2688000000 { opp-hz = /bits/ 64 <2688000000>; + opp-peak-kBps = <(1689600 * 32)>; }; opp-2803200000 { opp-hz = /bits/ 64 <2803200000>; + opp-peak-kBps = <(1689600 * 32)>; }; opp-2899200000 { opp-hz = /bits/ 64 <2899200000>; + opp-peak-kBps = <(1689600 * 32)>; }; opp-2995200000 { opp-hz = /bits/ 64 <2995200000>; + opp-peak-kBps = <(1689600 * 32)>; }; }; @@ -185,6 +228,7 @@ CPU0: cpu@0 { power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 0>; operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; #cooling-cells = <2>; L2_0: l2-cache { compatible = "cache"; @@ -206,6 +250,7 @@ CPU1: cpu@100 { power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 0>; operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; #cooling-cells = <2>; L2_100: l2-cache { compatible = "cache"; @@ -224,6 +269,7 @@ CPU2: cpu@200 { power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 0>; operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; #cooling-cells = <2>; L2_200: l2-cache { compatible = "cache"; @@ -242,6 +288,7 @@ CPU3: cpu@300 { power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 0>; operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; #cooling-cells = <2>; L2_300: l2-cache { compatible = "cache"; @@ -260,6 +307,7 @@ CPU4: cpu@400 { power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 1>; operating-points-v2 = <&cpu4_opp_table>; + interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; #cooling-cells = <2>; L2_400: l2-cache { compatible = "cache"; @@ -278,6 +326,7 @@ CPU5: cpu@500 { power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 1>; operating-points-v2 = <&cpu4_opp_table>; + interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; #cooling-cells = <2>; L2_500: l2-cache { compatible = "cache"; @@ -296,6 +345,7 @@ CPU6: cpu@600 { power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 1>; operating-points-v2 = <&cpu4_opp_table>; + interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; #cooling-cells = <2>; L2_600: l2-cache { compatible = "cache"; @@ -314,6 +364,7 @@ CPU7: cpu@700 { power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 1>; operating-points-v2 = <&cpu4_opp_table>; + interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; #cooling-cells = <2>; L2_700: l2-cache { compatible = "cache"; From patchwork Fri Oct 28 03:41:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 13023035 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 64162FA374E for ; Fri, 28 Oct 2022 03:42:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236225AbiJ1DmZ (ORCPT ); Thu, 27 Oct 2022 23:42:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56588 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236050AbiJ1DmR (ORCPT ); Thu, 27 Oct 2022 23:42:17 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3E73ED0CC0; Thu, 27 Oct 2022 20:42:17 -0700 (PDT) Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 29S1gJ9D021214; Fri, 28 Oct 2022 03:42:07 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=47+CpATZbRiWrGynsjocd6H0hMwOJCdPY1a06accgnM=; b=e9AZ8ioEPTejB61KEir3g0F1MwZGURfYoKKdsjnTIYy9XPzMPEt3r5B6NJcYPUBTp30E TsizElAoaQLfJX+iiNL3/rEhYqFXpVtafQ/1oYkCVRGhDqyu2HWUDLybzCCBtoWzXZ7p FdTuR4Xmxtygc328diVNQ5eJYmLgdnYZJxbSmh5tT3ohik4e+SPpnp4WAaPF6xo2GXp9 dUbAvWVDSJ1eU81Y7bw7olm85Ao3KDUoCPJ3NXL1ooX37NiDkcC1RboPHBqiKRQ/jf7+ uCvrxDBHx0GhqO7qvLVgi85dnMLwN8PJKkN2MVkvTNmXdrF55Uz//gDLfhcJ8pKYb+Jo mw== Received: from nalasppmta03.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3kfw059my7-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 28 Oct 2022 03:42:06 +0000 Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 29S3g6p7018615 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 28 Oct 2022 03:42:06 GMT Received: from th-lint-050.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Thu, 27 Oct 2022 20:42:05 -0700 From: Bjorn Andersson To: Krzysztof Kozlowski , Georgi Djakov , Rob Herring , Sibi Sankar CC: Bjorn Andersson , Konrad Dybcio , Mike Tipton , Johan Hovold , , , , Subject: [PATCH 09/10] dt-bindings: interconnect: qcom,msm8998-bwmon: Add sc8280xp bwmon instances Date: Thu, 27 Oct 2022 20:41:54 -0700 Message-ID: <20221028034155.5580-10-quic_bjorande@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221028034155.5580-1-quic_bjorande@quicinc.com> References: <20221028034155.5580-1-quic_bjorande@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 5wr8OAyIhuRTXqtevcXmGWUGfU6p6xQd X-Proofpoint-ORIG-GUID: 5wr8OAyIhuRTXqtevcXmGWUGfU6p6xQd X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-10-27_07,2022-10-27_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 suspectscore=0 spamscore=0 malwarescore=0 bulkscore=0 mlxlogscore=999 mlxscore=0 priorityscore=1501 adultscore=0 impostorscore=0 clxscore=1015 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2210170000 definitions=main-2210280022 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org The sc8280xp platform has two BWMON instances, one v4 and one v5. Extend the existing qcom,msm8998-bwmon and qcom,sc7280-llcc-bwmon to describe these. Signed-off-by: Bjorn Andersson --- .../devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml b/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml index be29e0b80995..223cd6ecf279 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml @@ -25,9 +25,14 @@ properties: - items: - enum: - qcom,sc7280-cpu-bwmon + - qcom,sc8280xp-bwmon - qcom,sdm845-bwmon - const: qcom,msm8998-bwmon - const: qcom,msm8998-bwmon # BWMON v4 + - items: + - enum: + - qcom,sc8280xp-llcc-bwmon + - const: qcom,sc7280-llcc-bwmon - const: qcom,sc7280-llcc-bwmon # BWMON v5 - const: qcom,sdm845-llcc-bwmon # BWMON v5 From patchwork Fri Oct 28 03:41:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 13023036 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 75847ECAAA1 for ; Fri, 28 Oct 2022 03:42:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236265AbiJ1Dm0 (ORCPT ); Thu, 27 Oct 2022 23:42:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56606 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235121AbiJ1DmT (ORCPT ); Thu, 27 Oct 2022 23:42:19 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8B903D18C3; Thu, 27 Oct 2022 20:42:18 -0700 (PDT) Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 29S2qNEb012858; Fri, 28 Oct 2022 03:42:08 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=dcvGEyCk5HBE8N9yo00NnbAt3RtvsmvtwzwfhcFvfm8=; b=DpIXBgOcL9pgTaQS4FCbPoz2E2rX7k4gCI3gDuhrSFhodqb2ldOvdr9nQxxaaPiJfdjD zRovlxidGNjw5sd20ey/kKk0nd/BUfp1QP3q0hMNYoCIXEWlh3KKYeBa5inXxwHYbAy/ M3BhU5pO9XNqb0u3UhlbObP59O8YzdSwFrhtKz3GdctmTkk9Yqa06YftaaW3JLUP5UNd jwEuheJbPQdi7m2GHRKXCvd5wLAc6ivoiHTwl2iwjoGpN6IQA9HcwTogtTFbTfkyvJnd Pl57LVTvGazYiYk+hztOLegWELCmJneoveMTkTee9Ga+PL7n/TMa4YyKN3y6hXUX55DM jg== Received: from nalasppmta04.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3kfahvuxux-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 28 Oct 2022 03:42:07 +0000 Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 29S3g6Qq003756 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 28 Oct 2022 03:42:06 GMT Received: from th-lint-050.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Thu, 27 Oct 2022 20:42:06 -0700 From: Bjorn Andersson To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Sibi Sankar CC: Krzysztof Kozlowski , Georgi Djakov , Mike Tipton , Johan Hovold , , , , Subject: [PATCH 10/10] arm64: dts: qcom: sc8280xp: Add bwmon instances Date: Thu, 27 Oct 2022 20:41:55 -0700 Message-ID: <20221028034155.5580-11-quic_bjorande@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221028034155.5580-1-quic_bjorande@quicinc.com> References: <20221028034155.5580-1-quic_bjorande@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: _p6_VENDhfT4NPW1-D_l3Amkgv6at4O_ X-Proofpoint-ORIG-GUID: _p6_VENDhfT4NPW1-D_l3Amkgv6at4O_ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-10-27_07,2022-10-27_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 malwarescore=0 impostorscore=0 lowpriorityscore=0 mlxscore=0 clxscore=1015 suspectscore=0 spamscore=0 priorityscore=1501 adultscore=0 phishscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2210170000 definitions=main-2210280022 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Add the two bwmon instances and define votes for CPU -> LLCC and LLCC -> DDR, with bandwidth values based on the downstream DeviceTree. Signed-off-by: Bjorn Andersson Reviewed-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 91 ++++++++++++++++++++++++++ 1 file changed, 91 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index e62245e37a61..86c5bfb33357 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -1296,6 +1296,97 @@ usb_1_ssphy: usb3-phy@8903400 { }; }; + pmu@9091000 { + compatible = "qcom,sc8280xp-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; + reg = <0 0x9091000 0 0x1000>; + + interrupts = ; + + interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>; + + operating-points-v2 = <&llcc_bwmon_opp_table>; + + llcc_bwmon_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-0 { + opp-peak-kBps = <762000>; + }; + opp-1 { + opp-peak-kBps = <1720000>; + }; + opp-2 { + opp-peak-kBps = <2086000>; + }; + opp-3 { + opp-peak-kBps = <2597000>; + }; + opp-4 { + opp-peak-kBps = <2929000>; + }; + opp-5 { + opp-peak-kBps = <3879000>; + }; + opp-6 { + opp-peak-kBps = <5161000>; + }; + opp-7 { + opp-peak-kBps = <5931000>; + }; + opp-8 { + opp-peak-kBps = <6515000>; + }; + opp-9 { + opp-peak-kBps = <7980000>; + }; + opp-10 { + opp-peak-kBps = <8136000>; + }; + opp-11 { + opp-peak-kBps = <10437000>; + }; + opp-12 { + opp-peak-kBps = <12191000>; + }; + }; + }; + + pmu@90b6400 { + compatible = "qcom,sc8280xp-bwmon", "qcom,msm8998-bwmon"; + reg = <0 0x090b6400 0 0x600>; + + interrupts = ; + + interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>; + operating-points-v2 = <&cpu_bwmon_opp_table>; + + cpu_bwmon_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-0 { + opp-peak-kBps = <2288000>; + }; + opp-1 { + opp-peak-kBps = <4577000>; + }; + opp-2 { + opp-peak-kBps = <7110000>; + }; + opp-3 { + opp-peak-kBps = <9155000>; + }; + opp-4 { + opp-peak-kBps = <12298000>; + }; + opp-5 { + opp-peak-kBps = <14236000>; + }; + opp-6 { + opp-peak-kBps = <15258001>; + }; + }; + }; + system-cache-controller@9200000 { compatible = "qcom,sc8280xp-llcc"; reg = <0 0x09200000 0 0x58000>, <0 0x09600000 0 0x58000>;