From patchwork Fri Oct 28 20:48:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Walker X-Patchwork-Id: 13024287 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 45577ECAAA1 for ; Fri, 28 Oct 2022 20:48:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229851AbiJ1Use (ORCPT ); Fri, 28 Oct 2022 16:48:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47890 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229898AbiJ1Us3 (ORCPT ); Fri, 28 Oct 2022 16:48:29 -0400 Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 110BD23AB7E; Fri, 28 Oct 2022 13:48:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1666990106; x=1698526106; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=TzcP1yHmtwweYfkjNw9hfdumqxigqt50I2pQJenZIcE=; b=JQdY02WqVe5V9/R02urTqbWtvGV7nIVuOIK1o6cbwy27YQm7Uh463V6H V+rLhZB78yf6yCfPDEFZZDxVbpkTQExdZO58Mzc3TNG4hpbbRfrP7yB6O f9TbVcQBX+bS3ktzPgixwAj6cxKKc4GNuocbv86XMI2O6xB7eEc0wcfdb wHwwaVwJIqbWIZGlQkgvD69o0JrJfMX51NxU/Nu2Pk/q/tgT6PMdOcJf1 8senbWXVIx8QMarW7U3sHueCOhgYoiBUdDt+D8H5yZNiqnAhmGYs+7YuP AVBCFubdpdKmIqIWrKebfQsuc19/zK2vrZxwWLjc2+59Bfvq3hpS5cNmR A==; X-IronPort-AV: E=McAfee;i="6500,9779,10514"; a="291885090" X-IronPort-AV: E=Sophos;i="5.95,222,1661842800"; d="scan'208";a="291885090" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Oct 2022 13:48:21 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10514"; a="962159798" X-IronPort-AV: E=Sophos;i="5.95,222,1661842800"; d="scan'208";a="962159798" Received: from bwalker-desk.ch.intel.com ([143.182.136.162]) by fmsmga005.fm.intel.com with ESMTP; 28 Oct 2022 13:48:20 -0700 From: Ben Walker To: vkoul@kernel.org Cc: dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, Dave Jiang Subject: [PATCH v6 1/7] dmaengine: Remove dma_async_is_complete from client API Date: Fri, 28 Oct 2022 13:48:06 -0700 Message-Id: <20221028204812.1772736-2-benjamin.walker@intel.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221028204812.1772736-1-benjamin.walker@intel.com> References: <20220829203537.30676-1-benjamin.walker@intel.com> <20221028204812.1772736-1-benjamin.walker@intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org This is never actually used by any existing DMA clients. It is only used, via dma_cookie_status, by providers. Signed-off-by: Ben Walker Reviewed-by: Dave Jiang --- Documentation/driver-api/dmaengine/client.rst | 5 ++-- drivers/dma/dmaengine.h | 10 ++++++- include/linux/dmaengine.h | 28 ++----------------- 3 files changed, 14 insertions(+), 29 deletions(-) diff --git a/Documentation/driver-api/dmaengine/client.rst b/Documentation/driver-api/dmaengine/client.rst index bfd057b21a000..85ecec2c40005 100644 --- a/Documentation/driver-api/dmaengine/client.rst +++ b/Documentation/driver-api/dmaengine/client.rst @@ -346,9 +346,8 @@ Further APIs the documentation in include/linux/dmaengine.h for a more complete description of this API. - This can be used in conjunction with dma_async_is_complete() and - the cookie returned from dmaengine_submit() to check for - completion of a specific DMA transaction. + This can be used with the cookie returned from dmaengine_submit() + to check for completion of a specific DMA transaction. .. note:: diff --git a/drivers/dma/dmaengine.h b/drivers/dma/dmaengine.h index 53f16d3f00294..a2ce377e9ed0f 100644 --- a/drivers/dma/dmaengine.h +++ b/drivers/dma/dmaengine.h @@ -79,7 +79,15 @@ static inline enum dma_status dma_cookie_status(struct dma_chan *chan, state->residue = 0; state->in_flight_bytes = 0; } - return dma_async_is_complete(cookie, complete, used); + + if (complete <= used) { + if ((cookie <= complete) || (cookie > used)) + return DMA_COMPLETE; + } else { + if ((cookie <= complete) && (cookie > used)) + return DMA_COMPLETE; + } + return DMA_IN_PROGRESS; } static inline void dma_set_residue(struct dma_tx_state *state, u32 residue) diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h index c923f4e60f240..c55dcae7dc620 100644 --- a/include/linux/dmaengine.h +++ b/include/linux/dmaengine.h @@ -1426,9 +1426,9 @@ static inline void dma_async_issue_pending(struct dma_chan *chan) * @last: returns last completed cookie, can be NULL * @used: returns last issued cookie, can be NULL * - * If @last and @used are passed in, upon return they reflect the driver - * internal state and can be used with dma_async_is_complete() to check - * the status of multiple cookies without re-checking hardware state. + * If @last and @used are passed in, upon return they reflect the most + * recently submitted (used) cookie and the most recently completed + * cookie. */ static inline enum dma_status dma_async_is_tx_complete(struct dma_chan *chan, dma_cookie_t cookie, dma_cookie_t *last, dma_cookie_t *used) @@ -1444,28 +1444,6 @@ static inline enum dma_status dma_async_is_tx_complete(struct dma_chan *chan, return status; } -/** - * dma_async_is_complete - test a cookie against chan state - * @cookie: transaction identifier to test status of - * @last_complete: last know completed transaction - * @last_used: last cookie value handed out - * - * dma_async_is_complete() is used in dma_async_is_tx_complete() - * the test logic is separated for lightweight testing of multiple cookies - */ -static inline enum dma_status dma_async_is_complete(dma_cookie_t cookie, - dma_cookie_t last_complete, dma_cookie_t last_used) -{ - if (last_complete <= last_used) { - if ((cookie <= last_complete) || (cookie > last_used)) - return DMA_COMPLETE; - } else { - if ((cookie <= last_complete) && (cookie > last_used)) - return DMA_COMPLETE; - } - return DMA_IN_PROGRESS; -} - static inline void dma_set_tx_state(struct dma_tx_state *st, dma_cookie_t last, dma_cookie_t used, u32 residue) { From patchwork Fri Oct 28 20:48:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Walker X-Patchwork-Id: 13024288 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2ED99C38A02 for ; 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X-IronPort-AV: E=McAfee;i="6500,9779,10514"; a="291885104" X-IronPort-AV: E=Sophos;i="5.95,222,1661842800"; d="scan'208";a="291885104" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Oct 2022 13:48:27 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10514"; a="962159823" X-IronPort-AV: E=Sophos;i="5.95,222,1661842800"; d="scan'208";a="962159823" Received: from bwalker-desk.ch.intel.com ([143.182.136.162]) by fmsmga005.fm.intel.com with ESMTP; 28 Oct 2022 13:48:26 -0700 From: Ben Walker To: vkoul@kernel.org Cc: dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, Dave Jiang Subject: [PATCH v6 2/7] dmaengine: Move dma_set_tx_state to the provider API header Date: Fri, 28 Oct 2022 13:48:07 -0700 Message-Id: <20221028204812.1772736-3-benjamin.walker@intel.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221028204812.1772736-1-benjamin.walker@intel.com> References: <20220829203537.30676-1-benjamin.walker@intel.com> <20221028204812.1772736-1-benjamin.walker@intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org This is only used by DMA providers, not DMA clients. Move it next to the other cookie utility functions. Signed-off-by: Ben Walker Reviewed-by: Dave Jiang --- drivers/dma/dmaengine.h | 11 +++++++++++ include/linux/dmaengine.h | 11 ----------- 2 files changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/dma/dmaengine.h b/drivers/dma/dmaengine.h index a2ce377e9ed0f..e72876a512a39 100644 --- a/drivers/dma/dmaengine.h +++ b/drivers/dma/dmaengine.h @@ -90,6 +90,17 @@ static inline enum dma_status dma_cookie_status(struct dma_chan *chan, return DMA_IN_PROGRESS; } +static inline void dma_set_tx_state(struct dma_tx_state *st, + dma_cookie_t last, dma_cookie_t used, u32 residue) +{ + if (!st) + return; + + st->last = last; + st->used = used; + st->residue = residue; +} + static inline void dma_set_residue(struct dma_tx_state *state, u32 residue) { if (state) diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h index c55dcae7dc620..5ae881729b620 100644 --- a/include/linux/dmaengine.h +++ b/include/linux/dmaengine.h @@ -1444,17 +1444,6 @@ static inline enum dma_status dma_async_is_tx_complete(struct dma_chan *chan, return status; } -static inline void -dma_set_tx_state(struct dma_tx_state *st, dma_cookie_t last, dma_cookie_t used, u32 residue) -{ - if (!st) - return; - - st->last = last; - st->used = used; - st->residue = residue; -} - #ifdef CONFIG_DMA_ENGINE struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type); enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie); From patchwork Fri Oct 28 20:48:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Walker X-Patchwork-Id: 13024289 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9656EECAAA1 for ; Fri, 28 Oct 2022 20:48:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229877AbiJ1Usi (ORCPT ); Fri, 28 Oct 2022 16:48:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47856 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229846AbiJ1Usd (ORCPT ); Fri, 28 Oct 2022 16:48:33 -0400 Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1D1AE23B684; Fri, 28 Oct 2022 13:48:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1666990112; x=1698526112; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Nk/K5i7j65qqOGXiPvtxT8raiuWpDxteaKLaAofkBog=; b=n4uHuGkJHi67yD7hYETT/XV1UebksWNNcQi1lU2fZbMz2xUarL4PwnhO UoOmafDOvFkyMfLeOYw0PJba4SJ/cFAxQreSNY1umLhdSQW12ZBr3LGgu B+6xbRFIanUTrttJqaSxyQVDoCeJE0z0ihKAyC9DaXCs3iwz7Y7e8BnNF Us2kIKe+5XHaHqZAAKpfiy+xNTWgUXyNkTEm0oAEmTOveigVU/0hiG6Wv qBy01PL67XKhO0N7/9batjF1uRiba5byq+yoB3l0q0XJGRFrpqftIRMdU chrKaG8nIc/1FSZ+bv6NVUeocX6a23RSS7wa/reRlYYjdd/isvpBXU3qi Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10514"; a="291885114" X-IronPort-AV: E=Sophos;i="5.95,222,1661842800"; d="scan'208";a="291885114" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Oct 2022 13:48:31 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10514"; a="962159835" X-IronPort-AV: E=Sophos;i="5.95,222,1661842800"; d="scan'208";a="962159835" Received: from bwalker-desk.ch.intel.com ([143.182.136.162]) by fmsmga005.fm.intel.com with ESMTP; 28 Oct 2022 13:48:30 -0700 From: Ben Walker To: vkoul@kernel.org Cc: dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, Dave Jiang Subject: [PATCH v6 3/7] dmaengine: Add dmaengine_is_tx_complete Date: Fri, 28 Oct 2022 13:48:08 -0700 Message-Id: <20221028204812.1772736-4-benjamin.walker@intel.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221028204812.1772736-1-benjamin.walker@intel.com> References: <20220829203537.30676-1-benjamin.walker@intel.com> <20221028204812.1772736-1-benjamin.walker@intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org This is the replacement for dma_async_is_tx_complete with two changes: 1) The name prefix is 'dmaengine' as per convention 2) It no longer reports the 'last' or 'used' cookie Drivers should convert to using dmaengine_is_tx_complete. Signed-off-by: Ben Walker Reviewed-by: Dave Jiang --- Documentation/driver-api/dmaengine/client.rst | 19 ++++--------------- .../driver-api/dmaengine/provider.rst | 6 +++--- drivers/dma/dmaengine.c | 2 +- drivers/dma/dmatest.c | 3 +-- include/linux/dmaengine.h | 16 ++++++++++++++++ 5 files changed, 25 insertions(+), 21 deletions(-) diff --git a/Documentation/driver-api/dmaengine/client.rst b/Documentation/driver-api/dmaengine/client.rst index 85ecec2c40005..9e737041d65ea 100644 --- a/Documentation/driver-api/dmaengine/client.rst +++ b/Documentation/driver-api/dmaengine/client.rst @@ -259,8 +259,8 @@ The details of these operations are: dma_cookie_t dmaengine_submit(struct dma_async_tx_descriptor *desc) - This returns a cookie can be used to check the progress of DMA engine - activity via other DMA engine calls not covered in this document. + This returns a cookie that can be used to check the progress of a transaction + via dmaengine_is_tx_complete(). dmaengine_submit() will not start the DMA operation, it merely adds it to the pending queue. For this, see step 5, dma_async_issue_pending. @@ -339,23 +339,12 @@ Further APIs .. code-block:: c - enum dma_status dma_async_is_tx_complete(struct dma_chan *chan, - dma_cookie_t cookie, dma_cookie_t *last, dma_cookie_t *used) - - This can be used to check the status of the channel. Please see - the documentation in include/linux/dmaengine.h for a more complete - description of this API. + enum dma_status dmaengine_is_tx_complete(struct dma_chan *chan, + dma_cookie_t cookie) This can be used with the cookie returned from dmaengine_submit() to check for completion of a specific DMA transaction. - .. note:: - - Not all DMA engine drivers can return reliable information for - a running DMA channel. It is recommended that DMA engine users - pause or stop (via dmaengine_terminate_all()) the channel before - using this API. - 5. Synchronize termination API .. code-block:: c diff --git a/Documentation/driver-api/dmaengine/provider.rst b/Documentation/driver-api/dmaengine/provider.rst index ceac2a300e328..1d0da2777921d 100644 --- a/Documentation/driver-api/dmaengine/provider.rst +++ b/Documentation/driver-api/dmaengine/provider.rst @@ -539,10 +539,10 @@ where to put them) dma_cookie_t -- it's a DMA transaction ID that will increment over time. +- it's a DMA transaction ID. -- Not really relevant any more since the introduction of ``virt-dma`` - that abstracts it away. +- The value can be chosen by the provider, or use the helper APIs + such as dma_cookie_assign() and dma_cookie_complete(). DMA_CTRL_ACK diff --git a/drivers/dma/dmaengine.c b/drivers/dma/dmaengine.c index c741b6431958c..74bc92e51a5a7 100644 --- a/drivers/dma/dmaengine.c +++ b/drivers/dma/dmaengine.c @@ -523,7 +523,7 @@ enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie) dma_async_issue_pending(chan); do { - status = dma_async_is_tx_complete(chan, cookie, NULL, NULL); + status = dmaengine_is_tx_complete(chan, cookie); if (time_after_eq(jiffies, dma_sync_wait_timeout)) { dev_err(chan->device->dev, "%s: timeout!\n", __func__); return DMA_ERROR; diff --git a/drivers/dma/dmatest.c b/drivers/dma/dmatest.c index ffe621695e472..76a027e95d2aa 100644 --- a/drivers/dma/dmatest.c +++ b/drivers/dma/dmatest.c @@ -831,8 +831,7 @@ static int dmatest_func(void *data) done->done, msecs_to_jiffies(params->timeout)); - status = dma_async_is_tx_complete(chan, cookie, NULL, - NULL); + status = dmaengine_is_tx_complete(chan, cookie); } if (!done->done) { diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h index 5ae881729b620..72b7d51fe41de 100644 --- a/include/linux/dmaengine.h +++ b/include/linux/dmaengine.h @@ -1426,6 +1426,8 @@ static inline void dma_async_issue_pending(struct dma_chan *chan) * @last: returns last completed cookie, can be NULL * @used: returns last issued cookie, can be NULL * + * Note: This is deprecated. Use dmaengine_is_tx_complete instead. + * * If @last and @used are passed in, upon return they reflect the most * recently submitted (used) cookie and the most recently completed * cookie. @@ -1444,6 +1446,20 @@ static inline enum dma_status dma_async_is_tx_complete(struct dma_chan *chan, return status; } +/** + * dmaengine_is_tx_complete - poll for transaction completion + * @chan: DMA channel + * @cookie: transaction identifier to check status of + * + */ +static inline enum dma_status dmaengine_is_tx_complete(struct dma_chan *chan, + dma_cookie_t cookie) +{ + struct dma_tx_state state; + + return chan->device->device_tx_status(chan, cookie, &state); +} + #ifdef CONFIG_DMA_ENGINE struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type); enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie); From patchwork Fri Oct 28 20:48:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Walker X-Patchwork-Id: 13024290 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1B717C38A02 for ; Fri, 28 Oct 2022 20:48:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229597AbiJ1Usj (ORCPT ); Fri, 28 Oct 2022 16:48:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47894 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229868AbiJ1Usf (ORCPT ); Fri, 28 Oct 2022 16:48:35 -0400 Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D854523AB61; Fri, 28 Oct 2022 13:48:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1666990114; x=1698526114; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=3SWIcRGRt8kh18AXJXrL3bsHSZdCuMtCu2X+SbLmmGE=; b=GTOlf4FQdHDGdMITgG+cU06B1jnQQL5xwMXSWnW5tZwkGT2RZX2HyXpY UP+Gxgai/JekWDqTxD2r0nrAyx0M6zCMO7op8zSTVPvnDRp4WdGIW01Pb Lm30PRxlEzVdcdt/d58rCWYVsUcvMpZXuXgiYx0J88zIMZBtLOxHu5Ca+ IrAi2QTg+8oV4rq+U84+9iZZxT/NITdTVA79iqcGx9LmEN6HijOgXM7BF JX8Yv56kDtnAPYiP2Ow89MgLnvaVJ+t/bi0Qx0HjURANfSsXz2z9sQh6T elU9Dcu9oNpVHOokSqYv58sgUZzXq89W1mIAcwQtmarCfOWZN3jUPk4wG A==; X-IronPort-AV: E=McAfee;i="6500,9779,10514"; a="291885119" X-IronPort-AV: E=Sophos;i="5.95,222,1661842800"; d="scan'208";a="291885119" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Oct 2022 13:48:34 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10514"; a="962159863" X-IronPort-AV: E=Sophos;i="5.95,222,1661842800"; d="scan'208";a="962159863" Received: from bwalker-desk.ch.intel.com ([143.182.136.162]) by fmsmga005.fm.intel.com with ESMTP; 28 Oct 2022 13:48:34 -0700 From: Ben Walker To: vkoul@kernel.org Cc: dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, Dave Jiang Subject: [PATCH v6 4/7] dmaengine: Add provider documentation on cookie assignment Date: Fri, 28 Oct 2022 13:48:09 -0700 Message-Id: <20221028204812.1772736-5-benjamin.walker@intel.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221028204812.1772736-1-benjamin.walker@intel.com> References: <20220829203537.30676-1-benjamin.walker@intel.com> <20221028204812.1772736-1-benjamin.walker@intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org Clarify the rules on assigning cookies to DMA transactions. Signed-off-by: Ben Walker Reviewed-by: Dave Jiang --- .../driver-api/dmaengine/provider.rst | 45 +++++++++++++++---- 1 file changed, 37 insertions(+), 8 deletions(-) diff --git a/Documentation/driver-api/dmaengine/provider.rst b/Documentation/driver-api/dmaengine/provider.rst index 1d0da2777921d..a5539f816d125 100644 --- a/Documentation/driver-api/dmaengine/provider.rst +++ b/Documentation/driver-api/dmaengine/provider.rst @@ -417,7 +417,9 @@ supported. - tx_submit: A pointer to a function you have to implement, that is supposed to push the current transaction descriptor to a - pending queue, waiting for issue_pending to be called. + pending queue, waiting for issue_pending to be called. Each + descriptor is given a cookie to identify it. See the section + "Cookie Management" below. - In this structure the function pointer callback_result can be initialized in order for the submitter to be notified that a @@ -522,6 +524,40 @@ supported. - May sleep. +Cookie Management +------------------ + +When a transaction is queued for submission via tx_submit(), the provider +must assign that transaction a cookie (dma_cookie_t) to uniquely identify it. +The provider is allowed to perform this assignment however it wants, but for +convenience the following utility functions are available to create +monotonically increasing cookies + + .. code-block:: c + + void dma_cookie_init(struct dma_chan *chan); + + Called once at channel creation + + .. code-block:: c + + dma_cookie_t dma_cookie_assign(struct dma_async_tx_descriptor *tx); + + Assign a cookie to the given descriptor + + .. code-block:: c + + void dma_cookie_complete(struct dma_async_tx_descriptor *tx); + + Mark the descriptor as complete and invalidate the cookie + + .. code-block:: c + + enum dma_status dma_cookie_status(struct dma_chan *chan, + dma_cookie_t cookie, struct dma_tx_state *state); + + Report the status of the cookie and filling in state, if not NULL. + Misc notes ========== @@ -537,13 +573,6 @@ where to put them) - Makes sure that dependent operations are run before marking it as complete. -dma_cookie_t - -- it's a DMA transaction ID. - -- The value can be chosen by the provider, or use the helper APIs - such as dma_cookie_assign() and dma_cookie_complete(). - DMA_CTRL_ACK - If clear, the descriptor cannot be reused by provider until the From patchwork Fri Oct 28 20:48:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Walker X-Patchwork-Id: 13024291 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B0D57FA3740 for ; Fri, 28 Oct 2022 20:48:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229945AbiJ1Usm (ORCPT ); Fri, 28 Oct 2022 16:48:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47866 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229838AbiJ1Ush (ORCPT ); Fri, 28 Oct 2022 16:48:37 -0400 Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2049123AB6C; Fri, 28 Oct 2022 13:48:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1666990117; x=1698526117; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=cV0R+8GoIkGqd7y8oYhqM5PrpbnhFRPNwiSxTQR2btQ=; b=j+g714N+mVYs5CT/uBi6Wav7bPUucsbAPRdt4ynEASqh5ys+sPwQ+249 TxQQKHHPhlZbDjJDrbWp3d5zNdV4/i6LnWKqh3Mv/4oX/CJPxaJmGwF3f ILZpijgbyvzNyfIiop62/wT7lGygswV0F6G9xXwlJTlf0WdNxGIolgb5m /PRZme6eCYY8bte6rEiS6hTTsIdepw3GQEQqzNcrOeviDdigxwLFmNpul ZyrYqLUCNlfzcfXPDxSXLsfU3m3xIXKmRip1XH6FHN4WbeRgPII5lmpvX VD7vlpEFGiLIT2/ENcxmXKLqNYsVaMdulQKHcsJwmE/gr6ihW4uUmsPxK Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10514"; a="291885122" X-IronPort-AV: E=Sophos;i="5.95,222,1661842800"; d="scan'208";a="291885122" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Oct 2022 13:48:36 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10514"; a="962159875" X-IronPort-AV: E=Sophos;i="5.95,222,1661842800"; d="scan'208";a="962159875" Received: from bwalker-desk.ch.intel.com ([143.182.136.162]) by fmsmga005.fm.intel.com with ESMTP; 28 Oct 2022 13:48:36 -0700 From: Ben Walker To: vkoul@kernel.org Cc: dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, Dave Jiang Subject: [PATCH v6 5/7] dmaengine: idxd: idxd_desc.id is now a u16 Date: Fri, 28 Oct 2022 13:48:10 -0700 Message-Id: <20221028204812.1772736-6-benjamin.walker@intel.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221028204812.1772736-1-benjamin.walker@intel.com> References: <20220829203537.30676-1-benjamin.walker@intel.com> <20221028204812.1772736-1-benjamin.walker@intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org This is going to be packed into the cookie. It does not need to be negative or larger than u16. Signed-off-by: Ben Walker Reviewed-by: Dave Jiang --- drivers/dma/idxd/idxd.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/dma/idxd/idxd.h b/drivers/dma/idxd/idxd.h index 1196ab342f011..d9096dfb27422 100644 --- a/drivers/dma/idxd/idxd.h +++ b/drivers/dma/idxd/idxd.h @@ -333,7 +333,7 @@ struct idxd_desc { struct dma_async_tx_descriptor txd; struct llist_node llnode; struct list_head list; - int id; + u16 id; int cpu; struct idxd_wq *wq; }; From patchwork Fri Oct 28 20:48:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Walker X-Patchwork-Id: 13024292 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EF2A0ECAAA1 for ; Fri, 28 Oct 2022 20:48:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229915AbiJ1Uso (ORCPT ); Fri, 28 Oct 2022 16:48:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48026 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229912AbiJ1Usk (ORCPT ); Fri, 28 Oct 2022 16:48:40 -0400 Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9111023AB74; Fri, 28 Oct 2022 13:48:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1666990119; x=1698526119; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=evvx+nDuoiHJQ8Cz/68x5eQqcsBuh3i6RV3xt1h3Odo=; b=nc0j8zWGnP5uG3mRMkB+3xGJQTQB9e88eXXJm4Nm8MKTB2paGgQG7GD7 l7mSQQD0+kKAOoerg5qvLBcT7D0JqdENvWnhm9U73sBVR49ZwJB8SBfes g5VjBmmXx2jDROmUch+OgqjC+FhMZuCz6F1CgKqvHSNacVKbY0c2IGBte dMFJg1geWO2+qH59xGVy5tpVsPFV/ZNBEq+8B9cbB/hWLt3rssc8W8EjF u/Sb+sjqO9xAGVVh+9BTV5CcmBZL3m+RkclE4XvAY1F17QKxbrx1ENKUc BF/9sG+2fA9oPgT9Fzz5wBszt3/NnBop9+H/voVr5/6eDuLlbU6SRiUrh Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10514"; a="291885126" X-IronPort-AV: E=Sophos;i="5.95,222,1661842800"; d="scan'208";a="291885126" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Oct 2022 13:48:39 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10514"; a="962159886" X-IronPort-AV: E=Sophos;i="5.95,222,1661842800"; d="scan'208";a="962159886" Received: from bwalker-desk.ch.intel.com ([143.182.136.162]) by fmsmga005.fm.intel.com with ESMTP; 28 Oct 2022 13:48:39 -0700 From: Ben Walker To: vkoul@kernel.org Cc: dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, Dave Jiang Subject: [PATCH v6 6/7] dmaengine: idxd: Support device_tx_status Date: Fri, 28 Oct 2022 13:48:11 -0700 Message-Id: <20221028204812.1772736-7-benjamin.walker@intel.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221028204812.1772736-1-benjamin.walker@intel.com> References: <20220829203537.30676-1-benjamin.walker@intel.com> <20221028204812.1772736-1-benjamin.walker@intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org This can now be supported even for devices that complete operations out of order. Add support for directly polling transactions. Signed-off-by: Ben Walker Reviewed-by: Dave Jiang --- drivers/dma/idxd/device.c | 1 + drivers/dma/idxd/dma.c | 84 ++++++++++++++++++++++++++++++++++++++- drivers/dma/idxd/idxd.h | 1 + 3 files changed, 84 insertions(+), 2 deletions(-) diff --git a/drivers/dma/idxd/device.c b/drivers/dma/idxd/device.c index 2c1e6f6daa628..870e7adfdd240 100644 --- a/drivers/dma/idxd/device.c +++ b/drivers/dma/idxd/device.c @@ -148,6 +148,7 @@ int idxd_wq_alloc_resources(struct idxd_wq *wq) desc->iax_completion = &wq->iax_compls[i]; desc->compl_dma = wq->compls_addr + idxd->data->compl_size * i; desc->id = i; + desc->gen = 1; desc->wq = wq; desc->cpu = -1; } diff --git a/drivers/dma/idxd/dma.c b/drivers/dma/idxd/dma.c index e0874cb4721c8..87749efec311b 100644 --- a/drivers/dma/idxd/dma.c +++ b/drivers/dma/idxd/dma.c @@ -12,6 +12,23 @@ #include "registers.h" #include "idxd.h" + +#define DMA_COOKIE_BITS (sizeof(dma_cookie_t) * 8) +/* + * The descriptor id takes the lower 16 bits of the cookie. + */ +#define DESC_ID_BITS 16 +#define DESC_ID_MASK ((1 << DESC_ID_BITS) - 1) +/* + * The 'generation' is in the upper half of the cookie. But dma_cookie_t + * is signed, so we leave the upper-most bit for the sign. Further, we + * need to flag whether a cookie corresponds to an operation that is + * being completed via interrupt to avoid polling it, which takes + * the second most upper bit. So we subtract two bits from the upper half. + */ +#define DESC_GEN_MAX ((1 << (DMA_COOKIE_BITS - DESC_ID_BITS - 2)) - 1) +#define DESC_INTERRUPT_FLAG (1 << (DMA_COOKIE_BITS - 2)) + static inline struct idxd_wq *to_idxd_wq(struct dma_chan *c) { struct idxd_dma_chan *idxd_chan; @@ -162,9 +179,62 @@ static enum dma_status idxd_dma_tx_status(struct dma_chan *dma_chan, dma_cookie_t cookie, struct dma_tx_state *txstate) { - return DMA_OUT_OF_ORDER; + u8 status; + struct idxd_wq *wq; + struct idxd_desc *desc; + u32 idx; + + memset(txstate, 0, sizeof(*txstate)); + + if (dma_submit_error(cookie)) + return DMA_ERROR; + + wq = to_idxd_wq(dma_chan); + + idx = cookie & DESC_ID_MASK; + if (idx >= wq->num_descs) + return DMA_ERROR; + + desc = wq->descs[idx]; + + if (desc->txd.cookie != cookie) { + /* + * The user asked about an old transaction + */ + return DMA_COMPLETE; + } + + /* + * For descriptors completed via interrupt, we can't go + * look at the completion status directly because it races + * with the IRQ handler recyling the descriptor. However, + * since in this case we can rely on the interrupt handler + * to invalidate the cookie when the command completes we + * know that if we get here, the command is still in + * progress. + */ + if ((cookie & DESC_INTERRUPT_FLAG) != 0) + return DMA_IN_PROGRESS; + + status = desc->completion->status & DSA_COMP_STATUS_MASK; + + if (status) { + /* + * Check against the original status as ABORT is software defined + * and 0xff, which DSA_COMP_STATUS_MASK can mask out. + */ + if (unlikely(desc->completion->status == IDXD_COMP_DESC_ABORT)) + idxd_dma_complete_txd(desc, IDXD_COMPLETE_ABORT, true); + else + idxd_dma_complete_txd(desc, IDXD_COMPLETE_NORMAL, true); + + return DMA_COMPLETE; + } + + return DMA_IN_PROGRESS; } + /* * issue_pending() does not need to do anything since tx_submit() does the job * already. @@ -181,7 +251,17 @@ static dma_cookie_t idxd_dma_tx_submit(struct dma_async_tx_descriptor *tx) int rc; struct idxd_desc *desc = container_of(tx, struct idxd_desc, txd); - cookie = dma_cookie_assign(tx); + cookie = (desc->gen << DESC_ID_BITS) | (desc->id & DESC_ID_MASK); + + if ((desc->hw->flags & IDXD_OP_FLAG_RCI) != 0) + cookie |= DESC_INTERRUPT_FLAG; + + if (desc->gen == DESC_GEN_MAX) + desc->gen = 1; + else + desc->gen++; + + tx->cookie = cookie; rc = idxd_submit_desc(wq, desc); if (rc < 0) { diff --git a/drivers/dma/idxd/idxd.h b/drivers/dma/idxd/idxd.h index d9096dfb27422..739c55e56502c 100644 --- a/drivers/dma/idxd/idxd.h +++ b/drivers/dma/idxd/idxd.h @@ -334,6 +334,7 @@ struct idxd_desc { struct llist_node llnode; struct list_head list; u16 id; + u16 gen; int cpu; struct idxd_wq *wq; }; From patchwork Fri Oct 28 20:48:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Walker X-Patchwork-Id: 13024293 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 77DB6C38A02 for ; Fri, 28 Oct 2022 20:49:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229971AbiJ1UtI (ORCPT ); Fri, 28 Oct 2022 16:49:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48154 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229968AbiJ1Usp (ORCPT ); Fri, 28 Oct 2022 16:48:45 -0400 Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 02D8523AB79; Fri, 28 Oct 2022 13:48:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1666990123; x=1698526123; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=vMCqd5k3WahxigGt7TY5NIkIs3Luf/Dyqdfr9vdCMF4=; b=lhejwK6VQFY/XI6uO9PolGv+ejCPdJ7MZNYYIV9p50yyqrgS4elkrMAB ARNfIhMu0BxAnkC3astDh+FU90emG6SOrxIheH92Pcw9ClM6+0ICR23tr N1vuE6ZaXlYMeeK8fdNYu6VVKy8u9ijHHSGDNfIKpvqZvJ+0wLSpSPMKZ /ZX8VuyNiro2ZYg0tMCTGn4QNH4AFF31o1zF7pCl2uICnc7F5suwq2tB/ 0C6LyLm4yI6N5W/xhv3Xo95pqEZW6Gy5xVoA4eBpFaoW1sClLjnwgHZ/C 2MiFhaCKIuPfPRsurhE8nJGr0jU7PKTKqctbn3xcY0NPLkl87lpnF5lRv Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10514"; a="291885132" X-IronPort-AV: E=Sophos;i="5.95,222,1661842800"; d="scan'208";a="291885132" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Oct 2022 13:48:42 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10514"; a="962159903" X-IronPort-AV: E=Sophos;i="5.95,222,1661842800"; d="scan'208";a="962159903" Received: from bwalker-desk.ch.intel.com ([143.182.136.162]) by fmsmga005.fm.intel.com with ESMTP; 28 Oct 2022 13:48:42 -0700 From: Ben Walker To: vkoul@kernel.org Cc: dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, Dave Jiang Subject: [PATCH v6 7/7] dmaengine: Revert "cookie bypass for out of order completion" Date: Fri, 28 Oct 2022 13:48:12 -0700 Message-Id: <20221028204812.1772736-8-benjamin.walker@intel.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221028204812.1772736-1-benjamin.walker@intel.com> References: <20220829203537.30676-1-benjamin.walker@intel.com> <20221028204812.1772736-1-benjamin.walker@intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org This reverts commit 47ec7f09bc107720905c96bc37771e4ed1ff0aed. This is no longer necessary now that all assumptions about the order of completions have been removed from the dmaengine client API. Signed-off-by: Ben Walker Reviewed-by: Dave Jiang --- .../driver-api/dmaengine/provider.rst | 19 ------------------- drivers/dma/dmatest.c | 11 +---------- drivers/dma/idxd/dma.c | 1 - include/linux/dmaengine.h | 2 -- 4 files changed, 1 insertion(+), 32 deletions(-) diff --git a/Documentation/driver-api/dmaengine/provider.rst b/Documentation/driver-api/dmaengine/provider.rst index a5539f816d125..8d1510c8cb66f 100644 --- a/Documentation/driver-api/dmaengine/provider.rst +++ b/Documentation/driver-api/dmaengine/provider.rst @@ -258,22 +258,6 @@ Currently, the types available are: want to transfer a portion of uncompressed data directly to the display to print it -- DMA_COMPLETION_NO_ORDER - - - The device does not support in order completion. - - - The driver should return DMA_OUT_OF_ORDER for device_tx_status if - the device is setting this capability. - - - All cookie tracking and checking API should be treated as invalid if - the device exports this capability. - - - At this point, this is incompatible with polling option for dmatest. - - - If this cap is set, the user is recommended to provide an unique - identifier for each descriptor sent to the DMA device in order to - properly track the completion. - - DMA_REPEAT - The device supports repeated transfers. A repeated transfer, indicated by @@ -457,9 +441,6 @@ supported. - In the case of a cyclic transfer, it should only take into account the total size of the cyclic buffer. - - Should return DMA_OUT_OF_ORDER if the device does not support in order - completion and is completing the operation out of order. - - This function can be called in an interrupt context. - device_config diff --git a/drivers/dma/dmatest.c b/drivers/dma/dmatest.c index 76a027e95d2aa..2febc179a7074 100644 --- a/drivers/dma/dmatest.c +++ b/drivers/dma/dmatest.c @@ -838,10 +838,7 @@ static int dmatest_func(void *data) result("test timed out", total_tests, src->off, dst->off, len, 0); goto error_unmap_continue; - } else if (status != DMA_COMPLETE && - !(dma_has_cap(DMA_COMPLETION_NO_ORDER, - dev->cap_mask) && - status == DMA_OUT_OF_ORDER)) { + } else if (status != DMA_COMPLETE) { result(status == DMA_ERROR ? "completion error status" : "completion busy status", total_tests, src->off, @@ -1019,12 +1016,6 @@ static int dmatest_add_channel(struct dmatest_info *info, dtc->chan = chan; INIT_LIST_HEAD(&dtc->threads); - if (dma_has_cap(DMA_COMPLETION_NO_ORDER, dma_dev->cap_mask) && - info->params.polled) { - info->params.polled = false; - pr_warn("DMA_COMPLETION_NO_ORDER, polled disabled\n"); - } - if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) { if (dmatest == 0) { cnt = dmatest_add_threads(info, dtc, DMA_MEMCPY); diff --git a/drivers/dma/idxd/dma.c b/drivers/dma/idxd/dma.c index 87749efec311b..071aafec3de1b 100644 --- a/drivers/dma/idxd/dma.c +++ b/drivers/dma/idxd/dma.c @@ -296,7 +296,6 @@ int idxd_register_dma_device(struct idxd_device *idxd) dma_cap_set(DMA_INTERRUPT, dma->cap_mask); dma_cap_set(DMA_PRIVATE, dma->cap_mask); - dma_cap_set(DMA_COMPLETION_NO_ORDER, dma->cap_mask); dma->device_release = idxd_dma_release; dma->device_prep_dma_interrupt = idxd_dma_prep_interrupt; diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h index 72b7d51fe41de..59c7f67cb3b5a 100644 --- a/include/linux/dmaengine.h +++ b/include/linux/dmaengine.h @@ -39,7 +39,6 @@ enum dma_status { DMA_IN_PROGRESS, DMA_PAUSED, DMA_ERROR, - DMA_OUT_OF_ORDER, }; /** @@ -62,7 +61,6 @@ enum dma_transaction_type { DMA_SLAVE, DMA_CYCLIC, DMA_INTERLEAVE, - DMA_COMPLETION_NO_ORDER, DMA_REPEAT, DMA_LOAD_EOT, /* last transaction type for creation of the capabilities mask */