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pr=C From: Ayan Kumar Halder To: CC: , , , , , , Ayan Kumar Halder Subject: [XEN v1] xen/Arm: Enforce alignment check for atomic read/write Date: Sat, 29 Oct 2022 23:48:02 +0100 Message-ID: <20221029224802.464-1-ayankuma@amd.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000B8EE:EE_|DM6PR12MB4925:EE_ X-MS-Office365-Filtering-Correlation-Id: 1cf0c26c-0999-4ac1-e6a1-08dab9ffa8b9 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: YR90vqEmavmUqT+iD6csEi2DTGa1trLGF+FihRH4XHmd/LtJffPBD9y/MlRPPtnfBq0vVx2X34xbMZxKf/SLymdN08elvJb0RL5f6HjadKYDGQ24TdaHEUjQyxyOZEmHxhMoUEvZjb8kCWLK5wSNYfnpyc1azUxFzrVFls51DwRzfbRdBe4w2GS9nJv8X6uv6AhRBj9IN1M2Ga3PvQCj6hP66qv9xPTqs9SdxWhqeVeHa4B5qNcsYixFLIVx83X8pCgxv8s5z1P85fTfj9oAPGNuTpOxCp+DCyh9URhXXXLJcg5YEiK15kjFSFoYlMt8OhgRXHaFqqSJTNpiNFBaqe0T65LsAwuSFcwNiV71alYE2PEl27qrSY6h50ocTGMlpw2q0Rva3lcJETteSPiHDHi210cK+m0NCh1SSH9X0ibsdQJKXn7wHieUVNADaVOqrEj2+xSGl/tFhghSGHkmZ6KUMhGg3TWFyeMM4578XYKUJhkRbGr1BfK/+ZjOZbhtTc+DeLWq8SLb0/1HCS3mirj099VM0eFBsVJDE5BSWb5VRZirgF8v4yXLTsri3rYPkqY0dRcD8x2EDUpn9kuIomvaDxxLjt5fRR85Sa/4lSXnqXmAaNBchsyLEkpS5M2W+Q1wCZd/OtARswuCvhDJRMIagIcj4R/k9rkWI8/5HWRKKMu2wB898fabD0a7QBMHnfSoZztBf6hEhPjRLchx3usQBYsC5sUSmmhRvNimZufZce2J9c6HPPLtG7ED2GEhNgLmFW5ZALU18L7thX/RU+FdQ705N4ts3rMQnWJKq4tnPnbcpybgX3dAdKY3dIhTDFd1sP3AE9ygozXx6ieVHw== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(39860400002)(376002)(346002)(396003)(136003)(451199015)(36840700001)(40470700004)(46966006)(8676002)(70206006)(70586007)(4326008)(2906002)(5660300002)(8936002)(41300700001)(40480700001)(82310400005)(966005)(36860700001)(26005)(478600001)(6666004)(316002)(54906003)(6916009)(426003)(81166007)(356005)(40460700003)(82740400003)(47076005)(186003)(1076003)(336012)(2616005)(36756003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Oct 2022 22:48:12.3806 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1cf0c26c-0999-4ac1-e6a1-08dab9ffa8b9 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000B8EE.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4925 Refer ARM DDI 0487G.b ID072021, B2.2.1 "Requirements for single-copy atomicity - A read that is generated by a load instruction that loads a single general-purpose register and is aligned to the size of the read in the instruction is single-copy atomic. -A write that is generated by a store instruction that stores a single general-purpose register and is aligned to the size of the write in the instruction is single-copy atomic" On AArch32, the alignment check is enabled at boot time by setting HSCTLR.A bit. ("HSCTLR, Hyp System Control Register"). However in AArch64, alignment check is not enabled at boot time. Thus, one needs to check for alignment when performing atomic operations. Signed-off-by: Ayan Kumar Halder Reviewed-by: Michal Orzel