From patchwork Sun Oct 30 09:42:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Iskren Chernev X-Patchwork-Id: 13025039 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6344FFA3740 for ; Sun, 30 Oct 2022 09:43:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229958AbiJ3JnQ (ORCPT ); Sun, 30 Oct 2022 05:43:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41026 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229945AbiJ3JnK (ORCPT ); Sun, 30 Oct 2022 05:43:10 -0400 Received: from mail-wr1-x42c.google.com (mail-wr1-x42c.google.com [IPv6:2a00:1450:4864:20::42c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 06C46CE30; Sun, 30 Oct 2022 02:43:06 -0700 (PDT) Received: by mail-wr1-x42c.google.com with SMTP id j15so12104384wrq.3; Sun, 30 Oct 2022 02:43:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=tBK4eajyaayOpX9DdVnDzlG8OxVihLhLym73hQV3R9Y=; b=H6vHTPf4Qxb/TisGjjb7Q2+YLGroPJY6+Ryhql/XhosjWnKyp38sJZj4nhfJcrWJBd sAAvXjCwyHkWTOnyzIXmne6A9obDowMue64dViuUq4viJSmHQE9Mr0IkmbOmWF9KLLzX Qe4JBlCquV5Wc3vUdYn36wCQQJVBgEuiutH/Gi24IPdlpxaGCkCNz0PV+Y5A88Ee8+IR gaR+Rc+/DdYC9H1K8nOncGowgdqZG1IRzDOC7p8ks4q8oNeY0VIdCQGarPeLEzanCtY0 NLb18rxWTIQ6nCEUjJTQoy3Yp1tU3aWypaxaEtibUZh0/uNXVfCL8P8tJyi3CAcz5u9w 9o9A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=tBK4eajyaayOpX9DdVnDzlG8OxVihLhLym73hQV3R9Y=; b=3dueflPhrsz4qRhqiONuGLGm+RBqqusViIXygyY4UAugGcRvzsHdqek527D/5clMp+ NqAZWK6mktkimjW9PIhQQL11DiFMcRKJWPomoI2c5qT8hiO6qrbQZ7e9du0Q81xSBfLg bUhHS/qOXErrFp85vASomJDCgFe3vX275gbUbkf0z4oCUS5n+7RRfatxfFOfUsjdG9DW WfwKrt/mPoMQTFhMa3NVbb8ZBvl9WeGhOHsyLmF1qZUP3i8Z9VD0Qr6tUC1DtoMXoYcc SwfyjI7wV0OQii8aITjOS1+6FSBVPz6pewcKVf2dNpYMUOebf6p77eia9l5BcVVXCko2 ZwLA== X-Gm-Message-State: ACrzQf2hf+exX5Uf2E8d4JHhErtDxq8Y4+cXhgCTj6TD3IGPqQK8y7B4 oiLGR7cZ8jvoKebJkrdl3uY= X-Google-Smtp-Source: AMsMyM7tg/AKZ2BWnj8GOYyUbHyqMOD8dDbX+1Qno7SXFEzR3p2nycair8V+eIGl/0J8yt0P+IXzhQ== X-Received: by 2002:a5d:47c5:0:b0:22e:6941:81eb with SMTP id o5-20020a5d47c5000000b0022e694181ebmr4479204wrc.408.1667122985385; Sun, 30 Oct 2022 02:43:05 -0700 (PDT) Received: from localhost ([77.78.20.135]) by smtp.gmail.com with ESMTPSA id p14-20020a05600c358e00b003c6b9749505sm4057032wmq.30.2022.10.30.02.43.03 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 30 Oct 2022 02:43:04 -0700 (PDT) From: Iskren Chernev To: Krzysztof Kozlowski , Bjorn Andersson , Rob Herring Cc: phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Iskren Chernev , Andy Gross , Konrad Dybcio , Alim Akhtar , Avri Altman , Bart Van Assche , Krzysztof Kozlowski , linux-scsi@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 1/8] dt-bindings: ufs: qcom: Add sm6115 binding Date: Sun, 30 Oct 2022 11:42:51 +0200 Message-Id: <20221030094258.486428-2-iskren.chernev@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221030094258.486428-1-iskren.chernev@gmail.com> References: <20221030094258.486428-1-iskren.chernev@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add SM6115 UFS to DT schema. Signed-off-by: Iskren Chernev Reviewed-by: Krzysztof Kozlowski Reviewed-by: Bhupesh Sharma --- .../devicetree/bindings/ufs/qcom,ufs.yaml | 26 +++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml index f2d6298d926c..b517d76215e3 100644 --- a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml +++ b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml @@ -28,6 +28,7 @@ properties: - qcom,msm8998-ufshc - qcom,sc8280xp-ufshc - qcom,sdm845-ufshc + - qcom,sm6115-ufshc - qcom,sm6350-ufshc - qcom,sm8150-ufshc - qcom,sm8250-ufshc @@ -178,6 +179,31 @@ allOf: minItems: 1 maxItems: 1 + - if: + properties: + compatible: + contains: + enum: + - qcom,sm6115-ufshc + then: + properties: + clocks: + minItems: 8 + maxItems: 8 + clock-names: + items: + - const: core_clk + - const: bus_aggr_clk + - const: iface_clk + - const: core_clk_unipro + - const: ref_clk + - const: tx_lane0_sync_clk + - const: rx_lane0_sync_clk + - const: ice_core_clk + reg: + minItems: 2 + maxItems: 2 + # TODO: define clock bindings for qcom,msm8994-ufshc unevaluatedProperties: false From patchwork Sun Oct 30 09:42:52 2022 Content-Type: text/plain; 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Sun, 30 Oct 2022 02:43:08 -0700 (PDT) Received: from localhost ([77.78.20.135]) by smtp.gmail.com with ESMTPSA id bg14-20020a05600c3c8e00b003b497138093sm4068150wmb.47.2022.10.30.02.43.06 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 30 Oct 2022 02:43:07 -0700 (PDT) From: Iskren Chernev To: Krzysztof Kozlowski , Bjorn Andersson , Rob Herring Cc: phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Iskren Chernev , Caleb Connolly , Andy Gross , Konrad Dybcio , Krzysztof Kozlowski , linux-kernel@vger.kernel.org Subject: [PATCH v5 2/8] dt-bindings: arm: qcom: Add compatible for oneplus,billie2 phone Date: Sun, 30 Oct 2022 11:42:52 +0200 Message-Id: <20221030094258.486428-3-iskren.chernev@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221030094258.486428-1-iskren.chernev@gmail.com> References: <20221030094258.486428-1-iskren.chernev@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org oneplus,billie2 (OnePlus Nord N100) is based on QualComm Snapdragon SM4250 SoC. Add support for the same in dt-bindings. Signed-off-by: Iskren Chernev Reviewed-by: Krzysztof Kozlowski Reviewed-by: Caleb Connolly --- Documentation/devicetree/bindings/arm/qcom.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 207e28260206..7048a1fd77a7 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -54,6 +54,8 @@ description: | sdm845 sdx55 sdx65 + sm4250 + sm6115 sm6125 sm6350 sm7225 @@ -708,6 +710,11 @@ properties: - xiaomi,polaris - const: qcom,sdm845 + - items: + - enum: + - oneplus,billie2 + - const: qcom,sm4250 + - items: - enum: - sony,pdx201 From patchwork Sun Oct 30 09:42:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Iskren Chernev X-Patchwork-Id: 13025041 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 12E4FC38A02 for ; Sun, 30 Oct 2022 09:43:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229770AbiJ3Jnc (ORCPT ); Sun, 30 Oct 2022 05:43:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40898 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229853AbiJ3JnN (ORCPT ); Sun, 30 Oct 2022 05:43:13 -0400 Received: from mail-wr1-x434.google.com (mail-wr1-x434.google.com [IPv6:2a00:1450:4864:20::434]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 657FBD10A; Sun, 30 Oct 2022 02:43:12 -0700 (PDT) Received: by mail-wr1-x434.google.com with SMTP id l14so12116177wrw.2; Sun, 30 Oct 2022 02:43:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=cEHqsPqv95R3eGrYKhg4ruWGo3ymO/H/xi/Qhw4VFG0=; b=WK2hF+vuK3yG0ecPgY6uKRUUPFghjZB9XmWCti0Jk/MWl4A5UFU620msKEzGSiSdB5 xwDV3KiEWdaEO3jjnY1xenzUh4JzhHF61broc17FdKC+adqFZ/EbDyE3dL8UV9VMyUc/ 1q3b86DQntJXMK2By1KrJTirZ9v/RD3TK6Mw0y03B1Ss8Zmr53KayO/7kSED1KuSfV6S VPy/gzErZCgfy48SIiSYuBhxJmJ+fcwA7hA54cJtMebRqlXTPZoV7kG426m1Gj67Hauu ifxZW4j1QhiKXkJBiicUSvR2PuiWXbcqAVXItdlChcFwIJxL7+Kv5cvrnUZ9pNuLW2iH bcJw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=cEHqsPqv95R3eGrYKhg4ruWGo3ymO/H/xi/Qhw4VFG0=; b=Tk67YWZROIo3ehC6uMB9T1MOVrB3mrOtO7z+hu7lwNCiKjCuICN9MHXrN92+u/EV2V ZiXqCsGy8jDzCPIeTEtPSdCjFEUvsuXDEItWHnmUPpNh3rlcQx9XvhMhelT8CMe5UwRS Az0lFyw981Tct1ugScm3jW/FNJkKg14xqZcYJvzEeItdxy/LbfWYVs8elag073ekx8C+ EQsmFh69t0UJhXSKmT8Aa/tzFKekKz0i4FT31LazUujukWni4uJVuhFND7Js5icNJJ5m 22bJv6t1s8OGg/rYG6P7rcTvxTzuaACLtU5ZqP4/vzKA/WI731iYJ8VosYWsnr3AfHKJ g6xQ== X-Gm-Message-State: ACrzQf2MpUuoFAGIY54tKysdOan3UfOdTLlrq9skNerBPsv8XdhZrOPP HD5W9mtMYWzYBca54xeB0Ig= X-Google-Smtp-Source: AMsMyM66e4g3WQ6fedXjdOCMEKxZ3pSirsYGsXa5o877lNeILtX1jNDDqqDvS106b3qK0FCV/GqiRg== X-Received: by 2002:a05:6000:408c:b0:236:a7b4:fb4d with SMTP id da12-20020a056000408c00b00236a7b4fb4dmr4407306wrb.524.1667122990901; Sun, 30 Oct 2022 02:43:10 -0700 (PDT) Received: from localhost ([77.78.20.135]) by smtp.gmail.com with ESMTPSA id s4-20020a05600c384400b003c3a1d8c8e6sm3916879wmr.19.2022.10.30.02.43.09 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 30 Oct 2022 02:43:10 -0700 (PDT) From: Iskren Chernev To: Krzysztof Kozlowski , Bjorn Andersson , Rob Herring Cc: phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Adam Skladowski , Iskren Chernev , Andy Gross , Konrad Dybcio , Vinod Koul , Krzysztof Kozlowski , dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 3/8] dt-bindings: dmaengine: qcom: gpi: add compatible for SM6115 Date: Sun, 30 Oct 2022 11:42:53 +0200 Message-Id: <20221030094258.486428-4-iskren.chernev@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221030094258.486428-1-iskren.chernev@gmail.com> References: <20221030094258.486428-1-iskren.chernev@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Adam Skladowski Document the compatible for GPI DMA controller on SM6115 SoC. Signed-off-by: Adam Skladowski Signed-off-by: Iskren Chernev Acked-by: Rob Herring --- Documentation/devicetree/bindings/dma/qcom,gpi.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/dma/qcom,gpi.yaml b/Documentation/devicetree/bindings/dma/qcom,gpi.yaml index 0c2894498845..232895fa1d8d 100644 --- a/Documentation/devicetree/bindings/dma/qcom,gpi.yaml +++ b/Documentation/devicetree/bindings/dma/qcom,gpi.yaml @@ -25,6 +25,7 @@ properties: - items: - enum: - qcom,sc7280-gpi-dma + - qcom,sm6115-gpi-dma - qcom,sm8350-gpi-dma - qcom,sm8450-gpi-dma - const: qcom,sm6350-gpi-dma From patchwork Sun Oct 30 09:42:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Iskren Chernev X-Patchwork-Id: 13025042 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C06E2FA3744 for ; Sun, 30 Oct 2022 09:43:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230047AbiJ3Jnf (ORCPT ); Sun, 30 Oct 2022 05:43:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41176 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229637AbiJ3JnQ (ORCPT ); Sun, 30 Oct 2022 05:43:16 -0400 Received: from mail-wr1-x430.google.com (mail-wr1-x430.google.com [IPv6:2a00:1450:4864:20::430]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 33810BE11; Sun, 30 Oct 2022 02:43:15 -0700 (PDT) Received: by mail-wr1-x430.google.com with SMTP id w14so12066090wru.8; Sun, 30 Oct 2022 02:43:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=rUpdkVpaImdCke90/hvYwepQ6uJUg8seHB9Am7OQuCE=; b=YDoaDcvGm5/74XBRKcUtgPnpzebTfHlZ9NG8NTgrAJ2M1ghiBCDB7AGgPG1pAg81Yl YOMTtbPi0eJgKr+Rwkih1doM8lSTYuIQ46Jxxwkxt+GH8LUlJaVmrLtXO+zOiDqkl6bG DQpgngULw570soTwcEqpYHV4zk8t35OllQP4rsjoVV7UMOaKLUYL22XmXgTHtnngmMO7 OumsUKl8O1FxL9SvuX67lsSsLh+5wRYpqYaBWQGdS2D3cAnKJYsYhbseGzxg9O8IpY9C 0C2XkF8bsPqHwgCPCBMUs96kC8PxxFEpwSlhZYqFVDhnpXKqlKefqCmxWBzl5asTl97U aJsw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rUpdkVpaImdCke90/hvYwepQ6uJUg8seHB9Am7OQuCE=; b=STIlAHXfbh7FRJuFtOCzUeMSL4yvwfACG/bMBLt9omKprXupcObH1hwFb/43H96pD/ ekHr/oR0wgn/KIoP8jk5ZTti2NigNInyOKsm9mXihpJSRNL1Hw/WXikU03hdn+iE2oyZ ZOLONbfqhGGC6F/NZfOcmEB2JFnX1LiYXJXnvuztSb5vKrASzP3exdd5HXP8ecQcTFvQ 6dYKxwKP/6GcD3kVrERlgoypD3BhlbGmyxMetij8RiK0GmfYHY5ZEwfjjdC8AsvTkFW2 c8IADQeDEwvwcY22T8LaX04UlleGSTvb8SZx6mzGnxVq+5p5L76ZC4Y0O+YgxeBpv7n3 7HTg== X-Gm-Message-State: ACrzQf1/DdeTst2R7kchHbitrkWfU8wcXnThppAK3EWgkKmIwLSWyGW/ QumbW2C0JyjBTYGN12Y/nPs= X-Google-Smtp-Source: AMsMyM7heg9wKmi/oOgWiJ/mRAMCVBFekD7edTZFfwYWgxwAdc4pO/kOVbDCqV13pcsJDN0mRiNgfQ== X-Received: by 2002:adf:b644:0:b0:236:59c7:c6de with SMTP id i4-20020adfb644000000b0023659c7c6demr4463776wre.186.1667122993833; Sun, 30 Oct 2022 02:43:13 -0700 (PDT) Received: from localhost ([77.78.20.135]) by smtp.gmail.com with ESMTPSA id k3-20020a05600c1c8300b003c6b7f5567csm18453039wms.0.2022.10.30.02.43.12 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 30 Oct 2022 02:43:12 -0700 (PDT) From: Iskren Chernev To: Krzysztof Kozlowski , Bjorn Andersson , Rob Herring Cc: phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Adam Skladowski , Iskren Chernev , Will Deacon , Robin Murphy , Joerg Roedel , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH v5 4/8] dt-bindings: arm-smmu: Add compatible for Qualcomm SM6115 Date: Sun, 30 Oct 2022 11:42:54 +0200 Message-Id: <20221030094258.486428-5-iskren.chernev@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221030094258.486428-1-iskren.chernev@gmail.com> References: <20221030094258.486428-1-iskren.chernev@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Adam Skladowski Add compatible for the Qualcomm SM6115 platform to the ARM SMMU DeviceTree binding. Signed-off-by: Adam Skladowski Signed-off-by: Iskren Chernev Acked-by: Rob Herring --- Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml index 9066e6df1ba1..71f8f638a1f8 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml @@ -41,6 +41,7 @@ properties: - qcom,sdm845-smmu-500 - qcom,sdx55-smmu-500 - qcom,sdx65-smmu-500 + - qcom,sm6115-smmu-500 - qcom,sm6350-smmu-500 - qcom,sm6375-smmu-500 - qcom,sm8150-smmu-500 From patchwork Sun Oct 30 09:42:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Iskren Chernev X-Patchwork-Id: 13025043 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 759A2FA3740 for ; Sun, 30 Oct 2022 09:43:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230083AbiJ3Jnj (ORCPT ); Sun, 30 Oct 2022 05:43:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41478 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229996AbiJ3JnV (ORCPT ); Sun, 30 Oct 2022 05:43:21 -0400 Received: from mail-wm1-x332.google.com (mail-wm1-x332.google.com [IPv6:2a00:1450:4864:20::332]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3C007CE39; Sun, 30 Oct 2022 02:43:20 -0700 (PDT) Received: by mail-wm1-x332.google.com with SMTP id l32so5609205wms.2; Sun, 30 Oct 2022 02:43:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=g/VLR/q0mJpm1g0Mv+FaKiNU++ksU9JCwtcy+gU033k=; b=kz4BtlExlvZie5t39yqkV7DvNLu31S3E9vbQEZv+uNOaMKpiL2NugTxhtRkjmiGeM3 OuYEV2diE//sUBC3GBZfdoqqK78he3cFaVvmre4Ix30d6hS6pA+lEuuL1d9JdtnjqehU T2AiKY3akNxn24eTwzG5ZUPux2VDa0ys5+BFI0lIa3FIbtTDBhHYdg5HRCEC1ZAy3SKx Z2O092dnZVg9V0SFPb1iNSeBFnkVDoIGRFSIhk4CCB7wASYlw4UX4ekjiMlxHwGAx5LJ 0XD/iqoA0duiD7fPbmgv8mwM4F1RElzKm5V+/4YFxQRQX8sQ6k7eZfCEgReRKz1uRmeX /k8Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=g/VLR/q0mJpm1g0Mv+FaKiNU++ksU9JCwtcy+gU033k=; b=ZonCooIg1WIsdstkh4cYkk4Yeo45voUc6SxRQTtPG5P7AyaC37STaD+P0//5BLqaCJ aFlq9jNpkEOBQHYv5Ue0Dv7Lm4iNjWn1hTemyT5X7SEtocZAbHRd9U17DD9oPFCHAPe9 J+HSqNWRWyizUc6aEHoTYMKdHs+ukJ1LQeXDS8JUBZAIvMA12o9/bDxjg4aNb3Q0TgKb wqdVqCmui6uZFyFCJyjyy4sLmcGrTjclPIPidGcLbuZ8H/c8Jmnw5ufclSzA0eUJ3gJb Y8GCbntgD3cZdJ6L/hHFpslhMcIxFRn9oAkDBINXCuRfeQMuXGiaAJrpSfV9i+kgfqFW ZU6g== X-Gm-Message-State: ACrzQf0DuR3vHzbIs3dWLob4c4Kfd16+ooa5K/2vh1yI4dQ0NFzHBcVk SrP/msTKUAyQuoT5wtWgfaI= X-Google-Smtp-Source: AMsMyM5WjDIC4d7iLHlIggwJ4nnImN8lrJOG27Gx0B7OH+u8AcgoXXAis/9grLtUtsFZpfKiKvhTHg== X-Received: by 2002:a05:600c:4252:b0:3cf:678a:d189 with SMTP id r18-20020a05600c425200b003cf678ad189mr3572561wmm.51.1667122998733; Sun, 30 Oct 2022 02:43:18 -0700 (PDT) Received: from localhost ([77.78.20.135]) by smtp.gmail.com with ESMTPSA id a17-20020a05600c349100b003b47ff307e1sm3925965wmq.31.2022.10.30.02.43.16 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 30 Oct 2022 02:43:17 -0700 (PDT) From: Iskren Chernev To: Krzysztof Kozlowski , Bjorn Andersson , Rob Herring Cc: phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Adam Skladowski , Iskren Chernev , Will Deacon , Robin Murphy , Joerg Roedel , Konrad Dybcio , Sai Prakash Ranjan , Emma Anholt , Rob Clark , linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH v5 5/8] iommu/arm-smmu-qcom: Add SM6115 support Date: Sun, 30 Oct 2022 11:42:55 +0200 Message-Id: <20221030094258.486428-6-iskren.chernev@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221030094258.486428-1-iskren.chernev@gmail.com> References: <20221030094258.486428-1-iskren.chernev@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Adam Skladowski Add the Qualcomm SM6115 platform to the list of compatible, this target uses MMU500 for both APSS and GPU. Signed-off-by: Adam Skladowski Signed-off-by: Iskren Chernev --- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c index b2708de25ea3..526fec79b4fe 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -432,6 +432,7 @@ static const struct of_device_id __maybe_unused qcom_smmu_impl_of_match[] = { { .compatible = "qcom,sc8280xp-smmu-500" }, { .compatible = "qcom,sdm630-smmu-v2" }, { .compatible = "qcom,sdm845-smmu-500" }, + { .compatible = "qcom,sm6115-smmu-500" }, { .compatible = "qcom,sm6125-smmu-500" }, { .compatible = "qcom,sm6350-smmu-500" }, { .compatible = "qcom,sm6375-smmu-500" }, From patchwork Sun Oct 30 09:42:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Iskren Chernev X-Patchwork-Id: 13025044 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 58B54C38A02 for ; Sun, 30 Oct 2022 09:44:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230115AbiJ3Jnz (ORCPT ); Sun, 30 Oct 2022 05:43:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41746 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230020AbiJ3Jnc (ORCPT ); Sun, 30 Oct 2022 05:43:32 -0400 Received: from mail-wm1-x329.google.com (mail-wm1-x329.google.com [IPv6:2a00:1450:4864:20::329]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B7583D128; Sun, 30 Oct 2022 02:43:24 -0700 (PDT) Received: by mail-wm1-x329.google.com with SMTP id v130-20020a1cac88000000b003bcde03bd44so9088507wme.5; Sun, 30 Oct 2022 02:43:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=QKLnyS1dI/VsC5RjU6rtIktExiExbn9qlM4kF/V4ru8=; b=imswqNBk7/ppbSvhOXm9lkvmZOiW58fdVDm3s9RBMTq2G+ZHknGO3uufh7PALfcEVf qcCw+Dyza1AXK0bawgxqOxqzXKS5B43e6BesgyP5k1zSsQbd2sPyGvkx5i3Gyw28vIk9 dNZmUjnwhpHdrqchBh2ln6I4ma5PFwBPcYkZ9n/RhYlDKSz0CPmWarlXtZSKvmdxWtrl U8euep+V9TfQfpKSU3lEUO+OWcZmGDFWW+p4FQT/BNRI8eN1iSSOF3MVKj/BizRw8BD7 QgpCZrIQfnmbnsBx4vGKpW5Q6Xwzqsk96QyfG0Mldl0LC6tF4U4/ors9vSBijLz99mIk ajiA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QKLnyS1dI/VsC5RjU6rtIktExiExbn9qlM4kF/V4ru8=; b=VtnyU4E/pEbDS3JVZRZUW2NyYjC59+3DnB2uhN0HvM4csLAPjEpu7IEWjQJwx93txh 1BFClPROwElc17n/ALSj9z2xgQ3N3BcVkGFmZKTv+N3kEYO8dSJyz0YN/+ZrAMV1joK8 aozyNbO8Nnnx3eG9BUd5w/ClsnqVEXToG6++zy8vntBTxQYM4bb7+b4H9VcDwmVeZkJo DlOxMwfdCrARo+TdY1sC52R5sbJ//WdFqgVZzqRohLHF+gFGwfSSPthghKI2FqvWhT/M XA6gm/tLNpNnBML0nlu0WL8OJZYSqWuKySmKCJBBiB1cwqbbeiLCQ2zoKkrCS/wWE82r ivew== X-Gm-Message-State: ACrzQf2b7Wwil7dih9NXo8w2U2EiGZt23fzm7dt1bPae46pjjsDNRlXB u4BGk875mxYLI7c1Gpfgxr8= X-Google-Smtp-Source: AMsMyM7xKY50gq51AwQGooCmzb92oqhjWfoqtpJzjWJpuBNE0o4ojWB2Sp43spzNn4HuLN/GV8Zjmg== X-Received: by 2002:a05:600c:231a:b0:3cf:69d4:72d6 with SMTP id 26-20020a05600c231a00b003cf69d472d6mr2708556wmo.32.1667123002926; Sun, 30 Oct 2022 02:43:22 -0700 (PDT) Received: from localhost ([77.78.20.135]) by smtp.gmail.com with ESMTPSA id h5-20020adff185000000b00236863c02f5sm3670568wro.96.2022.10.30.02.43.21 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 30 Oct 2022 02:43:22 -0700 (PDT) From: Iskren Chernev To: Krzysztof Kozlowski , Bjorn Andersson , Rob Herring Cc: phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Iskren Chernev , Andy Gross , Konrad Dybcio , Krzysztof Kozlowski , linux-kernel@vger.kernel.org Subject: [PATCH v5 6/8] arm64: dts: qcom: sm6115: Add basic soc dtsi Date: Sun, 30 Oct 2022 11:42:56 +0200 Message-Id: <20221030094258.486428-7-iskren.chernev@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221030094258.486428-1-iskren.chernev@gmail.com> References: <20221030094258.486428-1-iskren.chernev@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add support for Qualcomm SM6115 SoC. This includes: - GCC - Pinctrl - RPM (CC+PD) - USB - MMC - UFS Signed-off-by: Iskren Chernev Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm6115.dtsi | 854 +++++++++++++++++++++++++++ 1 file changed, 854 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sm6115.dtsi diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi new file mode 100644 index 000000000000..0340ed21be05 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -0,0 +1,854 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (c) 2021, Iskren Chernev + */ + +#include +#include +#include +#include +#include + +/ { + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + + chosen { }; + + clocks { + xo_board: xo-board { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "qcom,kryo260"; + reg = <0x0 0x0>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + L2_0: l2-cache { + compatible = "cache"; + cache-level = <2>; + }; + }; + + CPU1: cpu@1 { + device_type = "cpu"; + compatible = "qcom,kryo260"; + reg = <0x0 0x1>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + + CPU2: cpu@2 { + device_type = "cpu"; + compatible = "qcom,kryo260"; + reg = <0x0 0x2>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + + CPU3: cpu@3 { + device_type = "cpu"; + compatible = "qcom,kryo260"; + reg = <0x0 0x3>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + + CPU4: cpu@100 { + device_type = "cpu"; + compatible = "qcom,kryo260"; + reg = <0x0 0x100>; + enable-method = "psci"; + capacity-dmips-mhz = <1638>; + dynamic-power-coefficient = <282>; + next-level-cache = <&L2_1>; + L2_1: l2-cache { + compatible = "cache"; + cache-level = <2>; + }; + }; + + CPU5: cpu@101 { + device_type = "cpu"; + compatible = "qcom,kryo260"; + reg = <0x0 0x101>; + capacity-dmips-mhz = <1638>; + dynamic-power-coefficient = <282>; + enable-method = "psci"; + next-level-cache = <&L2_1>; + }; + + CPU6: cpu@102 { + device_type = "cpu"; + compatible = "qcom,kryo260"; + reg = <0x0 0x102>; + capacity-dmips-mhz = <1638>; + dynamic-power-coefficient = <282>; + enable-method = "psci"; + next-level-cache = <&L2_1>; + }; + + CPU7: cpu@103 { + device_type = "cpu"; + compatible = "qcom,kryo260"; + reg = <0x0 0x103>; + capacity-dmips-mhz = <1638>; + dynamic-power-coefficient = <282>; + enable-method = "psci"; + next-level-cache = <&L2_1>; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + }; + + cluster1 { + core0 { + cpu = <&CPU4>; + }; + + core1 { + cpu = <&CPU5>; + }; + + core2 { + cpu = <&CPU6>; + }; + + core3 { + cpu = <&CPU7>; + }; + }; + }; + }; + + firmware { + scm: scm { + compatible = "qcom,scm-sm6115", "qcom,scm"; + #reset-cells = <1>; + }; + }; + + memory@80000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the size */ + reg = <0 0x80000000 0 0>; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = ; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + hyp_mem: memory@45700000 { + reg = <0x0 0x45700000 0x0 0x600000>; + no-map; + }; + + xbl_aop_mem: memory@45e00000 { + reg = <0x0 0x45e00000 0x0 0x140000>; + no-map; + }; + + sec_apps_mem: memory@45fff000 { + reg = <0x0 0x45fff000 0x0 0x1000>; + no-map; + }; + + smem_mem: memory@46000000 { + compatible = "qcom,smem"; + reg = <0x0 0x46000000 0x0 0x200000>; + no-map; + + hwlocks = <&tcsr_mutex 3>; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + }; + + cdsp_sec_mem: memory@46200000 { + reg = <0x0 0x46200000 0x0 0x1e00000>; + no-map; + }; + + pil_modem_mem: memory@4ab00000 { + reg = <0x0 0x4ab00000 0x0 0x6900000>; + no-map; + }; + + pil_video_mem: memory@51400000 { + reg = <0x0 0x51400000 0x0 0x500000>; + no-map; + }; + + wlan_msa_mem: memory@51900000 { + reg = <0x0 0x51900000 0x0 0x100000>; + no-map; + }; + + pil_cdsp_mem: memory@51a00000 { + reg = <0x0 0x51a00000 0x0 0x1e00000>; + no-map; + }; + + pil_adsp_mem: memory@53800000 { + reg = <0x0 0x53800000 0x0 0x2800000>; + no-map; + }; + + pil_ipa_fw_mem: memory@56100000 { + reg = <0x0 0x56100000 0x0 0x10000>; + no-map; + }; + + pil_ipa_gsi_mem: memory@56110000 { + reg = <0x0 0x56110000 0x0 0x5000>; + no-map; + }; + + pil_gpu_mem: memory@56115000 { + reg = <0x0 0x56115000 0x0 0x2000>; + no-map; + }; + + cont_splash_memory: memory@5c000000 { + reg = <0x0 0x5c000000 0x0 0x00f00000>; + no-map; + }; + + dfps_data_memory: memory@5cf00000 { + reg = <0x0 0x5cf00000 0x0 0x0100000>; + no-map; + }; + + removed_mem: memory@60000000 { + reg = <0x0 0x60000000 0x0 0x3900000>; + no-map; + }; + }; + + rpm-glink { + compatible = "qcom,glink-rpm"; + + interrupts = ; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + mboxes = <&apcs_glb 0>; + + rpm_requests: rpm-requests { + compatible = "qcom,rpm-sm6115"; + qcom,glink-channels = "rpm_requests"; + + rpmcc: clock-controller { + compatible = "qcom,rpmcc-sm6115", "qcom,rpmcc"; + #clock-cells = <1>; + }; + + rpmpd: power-controller { + compatible = "qcom,sm6115-rpmpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmpd_opp_table>; + + rpmpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmpd_opp_min_svs: opp1 { + opp-level = ; + }; + + rpmpd_opp_low_svs: opp2 { + opp-level = ; + }; + + rpmpd_opp_svs: opp3 { + opp-level = ; + }; + + rpmpd_opp_svs_plus: opp4 { + opp-level = ; + }; + + rpmpd_opp_nom: opp5 { + opp-level = ; + }; + + rpmpd_opp_nom_plus: opp6 { + opp-level = ; + }; + + rpmpd_opp_turbo: opp7 { + opp-level = ; + }; + + rpmpd_opp_turbo_plus: opp8 { + opp-level = ; + }; + }; + }; + }; + }; + + soc: soc@0 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + + tcsr_mutex: hwlock@340000 { + compatible = "qcom,tcsr-mutex"; + reg = <0x00340000 0x20000>; + #hwlock-cells = <1>; + }; + + tlmm: pinctrl@500000 { + compatible = "qcom,sm6115-tlmm"; + reg = <0x00500000 0x400000>, <0x00900000 0x400000>, <0x00d00000 0x400000>; + reg-names = "west", "south", "east"; + interrupts = ; + gpio-controller; + gpio-ranges = <&tlmm 0 0 121>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + + sdc1_state_on: sdc1-on-state { + clk-pins { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <16>; + }; + + cmd-pins { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + data-pins { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <10>; + }; + + rclk-pins { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc1_state_off: sdc1-off-state { + clk-pins { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <2>; + }; + + cmd-pins { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + data-pins { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <2>; + }; + + rclk-pins { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc2_state_on: sdc2-on-state { + clk-pins { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <16>; + }; + + cmd-pins { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + data-pins { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <10>; + }; + + sd-cd-pins { + pins = "gpio88"; + function = "gpio"; + bias-pull-up; + drive-strength = <2>; + }; + }; + + sdc2_state_off: sdc2-off-state { + clk-pins { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <2>; + }; + + cmd-pins { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + data-pins { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <2>; + }; + + sd-cd-pins { + pins = "gpio88"; + function = "gpio"; + bias-disable; + drive-strength = <2>; + }; + }; + }; + + gcc: clock-controller@1400000 { + compatible = "qcom,gcc-sm6115"; + reg = <0x01400000 0x1f0000>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>; + clock-names = "bi_tcxo", "sleep_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + usb_1_hsphy: phy@1613000 { + compatible = "qcom,sm6115-qusb2-phy"; + reg = <0x01613000 0x180>; + #phy-cells = <0>; + + clocks = <&gcc GCC_AHB2PHY_USB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "cfg_ahb", "ref"; + + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + nvmem-cells = <&qusb2_hstx_trim>; + + status = "disabled"; + }; + + qfprom@1b40000 { + compatible = "qcom,sm6115-qfprom", "qcom,qfprom"; + reg = <0x01b40000 0x7000>; + #address-cells = <1>; + #size-cells = <1>; + + qusb2_hstx_trim: hstx-trim@25b { + reg = <0x25b 0x1>; + bits = <1 4>; + }; + }; + + spmi_bus: spmi@1c40000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0x01c40000 0x1100>, + <0x01e00000 0x2000000>, + <0x03e00000 0x100000>, + <0x03f00000 0xa0000>, + <0x01c0a000 0x26000>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupt-names = "periph_irq"; + interrupts = ; + qcom,ee = <0>; + qcom,channel = <0>; + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + }; + + rpm_msg_ram: sram@45f0000 { + compatible = "qcom,rpm-msg-ram"; + reg = <0x045f0000 0x7000>; + }; + + sdhc_1: mmc@4744000 { + compatible = "qcom,sm6115-sdhci", "qcom,sdhci-msm-v5"; + reg = <0x04744000 0x1000>, <0x04745000 0x1000>, <0x04748000 0x8000>; + reg-names = "hc", "cqhci", "ice"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, + <&xo_board>, + <&gcc GCC_SDCC1_ICE_CORE_CLK>; + clock-names = "iface", "core", "xo", "ice"; + + pinctrl-0 = <&sdc1_state_on>; + pinctrl-1 = <&sdc1_state_off>; + pinctrl-names = "default", "sleep"; + + bus-width = <8>; + status = "disabled"; + }; + + sdhc_2: mmc@4784000 { + compatible = "qcom,sm6115-sdhci", "qcom,sdhci-msm-v5"; + reg = <0x04784000 0x1000>; + reg-names = "hc"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC2_AHB_CLK>, <&gcc GCC_SDCC2_APPS_CLK>, <&xo_board>; + clock-names = "iface", "core", "xo"; + + pinctrl-0 = <&sdc2_state_on>; + pinctrl-1 = <&sdc2_state_off>; + pinctrl-names = "default", "sleep"; + + power-domains = <&rpmpd SM6115_VDDCX>; + operating-points-v2 = <&sdhc2_opp_table>; + iommus = <&apps_smmu 0x00a0 0x0>; + resets = <&gcc GCC_SDCC2_BCR>; + + bus-width = <4>; + qcom,dll-config = <0x0007642c>; + qcom,ddr-config = <0x80040868>; + status = "disabled"; + + sdhc2_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmpd_opp_low_svs>; + }; + + opp-202000000 { + opp-hz = /bits/ 64 <202000000>; + required-opps = <&rpmpd_opp_nom>; + }; + }; + }; + + ufs_mem_hc: ufs@4804000 { + compatible = "qcom,sm6115-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; + reg = <0x04804000 0x3000>, <0x04810000 0x8000>; + interrupts = ; + phys = <&ufs_mem_phy_lanes>; + phy-names = "ufsphy"; + lanes-per-direction = <1>; + #reset-cells = <1>; + resets = <&gcc GCC_UFS_PHY_BCR>; + reset-names = "rst"; + + power-domains = <&gcc GCC_UFS_PHY_GDSC>; + iommus = <&apps_smmu 0x100 0>; + + clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_SYS_NOC_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + clock-names = "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "ice_core_clk"; + + freq-table-hz = <50000000 200000000>, + <0 0>, + <0 0>, + <37500000 150000000>, + <75000000 300000000>, + <0 0>, + <0 0>, + <0 0>; + + status = "disabled"; + }; + + ufs_mem_phy: phy@4807000 { + compatible = "qcom,sm6115-qmp-ufs-phy"; + reg = <0x04807000 0x1c4>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clocks = <&gcc GCC_UFS_CLKREF_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; + clock-names = "ref", "ref_aux"; + + resets = <&ufs_mem_hc 0>; + reset-names = "ufsphy"; + status = "disabled"; + + ufs_mem_phy_lanes: phy@4807400 { + reg = <0x4807400 0x098>, + <0x4807600 0x130>, + <0x4807c00 0x16c>; + #phy-cells = <0>; + }; + }; + + usb_1: usb@4ef8800 { + compatible = "qcom,sm6115-dwc3", "qcom,dwc3"; + reg = <0x04ef8800 0x400>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB3_PRIM_CLKREF_CLK>; + clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", "xo"; + + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>; + assigned-clock-rates = <19200000>, <66666667>; + + interrupts = , + ; + interrupt-names = "hs_phy_irq", "ss_phy_irq"; + + resets = <&gcc GCC_USB30_PRIM_BCR>; + power-domains = <&gcc GCC_USB30_PRIM_GDSC>; + qcom,select-utmi-as-pipe-clk; + status = "disabled"; + + usb_1_dwc3: usb@4e00000 { + compatible = "snps,dwc3"; + reg = <0x04e00000 0xcd00>; + interrupts = ; + phys = <&usb_1_hsphy>; + phy-names = "usb2-phy"; + iommus = <&apps_smmu 0x120 0x0>; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x10>; + snps,usb3_lpm_capable; + maximum-speed = "high-speed"; + dr_mode = "peripheral"; + }; + }; + + apps_smmu: iommu@c600000 { + compatible = "qcom,sm6115-smmu-500", "arm,mmu-500"; + reg = <0x0c600000 0x80000>; + #iommu-cells = <2>; + #global-interrupts = <1>; + + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + apcs_glb: mailbox@f111000 { + compatible = "qcom,sm6115-apcs-hmss-global"; + reg = <0x0f111000 0x1000>; + + #mbox-cells = <1>; + }; + + timer@f120000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x0f120000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clock-frequency = <19200000>; + + frame@f121000 { + reg = <0x0f121000 0x1000>, <0x0f122000 0x1000>; + frame-number = <0>; + interrupts = , + ; + }; + + frame@f123000 { + reg = <0x0f123000 0x1000>; + frame-number = <1>; + interrupts = ; + status = "disabled"; + }; + + frame@f124000 { + reg = <0x0f124000 0x1000>; + frame-number = <2>; + interrupts = ; + status = "disabled"; + }; + + frame@f125000 { + reg = <0x0f125000 0x1000>; + frame-number = <3>; + interrupts = ; + status = "disabled"; + }; + + frame@f126000 { + reg = <0x0f126000 0x1000>; + frame-number = <4>; + interrupts = ; + status = "disabled"; + }; + + frame@f127000 { + reg = <0x0f127000 0x1000>; + frame-number = <5>; + interrupts = ; + status = "disabled"; + }; + + frame@f128000 { + reg = <0x0f128000 0x1000>; + frame-number = <6>; + interrupts = ; + status = "disabled"; + }; + }; + + intc: interrupt-controller@f200000 { + compatible = "arm,gic-v3"; + reg = <0x0f200000 0x10000>, <0x0f300000 0x100000>; + #interrupt-cells = <3>; + interrupt-controller; + interrupt-parent = <&intc>; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x20000>; + interrupts = ; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; +}; From patchwork Sun Oct 30 09:42:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Iskren Chernev X-Patchwork-Id: 13025045 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6E9BAFA3740 for ; Sun, 30 Oct 2022 09:44:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230020AbiJ3JoF (ORCPT ); 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Sun, 30 Oct 2022 02:43:26 -0700 (PDT) From: Iskren Chernev To: Krzysztof Kozlowski , Bjorn Andersson , Rob Herring Cc: phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Iskren Chernev , Andy Gross , Konrad Dybcio , Krzysztof Kozlowski , linux-kernel@vger.kernel.org Subject: [PATCH v5 7/8] arm64: dts: qcom: sm4250: Add soc dtsi Date: Sun, 30 Oct 2022 11:42:57 +0200 Message-Id: <20221030094258.486428-8-iskren.chernev@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221030094258.486428-1-iskren.chernev@gmail.com> References: <20221030094258.486428-1-iskren.chernev@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The SM4250 is a downclocked version of the SM6115. Signed-off-by: Iskren Chernev Reviewed-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm4250.dtsi | 38 ++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sm4250.dtsi diff --git a/arch/arm64/boot/dts/qcom/sm4250.dtsi b/arch/arm64/boot/dts/qcom/sm4250.dtsi new file mode 100644 index 000000000000..c5add8f44fc0 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm4250.dtsi @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (c) 2021, Iskren Chernev + */ + +#include "sm6115.dtsi" + +&CPU0 { + compatible = "qcom,kryo240"; +}; + +&CPU1 { + compatible = "qcom,kryo240"; +}; + +&CPU2 { + compatible = "qcom,kryo240"; +}; + +&CPU3 { + compatible = "qcom,kryo240"; +}; + +&CPU4 { + compatible = "qcom,kryo240"; +}; + +&CPU5 { + compatible = "qcom,kryo240"; +}; + +&CPU6 { + compatible = "qcom,kryo240"; +}; + +&CPU7 { + compatible = "qcom,kryo240"; +}; From patchwork Sun Oct 30 09:42:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Iskren Chernev X-Patchwork-Id: 13025046 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A281CC38A02 for ; Sun, 30 Oct 2022 09:44:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230045AbiJ3JoJ (ORCPT ); Sun, 30 Oct 2022 05:44:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41230 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230062AbiJ3Jng (ORCPT ); Sun, 30 Oct 2022 05:43:36 -0400 Received: from mail-wm1-x336.google.com (mail-wm1-x336.google.com [IPv6:2a00:1450:4864:20::336]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7485DD2CC; Sun, 30 Oct 2022 02:43:32 -0700 (PDT) Received: by mail-wm1-x336.google.com with SMTP id l16-20020a05600c4f1000b003c6c0d2a445so6386664wmq.4; Sun, 30 Oct 2022 02:43:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=wGW3s7VAfdS0LxK3XABjCKqjaFAM6/EYoTFRFX90Zzg=; b=U+dZIB5Rf38yZpmjdy33P2ObW6lqtr2ScbAKSESDDwvyyQkoaA0+lAqlaEzDGaXDUG jA/sa3jRmVNuk8Wru2pbM/NAF6v8rAWRr9iI+YkS/3bNUn9E9m563DglnPVD4SKxpe7s +XGNtc5doQf/I2ejg3wcDNmlgrYlcXjKZKlp9rctGd3kA9KXdM6Lz8ILcJMJ/mL7DjMi aLLsDaFeMmDOLOWNKqyXJPaV8ByYG4/sMmC5PAUXdcqeVMjH+hMtLvS2Xre9oFiDd61h wOaL2R2pCi67yII8mgyqOQQqgM6BJPZ4n6nKnJCX/SzIqqAwoPPSMtZ+PTdEg4LmB5jj 3tsQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wGW3s7VAfdS0LxK3XABjCKqjaFAM6/EYoTFRFX90Zzg=; b=MdvRgq8w+Sd3ZZI3W9cM1mnPxyWdBQawb4EP8c8zXlp7bUntXPVBjpMerEfgODOz1a FFRL2LcSdeBPDZnRkHOjyYaAzbggnX+c/ppFE3EP07VJsCstUa90bhHvTt5wrLv73/lp qaYr1f4cy5r0zGObO/5gjF9QQuGUXDQSyk5boQjrPGqS/sYkKwA3n1GuPgYnhVB/Q8oH eqfKch92LLX8wQKJn5QkUG5TsVDHjPyLx1QI/vG6d/ehL0i5gqug0JCUZ+uWOFbSnFoO me8xDIIWd2oCE2dVNCuCFgYNkIfO1MKbQVLD6LojsAgADk+hOunC/lVRjqmOaStG1Z89 6S4g== X-Gm-Message-State: ACrzQf2KFHY0ljM3esbtRaJkd9JoSMktgvadRo6FWs29i8HkcyUYnhxo mWHV+OUx4myAb0rdCMfrVDU= X-Google-Smtp-Source: AMsMyM63jZ4gtRX0nXL5wOtj0PyiWp4s9Kby1XaTjqhRKKShlq//0+nNflxruEZG4/lZZBOKTEWQrQ== X-Received: by 2002:a05:600c:3585:b0:3c7:9f:5f87 with SMTP id p5-20020a05600c358500b003c7009f5f87mr15284457wmq.76.1667123010972; Sun, 30 Oct 2022 02:43:30 -0700 (PDT) Received: from localhost ([77.78.20.135]) by smtp.gmail.com with ESMTPSA id k36-20020a05600c1ca400b003b47b80cec3sm3805282wms.42.2022.10.30.02.43.29 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 30 Oct 2022 02:43:30 -0700 (PDT) From: Iskren Chernev To: Krzysztof Kozlowski , Bjorn Andersson , Rob Herring Cc: phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Iskren Chernev , Andy Gross , Konrad Dybcio , Krzysztof Kozlowski , Kees Cook , Tony Luck , "Guilherme G. Piccoli" , linux-kernel@vger.kernel.org, linux-hardening@vger.kernel.org Subject: [PATCH v5 8/8] arm64: dts: qcom: sm4250: Add support for oneplus-billie2 Date: Sun, 30 Oct 2022 11:42:58 +0200 Message-Id: <20221030094258.486428-9-iskren.chernev@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221030094258.486428-1-iskren.chernev@gmail.com> References: <20221030094258.486428-1-iskren.chernev@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add initial support for OnePlus Nord N100, based on SM4250. Currently working: - boots - usb - built-in flash storage (UFS) - SD card reader Signed-off-by: Iskren Chernev Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../boot/dts/qcom/sm4250-oneplus-billie2.dts | 241 ++++++++++++++++++ 2 files changed, 242 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index b0558d3389e5..eb2a58b8af5f 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -142,6 +142,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm845-xiaomi-polaris.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-shift-axolotl.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm850-lenovo-yoga-c630.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm850-samsung-w737.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm4250-oneplus-billie2.dtb dtb-$(CONFIG_ARCH_QCOM) += sm6125-sony-xperia-seine-pdx201.dtb dtb-$(CONFIG_ARCH_QCOM) += sm6350-sony-xperia-lena-pdx213.dtb dtb-$(CONFIG_ARCH_QCOM) += sm7225-fairphone-fp4.dtb diff --git a/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts b/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts new file mode 100644 index 000000000000..a3f1c7c41fd7 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts @@ -0,0 +1,241 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (c) 2021, Iskren Chernev + */ + +/dts-v1/; + +#include "sm4250.dtsi" + +/ { + model = "OnePlus Nord N100"; + compatible = "oneplus,billie2", "qcom,sm4250"; + + /* required for bootloader to select correct board */ + qcom,msm-id = <0x1a1 0x10000 0x1bc 0x10000>; + qcom,board-id = <0x1000b 0x00>; + + aliases { + }; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + stdout-path = "framebuffer0"; + + framebuffer0: framebuffer@9d400000 { + compatible = "simple-framebuffer"; + reg = <0 0x5c000000 0 (1600 * 720 * 4)>; + width = <720>; + height = <1600>; + stride = <(720 * 4)>; + format = "a8r8g8b8"; + }; + }; +}; + +&reserved_memory { + bootloader_log_mem: memory@5fff7000 { + reg = <0x0 0x5fff7000 0x0 0x8000>; + no-map; + }; + + ramoops@cbe00000 { + compatible = "ramoops"; + reg = <0x0 0xcbe00000 0x0 0x400000>; + record-size = <0x40000>; + pmsg-size = <0x200000>; + console-size = <0x40000>; + ftrace-size = <0x40000>; + }; + + param_mem: memory@cc200000 { + reg = <0x0 0xcc200000 0x0 0x100000>; + no-map; + }; + + mtp_mem: memory@cc300000 { + reg = <0x00 0xcc300000 0x00 0xb00000>; + no-map; + }; +}; + +&rpm_requests { + regulators-0 { + compatible = "qcom,rpm-pm6125-regulators"; + + vreg_s6a: s6 { + regulator-min-microvolt = <320000>; + regulator-max-microvolt = <1456000>; + }; + + vreg_s7a: s7 { + regulator-min-microvolt = <1280000>; + regulator-max-microvolt = <2040000>; + }; + + vreg_s8a: s8 { + regulator-min-microvolt = <1064000>; + regulator-max-microvolt = <1304000>; + }; + + vreg_l1a: l1 { + regulator-min-microvolt = <952000>; + regulator-max-microvolt = <1152000>; + }; + + vreg_l4a: l4 { + regulator-min-microvolt = <488000>; + regulator-max-microvolt = <1000000>; + }; + + vreg_l5a: l5 { + regulator-min-microvolt = <1648000>; + regulator-max-microvolt = <3056000>; + }; + + vreg_l6a: l6 { + regulator-min-microvolt = <576000>; + regulator-max-microvolt = <656000>; + }; + + vreg_l7a: l7 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1304000>; + }; + + vreg_l8a: l8 { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <728000>; + }; + + vreg_l9a: l9 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2000000>; + }; + + vreg_l10a: l10 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <1904000>; + }; + + vreg_l11a: l11 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <1952000>; + }; + + vreg_l12a: l12 { + regulator-min-microvolt = <1624000>; + regulator-max-microvolt = <1984000>; + }; + + vreg_l13a: l13 { + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <1952000>; + }; + + vreg_l14a: l14 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <1904000>; + }; + + vreg_l15a: l15 { + regulator-min-microvolt = <2920000>; + regulator-max-microvolt = <3232000>; + }; + + vreg_l16a: l16 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <1904000>; + }; + + vreg_l17a: l17 { + regulator-min-microvolt = <1152000>; + regulator-max-microvolt = <1304000>; + }; + + vreg_l18a: l18 { + regulator-min-microvolt = <1104000>; + regulator-max-microvolt = <1304000>; + }; + + vreg_l19a: l19 { + regulator-min-microvolt = <1624000>; + regulator-max-microvolt = <3304000>; + }; + + vreg_l20a: l20 { + regulator-min-microvolt = <1624000>; + regulator-max-microvolt = <3304000>; + }; + + vreg_l21a: l21 { + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <3544000>; + }; + + vreg_l22a: l22 { + regulator-min-microvolt = <2952000>; + regulator-max-microvolt = <3304000>; + }; + + vreg_l23a: l23 { + regulator-min-microvolt = <3296000>; + regulator-max-microvolt = <3304000>; + }; + + vreg_l24a: l24 { + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <3544000>; + }; + }; +}; + +&sleep_clk { + clock-frequency = <32764>; +}; + +&sdhc_2 { + vmmc-supply = <&vreg_l22a>; + vqmmc-supply = <&vreg_l5a>; + + cd-gpios = <&tlmm 88 GPIO_ACTIVE_HIGH>; + + status = "okay"; +}; + +&tlmm { + gpio-reserved-ranges = <14 4>; +}; + +&ufs_mem_hc { + vcc-supply = <&vreg_l24a>; + vcc-max-microamp = <600000>; + vccq2-supply = <&vreg_l11a>; + vccq2-max-microamp = <600000>; + status = "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply = <&vreg_l4a>; + vdda-pll-supply = <&vreg_l12a>; + vddp-ref-clk-supply = <&vreg_l18a>; + status = "okay"; +}; + +&usb_1 { + status = "okay"; +}; + +&usb_1_hsphy { + vdd-supply = <&vreg_l4a>; + vdda-pll-supply = <&vreg_l12a>; + vdda-phy-dpdm-supply = <&vreg_l15a>; + status = "okay"; +}; + +&xo_board { + clock-frequency = <19200000>; +};