From patchwork Mon Oct 31 05:10:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Dixit, Ashutosh" X-Patchwork-Id: 13025377 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6A7F5C38A02 for ; Mon, 31 Oct 2022 05:11:15 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 97A7B10E101; Mon, 31 Oct 2022 05:11:04 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0B11F10E0F8; Mon, 31 Oct 2022 05:10:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1667193058; x=1698729058; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=J/RX3CIISXh4uRtVCwaoTBXy012CI0jVtOzkItQhTjM=; b=Sa3i8w8171WPSTpvs4ThBMmCfeYNN1wWGp3UKz1ftw04WvcJVUmJ3twe fCW0dBeMtB9EUnB9bTRO+jzAFzeZXHviCvx/NmlLmMNagtidb8Eao8+Lj 0FdOlsfsQeVfyyjI5yR9IXHyvn/Oot+GL7JKFEdEVxaaRy+fSt+Xo/BaB VUOXEt7JJCC1inlZ7qSKour50qYyx55JuULPzc6VlHz56y0J+YVFGx9vl h65h4C18OMZPKhRhOdmMZVfYu4k8zj32kVMAOoeS/Oj2zkn1APqAqFilA 2B/HrKb49Gr2JjJaJlNOMgywGO6Cwb6V+OZA0EWxwfC34PMlLMHmYXWzy A==; X-IronPort-AV: E=McAfee;i="6500,9779,10516"; a="395134224" X-IronPort-AV: E=Sophos;i="5.95,227,1661842800"; d="scan'208";a="395134224" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Oct 2022 22:10:57 -0700 X-IronPort-AV: E=McAfee;i="6500,9779,10516"; a="635922323" X-IronPort-AV: E=Sophos;i="5.95,227,1661842800"; d="scan'208";a="635922323" Received: from orsosgc001.jf.intel.com (HELO unerlige-ril.jf.intel.com) ([10.165.21.138]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Oct 2022 22:10:56 -0700 From: Ashutosh Dixit To: intel-gfx@lists.freedesktop.org Date: Sun, 30 Oct 2022 22:10:51 -0700 Message-Id: <20221031051051.553812-1-ashutosh.dixit@intel.com> X-Mailer: git-send-email 2.38.0 MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH] drm/i915/hwmon: Don't use FIELD_PREP X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andi Shyti , llvm@lists.linux.dev, ndesaulniers@google.com, dri-devel@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" FIELD_PREP and REG_FIELD_PREP have checks requiring a compile time constant mask. When the mask comes in as the argument of a function these checks can can fail depending on the compiler (gcc vs clang), optimization level, etc. Use a simpler local version of FIELD_PREP which skips these checks. The checks are not needed because the mask is formed using REG_GENMASK (so is actually a compile time constant). Bug: https://gitlab.freedesktop.org/drm/intel/-/issues/7354 Signed-off-by: Ashutosh Dixit --- drivers/gpu/drm/i915/i915_hwmon.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_hwmon.c b/drivers/gpu/drm/i915/i915_hwmon.c index 9e97814930254..a3ec9a73a4e49 100644 --- a/drivers/gpu/drm/i915/i915_hwmon.c +++ b/drivers/gpu/drm/i915/i915_hwmon.c @@ -62,6 +62,12 @@ struct i915_hwmon { int scl_shift_time; }; +/* FIELD_PREP and REG_FIELD_PREP require a compile time constant mask */ +static u32 hwm_field_prep(u32 mask, u32 val) +{ + return (val << __bf_shf(mask)) & mask; +} + static void hwm_locked_with_pm_intel_uncore_rmw(struct hwm_drvdata *ddat, i915_reg_t reg, u32 clear, u32 set) @@ -112,7 +118,7 @@ hwm_field_scale_and_write(struct hwm_drvdata *ddat, i915_reg_t rgadr, nval = DIV_ROUND_CLOSEST_ULL((u64)lval << nshift, scale_factor); bits_to_clear = field_msk; - bits_to_set = FIELD_PREP(field_msk, nval); + bits_to_set = hwm_field_prep(field_msk, nval); hwm_locked_with_pm_intel_uncore_rmw(ddat, rgadr, bits_to_clear, bits_to_set);