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Mon, 31 Oct 2022 10:11:18 +0000 Received: from VI1PR0402MB3439.eurprd04.prod.outlook.com ([fe80::41c4:5b70:6fec:a963]) by VI1PR0402MB3439.eurprd04.prod.outlook.com ([fe80::41c4:5b70:6fec:a963%7]) with mapi id 15.20.5746.028; Mon, 31 Oct 2022 10:11:18 +0000 From: Chester Lin To: Alexandre Torgue , Giuseppe Cavallaro , Jose Abreu , Rob Herring , Krzysztof Kozlowski Cc: Chester Lin , netdev@vger.kernel.org, s32@nxp.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, =?utf-8?q?Andreas_F=C3=A4rber?= , Matthias Brugger , Jan Petrous Subject: [PATCH 1/5] dt-bindings: net: snps, dwmac: add NXP S32CC support Date: Mon, 31 Oct 2022 18:10:48 +0800 Message-Id: <20221031101052.14956-2-clin@suse.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221031101052.14956-1-clin@suse.com> References: <20221031101052.14956-1-clin@suse.com> X-ClientProxiedBy: TYAPR01CA0210.jpnprd01.prod.outlook.com (2603:1096:404:29::30) To VI1PR0402MB3439.eurprd04.prod.outlook.com (2603:10a6:803:4::13) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: VI1PR0402MB3439:EE_|VE1PR04MB7261:EE_ X-MS-Office365-Filtering-Correlation-Id: 4d94bfc9-5f4a-465f-24dc-08dabb28406d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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The maxItems of clock and clock-names need be increased because S32CC has up to 11 clocks for its DWMAC. Signed-off-by: Chester Lin --- Documentation/devicetree/bindings/net/snps,dwmac.yaml | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/net/snps,dwmac.yaml b/Documentation/devicetree/bindings/net/snps,dwmac.yaml index 13b984076af5..c174d173591e 100644 --- a/Documentation/devicetree/bindings/net/snps,dwmac.yaml +++ b/Documentation/devicetree/bindings/net/snps,dwmac.yaml @@ -65,6 +65,7 @@ properties: - ingenic,x2000-mac - loongson,ls2k-dwmac - loongson,ls7a-dwmac + - nxp,s32cc-dwmac - renesas,r9a06g032-gmac - renesas,rzn1-gmac - rockchip,px30-gmac @@ -110,7 +111,7 @@ properties: clocks: minItems: 1 - maxItems: 8 + maxItems: 11 additionalItems: true items: - description: GMAC main clock @@ -122,7 +123,7 @@ properties: clock-names: minItems: 1 - maxItems: 8 + maxItems: 11 additionalItems: true contains: enum: From patchwork Mon Oct 31 10:10:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chester Lin X-Patchwork-Id: 13025544 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 319D1FA3740 for ; Mon, 31 Oct 2022 10:11:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230386AbiJaKLl (ORCPT ); Mon, 31 Oct 2022 06:11:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35684 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230397AbiJaKLf (ORCPT ); Mon, 31 Oct 2022 06:11:35 -0400 Received: from EUR03-DBA-obe.outbound.protection.outlook.com (mail-dbaeur03on2087.outbound.protection.outlook.com [40.107.104.87]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A3EF2DF7A; Mon, 31 Oct 2022 03:11:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Qididk6yo9AiDPTB3pWZVYm9oRqsHj3o1mWOPx8XpWUC+4XHPEBDC10sVaX2j2GYO9vBrxe9hiIm6ZRlxCXu9DvW2ZmulGiexp7vcDeggb0jEzfhJkuRytoDeHSYc40LVOZ01ObpStlqbWXhSHfDCHE8P6FRWQ9uDtuR1JxS7d8wFHeaXXL4+tSIeFseKqWN5eebWXWcXd91hozOUnUcuu8PtfAaQlcx+3Ro4qjnQHUJMADdUevl4byYwel8sSFkmaFKqLcm94/eMxqR/JfanDHk0GvN95ELgRrr79/Row+iTuqSLBkwoqU81fqfClpyxsbNVI9rsvmh6ThiBQnXfw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=Zn2ro5pLzd/AgGErCLQjExxP3xd0AXsaLXFhRxpZhWE=; b=oPP8h/0p1zLxPzqKkAOu4hs13B1oXiJht44Ofvv7EcZSypNmP2yw6bNjkwxoIYubU4dpOG88HMyLGkjFQQLS8X9JgBMpUwQkGrjvaK5aaIqAiUtaVm3d7Fi/ug1znq8eoWI156R+w0RmQdeQ0A1CN2VCRJvYoI/limhhytraJqlPxCOhO0TOrTi5k19wbqTzPKA7Yr5CFRwmlfN5EiZj6Mj3TzSUtexN8T0FAOp6SOgWVq46FVF8M9GK9t981AH87ymg/EZ6TUgmGzoerr7qmVtSl1kD6SdHOxPbC3KYxDHHZ1gqTjfnEvCOktJ15LJOiPN+60tKI3LSe1igKYHPcw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=suse.com; dmarc=pass action=none header.from=suse.com; dkim=pass header.d=suse.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=Zn2ro5pLzd/AgGErCLQjExxP3xd0AXsaLXFhRxpZhWE=; b=mcC9BPoEdKLfpDn/qipYEwwDK3p0EULJw2/CjDF60JiXPysMKaMHGv8tp90I7RZa5tTenMn/XBbEns4Ngfd1NqEBbHyI33ATRtoF5llgKwPdl8IKDnYcUnGIQUmXqvBpXO9rvdeHftSeQd/LMUWKn2LbAd0C1Zu+7DyTkqZqYz7aRSg5OwTz8i2o3xa85ocKrP1P2UgrS4n8AvP6E1H4Q+Sjk5ZMISoJueyRYMTCpuTTQEv39RIa7p0xcE7he76vgaNn6O79sBqH082t52rC0w1clExSzRvMSW8BeqCRJP2/cchqUreuMhk7W1E/LVasJcvT0+vS02eJE/p6bWMyFQ== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=suse.com; Received: from VI1PR0402MB3439.eurprd04.prod.outlook.com (2603:10a6:803:4::13) by VE1PR04MB7261.eurprd04.prod.outlook.com (2603:10a6:800:1a3::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5769.15; Mon, 31 Oct 2022 10:11:28 +0000 Received: from VI1PR0402MB3439.eurprd04.prod.outlook.com ([fe80::41c4:5b70:6fec:a963]) by VI1PR0402MB3439.eurprd04.prod.outlook.com ([fe80::41c4:5b70:6fec:a963%7]) with mapi id 15.20.5746.028; Mon, 31 Oct 2022 10:11:28 +0000 From: Chester Lin To: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Jan Petrous Cc: Chester Lin , netdev@vger.kernel.org, s32@nxp.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, =?utf-8?q?Andreas_F=C3=A4rber?= , Matthias Brugger Subject: [PATCH 2/5] dt-bindings: net: add schema for NXP S32CC dwmac glue driver Date: Mon, 31 Oct 2022 18:10:49 +0800 Message-Id: <20221031101052.14956-3-clin@suse.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221031101052.14956-1-clin@suse.com> References: <20221031101052.14956-1-clin@suse.com> X-ClientProxiedBy: TYAPR01CA0214.jpnprd01.prod.outlook.com (2603:1096:404:29::34) To VI1PR0402MB3439.eurprd04.prod.outlook.com (2603:10a6:803:4::13) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: VI1PR0402MB3439:EE_|VE1PR04MB7261:EE_ X-MS-Office365-Filtering-Correlation-Id: 0094a077-81af-4d5f-b6a6-08dabb28467a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 7QrfLYy7NyiSe6ygjSnLT4oUUWVbrED0gs/GiLE4vMdD6NCg79N9GU4cyIfUNb448NYQZXzbSOuL7ZmILNH6h68clGCj7zne2GDZCwTbJDjPdRhFcee/fm/fdAtWCmYP8Mos4MeJCY6REsSNf80gV7CW1QZURJpzfbsvjL4JWivUK5w3aZ7+8MZMVvXaYMlWILZqXK0EtpBiARLWVh9g7ZS1yJQ4hPNNXRKV5cd7lia+I0d6HEAVnFIwuzO4HDYIX4F8YPrNFx+HA/GbSNMNRjy3Dyq2vIJZk6l3h1ffWe0TE+8QM7RxrMMHap5QYdDJEw0iWeepxY47jVXKx6JuE4y7QFGwBw8B56sqGb6ERoTxi+LLkgg2A2cvR8/5JWKGMZlnDRat4Lku3F7Hs4DW/qkH92Q+GAMp2MJZh17Ig0ZzPEKePk9lbcT9DYTxjhveRapa4ggod7zo9ekynVZu8ktEpf3+l7v+8CpE/8TE6GDhK7KE1RDdx14d009e5+jeYxTmDoP3DJPxvzlo4eDhC4Pj3x43EmWGVGoDJJGEa098PJrYArNe0p/pAiqZ6y9QQBjZ/CrRlSwj54yqp76CzTcTSI/mInXVGvTflM52wMJDZ5XMwsKiFpGllILToBgO4O4zpV/1EeLO5L0/DbAhgyVzCjlro/3YQPxuSzBqQ4tkBD58gGYpiOSk/ednoASBPOcDPcwwiqVQnb0GfP8XorZHtSHrLT7qFhurlzjrzEM= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:VI1PR0402MB3439.eurprd04.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230022)(136003)(396003)(39850400004)(376002)(366004)(346002)(451199015)(6486002)(107886003)(478600001)(110136005)(54906003)(316002)(6666004)(86362001)(8676002)(6506007)(4326008)(66476007)(66946007)(66556008)(2906002)(26005)(38100700002)(41300700001)(6512007)(2616005)(186003)(1076003)(83380400001)(8936002)(36756003)(7416002)(5660300002);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: WtrLQMznBhE4C7xMc2WcjeyAwn2m+XGYwQ1lDLusqV1TTpEOxv5Rbyau6FamaD452Gna2tb0+xJnhl0VD2x+/1dQBnjTLoqTtzPlRNynbJJIuq36gMW1iz+CdsdTdda9L5Q2KEalfBzVNYVwkkwob9r2kn+rDwuFT4MoGgTJDQazis0IaHp2TcFyr4CpwLUjYLDQ1Jsri9qvRr8+wcnqNiaGp/H+sGWqIwQMiXVr/jR0ZH3TEyukq0cIMKhgoGY72hNj+DjomPktKMBQTgucBMtcjsx27DpRof79fjiUT/+/rYB77tJx+WXO+Ic4X4N2fyV1QEnh1yNXJ7fK61dFLMTG7jxZmQCwfLbhFrO9RirvPsaJh1I+zwNK4cIHoGfS0iTG5wVwRWYbBJPbKqZYvwLT3WROPIPUuTkqFBwcuW4RUfPh4QL2Q/zifGITzaG6KmKUPEZYNYfQaok7/9fjFd6CUuEF8PYCI3WPE7tnSKJKPy+7rcMxnDbH6wAfcmU3nhFW12aOR6AYOW+edvBC7OHeQA1K4y1dp3h3DjKlNk5uXPcvHfjngRgLNntmMcyiKLJwco+bXPf0lqfc0iJ1BvcDu7/GxtaxHbhYNTl480hjj/6++1yJXcNpgYkmjbZUKBUMYjsnaeEpoR5FQuwfKmIuD34up5x9YIiyrDTIAHTlpbrTfEmFjKh15FDA3ccbw9Ur3tGc0t6iwoJt1VtjWXw7v2pnNMN2jNSyuhDQJcbBrttisD1NHAxREFi1UtRgV7PDMVjfM+KPJ9Bptsg4TdNy68fMVC4N2J8jS/df8EoH3pB/bp8bivV15DWgJW32EYZc68zc4Jetp0Y37/ayf5WNmL9f4Snp+iNAxTQTETPWUPWYyD/tY1cx7MsY3kgBTvUcpOST77NLs1+Sv3ZhIVH6O95XrPP3O7wBzhcKLKGjit7SCGH1mXqotu3vokXN8RwLqZWTSz4UoA4q10bAxr+YEUcDeCuPDdE58MW6SCosJbon8bf9fFG1FBbDvBAZ1vkmDyne+y0Dwn8yZn0Q37A7urRJ/TocKZYjQh3FizXOtC6mfJe0jn1axVf1h8lIKk0p788ZP/xrzNc7C5hzgOBBpzWhOzjsk31S3hhNWHalsdjr+c+5IXB8wRc/XGWm0fGAiCp0K15IQva5pYGeoQ18sT/vBrHXKKgs41yignoYH56rtqDKxnhsMP9H6MaIWNGB8xAFwBYqWmc8NTKn9Mw/aiIkndC6xnPme+FNw2TdbvjaaIqjUZnl6Xy7swjFSGdNPRi+gGW9ALXfK49XAudveaQ03ZXo0ItS1J4iasKQiO6HlpMlwBWSwbeat4dc0oMCMsNrLTjebSVFrf7zQtPhvH4Dy8MIRxg2Y+4h2RNUANiC/BnDZNDNVrZEMTdSomMtPgArYD/ypYOzMGj1Xk8XbmoOSPsLuTNINB39m+pTdHSYM9rhudCYrs/fddaB0NvZ1rQQZoAftEQwKgkrUqZ8Q3ZO2MHJPvN2GYCmI4ojmq9tC7DKZGgho6qahpZocsXOFOz0QIPuXBQ6kmip+u/Sb9FiWcym3y9ICbkNvEc= X-OriginatorOrg: suse.com X-MS-Exchange-CrossTenant-Network-Message-Id: 0094a077-81af-4d5f-b6a6-08dabb28467a X-MS-Exchange-CrossTenant-AuthSource: VI1PR0402MB3439.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 Oct 2022 10:11:28.3442 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f7a17af6-1c5c-4a36-aa8b-f5be247aa4ba X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 6O3TGAn7HknYPrF7820NIs5vXYk/qw406ccS+oxgznPYImmIY7rDgFGNU12LkDx9 X-MS-Exchange-Transport-CrossTenantHeadersStamped: VE1PR04MB7261 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org Add the DT schema for the DWMAC Ethernet controller on NXP S32 Common Chassis. Signed-off-by: Jan Petrous Signed-off-by: Chester Lin --- .../bindings/net/nxp,s32cc-dwmac.yaml | 145 ++++++++++++++++++ 1 file changed, 145 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/nxp,s32cc-dwmac.yaml diff --git a/Documentation/devicetree/bindings/net/nxp,s32cc-dwmac.yaml b/Documentation/devicetree/bindings/net/nxp,s32cc-dwmac.yaml new file mode 100644 index 000000000000..f6b8486f9d42 --- /dev/null +++ b/Documentation/devicetree/bindings/net/nxp,s32cc-dwmac.yaml @@ -0,0 +1,145 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright 2021-2022 NXP +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/net/nxp,s32cc-dwmac.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: NXP S32CC DWMAC Ethernet controller + +maintainers: + - Jan Petrous + - Chester Lin + +select: + properties: + compatible: + contains: + enum: + - nxp,s32cc-dwmac + required: + - compatible + +allOf: + - $ref: "snps,dwmac.yaml#" + +properties: + compatible: + contains: + enum: + - nxp,s32cc-dwmac + + reg: + items: + - description: Main GMAC registers + - description: S32 MAC control registers + + dma-coherent: + description: + Declares GMAC device as DMA coherent + + clocks: + items: + - description: Main GMAC clock + - description: Peripheral registers clock + - description: Transmit SGMII clock + - description: Transmit RGMII clock + - description: Transmit RMII clock + - description: Transmit MII clock + - description: Receive SGMII clock + - description: Receive RGMII clock + - description: Receive RMII clock + - description: Receive MII clock + - description: + PTP reference clock. This clock is used for programming the + Timestamp Addend Register. If not passed then the system + clock will be used. + + clock-names: + items: + - const: stmmaceth + - const: pclk + - const: tx_sgmii + - const: tx_rgmii + - const: tx_rmii + - const: tx_mii + - const: rx_sgmii + - const: rx_rgmii + - const: rx_rmii + - const: rx_mii + - const: ptp_ref + + tx-fifo-depth: + const: 20480 + + rx-fifo-depth: + const: 20480 + +required: + - compatible + - reg + - tx-fifo-depth + - rx-fifo-depth + - clocks + - clock-names + +additionalProperties: true + +examples: + - | + #include + #include + + #define S32GEN1_SCMI_CLK_GMAC0_AXI + #define S32GEN1_SCMI_CLK_GMAC0_TX_SGMII + #define S32GEN1_SCMI_CLK_GMAC0_TX_RGMII + #define S32GEN1_SCMI_CLK_GMAC0_TX_RMII + #define S32GEN1_SCMI_CLK_GMAC0_TX_MII + #define S32GEN1_SCMI_CLK_GMAC0_RX_SGMII + #define S32GEN1_SCMI_CLK_GMAC0_RX_RGMII + #define S32GEN1_SCMI_CLK_GMAC0_RX_RMII + #define S32GEN1_SCMI_CLK_GMAC0_RX_MII + #define S32GEN1_SCMI_CLK_GMAC0_TS + + soc { + #address-cells = <1>; + #size-cells = <1>; + + gmac0: ethernet@4033c000 { + compatible = "nxp,s32cc-dwmac"; + reg = <0x4033c000 0x2000>, /* gmac IP */ + <0x4007C004 0x4>; /* S32 CTRL_STS reg */ + interrupt-parent = <&gic>; + interrupts = ; + interrupt-names = "macirq"; + phy-mode = "rgmii-id"; + tx-fifo-depth = <20480>; + rx-fifo-depth = <20480>; + dma-coherent; + clocks = <&clks S32GEN1_SCMI_CLK_GMAC0_AXI>, + <&clks S32GEN1_SCMI_CLK_GMAC0_AXI>, + <&clks S32GEN1_SCMI_CLK_GMAC0_TX_SGMII>, + <&clks S32GEN1_SCMI_CLK_GMAC0_TX_RGMII>, + <&clks S32GEN1_SCMI_CLK_GMAC0_TX_RMII>, + <&clks S32GEN1_SCMI_CLK_GMAC0_TX_MII>, + <&clks S32GEN1_SCMI_CLK_GMAC0_RX_SGMII>, + <&clks S32GEN1_SCMI_CLK_GMAC0_RX_RGMII>, + <&clks S32GEN1_SCMI_CLK_GMAC0_RX_RMII>, + <&clks S32GEN1_SCMI_CLK_GMAC0_RX_MII>, + <&clks S32GEN1_SCMI_CLK_GMAC0_TS>; + clock-names = "stmmaceth", "pclk", + "tx_sgmii", "tx_rgmii", "tx_rmii", "tx_mii", + "rx_sgmii", "rx_rgmii", "rx_rmii", "rx_mii", + "ptp_ref"; + + gmac0_mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + + ethernet-phy@4 { + reg = <0x04>; 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Signed-off-by: Jan Petrous Signed-off-by: Chester Lin --- drivers/net/ethernet/stmicro/stmmac/common.h | 2 ++ drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 4 ++++ include/linux/stmmac.h | 2 ++ 3 files changed, 8 insertions(+) diff --git a/drivers/net/ethernet/stmicro/stmmac/common.h b/drivers/net/ethernet/stmicro/stmmac/common.h index 6b5d96bced47..5b7e8cc70439 100644 --- a/drivers/net/ethernet/stmicro/stmmac/common.h +++ b/drivers/net/ethernet/stmicro/stmmac/common.h @@ -222,6 +222,8 @@ struct stmmac_safety_stats { #define CSR_F_150M 150000000 #define CSR_F_250M 250000000 #define CSR_F_300M 300000000 +#define CSR_F_500M 500000000 +#define CSR_F_800M 800000000 #define MAC_CSR_H_FRQ_MASK 0x20 diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c index 8273e6a175c8..68ac3680c04e 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c @@ -323,6 +323,10 @@ static void stmmac_clk_csr_set(struct stmmac_priv *priv) priv->clk_csr = STMMAC_CSR_150_250M; else if ((clk_rate >= CSR_F_250M) && (clk_rate <= CSR_F_300M)) priv->clk_csr = STMMAC_CSR_250_300M; + else if ((clk_rate >= CSR_F_300M) && (clk_rate < CSR_F_500M)) + priv->clk_csr = STMMAC_CSR_300_500M; + else if ((clk_rate >= CSR_F_500M) && (clk_rate < CSR_F_800M)) + priv->clk_csr = STMMAC_CSR_500_800M; } if (priv->plat->has_sun8i) { diff --git a/include/linux/stmmac.h b/include/linux/stmmac.h index fb2e88614f5d..307980c808f7 100644 --- a/include/linux/stmmac.h +++ b/include/linux/stmmac.h @@ -34,6 +34,8 @@ #define STMMAC_CSR_35_60M 0x3 /* MDC = clk_scr_i/26 */ #define STMMAC_CSR_150_250M 0x4 /* MDC = clk_scr_i/102 */ #define STMMAC_CSR_250_300M 0x5 /* MDC = clk_scr_i/122 */ +#define STMMAC_CSR_300_500M 0x6 /* MDC = clk_scr_i/204 */ +#define STMMAC_CSR_500_800M 0x7 /* MDC = clk_scr_i/324 */ /* MTL algorithms identifiers */ #define MTL_TX_ALGORITHM_WRR 0x0 From patchwork Mon Oct 31 10:10:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chester Lin X-Patchwork-Id: 13025546 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 97EB7C38A02 for ; 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Signed-off-by: Ondrej Spacek Signed-off-by: Chester Lin --- drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c | 10 ++++++++++ drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h | 4 +++- drivers/net/ethernet/stmicro/stmmac/hwif.h | 5 +++++ drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 3 +++ include/linux/stmmac.h | 7 +++++++ 5 files changed, 28 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c b/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c index d99fa028c646..4e6e2952abfd 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c @@ -517,6 +517,15 @@ static int dwmac4_enable_tbs(void __iomem *ioaddr, bool en, u32 chan) return 0; } +static void dwmac4_axi4_cc(void __iomem *ioaddr, + struct stmmac_axi4_ace_ctrl *acecfg) +{ + /* Configure AXI4 cache coherency for Tx/Rx DMA channels */ + writel(acecfg->tx_ar_reg, ioaddr + DMA_AXI4_TX_AR_ACE_CONTROL); + writel(acecfg->rx_aw_reg, ioaddr + DMA_AXI4_RX_AW_ACE_CONTROL); + writel(acecfg->txrx_awar_reg, ioaddr + DMA_AXI4_TXRX_AWAR_ACE_CONTROL); +} + const struct stmmac_dma_ops dwmac4_dma_ops = { .reset = dwmac4_dma_reset, .init = dwmac4_dma_init, @@ -574,4 +583,5 @@ const struct stmmac_dma_ops dwmac410_dma_ops = { .set_bfsize = dwmac4_set_bfsize, .enable_sph = dwmac4_enable_sph, .enable_tbs = dwmac4_enable_tbs, + .axi4_cc = dwmac4_axi4_cc, }; diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h b/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h index 9321879b599c..7f491f2651b2 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h @@ -21,7 +21,9 @@ #define DMA_DEBUG_STATUS_0 0x0000100c #define DMA_DEBUG_STATUS_1 0x00001010 #define DMA_DEBUG_STATUS_2 0x00001014 -#define DMA_AXI_BUS_MODE 0x00001028 +#define DMA_AXI4_TX_AR_ACE_CONTROL 0x00001020 +#define DMA_AXI4_RX_AW_ACE_CONTROL 0x00001024 +#define DMA_AXI4_TXRX_AWAR_ACE_CONTROL 0x00001028 #define DMA_TBS_CTRL 0x00001050 /* DMA Bus Mode bitmap */ diff --git a/drivers/net/ethernet/stmicro/stmmac/hwif.h b/drivers/net/ethernet/stmicro/stmmac/hwif.h index 592b4067f9b8..bffe2ec36bb3 100644 --- a/drivers/net/ethernet/stmicro/stmmac/hwif.h +++ b/drivers/net/ethernet/stmicro/stmmac/hwif.h @@ -212,6 +212,9 @@ struct stmmac_dma_ops { void (*set_bfsize)(void __iomem *ioaddr, int bfsize, u32 chan); void (*enable_sph)(void __iomem *ioaddr, bool en, u32 chan); int (*enable_tbs)(void __iomem *ioaddr, bool en, u32 chan); + /* Configure AXI4 cache coherency for Tx and Rx DMA channels */ + void (*axi4_cc)(void __iomem *ioaddr, + struct stmmac_axi4_ace_ctrl *acecfg); }; #define stmmac_reset(__priv, __args...) \ @@ -272,6 +275,8 @@ struct stmmac_dma_ops { stmmac_do_void_callback(__priv, dma, enable_sph, __args) #define stmmac_enable_tbs(__priv, __args...) \ stmmac_do_callback(__priv, dma, enable_tbs, __args) +#define stmmac_axi4_cc(__priv, __args...) \ + stmmac_do_void_callback(__priv, dma, axi4_cc, __args) struct mac_device_info; struct net_device; diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c index 68ac3680c04e..1325d5425daf 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c @@ -2917,6 +2917,9 @@ static int stmmac_init_dma_engine(struct stmmac_priv *priv) if (priv->plat->axi) stmmac_axi(priv, priv->ioaddr, priv->plat->axi); + if (priv->plat->axi4_ace_ctrl) + stmmac_axi4_cc(priv, priv->ioaddr, priv->plat->axi4_ace_ctrl); + /* DMA CSR Channel configuration */ for (chan = 0; chan < dma_csr_ch; chan++) { stmmac_init_chan(priv, priv->ioaddr, priv->plat->dma_cfg, chan); diff --git a/include/linux/stmmac.h b/include/linux/stmmac.h index 307980c808f7..23e740c6c7b8 100644 --- a/include/linux/stmmac.h +++ b/include/linux/stmmac.h @@ -115,6 +115,12 @@ struct stmmac_axi { bool axi_rb; }; +struct stmmac_axi4_ace_ctrl { + u32 tx_ar_reg; + u32 rx_aw_reg; + u32 txrx_awar_reg; +}; + #define EST_GCL 1024 struct stmmac_est { struct mutex lock; @@ -248,6 +254,7 @@ struct plat_stmmacenet_data { struct reset_control *stmmac_rst; struct reset_control *stmmac_ahb_rst; struct stmmac_axi *axi; + struct stmmac_axi4_ace_ctrl *axi4_ace_ctrl; int has_gmac4; bool has_sun8i; bool tso_en; From patchwork Mon Oct 31 10:10:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chester Lin X-Patchwork-Id: 13025547 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CDC5DFA3740 for ; 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This driver is mainly based on NXP's downstream implementation on CodeAurora[1]. [1] https://source.codeaurora.org/external/autobsps32/linux/tree/drivers/net/ethernet/stmicro/stmmac?h=bsp34.0-5.10.120-rt Signed-off-by: Jan Petrous Signed-off-by: Ghennadi Procopciuc Signed-off-by: Andra-Teodora Ilie Signed-off-by: Chester Lin --- drivers/net/ethernet/stmicro/stmmac/Kconfig | 13 + drivers/net/ethernet/stmicro/stmmac/Makefile | 1 + .../net/ethernet/stmicro/stmmac/dwmac-s32cc.c | 318 ++++++++++++++++++ 3 files changed, 332 insertions(+) create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac-s32cc.c diff --git a/drivers/net/ethernet/stmicro/stmmac/Kconfig b/drivers/net/ethernet/stmicro/stmmac/Kconfig index 31ff35174034..dd3fb5e462b7 100644 --- a/drivers/net/ethernet/stmicro/stmmac/Kconfig +++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig @@ -153,6 +153,19 @@ config DWMAC_ROCKCHIP This selects the Rockchip RK3288 SoC glue layer support for the stmmac device driver. +config DWMAC_S32CC + tristate "NXP S32 series GMAC support" + default ARCH_S32 + depends on OF && (ARCH_S32 || COMPILE_TEST) + select MFD_SYSCON + select PHYLINK + help + Support for ethernet controller on NXP S32 series SOCs. + + This selects NXP SoC glue layer support for the stmmac + device driver. This driver is used for the S32 series + SOCs GMAC ethernet controller. + config DWMAC_SOCFPGA tristate "SOCFPGA dwmac support" default ARCH_INTEL_SOCFPGA diff --git a/drivers/net/ethernet/stmicro/stmmac/Makefile b/drivers/net/ethernet/stmicro/stmmac/Makefile index d4e12e9ace4f..ec92cc2becd7 100644 --- a/drivers/net/ethernet/stmicro/stmmac/Makefile +++ b/drivers/net/ethernet/stmicro/stmmac/Makefile @@ -32,6 +32,7 @@ obj-$(CONFIG_DWMAC_INTEL_PLAT) += dwmac-intel-plat.o obj-$(CONFIG_DWMAC_GENERIC) += dwmac-generic.o obj-$(CONFIG_DWMAC_IMX8) += dwmac-imx.o obj-$(CONFIG_DWMAC_VISCONTI) += dwmac-visconti.o +obj-$(CONFIG_DWMAC_S32CC) += dwmac-s32cc.o stmmac-platform-objs:= stmmac_platform.o dwmac-altr-socfpga-objs := altr_tse_pcs.o dwmac-socfpga.o diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-s32cc.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-s32cc.c new file mode 100644 index 000000000000..ac274cdfbe22 --- /dev/null +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-s32cc.c @@ -0,0 +1,318 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * DWMAC Specific Glue layer for NXP S32 Common Chassis + * + * Copyright (C) 2019-2022 NXP + * Copyright (C) 2022 SUSE LLC + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "stmmac_platform.h" + +#define GMAC_TX_RATE_125M 125000000 /* 125MHz */ +#define GMAC_TX_RATE_25M 25000000 /* 25MHz */ +#define GMAC_TX_RATE_2M5 2500000 /* 2.5MHz */ + +/* S32 SRC register for phyif selection */ +#define PHY_INTF_SEL_MII 0x00 +#define PHY_INTF_SEL_SGMII 0x01 +#define PHY_INTF_SEL_RGMII 0x02 +#define PHY_INTF_SEL_RMII 0x08 + +/* AXI4 ACE control settings */ +#define ACE_DOMAIN_SIGNAL 0x2 +#define ACE_CACHE_SIGNAL 0xf +#define ACE_CONTROL_SIGNALS ((ACE_DOMAIN_SIGNAL << 4) | ACE_CACHE_SIGNAL) +#define ACE_PROTECTION 0x2 + +struct s32cc_priv_data { + void __iomem *ctrl_sts; + struct device *dev; + phy_interface_t intf_mode; + struct clk *tx_clk; + struct clk *rx_clk; +}; + +static int s32cc_gmac_init(struct platform_device *pdev, void *priv) +{ + struct s32cc_priv_data *gmac = priv; + u32 intf_sel; + int ret; + + if (gmac->tx_clk) { + ret = clk_prepare_enable(gmac->tx_clk); + if (ret) { + dev_err(&pdev->dev, "Can't set tx clock\n"); + return ret; + } + } + + if (gmac->rx_clk) { + ret = clk_prepare_enable(gmac->rx_clk); + if (ret) { + dev_err(&pdev->dev, "Can't set rx clock\n"); + return ret; + } + } + + /* set interface mode */ + if (gmac->ctrl_sts) { + switch (gmac->intf_mode) { + default: + dev_info(&pdev->dev, "unsupported mode %u, set the default phy mode.\n", + gmac->intf_mode); + fallthrough; + case PHY_INTERFACE_MODE_SGMII: + dev_info(&pdev->dev, "phy mode set to SGMII\n"); + intf_sel = PHY_INTF_SEL_SGMII; + break; + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_TXID: + case PHY_INTERFACE_MODE_RGMII_RXID: + dev_info(&pdev->dev, "phy mode set to RGMII\n"); + intf_sel = PHY_INTF_SEL_RGMII; + break; + case PHY_INTERFACE_MODE_RMII: + dev_info(&pdev->dev, "phy mode set to RMII\n"); + intf_sel = PHY_INTF_SEL_RMII; + break; + case PHY_INTERFACE_MODE_MII: + dev_info(&pdev->dev, "phy mode set to MII\n"); + intf_sel = PHY_INTF_SEL_MII; + break; + } + + writel(intf_sel, gmac->ctrl_sts); + } + + return 0; +} + +static void s32cc_gmac_exit(struct platform_device *pdev, void *priv) +{ + struct s32cc_priv_data *gmac = priv; + + if (gmac->tx_clk) + clk_disable_unprepare(gmac->tx_clk); + + if (gmac->rx_clk) + clk_disable_unprepare(gmac->rx_clk); +} + +static void s32cc_fix_speed(void *priv, unsigned int speed) +{ + struct s32cc_priv_data *gmac = priv; + + if (!gmac->tx_clk || !gmac->rx_clk) + return; + + /* SGMII mode doesn't support the clock reconfiguration */ + if (gmac->intf_mode == PHY_INTERFACE_MODE_SGMII) + return; + + switch (speed) { + case SPEED_1000: + dev_info(gmac->dev, "Set TX clock to 125M\n"); + clk_set_rate(gmac->tx_clk, GMAC_TX_RATE_125M); + break; + case SPEED_100: + dev_info(gmac->dev, "Set TX clock to 25M\n"); + clk_set_rate(gmac->tx_clk, GMAC_TX_RATE_25M); + break; + case SPEED_10: + dev_info(gmac->dev, "Set TX clock to 2.5M\n"); + clk_set_rate(gmac->tx_clk, GMAC_TX_RATE_2M5); + break; + default: + dev_err(gmac->dev, "Unsupported/Invalid speed: %d\n", speed); + return; + } +} + +static int s32cc_config_cache_coherency(struct platform_device *pdev, + struct plat_stmmacenet_data *plat_dat) +{ + plat_dat->axi4_ace_ctrl = + devm_kzalloc(&pdev->dev, + sizeof(struct stmmac_axi4_ace_ctrl), + GFP_KERNEL); + + if (!plat_dat->axi4_ace_ctrl) { + dev_info(&pdev->dev, "Fail to allocate axi4_ace_ctrl\n"); + return -ENOMEM; + } + + plat_dat->axi4_ace_ctrl->tx_ar_reg = (ACE_CONTROL_SIGNALS << 16) + | (ACE_CONTROL_SIGNALS << 8) | ACE_CONTROL_SIGNALS; + + plat_dat->axi4_ace_ctrl->rx_aw_reg = (ACE_CONTROL_SIGNALS << 24) + | (ACE_CONTROL_SIGNALS << 16) | (ACE_CONTROL_SIGNALS << 8) + | ACE_CONTROL_SIGNALS; + + plat_dat->axi4_ace_ctrl->txrx_awar_reg = (ACE_PROTECTION << 20) + | (ACE_PROTECTION << 16) | (ACE_CONTROL_SIGNALS << 8) + | ACE_CONTROL_SIGNALS; + + return 0; +} + +static int s32cc_dwmac_probe(struct platform_device *pdev) +{ + struct plat_stmmacenet_data *plat_dat; + struct stmmac_resources stmmac_res; + struct s32cc_priv_data *gmac; + struct resource *res; + const char *tx_clk, *rx_clk; + int ret; + + ret = stmmac_get_platform_resources(pdev, &stmmac_res); + if (ret) + return ret; + + gmac = devm_kzalloc(&pdev->dev, sizeof(*gmac), GFP_KERNEL); + if (!gmac) + return PTR_ERR(gmac); + + gmac->dev = &pdev->dev; + + /* S32G control reg */ + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + gmac->ctrl_sts = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR_OR_NULL(gmac->ctrl_sts)) { + dev_err(&pdev->dev, "S32CC config region is missing\n"); + return PTR_ERR(gmac->ctrl_sts); + } + + plat_dat = stmmac_probe_config_dt(pdev, stmmac_res.mac); + if (IS_ERR(plat_dat)) + return PTR_ERR(plat_dat); + + plat_dat->bsp_priv = gmac; + + switch (plat_dat->phy_interface) { + case PHY_INTERFACE_MODE_SGMII: + tx_clk = "tx_sgmii"; + rx_clk = "rx_sgmii"; + break; + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_TXID: + case PHY_INTERFACE_MODE_RGMII_RXID: + tx_clk = "tx_rgmii"; + rx_clk = "rx_rgmii"; + break; + case PHY_INTERFACE_MODE_RMII: + tx_clk = "tx_rmii"; + rx_clk = "rx_rmii"; + break; + case PHY_INTERFACE_MODE_MII: + tx_clk = "tx_mii"; + rx_clk = "rx_mii"; + break; + default: + dev_err(&pdev->dev, "Not supported phy interface mode: [%s]\n", + phy_modes(plat_dat->phy_interface)); + return -EINVAL; + }; + + gmac->intf_mode = plat_dat->phy_interface; + + /* DMA cache coherency settings */ + if (of_dma_is_coherent(pdev->dev.of_node)) { + ret = s32cc_config_cache_coherency(pdev, plat_dat); + if (ret) + goto err_remove_config_dt; + } + + /* tx clock */ + gmac->tx_clk = devm_clk_get(&pdev->dev, tx_clk); + if (IS_ERR(gmac->tx_clk)) { + dev_info(&pdev->dev, "tx clock not found\n"); + gmac->tx_clk = NULL; + } + + /* rx clock */ + gmac->rx_clk = devm_clk_get(&pdev->dev, rx_clk); + if (IS_ERR(gmac->rx_clk)) { + dev_info(&pdev->dev, "rx clock not found\n"); + gmac->rx_clk = NULL; + } + + ret = s32cc_gmac_init(pdev, gmac); + if (ret) + goto err_remove_config_dt; + + /* core feature set */ + plat_dat->has_gmac4 = true; + plat_dat->pmt = 1; + + plat_dat->init = s32cc_gmac_init; + plat_dat->exit = s32cc_gmac_exit; + plat_dat->fix_mac_speed = s32cc_fix_speed; + + /* safety feature config */ + plat_dat->safety_feat_cfg = + devm_kzalloc(&pdev->dev, sizeof(*plat_dat->safety_feat_cfg), + GFP_KERNEL); + + if (!plat_dat->safety_feat_cfg) { + dev_info(&pdev->dev, "allocate safety_feat_cfg failed\n"); + goto err_gmac_exit; + } + + plat_dat->safety_feat_cfg->tsoee = 1; + plat_dat->safety_feat_cfg->mrxpee = 1; + plat_dat->safety_feat_cfg->mestee = 1; + plat_dat->safety_feat_cfg->mrxee = 1; + plat_dat->safety_feat_cfg->mtxee = 1; + plat_dat->safety_feat_cfg->epsi = 1; + plat_dat->safety_feat_cfg->edpp = 1; + plat_dat->safety_feat_cfg->prtyen = 1; + plat_dat->safety_feat_cfg->tmouten = 1; + + ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); + if (ret) + goto err_gmac_exit; + + return 0; + +err_gmac_exit: + s32cc_gmac_exit(pdev, plat_dat->bsp_priv); +err_remove_config_dt: + stmmac_remove_config_dt(pdev, plat_dat); + return ret; +} + +static const struct of_device_id s32_dwmac_match[] = { + { .compatible = "nxp,s32cc-dwmac" }, + { } +}; +MODULE_DEVICE_TABLE(of, s32_dwmac_match); + +static struct platform_driver s32_dwmac_driver = { + .probe = s32cc_dwmac_probe, + .remove = stmmac_pltfr_remove, + .driver = { + .name = "s32cc-dwmac", + .pm = &stmmac_pltfr_pm_ops, + .of_match_table = s32_dwmac_match, + }, +}; +module_platform_driver(s32_dwmac_driver); + +MODULE_AUTHOR("Jan Petrous "); +MODULE_DESCRIPTION("NXP S32 common chassis GMAC driver"); +MODULE_LICENSE("GPL v2");