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pr=C From: Ayan Kumar Halder To: CC: , , , , , , Ayan Kumar Halder Subject: [XEN v2 01/12] xen/Arm: vGICv3: Sysreg emulation is applicable for Aarch64 only Date: Mon, 31 Oct 2022 15:13:15 +0000 Message-ID: <20221031151326.22634-2-ayankuma@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221031151326.22634-1-ayankuma@amd.com> References: <20221031151326.22634-1-ayankuma@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT066:EE_|MN0PR12MB6102:EE_ X-MS-Office365-Filtering-Correlation-Id: f9b40064-74d7-478b-23a4-08dabb528867 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: otvrLXU7ddqHrK+99F4qQ1k3FBoKQ8Gg+QvQs28l0VmTvSVte3VL+40rNSlfCOsw5JAZH93O/XLp+NEyNBEHoM80tH1xntkRIV+Yl4reZfE0MqOD3rTWFDJ/gJrxzgrQihxMfPLElxqqSeB90/qYzYWrV0Rwr+7Yj72Mv1XB7uhGQ6t1AgW5SDGkFmrF29lqf5UfODy9Bz3Q4Gd+W6a5jBVlcCYUVDb+D73EtqBAn0PY+2Xe+R/kRM8kOUhg43CGvF5Mj9IPeBFMAjrRrt95BngDO0tMzAYVvkqfxhmOoMdm2KRbcOfXvTC6MszZuCQL7LXJ3XAj3mcZR3cnm3/OC46bIRm7J3gobbA7GXAxU/jxav9disCoQ9mCcoP3KzfY5VOu9UtP+6LFpxSCL+2H4Qk5g3jCl9f1vejwTfaxPyGdJcpfrwpJZLttAedGgTSHb0O2F/VSCnJ70jHUXFWD9ZVyvi0YACwqCqu/Q0y+cccHMT1WvV8S+cvaqT47sYcCeiGqFHQVSJJu0t+UW9iwC39P+g1j+9DhSUYSTgl2Ah6Nf2lYkTgNO9/hbv47VF8tx4XBhOHzHwNSnexCaHq52PcEYmOsvwow0djBekb1oLI2/n9LEFKyZWkW2Xm1lvwEQ3zEeF9ZwBZONNptmvuOkgPgJk4KIhh1nHf2LdVegfl/+Tz5s54BRD8LqJrM5G85eW+sbb4MdK/iElHuIij4jCsTdLAXCYviaIIAJvPUwQZSsLFbdi3+2hQR5CRu5/viKiEC0xUmqKTSCFSQC3dtYOdSCyr1NndUtn52vIMIY1E= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(346002)(376002)(136003)(39860400002)(396003)(451199015)(46966006)(36840700001)(40470700004)(26005)(8676002)(356005)(41300700001)(81166007)(4326008)(36756003)(36860700001)(47076005)(2616005)(83380400001)(426003)(8936002)(336012)(40460700003)(5660300002)(54906003)(82740400003)(186003)(2906002)(1076003)(6916009)(478600001)(316002)(6666004)(70206006)(82310400005)(70586007)(40480700001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 Oct 2022 15:13:57.6050 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f9b40064-74d7-478b-23a4-08dabb528867 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT066.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB6102 Refer ARM DDI 0487G.b ID072021, EC==0b011000 is supported for Aarch64 state only. Thus, vgic_v3_emulate_sysreg is enabled for CONFIG_ARM_64 only. Signed-off-by: Ayan Kumar Halder --- Changes from - v1 - 1. Updated the commit message. xen/arch/arm/vgic-v3.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/xen/arch/arm/vgic-v3.c b/xen/arch/arm/vgic-v3.c index 015446be17..3f4509dcd3 100644 --- a/xen/arch/arm/vgic-v3.c +++ b/xen/arch/arm/vgic-v3.c @@ -1519,6 +1519,7 @@ static bool vgic_v3_emulate_sgi1r(struct cpu_user_regs *regs, uint64_t *r, } } +#ifdef CONFIG_ARM_64 static bool vgic_v3_emulate_sysreg(struct cpu_user_regs *regs, union hsr hsr) { struct hsr_sysreg sysreg = hsr.sysreg; @@ -1539,6 +1540,7 @@ static bool vgic_v3_emulate_sysreg(struct cpu_user_regs *regs, union hsr hsr) return false; } } +#endif static bool vgic_v3_emulate_cp64(struct cpu_user_regs *regs, union hsr hsr) { @@ -1562,8 +1564,10 @@ static bool vgic_v3_emulate_reg(struct cpu_user_regs *regs, union hsr hsr) { switch (hsr.ec) { +#ifdef CONFIG_ARM_64 case HSR_EC_SYSREG: return vgic_v3_emulate_sysreg(regs, hsr); +#endif case HSR_EC_CP15_64: return vgic_v3_emulate_cp64(regs, hsr); default: From patchwork Mon Oct 31 15:13:16 2022 Content-Type: text/plain; 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pr=C From: Ayan Kumar Halder To: CC: , , , , , , Ayan Kumar Halder Subject: [XEN v2 02/12] xen/Arm: GICv3: Move the macros to compute the affnity level to arm64/arm32 Date: Mon, 31 Oct 2022 15:13:16 +0000 Message-ID: <20221031151326.22634-3-ayankuma@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221031151326.22634-1-ayankuma@amd.com> References: <20221031151326.22634-1-ayankuma@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT062:EE_|CH0PR12MB5172:EE_ X-MS-Office365-Filtering-Correlation-Id: 3810ea97-d708-4244-f7e8-08dabb5289de X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: mXatm7IFJ5qHFisGsuFJLLhHFwnaecEWyikHz1EFVtOose/YQ72RjaCW4nM+CXOhz0x2w/ysgztZL7V9s+7aRFylKW8tW629Txl0TNYrZCeAdnVR6Fn7phNM8RP3zy+cgsk+r3BcNQCWkFGw6lgtwcShcJ1I7/OZIyo6dAad7cm35J2Tv5RqzZB+35sixVLXazLQky/ggucVQNJE611X4WikNAuJIlJi8v6U/95T0KtLWThaOEO57lYbHxxcqiyL3Am35nc7ZEo9ERZN0otK3ABC5kNFTi+q/QsWWt2zuPROgcmOdNrgtybS/7ZT7EXRiPEDr0oVCjCpPa9itYXAIyzZdte2/LA+y9W+M8V7zqdGpKDuR06saiCVlNFT7iT+V1hlRIfeoYdXxjJWd7rx1h2yznqoGxd/a+2nJvzjD5moPBf3GAFDjvFzR3izCRp1daIoJVYx7ztEMjduGH/2uFKSLqDmjfGNOQSHlsS7AiHkqu+RG4MwuIACbnvoureDt3TQsj6M2M0DaiVkTyU4qzoC2dOnVfUjJhXvSjFCr5f8MTD+WCSHWm7cyW4d0MDpsC0AH+qoKCgbYX1PWaDXu2Yg9F/jbBUQk8lwtImSRy+E/6rKri+iS/ftYtcVaCkoVciBu5i3Lx/hB+4/k6Jkp/H++6pkSD3P4g8z/huyEXrvYGLQ9g/jtR/xO44OkmD9/2Fula/H9/lrQDYs/PFvXNTM5nOZIsdN1AbWHfWtBgpToX1p27kX6OZYqA8sS4IbFEES38GnUiY90AE3iktmDlcerhtPFp0aBd+bOmRZqCxY1L2g0SBJ0bjBaugtYqibrnTH8dja9VtQ/LsB6JHzfhAHtTbodiSDYiZ9Ef6s87yEi7p4NMFPj8DtQuNfHjuZ X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(376002)(39860400002)(396003)(346002)(136003)(451199015)(46966006)(40470700004)(36840700001)(82310400005)(36756003)(8936002)(6666004)(70586007)(4326008)(316002)(8676002)(966005)(36860700001)(70206006)(41300700001)(54906003)(6916009)(5660300002)(40480700001)(2906002)(81166007)(356005)(426003)(83380400001)(186003)(478600001)(40460700003)(1076003)(82740400003)(26005)(2616005)(336012)(47076005)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 Oct 2022 15:13:59.9900 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3810ea97-d708-4244-f7e8-08dabb5289de X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT062.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH0PR12MB5172 Refer https://elixir.bootlin.com/linux/v6.1-rc1/source/arch/arm64/ \ include/asm/cputype.h#L14 , for the macros specific for arm64. Refer https://elixir.bootlin.com/linux/v6.1-rc1/source/arch/arm/include/ \ asm/cputype.h#L54 , for the macros specific for arm32. MPIDR_LEVEL_SHIFT() differs between 64 and 32 bit. For 64 bit :- aff_lev3 aff_lev2 aff_lev1 aff_lev0 |________|________|________|________|________| 40 32 24 16 8 0 For 32 bit :- aff_lev3 aff_lev2 aff_lev1 aff_lev0 |________|________|________|________| 32 24 16 8 0 Signed-off-by: Ayan Kumar Halder --- Changes from :- v1 - 1. Rearranged the macro defines so that the common code (between arm32 and arm64) is placed in "arm/include/asm/processor.h". xen/arch/arm/include/asm/arm32/processor.h | 5 +++++ xen/arch/arm/include/asm/arm64/processor.h | 8 ++++++++ xen/arch/arm/include/asm/processor.h | 6 ------ 3 files changed, 13 insertions(+), 6 deletions(-) diff --git a/xen/arch/arm/include/asm/arm32/processor.h b/xen/arch/arm/include/asm/arm32/processor.h index 4e679f3273..82aa7f8d9d 100644 --- a/xen/arch/arm/include/asm/arm32/processor.h +++ b/xen/arch/arm/include/asm/arm32/processor.h @@ -56,6 +56,11 @@ struct cpu_user_regs uint32_t pad1; /* Doubleword-align the user half of the frame */ }; +/* + * Macros to extract affinity level. Picked from kernel + */ +#define MPIDR_LEVEL_SHIFT(level) (MPIDR_LEVEL_BITS * (level)) + #endif #endif /* __ASM_ARM_ARM32_PROCESSOR_H */ diff --git a/xen/arch/arm/include/asm/arm64/processor.h b/xen/arch/arm/include/asm/arm64/processor.h index c749f80ad9..295483a9dd 100644 --- a/xen/arch/arm/include/asm/arm64/processor.h +++ b/xen/arch/arm/include/asm/arm64/processor.h @@ -84,6 +84,14 @@ struct cpu_user_regs uint64_t sp_el1, elr_el1; }; +/* + * Macros to extract affinity level. picked from kernel + */ +#define MPIDR_LEVEL_BITS_SHIFT 3 + +#define MPIDR_LEVEL_SHIFT(level) \ + (((1 << (level)) >> 1) << MPIDR_LEVEL_BITS_SHIFT) + #undef __DECL_REG #endif /* __ASSEMBLY__ */ diff --git a/xen/arch/arm/include/asm/processor.h b/xen/arch/arm/include/asm/processor.h index 1dd81d7d52..ecfb62bbbe 100644 --- a/xen/arch/arm/include/asm/processor.h +++ b/xen/arch/arm/include/asm/processor.h @@ -122,13 +122,7 @@ /* * Macros to extract affinity level. picked from kernel */ - -#define MPIDR_LEVEL_BITS_SHIFT 3 #define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1) - -#define MPIDR_LEVEL_SHIFT(level) \ - (((1 << (level)) >> 1) << MPIDR_LEVEL_BITS_SHIFT) - #define MPIDR_AFFINITY_LEVEL(mpidr, level) \ (((mpidr) >> MPIDR_LEVEL_SHIFT(level)) & MPIDR_LEVEL_MASK) From patchwork Mon Oct 31 15:13:17 2022 Content-Type: text/plain; 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pr=C From: Ayan Kumar Halder To: CC: , , , , , , Ayan Kumar Halder Subject: [XEN v2 03/12] xen/Arm: vreg: Support vreg_reg64_* helpers on Aarch32 Date: Mon, 31 Oct 2022 15:13:17 +0000 Message-ID: <20221031151326.22634-4-ayankuma@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221031151326.22634-1-ayankuma@amd.com> References: <20221031151326.22634-1-ayankuma@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT099:EE_|BL0PR12MB5012:EE_ X-MS-Office365-Filtering-Correlation-Id: 585ad06b-5a1c-49df-3bcc-08dabb528c00 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: AQITzW39YdiiWYAHCrloLC8dKy880ND0vdkY+8xBrifbu1Ag+TzJ98exC3krQ4AyQS5idIFyEX/DjTr2CpDKER3uMOPyaYvPk3jlfjKevy7y69Gj0W/mi6oprsmVqDGnbUitmNBt8WAd1J2ueRUuaEWHDUMy2mGAnCQbD/03WY9P2plp52/CaaQ3DLhL7vtm8xGjm/7hZNiGow5+iCVX+Ok4z3VEmnOVY6iUAdJUaWVuEFS28gsDCBmJ3xegctGEfRs85Jh2uWjXs6hZ4kpw75nGGaVBlQFc9qwgwurdcQ5rhlmVvoomOXQQ5fjb7ERf6X15ctUFzZ+Ig4WijIHl1jq8FYert/cXSu5JCdSU/Mx6hdU/th5KhvE6vWP7sbPBCh3V08fmhp2Dzmq5mXHcrArzmsjqSq8704UEedJMC3DmWrUpA+VPo0smZG5kaaJjLrkCmgkfuldinL/epikE2Mw8P5ak1rksDihmx/W/x7RFZWUl6H/W377Bo2ZmuynjWEjlPWQr1ZvQ7jkGf1sWWt3ZsUiQ09iL0JzE6T6HhRZ+CniKB8d0kFpsp4PW0BZXX5WiDXzzzNZTmsLf9eDiEE9i8+pVWrBvOpJswTL95Q26JTKNf8Cjo4uBA7L6zzqsKsPC6bqhnwwvKXWpxZ5kpgydIDvLVzwe8mHLx6jCtkgJmzQwzT4OA7MZch1E2gJnIjaIaVgZJPz2CYtywNcBs+KHVd/uehs2z8IDYT/xEmk7hhKxKTzd6R6OeMTMis51feixqDLRYX94x/BdMfoZGedqRcq2uEdCFamSu8870ek= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(136003)(346002)(376002)(396003)(39860400002)(451199015)(40470700004)(46966006)(36840700001)(356005)(81166007)(82740400003)(40480700001)(36756003)(2906002)(6666004)(478600001)(70586007)(4326008)(70206006)(316002)(40460700003)(8676002)(5660300002)(6916009)(8936002)(54906003)(41300700001)(82310400005)(36860700001)(186003)(2616005)(26005)(1076003)(47076005)(83380400001)(426003)(336012)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 Oct 2022 15:14:03.5322 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 585ad06b-5a1c-49df-3bcc-08dabb528c00 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT099.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL0PR12MB5012 In some situations (eg GICR_TYPER), the hypervior may need to emulate 64bit registers in aarch32 mode. In such situations, the hypervisor may need to read/modify the lower or upper 32 bits of the 64 bit register. In aarch32, 'unsigned long' is 32 bits. Thus, we cannot use it for 64 bit registers. The correct approach is to typecast 'mask' based on the size of register access (ie uint32_t or uint64_t) instead of using 'unsigned long' as it will not generate the correct mask for the upper 32 bits of a 64 bit register. Also, 'val' needs to be typecasted so that it can correctly update the upper/ lower 32 bits of a 64 bit register. Signed-off-by: Ayan Kumar Halder --- Changes from :- v1 - 1. Remove vreg_reg_extract(), vreg_reg_update(), vreg_reg_setbits() and vreg_reg_clearbits(). Moved the implementation to vreg_reg##sz##_*. 'mask' and 'val' is now using uint##sz##_t. xen/arch/arm/include/asm/vreg.h | 88 ++++++++------------------------- 1 file changed, 20 insertions(+), 68 deletions(-) diff --git a/xen/arch/arm/include/asm/vreg.h b/xen/arch/arm/include/asm/vreg.h index f26a70d024..122ea79b65 100644 --- a/xen/arch/arm/include/asm/vreg.h +++ b/xen/arch/arm/include/asm/vreg.h @@ -89,107 +89,59 @@ static inline bool vreg_emulate_sysreg(struct cpu_user_regs *regs, union hsr hsr * The check on the size supported by the register has to be done by * the caller of vreg_regN_*. * - * vreg_reg_* should never be called directly. Instead use the vreg_regN_* - * according to size of the emulated register - * * Note that the alignment fault will always be taken in the guest * (see B3.12.7 DDI0406.b). */ -static inline register_t vreg_reg_extract(unsigned long reg, - unsigned int offset, - enum dabt_size size) -{ - reg >>= 8 * offset; - reg &= VREG_REG_MASK(size); - - return reg; -} - -static inline void vreg_reg_update(unsigned long *reg, register_t val, - unsigned int offset, - enum dabt_size size) -{ - unsigned long mask = VREG_REG_MASK(size); - int shift = offset * 8; - - *reg &= ~(mask << shift); - *reg |= ((unsigned long)val & mask) << shift; -} - -static inline void vreg_reg_setbits(unsigned long *reg, register_t bits, - unsigned int offset, - enum dabt_size size) -{ - unsigned long mask = VREG_REG_MASK(size); - int shift = offset * 8; - - *reg |= ((unsigned long)bits & mask) << shift; -} - -static inline void vreg_reg_clearbits(unsigned long *reg, register_t bits, - unsigned int offset, - enum dabt_size size) -{ - unsigned long mask = VREG_REG_MASK(size); - int shift = offset * 8; - - *reg &= ~(((unsigned long)bits & mask) << shift); -} /* N-bit register helpers */ #define VREG_REG_HELPERS(sz, offmask) \ static inline register_t vreg_reg##sz##_extract(uint##sz##_t reg, \ const mmio_info_t *info)\ { \ - return vreg_reg_extract(reg, info->gpa & (offmask), \ - info->dabt.size); \ + unsigned int offset = info->gpa & (offmask); \ + \ + reg >>= 8 * offset; \ + reg &= VREG_REG_MASK(info->dabt.size); \ + \ + return reg; \ } \ \ static inline void vreg_reg##sz##_update(uint##sz##_t *reg, \ register_t val, \ const mmio_info_t *info) \ { \ - unsigned long tmp = *reg; \ - \ - vreg_reg_update(&tmp, val, info->gpa & (offmask), \ - info->dabt.size); \ + unsigned int offset = info->gpa & (offmask); \ + uint##sz##_t mask = VREG_REG_MASK(info->dabt.size); \ + int shift = offset * 8; \ \ - *reg = tmp; \ + *reg &= ~(mask << shift); \ + *reg |= ((uint##sz##_t)val & mask) << shift; \ } \ \ static inline void vreg_reg##sz##_setbits(uint##sz##_t *reg, \ register_t bits, \ const mmio_info_t *info) \ { \ - unsigned long tmp = *reg; \ - \ - vreg_reg_setbits(&tmp, bits, info->gpa & (offmask), \ - info->dabt.size); \ + unsigned int offset = info->gpa & (offmask); \ + uint##sz##_t mask = VREG_REG_MASK(info->dabt.size); \ + int shift = offset * 8; \ \ - *reg = tmp; \ + *reg |= ((uint##sz##_t)bits & mask) << shift; \ } \ \ static inline void vreg_reg##sz##_clearbits(uint##sz##_t *reg, \ register_t bits, \ const mmio_info_t *info) \ { \ - unsigned long tmp = *reg; \ + unsigned int offset = info->gpa & (offmask); \ + uint##sz##_t mask = VREG_REG_MASK(info->dabt.size); \ + int shift = offset * 8; \ \ - vreg_reg_clearbits(&tmp, bits, info->gpa & (offmask), \ - info->dabt.size); \ - \ - *reg = tmp; \ + *reg &= ~(((uint##sz##_t)bits & mask) << shift); \ } -/* - * 64 bits registers are only supported on platform with 64-bit long. - * This is also allow us to optimize the 32 bit case by using - * unsigned long rather than uint64_t - */ -#if BITS_PER_LONG == 64 -VREG_REG_HELPERS(64, 0x7); -#endif VREG_REG_HELPERS(32, 0x3); +VREG_REG_HELPERS(64, 0x7); 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pr=C From: Ayan Kumar Halder To: CC: , , , , , , Ayan Kumar Halder Subject: [XEN v2 04/12] xen/Arm: vGICv3: Adapt emulation of GICR_TYPER for AArch32 Date: Mon, 31 Oct 2022 15:13:18 +0000 Message-ID: <20221031151326.22634-5-ayankuma@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221031151326.22634-1-ayankuma@amd.com> References: <20221031151326.22634-1-ayankuma@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT037:EE_|DM4PR12MB7693:EE_ X-MS-Office365-Filtering-Correlation-Id: e56154ff-efbd-46f4-d190-08dabb528c47 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: zoKfpl6yxS7d8XCNz/5HNEqxpTVgr2uL4pDaEC7r313hUyIunG5TRnY/+ulSkZ8w4Q0DuiMo5A/9zAt8KDl8EhqvoOfVJ5gvCS+KStrg0IA+fmy3h+NB7u3EjqUSD+xkfBpN8mgyJeMy+7jVkfPd16OJ1502juJgXMUr6AExsY3erZQCRPMp7PRkkJDjODVTgz0aSqwMZJdpHI40rClKbKwkqIExYBmnmxjgMCSEz3W7Q/8Qusv5vcIoP7Mxnk+Y5C3ciGKlNus2R4s7PvuJqJsnLeOMYvMIcZmAz2DZbZgzXMJZ4g4dx9BqwVpxVgqmzYne40Mg2tmd8NXqUbhsZKPmEn9DpghkABo/fJfJI/csY3aphkPddGvT8Sd7JXcybq6XbuGgMv53D7b7avx92/8m+I2UTt3cgxzzQ6CDtu7CH50jLXl/obBN/ffobr1pa1BMl6RheNVrXUfhN03P+QijxmxtNaHowN5RIiWsYQDt0ryC2BV6PkSnbQy8bf2+Qjsrky271ZWo6t3M+mwXSjbM5JoqjRKbe/rjBD9UF5MBvqzSY9XHmHliWCHj/OMmyMLpX9Gb2wijWCox1EDzBf414Zjo3Od2qFS4+vPAPfMkn+RF+SgxtjT/gYZIrDeJMj2hJhMr7jxCAwqBzmuwizx/nzGicByxlpD4Tyx+stGYlkSwAPKqM9yuJjNOlrgJ812Xf398tAUwGBmY8mNUgt8N4c2+ZgcScKRjCIRGtVlTLIlwAInfCnLgLD+9Lwtx5+5WGdHSpOsZqbBOZTvJOjFhR9jqpvyIfJn2oM02lS3IRckZPyuikNnk+UQlC2Up X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(346002)(376002)(39860400002)(136003)(396003)(451199015)(46966006)(36840700001)(40470700004)(54906003)(356005)(478600001)(1076003)(82740400003)(2906002)(81166007)(186003)(6916009)(6666004)(36756003)(316002)(41300700001)(82310400005)(336012)(70586007)(4326008)(8676002)(70206006)(40460700003)(8936002)(26005)(36860700001)(5660300002)(2616005)(47076005)(83380400001)(426003)(40480700001)(36900700001);DIR:OUT;SFP:1101; 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This is to enable left shifts for Aarch32 so that one can extract affinity bits. This is then assigned to 'typer' so that the affinity bits form the upper 32 bits. Refer Arm IHI 0069H ID020922, The upper 32 bits of GICR_TYPER represent the affinity whereas the lower 32 bits represent the other bits (eg processor number, etc). Signed-off-by: Ayan Kumar Halder --- Changes from :- 1. v1 - Assigned v->arch.vmpidr to "uint64_t vmpdir". Then, we can use MPIDR_AFFINITY_LEVEL macros to extract the affinity value. xen/arch/arm/vgic-v3.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/xen/arch/arm/vgic-v3.c b/xen/arch/arm/vgic-v3.c index 3f4509dcd3..e5e6f2c573 100644 --- a/xen/arch/arm/vgic-v3.c +++ b/xen/arch/arm/vgic-v3.c @@ -191,13 +191,15 @@ static int __vgic_v3_rdistr_rd_mmio_read(struct vcpu *v, mmio_info_t *info, case VREG64(GICR_TYPER): { uint64_t typer, aff; + uint64_t vmpidr = v->arch.vmpidr; if ( !vgic_reg64_check_access(dabt) ) goto bad_width; - aff = (MPIDR_AFFINITY_LEVEL(v->arch.vmpidr, 3) << 56 | - MPIDR_AFFINITY_LEVEL(v->arch.vmpidr, 2) << 48 | - MPIDR_AFFINITY_LEVEL(v->arch.vmpidr, 1) << 40 | - MPIDR_AFFINITY_LEVEL(v->arch.vmpidr, 0) << 32); + aff = (MPIDR_AFFINITY_LEVEL(vmpidr, 3) << 56 | + MPIDR_AFFINITY_LEVEL(vmpidr, 2) << 48 | + MPIDR_AFFINITY_LEVEL(vmpidr, 1) << 40 | + MPIDR_AFFINITY_LEVEL(vmpidr, 0) << 32); typer = aff; + /* We use the VCPU ID as the redistributor ID in bits[23:8] */ typer |= v->vcpu_id << GICR_TYPER_PROC_NUM_SHIFT; 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pr=C From: Ayan Kumar Halder To: CC: , , , , , , Ayan Kumar Halder Subject: [XEN v2 05/12] xen/Arm: GICv3: Fix GICR_{PENDBASER, PROPBASER} emulation on 32-bit host Date: Mon, 31 Oct 2022 15:13:19 +0000 Message-ID: <20221031151326.22634-6-ayankuma@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221031151326.22634-1-ayankuma@amd.com> References: <20221031151326.22634-1-ayankuma@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT009:EE_|PH7PR12MB6587:EE_ X-MS-Office365-Filtering-Correlation-Id: 307c3c1e-15e8-4f41-aba9-08dabb528e23 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: TlK4wcFgSFOPXpOkrK2fIndMYOWSf1ZOelYbkcKkHcNePuXYuKO2U219YIBunza7jxV4y2Lr6lGaj93JJV/mx8tE/m7xckyJdkXg89ASK3JL1zR5h5fCapwfOpupOfSbhdwJqMDZBnl8EJdcGN9quRWKOuWNkDv9L7UqQaC4e1U1IuYneGjgTR2Hxj4WzRsvBu42MWeWe4WWR9WCqfsuWPvezrsy7mMa8vYg6QfBiz9bBjrx/1ChYap2bQGfWxRJK9tyQh8/Gp0O/lFVG5L+eZ+avrYAqkDYCKoKTtbEEGEXd8YMSesH1padbeJ6UolAjkeZ7uaujLIpciLaibEfyAAJb4wYq70PKL3b1AyOU/oe820voKeMBBl3V51S2puSn6j1p3BWq60DplHWeU+I/BIwZooU+tNyvyEMXyl4BnaR/RCQwl53NWqKV2wWZK60c2twSwT4A3wIa6IwCd7aQSvYOLwtJkuBMezFI2Q5rnH5WlRnmSXQf6iAUk3Erfs/HcycHTJ/I+I02hOtvfFluNqMMldIu9ueKZeIRgIFqA+ZkOj9ztxpYmjLMPCmAswjcwCGOL1vidsfg1hzCv69OKhBhQAovJCzmw+0VIHfJXg2jwjZZAuTQekWajvfOILJXJwBjBG+tjA8CYExVkjkUDBjrJSxPAs95anapA4sjENw8LTFKlz8qWT6bgr895QYwpNURmrXSy9ltJ2BJD70i1/yOcVhDSeaI1ecfoV++z/hiUPWdYbJ/KWIavrR1NnLWEKu5YpgJvmt9JifyXqtp+J7FAqOAa1n6fftCO/YDklWldqa/Klom0QOjmjrqajUt0ciq+oGbm8XZG5CQwkY7g== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(136003)(396003)(376002)(346002)(39860400002)(451199015)(40470700004)(36840700001)(46966006)(82740400003)(82310400005)(81166007)(356005)(26005)(40480700001)(41300700001)(40460700003)(4326008)(8936002)(478600001)(6916009)(36860700001)(5660300002)(966005)(8676002)(70206006)(6666004)(54906003)(70586007)(316002)(2616005)(186003)(36756003)(426003)(47076005)(83380400001)(336012)(1076003)(2906002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 Oct 2022 15:14:07.2292 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 307c3c1e-15e8-4f41-aba9-08dabb528e23 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT009.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6587 'unsigned long long' is defined as 64 bit across both aarch32 and aarch64. So, use 'ULL' for 64 bit word instead of UL which is 32 bits for aarch32. GICR_PENDBASER and GICR_PROPBASER both are 64 bit registers. Signed-off-by: Ayan Kumar Halder Reviewed-by: Michal Orzel Acked-by: Julien Grall --- Changes from - v1 - 1. Extract the bug fix for incorrect bit clearing (GICR_PENDBASER_PTZ) into a separate patch fix. https://patchwork.kernel.org/project/xen-devel/patch/20221027185555.46125-1-ayankuma@amd.com/ xen/arch/arm/include/asm/gic_v3_defs.h | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/xen/arch/arm/include/asm/gic_v3_defs.h b/xen/arch/arm/include/asm/gic_v3_defs.h index 728e28d5e5..48a1bc401e 100644 --- a/xen/arch/arm/include/asm/gic_v3_defs.h +++ b/xen/arch/arm/include/asm/gic_v3_defs.h @@ -134,15 +134,15 @@ #define GICR_PROPBASER_OUTER_CACHEABILITY_SHIFT 56 #define GICR_PROPBASER_OUTER_CACHEABILITY_MASK \ - (7UL << GICR_PROPBASER_OUTER_CACHEABILITY_SHIFT) + (7ULL << GICR_PROPBASER_OUTER_CACHEABILITY_SHIFT) #define GICR_PROPBASER_SHAREABILITY_SHIFT 10 #define GICR_PROPBASER_SHAREABILITY_MASK \ - (3UL << GICR_PROPBASER_SHAREABILITY_SHIFT) + (3ULL << GICR_PROPBASER_SHAREABILITY_SHIFT) #define GICR_PROPBASER_INNER_CACHEABILITY_SHIFT 7 #define GICR_PROPBASER_INNER_CACHEABILITY_MASK \ - (7UL << GICR_PROPBASER_INNER_CACHEABILITY_SHIFT) + (7ULL << GICR_PROPBASER_INNER_CACHEABILITY_SHIFT) #define GICR_PROPBASER_RES0_MASK \ - (GENMASK(63, 59) | GENMASK(55, 52) | GENMASK(6, 5)) + (GENMASK_ULL(63, 59) | GENMASK_ULL(55, 52) | GENMASK_ULL(6, 5)) #define GICR_PENDBASER_SHAREABILITY_SHIFT 10 #define GICR_PENDBASER_INNER_CACHEABILITY_SHIFT 7 @@ -152,11 +152,11 @@ #define GICR_PENDBASER_INNER_CACHEABILITY_MASK \ (7UL << GICR_PENDBASER_INNER_CACHEABILITY_SHIFT) #define GICR_PENDBASER_OUTER_CACHEABILITY_MASK \ - (7UL << GICR_PENDBASER_OUTER_CACHEABILITY_SHIFT) -#define GICR_PENDBASER_PTZ BIT(62, UL) + (7ULL << GICR_PENDBASER_OUTER_CACHEABILITY_SHIFT) +#define GICR_PENDBASER_PTZ BIT(62, ULL) #define GICR_PENDBASER_RES0_MASK \ - (BIT(63, UL) | GENMASK(61, 59) | GENMASK(55, 52) | \ - GENMASK(15, 12) | GENMASK(6, 0)) + (BIT(63, ULL) | GENMASK_ULL(61, 59) | GENMASK_ULL(55, 52) | \ + GENMASK_ULL(15, 12) | GENMASK_ULL(6, 0)) #define DEFAULT_PMR_VALUE 0xff From patchwork Mon Oct 31 15:13:20 2022 Content-Type: text/plain; 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pr=C From: Ayan Kumar Halder To: CC: , , , , , , Ayan Kumar Halder Subject: [XEN v2 06/12] xen/Arm: vGICv3: Fix emulation of ICC_SGI1R on AArch32 Date: Mon, 31 Oct 2022 15:13:20 +0000 Message-ID: <20221031151326.22634-7-ayankuma@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221031151326.22634-1-ayankuma@amd.com> References: <20221031151326.22634-1-ayankuma@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT009:EE_|MW4PR12MB5604:EE_ X-MS-Office365-Filtering-Correlation-Id: d3368698-a592-4bf3-fdba-08dabb528f1d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: u2zsv+y3hAmCawjxYt94RzsDAytQR4BT5ImykO+zdI1E3ULKBltKQd/WbkXj9yORxH5BTlM69LXuY8tk+xrft47U39Q4hRVIMqVYQcVT0g3adhIpaBBYtjMN0kiU/GlTph7JShBIO/3MGzgWr3ovCS19YQZFTbcT8Ryd0hGGXxkxnTOTycUs5sp/WiTvOimvXikR+CVtv8+95EPlfmOMAV6jgDZqDkjdNgd0CsUKDX9u19PCRxN6zhWQ96oyk77RjD1Mf7C/AVGLVUuvK8m7I7iOkyINw//v4JhKzz1bc62COwHJzK0tvgjUtxz8HzkKHYf1JKnhajQ1HUsNkNe3QQ0jVAtYrE8VuaZv8UW3mNeE7z8EKiT1OZ49YpiMmEwRh7ZW0EtPd8LkuwMa9jD2cmX8/C59OITlfEWCIeA9a3A/v+9vNrcIg71twMTj4O0CXwJ7vitmWi0ViPccxGiKkl3xKowtnSiSv21muL+XqYhyCqCa8k98DHaaWFLuEkt2Tp79NOiToPY+l8fTAKhfnYeQKEotBz4JvMry+S9u9NYPwU06/UXr9fx/nCuA+XdoKIwPINAjD08s6S650lQukIMCb3vig2ZoXMpLsc+h2FGIvGmY9pEGYKV6TY9LcICvCqJAX6yOOoQjlVLl7PsNbh6xZt6AKsESNz2OviK0M07+ycHre1kU5nm5b0VZ0QOpC3DeZdKRAYcahncLe59tGPGXNurEmDBp2Kbns1KgkEoajcukABX49ljp6uxmHr204J0N2Q3YhnnJl/Ngy1ayb08MzEF0a00em9uhKn4symA= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(396003)(136003)(376002)(346002)(39860400002)(451199015)(46966006)(40470700004)(36840700001)(47076005)(426003)(8936002)(82740400003)(4326008)(83380400001)(5660300002)(4744005)(40460700003)(316002)(2906002)(36756003)(478600001)(70586007)(6666004)(40480700001)(6916009)(54906003)(82310400005)(2616005)(41300700001)(1076003)(336012)(186003)(356005)(26005)(81166007)(8676002)(70206006)(36860700001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 Oct 2022 15:14:08.8853 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d3368698-a592-4bf3-fdba-08dabb528f1d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT009.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB5604 Refer Arm IHI 0069H ID020922, 12.5.23, ICC_SGI1R is a 64 bit register on Aarch32 systems. Thus, the prototype needs to change to reflect this. The reason being 'register_t' is defined as 'u32' on AArch32. Signed-off-by: Ayan Kumar Halder Reviewed-by: Michal Orzel Acked-by: Julien Grall --- Changes from :- v1 - 1. Updated the commit message. xen/arch/arm/vgic-v3.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/xen/arch/arm/vgic-v3.c b/xen/arch/arm/vgic-v3.c index e5e6f2c573..1bae76a1e1 100644 --- a/xen/arch/arm/vgic-v3.c +++ b/xen/arch/arm/vgic-v3.c @@ -1477,7 +1477,7 @@ write_reserved: return 1; } -static bool vgic_v3_to_sgi(struct vcpu *v, register_t sgir) +static bool vgic_v3_to_sgi(struct vcpu *v, uint64_t sgir) { int virq; int irqmode; From patchwork Mon Oct 31 15:13:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ayan Kumar Halder X-Patchwork-Id: 13025993 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7B261FA3741 for ; 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bh=BI24R+ivZImTUK+YWSPNKctw7x9+YZOXWotaP6tXxI4=; b=qSAYQKPoPDoSPuZGfW1Oqwq2qqwKvNlAKZ5anGv7rkocDc4xpcsGooUzWOLe/fHF5AH28ghhqHiCqZI9bnf+qZSK+Ne2KRWe60pB0B86gBzgZhotnSSQlHHG6P51pOPCjGKHhB+MvPPfrEyLDX4kM1CFCY3Q6sSGCplRLTt/BjM= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C From: Ayan Kumar Halder To: CC: , , , , , , Ayan Kumar Halder Subject: [XEN v2 07/12] xen/Arm: GICv3: Define ICH_LR_EL2 on AArch32 Date: Mon, 31 Oct 2022 15:13:21 +0000 Message-ID: <20221031151326.22634-8-ayankuma@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221031151326.22634-1-ayankuma@amd.com> References: <20221031151326.22634-1-ayankuma@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT098:EE_|BY5PR12MB4321:EE_ X-MS-Office365-Filtering-Correlation-Id: 6e574610-819b-45c6-c575-08dabb529060 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 Oct 2022 15:14:10.8757 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6e574610-819b-45c6-c575-08dabb529060 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT098.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4321 Refer "Arm IHI 0069H ID020922", 12.4.6, Interrupt Controller List Registers AArch64 System register ICH_LR_EL2 bits [31:0] are architecturally mapped to AArch32 System register ICH_LR[31:0]. AArch64 System register ICH_LR_EL2 bits [63:32] are architecturally mapped to AArch32 System register ICH_LRC[31:0]. Defined ICH_LR<0...15>_EL2 and ICH_LRC<0...15>_EL2 for Aarch32. For AArch32, the link register is stored as :- (((uint64_t) ICH_LRC<0...15>_EL2) << 32) | ICH_LR<0...15>_EL2 Also, ICR_LR macros need to be modified as ULL is 64 bits for AArch32 and AArch64. Signed-off-by: Ayan Kumar Halder --- Changes from :- v1 - 1. Moved the coproc register definitions to asm/cpregs.h. 2. Use GENMASK(31, 0) to represent 0xFFFFFFFF 3. Use READ_CP32()/WRITE_CP32() instead of READ_SYSREG()/WRITE_SYSREG(). 4. Multi-line macro definitions should be enclosed within ({ }). xen/arch/arm/gic-v3.c | 132 +++++++++++------------ xen/arch/arm/include/asm/arm32/sysregs.h | 17 +++ xen/arch/arm/include/asm/arm64/sysregs.h | 3 + xen/arch/arm/include/asm/cpregs.h | 42 ++++++++ xen/arch/arm/include/asm/gic_v3_defs.h | 6 +- 5 files changed, 131 insertions(+), 69 deletions(-) diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c index 018fa0dfa0..8b4b168e78 100644 --- a/xen/arch/arm/gic-v3.c +++ b/xen/arch/arm/gic-v3.c @@ -73,37 +73,37 @@ static inline void gicv3_save_lrs(struct vcpu *v) switch ( gicv3_info.nr_lrs ) { case 16: - v->arch.gic.v3.lr[15] = READ_SYSREG(ICH_LR15_EL2); + v->arch.gic.v3.lr[15] = READ_SYSREG_LR(15); case 15: - v->arch.gic.v3.lr[14] = READ_SYSREG(ICH_LR14_EL2); + v->arch.gic.v3.lr[14] = READ_SYSREG_LR(14); case 14: - v->arch.gic.v3.lr[13] = READ_SYSREG(ICH_LR13_EL2); + v->arch.gic.v3.lr[13] = READ_SYSREG_LR(13); case 13: - v->arch.gic.v3.lr[12] = READ_SYSREG(ICH_LR12_EL2); + v->arch.gic.v3.lr[12] = READ_SYSREG_LR(12); case 12: - v->arch.gic.v3.lr[11] = READ_SYSREG(ICH_LR11_EL2); + v->arch.gic.v3.lr[11] = READ_SYSREG_LR(11); case 11: - v->arch.gic.v3.lr[10] = READ_SYSREG(ICH_LR10_EL2); + v->arch.gic.v3.lr[10] = READ_SYSREG_LR(10); case 10: - v->arch.gic.v3.lr[9] = READ_SYSREG(ICH_LR9_EL2); + v->arch.gic.v3.lr[9] = READ_SYSREG_LR(9); case 9: - v->arch.gic.v3.lr[8] = READ_SYSREG(ICH_LR8_EL2); + v->arch.gic.v3.lr[8] = READ_SYSREG_LR(8); case 8: - v->arch.gic.v3.lr[7] = READ_SYSREG(ICH_LR7_EL2); + v->arch.gic.v3.lr[7] = READ_SYSREG_LR(7); case 7: - v->arch.gic.v3.lr[6] = READ_SYSREG(ICH_LR6_EL2); + v->arch.gic.v3.lr[6] = READ_SYSREG_LR(6); case 6: - v->arch.gic.v3.lr[5] = READ_SYSREG(ICH_LR5_EL2); + v->arch.gic.v3.lr[5] = READ_SYSREG_LR(5); case 5: - v->arch.gic.v3.lr[4] = READ_SYSREG(ICH_LR4_EL2); + v->arch.gic.v3.lr[4] = READ_SYSREG_LR(4); case 4: - v->arch.gic.v3.lr[3] = READ_SYSREG(ICH_LR3_EL2); + v->arch.gic.v3.lr[3] = READ_SYSREG_LR(3); case 3: - v->arch.gic.v3.lr[2] = READ_SYSREG(ICH_LR2_EL2); + v->arch.gic.v3.lr[2] = READ_SYSREG_LR(2); case 2: - v->arch.gic.v3.lr[1] = READ_SYSREG(ICH_LR1_EL2); + v->arch.gic.v3.lr[1] = READ_SYSREG_LR(1); case 1: - v->arch.gic.v3.lr[0] = READ_SYSREG(ICH_LR0_EL2); + v->arch.gic.v3.lr[0] = READ_SYSREG_LR(0); break; default: BUG(); @@ -120,37 +120,37 @@ static inline void gicv3_restore_lrs(const struct vcpu *v) switch ( gicv3_info.nr_lrs ) { case 16: - WRITE_SYSREG(v->arch.gic.v3.lr[15], ICH_LR15_EL2); + WRITE_SYSREG_LR(15, v->arch.gic.v3.lr[15]); case 15: - WRITE_SYSREG(v->arch.gic.v3.lr[14], ICH_LR14_EL2); + WRITE_SYSREG_LR(14, v->arch.gic.v3.lr[14]); case 14: - WRITE_SYSREG(v->arch.gic.v3.lr[13], ICH_LR13_EL2); + WRITE_SYSREG_LR(13, v->arch.gic.v3.lr[13]); case 13: - WRITE_SYSREG(v->arch.gic.v3.lr[12], ICH_LR12_EL2); + WRITE_SYSREG_LR(12, v->arch.gic.v3.lr[12]); case 12: - WRITE_SYSREG(v->arch.gic.v3.lr[11], ICH_LR11_EL2); + WRITE_SYSREG_LR(11, v->arch.gic.v3.lr[11]); case 11: - WRITE_SYSREG(v->arch.gic.v3.lr[10], ICH_LR10_EL2); + WRITE_SYSREG_LR(10, v->arch.gic.v3.lr[10]); case 10: - WRITE_SYSREG(v->arch.gic.v3.lr[9], ICH_LR9_EL2); + WRITE_SYSREG_LR(9, v->arch.gic.v3.lr[9]); case 9: - WRITE_SYSREG(v->arch.gic.v3.lr[8], ICH_LR8_EL2); + WRITE_SYSREG_LR(8, v->arch.gic.v3.lr[8]); case 8: - WRITE_SYSREG(v->arch.gic.v3.lr[7], ICH_LR7_EL2); + WRITE_SYSREG_LR(7, v->arch.gic.v3.lr[7]); case 7: - WRITE_SYSREG(v->arch.gic.v3.lr[6], ICH_LR6_EL2); + WRITE_SYSREG_LR(6, v->arch.gic.v3.lr[6]); case 6: - WRITE_SYSREG(v->arch.gic.v3.lr[5], ICH_LR5_EL2); + WRITE_SYSREG_LR(5, v->arch.gic.v3.lr[5]); case 5: - WRITE_SYSREG(v->arch.gic.v3.lr[4], ICH_LR4_EL2); + WRITE_SYSREG_LR(4, v->arch.gic.v3.lr[4]); case 4: - WRITE_SYSREG(v->arch.gic.v3.lr[3], ICH_LR3_EL2); + WRITE_SYSREG_LR(3, v->arch.gic.v3.lr[3]); case 3: - WRITE_SYSREG(v->arch.gic.v3.lr[2], ICH_LR2_EL2); + WRITE_SYSREG_LR(2, v->arch.gic.v3.lr[2]); case 2: - WRITE_SYSREG(v->arch.gic.v3.lr[1], ICH_LR1_EL2); + WRITE_SYSREG_LR(1, v->arch.gic.v3.lr[1]); case 1: - WRITE_SYSREG(v->arch.gic.v3.lr[0], ICH_LR0_EL2); + WRITE_SYSREG_LR(0, v->arch.gic.v3.lr[0]); break; default: BUG(); @@ -161,22 +161,22 @@ static uint64_t gicv3_ich_read_lr(int lr) { switch ( lr ) { - case 0: return READ_SYSREG(ICH_LR0_EL2); - case 1: return READ_SYSREG(ICH_LR1_EL2); - case 2: return READ_SYSREG(ICH_LR2_EL2); - case 3: return READ_SYSREG(ICH_LR3_EL2); - case 4: return READ_SYSREG(ICH_LR4_EL2); - case 5: return READ_SYSREG(ICH_LR5_EL2); - case 6: return READ_SYSREG(ICH_LR6_EL2); - case 7: return READ_SYSREG(ICH_LR7_EL2); - case 8: return READ_SYSREG(ICH_LR8_EL2); - case 9: return READ_SYSREG(ICH_LR9_EL2); - case 10: return READ_SYSREG(ICH_LR10_EL2); - case 11: return READ_SYSREG(ICH_LR11_EL2); - case 12: return READ_SYSREG(ICH_LR12_EL2); - case 13: return READ_SYSREG(ICH_LR13_EL2); - case 14: return READ_SYSREG(ICH_LR14_EL2); - case 15: return READ_SYSREG(ICH_LR15_EL2); + case 0: return READ_SYSREG_LR(0); + case 1: return READ_SYSREG_LR(1); + case 2: return READ_SYSREG_LR(2); + case 3: return READ_SYSREG_LR(3); + case 4: return READ_SYSREG_LR(4); + case 5: return READ_SYSREG_LR(5); + case 6: return READ_SYSREG_LR(6); + case 7: return READ_SYSREG_LR(7); + case 8: return READ_SYSREG_LR(8); + case 9: return READ_SYSREG_LR(9); + case 10: return READ_SYSREG_LR(10); + case 11: return READ_SYSREG_LR(11); + case 12: return READ_SYSREG_LR(12); + case 13: return READ_SYSREG_LR(13); + case 14: return READ_SYSREG_LR(14); + case 15: return READ_SYSREG_LR(15); default: BUG(); } @@ -187,52 +187,52 @@ static void gicv3_ich_write_lr(int lr, uint64_t val) switch ( lr ) { case 0: - WRITE_SYSREG(val, ICH_LR0_EL2); + WRITE_SYSREG_LR(0, val); break; case 1: - WRITE_SYSREG(val, ICH_LR1_EL2); + WRITE_SYSREG_LR(1, val); break; case 2: - WRITE_SYSREG(val, ICH_LR2_EL2); + WRITE_SYSREG_LR(2, val); break; case 3: - WRITE_SYSREG(val, ICH_LR3_EL2); + WRITE_SYSREG_LR(3, val); break; case 4: - WRITE_SYSREG(val, ICH_LR4_EL2); + WRITE_SYSREG_LR(4, val); break; case 5: - WRITE_SYSREG(val, ICH_LR5_EL2); + WRITE_SYSREG_LR(5, val); break; case 6: - WRITE_SYSREG(val, ICH_LR6_EL2); + WRITE_SYSREG_LR(6, val); break; case 7: - WRITE_SYSREG(val, ICH_LR7_EL2); + WRITE_SYSREG_LR(7, val); break; case 8: - WRITE_SYSREG(val, ICH_LR8_EL2); + WRITE_SYSREG_LR(8, val); break; case 9: - WRITE_SYSREG(val, ICH_LR9_EL2); + WRITE_SYSREG_LR(9, val); break; case 10: - WRITE_SYSREG(val, ICH_LR10_EL2); + WRITE_SYSREG_LR(10, val); break; case 11: - WRITE_SYSREG(val, ICH_LR11_EL2); + WRITE_SYSREG_LR(11, val); break; case 12: - WRITE_SYSREG(val, ICH_LR12_EL2); + WRITE_SYSREG_LR(12, val); break; case 13: - WRITE_SYSREG(val, ICH_LR13_EL2); + WRITE_SYSREG_LR(13, val); break; case 14: - WRITE_SYSREG(val, ICH_LR14_EL2); + WRITE_SYSREG_LR(14, val); break; case 15: - WRITE_SYSREG(val, ICH_LR15_EL2); + WRITE_SYSREG_LR(15, val); break; default: return; @@ -417,12 +417,12 @@ static void gicv3_dump_state(const struct vcpu *v) if ( v == current ) { for ( i = 0; i < gicv3_info.nr_lrs; i++ ) - printk(" HW_LR[%d]=%lx\n", i, gicv3_ich_read_lr(i)); + printk(" HW_LR[%d]=%llx\n", i, gicv3_ich_read_lr(i)); } else { for ( i = 0; i < gicv3_info.nr_lrs; i++ ) - printk(" VCPU_LR[%d]=%lx\n", i, v->arch.gic.v3.lr[i]); + printk(" VCPU_LR[%d]=%llx\n", i, v->arch.gic.v3.lr[i]); } } diff --git a/xen/arch/arm/include/asm/arm32/sysregs.h b/xen/arch/arm/include/asm/arm32/sysregs.h index 6841d5de43..8a9a014bef 100644 --- a/xen/arch/arm/include/asm/arm32/sysregs.h +++ b/xen/arch/arm/include/asm/arm32/sysregs.h @@ -62,6 +62,23 @@ #define READ_SYSREG(R...) READ_SYSREG32(R) #define WRITE_SYSREG(V, R...) WRITE_SYSREG32(V, R) +#define ICH_LR_REG(INDEX) ICH_LR ## INDEX ## _EL2 +#define ICH_LRC_REG(INDEX) ICH_LRC ## INDEX ## _EL2 + +#define READ_SYSREG_LR(INDEX) ({ \ + uint64_t _val; \ + uint32_t _lrc = READ_CP32(ICH_LRC_REG(INDEX)); \ + uint32_t _lr = READ_CP32(ICH_LR_REG(INDEX)); \ + \ + _val = ((uint64_t) _lrc << 32) | _lr; \ + _val; }) + +#define WRITE_SYSREG_LR(INDEX, V) ({ \ + uint64_t _val = (V); \ + WRITE_CP32(_val & GENMASK(31, 0), ICH_LR_REG(INDEX)); \ + WRITE_CP32(_val >> 32, ICH_LRC_REG(INDEX)); \ +}); + /* MVFR2 is not defined on ARMv7 */ #define MVFR2_MAYBE_UNDEFINED diff --git a/xen/arch/arm/include/asm/arm64/sysregs.h b/xen/arch/arm/include/asm/arm64/sysregs.h index 54670084c3..353f0eea29 100644 --- a/xen/arch/arm/include/asm/arm64/sysregs.h +++ b/xen/arch/arm/include/asm/arm64/sysregs.h @@ -471,6 +471,9 @@ #define READ_SYSREG(name) READ_SYSREG64(name) #define WRITE_SYSREG(v, name) WRITE_SYSREG64(v, name) +#define ICH_LR_REG(index) ICH_LR ## index ## _EL2 +#define WRITE_SYSREG_LR(index, v) WRITE_SYSREG(v, ICH_LR_REG(index)) +#define READ_SYSREG_LR(index) READ_SYSREG(ICH_LR_REG(index)) #endif /* _ASM_ARM_ARM64_SYSREGS_H */ diff --git a/xen/arch/arm/include/asm/cpregs.h b/xen/arch/arm/include/asm/cpregs.h index 6daf2b1a30..4421dd49ac 100644 --- a/xen/arch/arm/include/asm/cpregs.h +++ b/xen/arch/arm/include/asm/cpregs.h @@ -362,6 +362,48 @@ #define MVFR0_EL1 MVFR0 #define MVFR1_EL1 MVFR1 #define MVFR2_EL1 MVFR2 + +#define ___CP32(a,b,c,d,e) a,b,c,d,e +#define __LR0_EL2(x) ___CP32(p15,4,c12,c12,x) +#define __LR8_EL2(x) ___CP32(p15,4,c12,c13,x) + +#define __LRC0_EL2(x) ___CP32(p15,4,c12,c14,x) +#define __LRC8_EL2(x) ___CP32(p15,4,c12,c15,x) + +#define ICH_LR0_EL2 __LR0_EL2(0) +#define ICH_LR1_EL2 __LR0_EL2(1) +#define ICH_LR2_EL2 __LR0_EL2(2) +#define ICH_LR3_EL2 __LR0_EL2(3) +#define ICH_LR4_EL2 __LR0_EL2(4) +#define ICH_LR5_EL2 __LR0_EL2(5) +#define ICH_LR6_EL2 __LR0_EL2(6) +#define ICH_LR7_EL2 __LR0_EL2(7) +#define ICH_LR8_EL2 __LR8_EL2(0) +#define ICH_LR9_EL2 __LR8_EL2(1) +#define ICH_LR10_EL2 __LR8_EL2(2) +#define ICH_LR11_EL2 __LR8_EL2(3) +#define ICH_LR12_EL2 __LR8_EL2(4) +#define ICH_LR13_EL2 __LR8_EL2(5) +#define ICH_LR14_EL2 __LR8_EL2(6) +#define ICH_LR15_EL2 __LR8_EL2(7) + +#define ICH_LRC0_EL2 __LRC0_EL2(0) +#define ICH_LRC1_EL2 __LRC0_EL2(1) +#define ICH_LRC2_EL2 __LRC0_EL2(2) +#define ICH_LRC3_EL2 __LRC0_EL2(3) +#define ICH_LRC4_EL2 __LRC0_EL2(4) +#define ICH_LRC5_EL2 __LRC0_EL2(5) +#define ICH_LRC6_EL2 __LRC0_EL2(6) +#define ICH_LRC7_EL2 __LRC0_EL2(7) +#define ICH_LRC8_EL2 __LRC8_EL2(0) +#define ICH_LRC9_EL2 __LRC8_EL2(1) +#define ICH_LRC10_EL2 __LRC8_EL2(2) +#define ICH_LRC11_EL2 __LRC8_EL2(3) +#define ICH_LRC12_EL2 __LRC8_EL2(4) +#define ICH_LRC13_EL2 __LRC8_EL2(5) +#define ICH_LRC14_EL2 __LRC8_EL2(6) +#define ICH_LRC15_EL2 __LRC8_EL2(7) + #endif #endif diff --git a/xen/arch/arm/include/asm/gic_v3_defs.h b/xen/arch/arm/include/asm/gic_v3_defs.h index 48a1bc401e..87115f8b25 100644 --- a/xen/arch/arm/include/asm/gic_v3_defs.h +++ b/xen/arch/arm/include/asm/gic_v3_defs.h @@ -185,9 +185,9 @@ #define ICH_LR_HW_SHIFT 61 #define ICH_LR_GRP_MASK 0x1 #define ICH_LR_GRP_SHIFT 60 -#define ICH_LR_MAINTENANCE_IRQ (1UL<<41) -#define ICH_LR_GRP1 (1UL<<60) -#define ICH_LR_HW (1UL<<61) +#define ICH_LR_MAINTENANCE_IRQ (1ULL<<41) +#define ICH_LR_GRP1 (1ULL<<60) +#define ICH_LR_HW (1ULL<<61) #define ICH_VTR_NRLRGS 0x3f #define ICH_VTR_PRIBITS_MASK 0x7 From patchwork Mon Oct 31 15:13:22 2022 Content-Type: text/plain; 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pr=C From: Ayan Kumar Halder To: CC: , , , , , , Ayan Kumar Halder Subject: [XEN v2 08/12] xen/Arm: GICv3: Define ICH_AP0R and ICH_AP1R for AArch32 Date: Mon, 31 Oct 2022 15:13:22 +0000 Message-ID: <20221031151326.22634-9-ayankuma@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221031151326.22634-1-ayankuma@amd.com> References: <20221031151326.22634-1-ayankuma@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT083:EE_|MN2PR12MB4269:EE_ X-MS-Office365-Filtering-Correlation-Id: 41a2843c-d5d2-4c25-76c8-08dabb52919b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: LUy5XsyIYlw1JIDWF55/M47+iXBehf3BfeMvc22vii0DQSz4tplkBrcaVchEQnBlVxRdt8XS+tJZutIfSHy6nLyhHV9VScfWRwxQZq9kySd0Xp90pKQVuki+kFf3h1j1um13VQ3nqiInFw7tUjX1T8ilQ84iIoBaBsONcLbiM4CdB1jYLMZI0B1y9JXGTblh6od9wov1QLNscxbfIkNERdal/qiAsXIYef4NrbND+AzGhoHP0gQbw8X3djtytoHaUhnUyDQRwxt0hrgUoYnyeuMNDW4IkzXTulLxXqG7KcieX/CxZpggXKs+EJ2EJ/5n3Rp8moy/1NbSxnEWw3r2xMPdDJjaN3zt0M7sod0N8rRbm74wCba8i1Ke3ja7TJfz0+v/x88NOWjRhD29dlJ2RYVUmdBj8q+4TCH6t84MwuVtY4qw/wFJAQvBTuoE634WNFbko7r0DezHHk5YwmGxIt8hOf9xoCV+ulZPv8cyNjfRNF7OrZMZaNDDE1WV9vWWR8QAAHtt/Wd+8vbyQgic0M1OMqhBK/cEpYTZdZcJBeMFEP8Elvay0Hu5KXOUOaPqtjN/nEgT7/TGYZ7nzP/SpTr+AqVZqCEqEeNSlZ/JB5b8U9EqPeMMMQOAvKTocfClO46+XPr2adLfKJNoBausCCX64lKef3lQVWoxqQtQuzyJAl66KkJ7qHF2cdOkiTfuLlfKTFjNHzBr0RF4i5CXb8F1PUxGeyZaO9UnLGs0g4XMc5QvNSewU2s3d9soiVKdCKHALC8buEwBFzYdb09sJsW0+LeVjHkZWmj//yVIRLAtnEQPhX3guqeuxKEpeCO0 X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(376002)(39860400002)(136003)(346002)(396003)(451199015)(40470700004)(46966006)(36840700001)(478600001)(6666004)(82310400005)(316002)(54906003)(26005)(6916009)(40480700001)(36860700001)(82740400003)(47076005)(2616005)(336012)(186003)(1076003)(36756003)(83380400001)(356005)(81166007)(40460700003)(426003)(2906002)(4326008)(8676002)(70586007)(70206006)(41300700001)(8936002)(5660300002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 Oct 2022 15:14:12.9381 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 41a2843c-d5d2-4c25-76c8-08dabb52919b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT083.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4269 Refer "Arm IHI 0069H ID020922", 12.7.1 - Interrupt Controller Hyp Active Priorities Group0 Registers 0-3 12.7.2 - Interrupt Controller Hyp Active Priorities Group1 Registers 0-3 Signed-off-by: Ayan Kumar Halder Reviewed-by: Michal Orzel Acked-by: Julien Grall --- Changes from :- v1 - 1. Moved coproc register definition to asm/cpregs.h. xen/arch/arm/include/asm/arm32/sysregs.h | 1 - xen/arch/arm/include/asm/cpregs.h | 11 +++++++++++ 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/xen/arch/arm/include/asm/arm32/sysregs.h b/xen/arch/arm/include/asm/arm32/sysregs.h index 8a9a014bef..1b2915a526 100644 --- a/xen/arch/arm/include/asm/arm32/sysregs.h +++ b/xen/arch/arm/include/asm/arm32/sysregs.h @@ -81,7 +81,6 @@ /* MVFR2 is not defined on ARMv7 */ #define MVFR2_MAYBE_UNDEFINED - #endif /* __ASSEMBLY__ */ #endif /* __ASM_ARM_ARM32_SYSREGS_H */ diff --git a/xen/arch/arm/include/asm/cpregs.h b/xen/arch/arm/include/asm/cpregs.h index 4421dd49ac..bfabee0bc3 100644 --- a/xen/arch/arm/include/asm/cpregs.h +++ b/xen/arch/arm/include/asm/cpregs.h @@ -404,6 +404,17 @@ #define ICH_LRC14_EL2 __LRC8_EL2(6) #define ICH_LRC15_EL2 __LRC8_EL2(7) +#define __AP0Rx_EL2(x) ___CP32(p15,4,c12,c8,x) +#define ICH_AP0R0_EL2 __AP0Rx_EL2(0) +#define ICH_AP0R1_EL2 __AP0Rx_EL2(1) +#define ICH_AP0R2_EL2 __AP0Rx_EL2(2) +#define ICH_AP0R3_EL2 __AP0Rx_EL2(3) + +#define __AP1Rx_EL2(x) ___CP32(p15,4,c12,c9,x) +#define ICH_AP1R0_EL2 __AP1Rx_EL2(0) +#define ICH_AP1R1_EL2 __AP1Rx_EL2(1) +#define ICH_AP1R2_EL2 __AP1Rx_EL2(2) +#define ICH_AP1R3_EL2 __AP1Rx_EL2(3) #endif #endif From patchwork Mon Oct 31 15:13:23 2022 Content-Type: text/plain; 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pr=C From: Ayan Kumar Halder To: CC: , , , , , , Ayan Kumar Halder Subject: [XEN v2 09/12] xen/Arm: GICv3: Define GIC registers for AArch32 Date: Mon, 31 Oct 2022 15:13:23 +0000 Message-ID: <20221031151326.22634-10-ayankuma@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221031151326.22634-1-ayankuma@amd.com> References: <20221031151326.22634-1-ayankuma@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT058:EE_|SA0PR12MB4445:EE_ X-MS-Office365-Filtering-Correlation-Id: 15361d85-abd4-4b4a-d8c0-08dabb529286 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Rtzy1kiD28sIrq5SEZteyYBkdydYraRp38SewTdraALTgVkpVHygHuQOyBWDFbYkpxDU/YOEUO56bHZp0qKO7JEDQS5eL0No7MIabba1uXDcsLXpzIev+juHqODKHzwc9CgOZ/5FxuSEnhRv4hDDNyZECBs2G6bmVJsPFQhkWLtdS9NlG46XevHYdEx/kvhlxS3yVOhKSm96GSYYYcyi0rO9xCVHz+JtaD8waNH6XGnzaxRp4p6YCm3WF05wuEElxwbpO2SB68tE5s7umekUgNIivOvHZhczT6Hpr0HKMzlQ1nGaxQBZTUkFGjDGxCRzXEW6avr7SSsd32GBBSYBQpuni4SO03fZ+AWTeFq+067EC8x0CLT6EbPtL/SX8r0QtHg9nqSFFTG7gsqtyNsYtchiCbootIGZsmQ5IKbnqY5YRdzDLpQI56znvxp7sTFa1VsIqF2sClycndosuHEJvd8xzftOODZhWAiWGeqegdTl2tNxqRynQbRp8AtoQHU8pQx5tO7i2d7mkM3SO2jeJj7O1tzNQuSDEeZtCQzu+5eSYE2IPyPqojivHyEo9wxqLS15+Ui+bhZxVlAf/3sCLWiWvL4Y5mSnWCwoN8kYvuvAhFYoRuH6d7Ar1mukL09OPeh4Ep1uC6KGnfxykV7qi13I2KB6FTgDzPXT0Pj0yflNCFGQH1vmj1aA5Kxjapyr83nGXVLS9suzuy3R4eO8oYIGYEoUaJlCxbMxIETR0iSc5/etP2x9L4ulJFWoKxcPnrluBU9C2VxkOmoitk2+uG7TgJgeaUoGM1PoVutIuSKeikqSb00OzJTsd7bah/eB X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(39860400002)(346002)(376002)(136003)(396003)(451199015)(36840700001)(40470700004)(46966006)(83380400001)(82740400003)(478600001)(426003)(47076005)(2906002)(336012)(36860700001)(356005)(70206006)(70586007)(8676002)(40480700001)(81166007)(4326008)(82310400005)(2616005)(1076003)(186003)(36756003)(41300700001)(26005)(54906003)(40460700003)(6916009)(316002)(5660300002)(8936002)(6666004)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 Oct 2022 15:14:14.5901 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 15361d85-abd4-4b4a-d8c0-08dabb529286 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT058.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB4445 Refer "Arm IHI 0069H ID020922" 12.5.23 ICC_SGI1R, Interrupt Controller Software Generated Interrupt Group 1 Register 12.5.12 ICC_HSRE, Interrupt Controller Hyp System Register Enable register 12.7.10 ICH_VTR, Interrupt Controller VGIC Type Register 12.7.5 ICH_HCR, Interrupt Controller Hyp Control Register 12.5.20 ICC_PMR, Interrupt Controller Interrupt Priority Mask Register 12.5.24 ICC_SRE, Interrupt Controller System Register Enable register 12.5.7 ICC_DIR, Interrupt Controller Deactivate Interrupt Register 12.5.9 ICC_EOIR1, Interrupt Controller End Of Interrupt Register 1 12.5.14 ICC_IAR1, Interrupt Controller Interrupt Acknowledge Register 1 12.5.5 ICC_BPR1, Interrupt Controller Binary Point Register 1 12.5.6 ICC_CTLR, Interrupt Controller Control Register 12.5.16 ICC_IGRPEN1, Interrupt Controller Interrupt Group 1 Enable register 12.7.9 ICH_VMCR, Interrupt Controller Virtual Machine Control Register Signed-off-by: Ayan Kumar Halder --- Changes from :- v1 - 1. Moved coproc regs definition to asm/cpregs.h xen/arch/arm/include/asm/cpregs.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/xen/arch/arm/include/asm/cpregs.h b/xen/arch/arm/include/asm/cpregs.h index bfabee0bc3..62b63f4cef 100644 --- a/xen/arch/arm/include/asm/cpregs.h +++ b/xen/arch/arm/include/asm/cpregs.h @@ -415,6 +415,22 @@ #define ICH_AP1R1_EL2 __AP1Rx_EL2(1) #define ICH_AP1R2_EL2 __AP1Rx_EL2(2) #define ICH_AP1R3_EL2 __AP1Rx_EL2(3) + +#define ICC_SGI1R_EL1 p15,0,c12 + +#define ICC_SRE_EL2 p15,4,c12,c9,5 +#define ICH_VTR_EL2 p15,4,c12,c11,1 +#define ICH_HCR_EL2 p15,4,c12,c11,0 + +#define ICC_PMR_EL1 p15,0,c4,c6,0 +#define ICC_SRE_EL1 p15,0,c12,c12,5 +#define ICC_DIR_EL1 p15,0,c12,c11,1 +#define ICC_EOIR1_EL1 p15,0,c12,c12,1 +#define ICC_IAR1_EL1 p15,0,c12,c12,0 +#define ICC_BPR1_EL1 p15,0,c12,c12,3 +#define ICC_CTLR_EL1 p15,0,c12,c12,4 +#define ICC_IGRPEN1_EL1 p15,0,c12,c12,7 +#define ICH_VMCR_EL2 p15,4,c12,c11,7 #endif #endif From patchwork Mon Oct 31 15:13:24 2022 Content-Type: text/plain; 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pr=C From: Ayan Kumar Halder To: CC: , , , , , , Ayan Kumar Halder Subject: [XEN v2 10/12] xen/Arm: GICv3: Use ULL instead of UL for 64bits Date: Mon, 31 Oct 2022 15:13:24 +0000 Message-ID: <20221031151326.22634-11-ayankuma@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221031151326.22634-1-ayankuma@amd.com> References: <20221031151326.22634-1-ayankuma@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT017:EE_|BY5PR12MB4289:EE_ X-MS-Office365-Filtering-Correlation-Id: d00e45a5-6ea6-4571-ac77-08dabb5293c7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: q3OU0pAqCKkVKEeX8Y++UZd2d4tIyKmJMc24hD+SdYuwPBeceZ/y+8mvJIiNNWwP/ypVdgLLnrRGb5OaSxlBZFfKCQCBgCNf1Rpj6vsVFBajMQyLfUF/f3leiaGIKuPZST26IaHvTS7muvamN8/KoD4hFO9kUjIqPtMg8wL4V9lg6WlO75J0Vg7uCD8Z1T5rIgccsV77ymIPVGaCd3rYFcF54Bdv6zXj44ktS1Iei0N3QVqe1w1clvvN7CJyGelzUkkb2Rde7N586QWnp5p/7wJgqQIqdBC/iHb2mxUeAYg3molsAmnPxH/AIzmlC0kPv2vTlwqaYXGlMIMgF7vZW8nPAWYVWn7A1x66RfR1uu3gTEdqon2u8bwSLaoSyDlQeajHC7Bxdy7kUdtV1EWVNEcz3W3zdrADVEYnBKTK1bW6xv/FnKQdVhu8ifnc8H/+dvdhnJZOuNnIY+znbWSKyDcHkr8W0iPHhtT68r/SiBlMv9f0d6QsiI9UJpM/gBm+a9Kq3xJRwNwVnscqmdsoIGScjFadXMSDO8GYAR83RKghtDORuj1qbu25iNUTMxQeOzjHI539+2H8xJMrbwszkUltNE8t8jppOegKb1579q/LHaZmX4XwZC6rDABzKZqQ4YbHtMgOUzLGIDtxJCODkSulTi9L+lxBSOIZ4GDWdRQa695oD9ryBy5v6v+ZvE+V6VXUj3vqU9vJOcN4ke2TfVzc9FjPkPEG8JSDF/PJ3kF3p/oml1s7thq0h0Ph2j58GSHWX7f2gpM1ZlEO8FlM1zuZxXhwdkxWsIsRRQUcHeFtcL+uISE/i7KhZh3g+Ok1 X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(346002)(39860400002)(136003)(376002)(396003)(451199015)(46966006)(36840700001)(40470700004)(41300700001)(2616005)(40480700001)(336012)(5660300002)(82740400003)(26005)(2906002)(6916009)(316002)(1076003)(83380400001)(36756003)(186003)(478600001)(6666004)(54906003)(81166007)(47076005)(4326008)(8676002)(8936002)(36860700001)(70586007)(82310400005)(426003)(40460700003)(70206006)(356005)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 Oct 2022 15:14:16.6926 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d00e45a5-6ea6-4571-ac77-08dabb5293c7 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT017.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4289 "unsigned long long" is defined as 64 bits on AArch64 and AArch32 Thus, one should this instead of "unsigned long" which is 32 bits on AArch32. Also use 'PRIx64' instead of 'lx' or 'llx' to print uint64_t. Signed-off-by: Ayan Kumar Halder --- Changed from :- v1 - 1. Replace PRIu64 with PRIx64 so that the values are printed in hex as desired. 2. Use ULL in GITS_BASER_RO_MASK as MMIO registers are always unsigned. xen/arch/arm/gic-v3-lpi.c | 8 ++++---- xen/arch/arm/gic-v3.c | 4 ++-- xen/arch/arm/include/asm/gic_v3_defs.h | 2 +- xen/arch/arm/include/asm/gic_v3_its.h | 2 +- xen/arch/arm/vgic-v3-its.c | 17 +++++++++-------- 5 files changed, 17 insertions(+), 16 deletions(-) diff --git a/xen/arch/arm/gic-v3-lpi.c b/xen/arch/arm/gic-v3-lpi.c index 61d90eb386..9ca74bc321 100644 --- a/xen/arch/arm/gic-v3-lpi.c +++ b/xen/arch/arm/gic-v3-lpi.c @@ -134,7 +134,7 @@ void gicv3_set_redist_address(paddr_t address, unsigned int redist_id) uint64_t gicv3_get_redist_address(unsigned int cpu, bool use_pta) { if ( use_pta ) - return per_cpu(lpi_redist, cpu).redist_addr & GENMASK(51, 16); + return per_cpu(lpi_redist, cpu).redist_addr & GENMASK_ULL(51, 16); else return per_cpu(lpi_redist, cpu).redist_id << 16; } @@ -253,7 +253,7 @@ static int gicv3_lpi_allocate_pendtable(unsigned int cpu) return -ENOMEM; /* Make sure the physical address can be encoded in the register. */ - if ( virt_to_maddr(pendtable) & ~GENMASK(51, 16) ) + if ( virt_to_maddr(pendtable) & ~GENMASK_ULL(51, 16) ) { xfree(pendtable); return -ERANGE; @@ -281,7 +281,7 @@ static int gicv3_lpi_set_pendtable(void __iomem *rdist_base) return -ENOMEM; } - ASSERT(!(virt_to_maddr(pendtable) & ~GENMASK(51, 16))); + ASSERT(!(virt_to_maddr(pendtable) & ~GENMASK_ULL(51, 16))); val = GIC_BASER_CACHE_RaWaWb << GICR_PENDBASER_INNER_CACHEABILITY_SHIFT; val |= GIC_BASER_CACHE_SameAsInner << GICR_PENDBASER_OUTER_CACHEABILITY_SHIFT; @@ -329,7 +329,7 @@ static int gicv3_lpi_set_proptable(void __iomem * rdist_base) return -ENOMEM; /* Make sure the physical address can be encoded in the register. */ - if ( (virt_to_maddr(table) & ~GENMASK(51, 12)) ) + if ( (virt_to_maddr(table) & ~GENMASK_ULL(51, 12)) ) { xfree(table); return -ERANGE; diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c index 8b4b168e78..d8ce0f46c6 100644 --- a/xen/arch/arm/gic-v3.c +++ b/xen/arch/arm/gic-v3.c @@ -417,12 +417,12 @@ static void gicv3_dump_state(const struct vcpu *v) if ( v == current ) { for ( i = 0; i < gicv3_info.nr_lrs; i++ ) - printk(" HW_LR[%d]=%llx\n", i, gicv3_ich_read_lr(i)); + printk(" HW_LR[%d]=%" PRIx64 "\n", i, gicv3_ich_read_lr(i)); } else { for ( i = 0; i < gicv3_info.nr_lrs; i++ ) - printk(" VCPU_LR[%d]=%llx\n", i, v->arch.gic.v3.lr[i]); + printk(" VCPU_LR[%d]=%" PRIx64 "\n", i, v->arch.gic.v3.lr[i]); } } diff --git a/xen/arch/arm/include/asm/gic_v3_defs.h b/xen/arch/arm/include/asm/gic_v3_defs.h index 87115f8b25..3a24bd4825 100644 --- a/xen/arch/arm/include/asm/gic_v3_defs.h +++ b/xen/arch/arm/include/asm/gic_v3_defs.h @@ -195,7 +195,7 @@ #define ICH_SGI_IRQMODE_SHIFT 40 #define ICH_SGI_IRQMODE_MASK 0x1 -#define ICH_SGI_TARGET_OTHERS 1UL +#define ICH_SGI_TARGET_OTHERS 1ULL #define ICH_SGI_TARGET_LIST 0 #define ICH_SGI_IRQ_SHIFT 24 #define ICH_SGI_IRQ_MASK 0xf diff --git a/xen/arch/arm/include/asm/gic_v3_its.h b/xen/arch/arm/include/asm/gic_v3_its.h index fae3f6ecef..5ae50b18ea 100644 --- a/xen/arch/arm/include/asm/gic_v3_its.h +++ b/xen/arch/arm/include/asm/gic_v3_its.h @@ -38,7 +38,7 @@ #define GITS_PIDR2 GICR_PIDR2 /* Register bits */ -#define GITS_VALID_BIT BIT(63, UL) +#define GITS_VALID_BIT BIT(63, ULL) #define GITS_CTLR_QUIESCENT BIT(31, UL) #define GITS_CTLR_ENABLE BIT(0, UL) diff --git a/xen/arch/arm/vgic-v3-its.c b/xen/arch/arm/vgic-v3-its.c index 58d939b85f..c5e02b2c41 100644 --- a/xen/arch/arm/vgic-v3-its.c +++ b/xen/arch/arm/vgic-v3-its.c @@ -96,13 +96,13 @@ typedef uint16_t coll_table_entry_t; * in the lowest 5 bits of the word. */ typedef uint64_t dev_table_entry_t; -#define DEV_TABLE_ITT_ADDR(x) ((x) & GENMASK(51, 8)) +#define DEV_TABLE_ITT_ADDR(x) ((x) & GENMASK_ULL(51, 8)) #define DEV_TABLE_ITT_SIZE(x) (BIT(((x) & GENMASK(4, 0)) + 1, UL)) #define DEV_TABLE_ENTRY(addr, bits) \ (((addr) & GENMASK(51, 8)) | (((bits) - 1) & GENMASK(4, 0))) #define GITS_BASER_RO_MASK (GITS_BASER_TYPE_MASK | \ - (0x1fL << GITS_BASER_ENTRY_SIZE_SHIFT)) + (0x1ULL << GITS_BASER_ENTRY_SIZE_SHIFT)) /* * The physical address is encoded slightly differently depending on @@ -112,10 +112,10 @@ typedef uint64_t dev_table_entry_t; static paddr_t get_baser_phys_addr(uint64_t reg) { if ( reg & BIT(9, UL) ) - return (reg & GENMASK(47, 16)) | + return (reg & GENMASK_ULL(47, 16)) | ((reg & GENMASK(15, 12)) << 36); else - return reg & GENMASK(47, 12); + return reg & GENMASK_ULL(47, 12); } /* Must be called with the ITS lock held. */ @@ -414,7 +414,7 @@ static int update_lpi_property(struct domain *d, struct pending_irq *p) if ( !d->arch.vgic.rdists_enabled ) return 0; - addr = d->arch.vgic.rdist_propbase & GENMASK(51, 12); + addr = d->arch.vgic.rdist_propbase & GENMASK_ULL(51, 12); ret = access_guest_memory_by_ipa(d, addr + p->irq - LPI_OFFSET, &property, sizeof(property), false); @@ -897,7 +897,8 @@ out_unlock: static void dump_its_command(uint64_t *command) { - gdprintk(XENLOG_WARNING, " cmd 0x%02lx: %016lx %016lx %016lx %016lx\n", + gdprintk(XENLOG_WARNING, " cmd 0x%" PRIx64 ": %" PRIx64 + "%" PRIx64 "%" PRIx64 "%" PRIx64 "\n", its_cmd_get_command(command), command[0], command[1], command[2], command[3]); } @@ -909,7 +910,7 @@ static void dump_its_command(uint64_t *command) */ static int vgic_its_handle_cmds(struct domain *d, struct virt_its *its) { - paddr_t addr = its->cbaser & GENMASK(51, 12); + paddr_t addr = its->cbaser & GENMASK_ULL(51, 12); uint64_t command[4]; ASSERT(spin_is_locked(&its->vcmd_lock)); @@ -1122,7 +1123,7 @@ read_as_zero_64: read_impl_defined: printk(XENLOG_G_DEBUG - "%pv: vGITS: RAZ on implementation defined register offset %#04lx\n", + "%pv: vGITS: RAZ on implementation defined register offset %" PRIx64 "#04llx\n", v, info->gpa & 0xffff); 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pr=C From: Ayan Kumar Halder To: CC: , , , , , , Ayan Kumar Halder Subject: [XEN v2 11/12] xen/Arm: GICv3: Define macros to read/write 64 bit Date: Mon, 31 Oct 2022 15:13:25 +0000 Message-ID: <20221031151326.22634-12-ayankuma@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221031151326.22634-1-ayankuma@amd.com> References: <20221031151326.22634-1-ayankuma@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT114:EE_|SJ1PR12MB6219:EE_ X-MS-Office365-Filtering-Correlation-Id: 817997c4-64d5-4f93-355f-08dabb529557 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: m4PCC5K6hhyznZfO+zO0ygAnQgAt+px1ZRTWOx9cBxJVifT8n2rD7kBxROJbNlNFE15FiBBfXLKiPfLEnkUGS0mI8O0z5YQPA7c6SvaBYZ58gsF39ZWAROquTF6YG5igIZE2NgGvlUz5TskZwY9ZnFbZALIk3QK20+NjqHQuu7VT7BdU/XTCi65uVwT9QY4YXYlXzTlTIP0WEwjxMAY7HxLwMr+rSEcTgE5hi7iQ30ZB/PD2bQiQKuCyppUi/lasgHgSqq1lRP1PAMXLba7eC8F+GcNuo52HvYcq8EzjJIGQdVEz3k767SMuK7x83Mh7PZ5M7A0PfJFPwe5iV3uqfwXQ+VREzUdqQjz96Hf2CcC0fxxqytoxNyCYcelGeXQ0keySbCxPEZACPyUNEYCEvnhkN+yro0oQt2uZCJisreC6Baapx1BvFiD2TKiP+qT1qJwmFbtzZEJDyFeN2G2RNcJ2opdGZd7fbzrTN76fxMGKDwmXrA5DmJoLB9fLelZchI8MPb4AAI2skk8DMnSGP0D6B1NSzPqmn4tBeY1Y/SFnOABBaMKk36fRs65qage2R9UrUxay8T33UHoih60zj1ZqdzfvhLOKhb6hBIJUPy6wEpRPnmkywbXLHqKl0MERf+8JH9zjMAM4lARYAEFXhGkTyKfMpp43VyxS9EiWYZablWCWv/1k3XpNNWzPnJF8iJJQ29FYR28aP4PlT+g+Qohc8XdPjAArOY99N4FydatLl8z0TL92yACfceR5SIuYFdM1TXSeYVFLt0dTl8x5ESPyiWLhaO5x+SqenP6jof7WjTb4uLWRPlv0aUXZdzP6 X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(39860400002)(346002)(376002)(396003)(136003)(451199015)(36840700001)(46966006)(40470700004)(82310400005)(70586007)(70206006)(8676002)(54906003)(316002)(6916009)(36860700001)(356005)(81166007)(83380400001)(2906002)(36756003)(478600001)(1076003)(8936002)(40480700001)(41300700001)(5660300002)(4326008)(336012)(2616005)(186003)(40460700003)(82740400003)(426003)(6666004)(47076005)(26005)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 Oct 2022 15:14:19.3110 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 817997c4-64d5-4f93-355f-08dabb529557 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT114.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ1PR12MB6219 Defined readq_relaxed()/writeq_relaxed() to read and write 64 bit regs. This uses ldrd/strd instructions. Signed-off-by: Ayan Kumar Halder --- Changes from :- v1 - 1. Use ldrd/strd for readq_relaxed()/writeq_relaxed(). 2. No need to use le64_to_cpu() as the returned byte order is already in cpu endianess. xen/arch/arm/include/asm/arm32/io.h | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/xen/arch/arm/include/asm/arm32/io.h b/xen/arch/arm/include/asm/arm32/io.h index 73a879e9fb..d9d19ad764 100644 --- a/xen/arch/arm/include/asm/arm32/io.h +++ b/xen/arch/arm/include/asm/arm32/io.h @@ -72,6 +72,22 @@ static inline u32 __raw_readl(const volatile void __iomem *addr) return val; } +static inline u64 __raw_readq(const volatile void __iomem *addr) +{ + u64 val; + asm volatile("ldrd %Q1, %R1, %0" + : "+Qo" (*(volatile u64 __force *)addr), + "=r" (val)); + return val; +} + +static inline void __raw_writeq(u64 val, const volatile void __iomem *addr) +{ + asm volatile("strd %Q1, %R1, %0" + : "+Q" (*(volatile u64 __force *)addr) + : "r" (val)); +} + #define __iormb() rmb() #define __iowmb() wmb() @@ -80,17 +96,22 @@ static inline u32 __raw_readl(const volatile void __iomem *addr) __raw_readw(c)); __r; }) #define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32) \ __raw_readl(c)); __r; }) +#define readq_relaxed(c) ({ u64 __r = le64_to_cpu((__force __le64) \ + __raw_readq(c)); __r; }) #define writeb_relaxed(v,c) __raw_writeb(v,c) #define writew_relaxed(v,c) __raw_writew((__force u16) cpu_to_le16(v),c) #define writel_relaxed(v,c) __raw_writel((__force u32) cpu_to_le32(v),c) +#define writeq_relaxed(v,c) __raw_writeq((__force u64) cpu_to_le64(v),c) #define readb(c) ({ u8 __v = readb_relaxed(c); __iormb(); __v; }) #define readw(c) ({ u16 __v = readw_relaxed(c); __iormb(); __v; }) #define readl(c) ({ u32 __v = readl_relaxed(c); __iormb(); __v; }) +#define readq(c) ({ u64 __v = readq_relaxed(c); __iormb(); __v; }) #define writeb(v,c) ({ __iowmb(); writeb_relaxed(v,c); }) #define writew(v,c) ({ __iowmb(); writew_relaxed(v,c); }) #define writel(v,c) ({ __iowmb(); writel_relaxed(v,c); }) +#define writeq(v,c) ({ __iowmb(); writeq_relaxed(v,c); }) #endif /* _ARM_ARM32_IO_H */ From patchwork Mon Oct 31 15:13:26 2022 Content-Type: text/plain; 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pr=C From: Ayan Kumar Halder To: CC: , , , , , , Ayan Kumar Halder Subject: [XEN v2 12/12] xen/Arm: GICv3: Enable GICv3 for AArch32 Date: Mon, 31 Oct 2022 15:13:26 +0000 Message-ID: <20221031151326.22634-13-ayankuma@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221031151326.22634-1-ayankuma@amd.com> References: <20221031151326.22634-1-ayankuma@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT079:EE_|MN2PR12MB4440:EE_ X-MS-Office365-Filtering-Correlation-Id: c5f961f8-e35e-41ba-6937-08dabb5296b7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Ul05mLEvhkOfwIr2YqPl13UCqovYsIUmykUUKu2cZkhqMJO86zranB6C5qNzh0N+iCbXDUcE49uZ2Ork/uq4MkrlzI9Xj7J99I75biCeXZm849Dr3V0HAvLQDvhspr+0lD9i3Tsn5a1AWoooeDDyguYpWdgrVfco/FW4ovieKHUlBe/CmEyb/p9B17zHwt5UQgex7qfLVQox95oM6wexjX6GM7C6GiLE70AQH3Bp36Att9fSsgPLf/oyERQSie22slt5VZebyMOafKGsd2w21cbQYjrg8GwR54iyjlBABCJMR+gUObWyiqnRd0rYAuT84hu7LIOL40SGEWMOvTsax8Ms0UmGAyJDylU6bHSmoPLT6iPlD2fK540e6Rvd/sBHrhg00c66/iR1DHDAC4qU/Bn4Dwn6/Sqk9X0H72f40y6G1xJvLEwAohDjJfLIPT5dkzdUHHiSFIoKQ610g1H1IrheMV0z6xXL23sOX55OiCfViyeWJGHGtndw40nNItxziK3Kv//Ul+8h1iGff/kgluN8k7/uCxwh16gBNtMMIE2UHPivBXSqIphaq57/aqCOd2gk8cmY+XiCm/60IlTUf5lErp+NHU0DP7wmfbtz8v3mQcT8UVrt86IWnEXBmqrZhlf0/Uc3hPP/pLVgES+8tQy71AAWnnN7WZK/gkRyzhaC+DJd/FuFni90yFusUnqUisZs21SozGAxGzk1hGYZTJnPWuWcT+0+4IWzycnt4kMFDYqKla8qBperfTDXLOfJsyfsP0433GG6U0dotyEIcGuFLFs8Vt8oKSNjMbfG79jVQjksfgtNqwcP+WdecLVR X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(396003)(39860400002)(376002)(136003)(346002)(451199015)(46966006)(36840700001)(40470700004)(6916009)(36756003)(54906003)(316002)(478600001)(41300700001)(40480700001)(83380400001)(5660300002)(1076003)(186003)(40460700003)(356005)(26005)(426003)(47076005)(336012)(2906002)(36860700001)(82740400003)(2616005)(81166007)(6666004)(8936002)(8676002)(70206006)(70586007)(4326008)(82310400005)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 Oct 2022 15:14:21.6192 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c5f961f8-e35e-41ba-6937-08dabb5296b7 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT079.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4440 Refer ARM DDI 0487G.b ID072021, D13.2.86 - ID_PFR1_EL1, AArch32 Processor Feature Register 1 GIC, bits[31:28] == 0b0001 for GIC3.0 on Aarch32 One can now enable GICv3 on AArch32 systems. However, ITS is not supported. The reason being currently we are trying to validate GICv3 on an AArch32_v8R system. Refer ARM DDI 0568A.c ID110520, B1.3.1, "A Generic Interrupt Controller (GIC) implemented with an Armv8-R PE must not implement LPI support." Updated SUPPORT.md. Signed-off-by: Ayan Kumar Halder --- Changed from :- v1 - 1. Remove "ARM_64 || ARM_32" as it is always true. 2. Updated SUPPORT.md. SUPPORT.md | 6 ++++++ xen/arch/arm/Kconfig | 4 ++-- xen/arch/arm/include/asm/cpufeature.h | 1 + 3 files changed, 9 insertions(+), 2 deletions(-) diff --git a/SUPPORT.md b/SUPPORT.md index cf2ddfacaf..0137855c66 100644 --- a/SUPPORT.md +++ b/SUPPORT.md @@ -82,6 +82,12 @@ Extension to the GICv3 interrupt controller to support MSI. Status: Experimental +### ARM/GICv3 + AArch32 ARM v8 + +GICv3 is supported on AArch32 ARMv8 (besides AArch64) + + Status: Supported, not security supported + ## Guest Type ### x86/PV diff --git a/xen/arch/arm/Kconfig b/xen/arch/arm/Kconfig index 1fe5faf847..7c3c6eb3bd 100644 --- a/xen/arch/arm/Kconfig +++ b/xen/arch/arm/Kconfig @@ -41,7 +41,7 @@ config ARM_EFI config GICV3 bool "GICv3 driver" - depends on ARM_64 && !NEW_VGIC + depends on !NEW_VGIC default y ---help--- @@ -50,7 +50,7 @@ config GICV3 config HAS_ITS bool "GICv3 ITS MSI controller support (UNSUPPORTED)" if UNSUPPORTED - depends on GICV3 && !NEW_VGIC + depends on GICV3 && !NEW_VGIC && !ARM_32 config HVM def_bool y diff --git a/xen/arch/arm/include/asm/cpufeature.h b/xen/arch/arm/include/asm/cpufeature.h index c86a2e7f29..c62cf6293f 100644 --- a/xen/arch/arm/include/asm/cpufeature.h +++ b/xen/arch/arm/include/asm/cpufeature.h @@ -33,6 +33,7 @@ #define cpu_has_aarch32 (cpu_has_arm || cpu_has_thumb) #ifdef CONFIG_ARM_32 +#define cpu_has_gicv3 (boot_cpu_feature32(gic) >= 1) #define cpu_has_gentimer (boot_cpu_feature32(gentimer) == 1) /* * On Armv7, the value 0 is used to indicate that PMUv2 is not