From patchwork Mon Oct 31 20:48:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 13026355 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 12F9EECAAA1 for ; Mon, 31 Oct 2022 20:49:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=d9HaYqa5w4lEdcBr34R98UxrMQ/G6FKcrvGTBKM7cwo=; b=vGrLSYLImitV+Q O3asTyIyZCXjzLUMpJ5JqKTPeLCBZ146ECkEBnSFIRE6AsM28AG2MNRURy1336ThJp5LV4N0w4Git Ky9DSMuE7dUQLDQeSAAztM1Tn9hOktZF2tBMydei6X2L4XrN5x9HQ6IenJadaSSsNuknEGyg0rTly 70NjNh2HG5FDunTXP50s2K/6QxUoluus7Fcd9LJuNyU8g2FzfofWI1TzTb2tJuGGShYUPs5v+KXEa ua5g4dNVr+yTo0erkfqdN+8WDRT4oWXsiUk6MhTZleseYg+TlMuBEnEz1ywgXqNRXIgkP+1HitdMq vgWzbo3iGG0fgPzaFOpA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1opbiG-00FImg-Au; Mon, 31 Oct 2022 20:48:52 +0000 Received: from phobos.denx.de ([2a01:238:438b:c500:173d:9f52:ddab:ee01]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1opbiD-00FIlu-1u for linux-arm-kernel@lists.infradead.org; Mon, 31 Oct 2022 20:48:50 +0000 Received: from tr.lan (ip-86-49-120-218.bb.vodafone.cz [86.49.120.218]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: marex@denx.de) by phobos.denx.de (Postfix) with ESMTPSA id CEB8B85508; Mon, 31 Oct 2022 21:48:43 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1667249324; bh=qNBLRYuEoiJWHAu06LNUBPhqI4/VuNJ7u+W5oihXzFM=; h=From:To:Cc:Subject:Date:From; b=P4BK2Bu298ZloubrkaSQEfEj/fzi/DBPbs85lYGKVxXIPDIoTEwPqbVNiq56bQoie QbEZmNnBhrotyCNvvOwVsM7HAbTvhdhSIgQX3aaDKxe1MqhDAwdiRaquJoENTBwyrv 1q7RBt19tTXwqk3iftIDAP+MxhMBZoaSqDeUK0KKicyHWevK5l1/n/495xdRQxj506 I77vlmnBKb2fJQRrxmgFeSe5NRTtILEZYWKrz4irCs9nIQhEPBNxsGL4hTDqhpjKXW hvLyNFozt7WMpZF4oxiAq3LtHJjISI0AYZL0tPz27D6J8KmxFJL7Yx9qnFccMAbIs/ YOun0zkz7lVSg== From: Marek Vasut To: linux-clk@vger.kernel.org Cc: Marek Vasut , Abel Vesa , Fabio Estevam , Sascha Hauer , Shawn Guo , Stephen Boyd , NXP Linux Team , linux-arm-kernel@lists.infradead.org Subject: [PATCH] clk: imx: pll14xx: Add 320 MHz and 640 MHz entries for PLL146x Date: Mon, 31 Oct 2022 21:48:38 +0100 Message-Id: <20221031204838.195292-1-marex@denx.de> X-Mailer: git-send-email 2.35.1 MIME-Version: 1.0 X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221031_134849_288096_D69F83CD X-CRM114-Status: GOOD ( 11.65 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The PLL146x is used to implement SYS_PLL3 on i.MX8MP and can be used to drive UARTn_ROOT clock. By setting the PLL3 to 320 MHz or 640 MHz, the PLL3 output can be divided down to supply UARTn_ROOT clock with precise 64 MHz, which divided down further by 16x oversampling factor used by the i.MX UART core yields 4 Mbdps baud base for the UART IP. This is useful e.g. for BCM bluetooth chips, which can operate up to 4 Mbdps. Add 320 MHz and 640 MHz entries so the PLL can be configured accordingly. Signed-off-by: Marek Vasut Reviewed-by: Abel Vesa --- Cc: Abel Vesa Cc: Fabio Estevam Cc: Sascha Hauer Cc: Shawn Guo Cc: Stephen Boyd Cc: NXP Linux Team Cc: linux-arm-kernel@lists.infradead.org To: linux-clk@vger.kernel.org --- drivers/clk/imx/clk-pll14xx.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c index 1d0f79e9c3467..828336873a98f 100644 --- a/drivers/clk/imx/clk-pll14xx.c +++ b/drivers/clk/imx/clk-pll14xx.c @@ -54,7 +54,9 @@ static const struct imx_pll14xx_rate_table imx_pll1416x_tbl[] = { PLL_1416X_RATE(800000000U, 200, 3, 1), PLL_1416X_RATE(750000000U, 250, 2, 2), PLL_1416X_RATE(700000000U, 350, 3, 2), + PLL_1416X_RATE(640000000U, 320, 3, 2), PLL_1416X_RATE(600000000U, 300, 3, 2), + PLL_1416X_RATE(320000000U, 160, 3, 2), }; static const struct imx_pll14xx_rate_table imx_pll1443x_tbl[] = {