From patchwork Tue Nov 1 07:59:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hongxing Zhu X-Patchwork-Id: 13026723 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A345FC433FE for ; Tue, 1 Nov 2022 08:22:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:List-Subscribe:List-Help: List-Post:List-Archive:List-Unsubscribe:List-Id:Message-Id:Date:Subject:Cc:To :From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=hJMDsLVoXxgn7wrh5yQVVBsiVlfIFPh1uEvw6Dn7g4g=; b=DNTJ+dlLfaxDaa 7jeQZmb/QNaVuPxt2cR9RDs2Zu0pL0Xmk/HERE5wMFttW3beBNtw8ZFO64IQ02XcSJyVM24OVimGF WBvXaxvd2Rp9xGY/rjlsGuYrTUht9r9m9pWni8qxNMN/7QY2Kq/mNF62jN2GqLzBmpxXlxcf4Cwmv /+682N8kcy9s8i15/CplSv2QCZ3fLiu/bYyonMnHsXgU75VD0/o73VcLb0i+EffEuhWOawLPfq6Zq WJsFKd9McKHpDmDmHGtqruZ5M0cy1H8Aw6Qq/ijDoTF2znfMYFMA1dfjC7P7Ah6oC8iwC7gmd3CZ8 +xNfiC0PxyyN+Fl0RMmw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1opmVt-003A08-OA; Tue, 01 Nov 2022 08:20:49 +0000 Received: from inva020.nxp.com ([92.121.34.13]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1opmVq-0039yd-Ov for linux-arm-kernel@lists.infradead.org; Tue, 01 Nov 2022 08:20:48 +0000 Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 2B81A1A03D2; Tue, 1 Nov 2022 09:20:41 +0100 (CET) Received: from aprdc01srsp001v.ap-rdc01.nxp.com (aprdc01srsp001v.ap-rdc01.nxp.com [165.114.16.16]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id F38281A03FE; Tue, 1 Nov 2022 09:20:40 +0100 (CET) Received: from localhost.localdomain (shlinux2.ap.freescale.net [10.192.224.44]) by aprdc01srsp001v.ap-rdc01.nxp.com (Postfix) with ESMTP id A0624180222A; Tue, 1 Nov 2022 16:20:39 +0800 (+08) From: Richard Zhu To: l.stach@pengutronix.de, bhelgaas@google.com, lorenzo.pieralisi@arm.com Cc: hongxing.zhu@nxp.com, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@pengutronix.de, linux-imx@nxp.com Subject: [PATCH v1] PCI: imx6: Set MSI enable bit of RC in resume Date: Tue, 1 Nov 2022 15:59:55 +0800 Message-Id: <1667289595-12440-1-git-send-email-hongxing.zhu@nxp.com> X-Mailer: git-send-email 2.7.4 X-Virus-Scanned: ClamAV using ClamSMTP X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221101_012046_984230_2E6B4551 X-CRM114-Status: GOOD ( 12.16 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The MSI Enable bit controls delivery of MSI interrupts from components below the Root Port. This bit might lost during the suspend, should be re-configured during resume. Encapsulate the MSI enable set into a standalone function, and invoke it in both probe and resume. Signed-off-by: Richard Zhu --- drivers/pci/controller/dwc/pci-imx6.c | 24 +++++++++++++++++------- 1 file changed, 17 insertions(+), 7 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index 2616585ca5f8..dba15546075f 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -1041,6 +1041,21 @@ static void imx6_pcie_pm_turnoff(struct imx6_pcie *imx6_pcie) usleep_range(1000, 10000); } +static void pci_imx_set_msi_en(struct dw_pcie *pci) +{ + u8 offset; + u16 val; + + if (pci_msi_enabled()) { + offset = dw_pcie_find_capability(pci, PCI_CAP_ID_MSI); + dw_pcie_dbi_ro_wr_en(pci); + val = dw_pcie_readw_dbi(pci, offset + PCI_MSI_FLAGS); + val |= PCI_MSI_FLAGS_ENABLE; + dw_pcie_writew_dbi(pci, offset + PCI_MSI_FLAGS, val); + dw_pcie_dbi_ro_wr_dis(pci); + } +} + static int imx6_pcie_suspend_noirq(struct device *dev) { struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev); @@ -1073,6 +1088,7 @@ static int imx6_pcie_resume_noirq(struct device *dev) if (imx6_pcie->link_is_up) imx6_pcie_start_link(imx6_pcie->pci); + pci_imx_set_msi_en(imx6_pcie->pci); return 0; } @@ -1090,7 +1106,6 @@ static int imx6_pcie_probe(struct platform_device *pdev) struct resource *dbi_base; struct device_node *node = dev->of_node; int ret; - u16 val; imx6_pcie = devm_kzalloc(dev, sizeof(*imx6_pcie), GFP_KERNEL); if (!imx6_pcie) @@ -1282,12 +1297,7 @@ static int imx6_pcie_probe(struct platform_device *pdev) if (ret < 0) return ret; - if (pci_msi_enabled()) { - u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_MSI); - val = dw_pcie_readw_dbi(pci, offset + PCI_MSI_FLAGS); - val |= PCI_MSI_FLAGS_ENABLE; - dw_pcie_writew_dbi(pci, offset + PCI_MSI_FLAGS, val); - } + pci_imx_set_msi_en(pci); return 0; }