From patchwork Tue Nov 1 14:33:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 13026980 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 51CA2C4332F for ; Tue, 1 Nov 2022 14:39:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229717AbiKAOj1 (ORCPT ); Tue, 1 Nov 2022 10:39:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52858 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230346AbiKAOjV (ORCPT ); Tue, 1 Nov 2022 10:39:21 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9AC3A1C12D for ; Tue, 1 Nov 2022 07:39:19 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 54D1FB81DDF for ; Tue, 1 Nov 2022 14:39:18 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 847AFC43470; Tue, 1 Nov 2022 14:39:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1667313557; bh=feYAW/OZGfAMtc0rPHOMdt7oiYR1Iy5pxL7FHo9QLg8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=CXBkMkmqcybahJFovRWY4Pa4nzrDSF9hUXPsaKG6Xdvj2NBXcuzg1agPN7mW2iyrZ uYNjBUxmV4A4DxXfD+rlvY3ln/qSkz8wXbRXtAKPRIaQD6U+AmwY2kv9Rw8bxAces0 35E5JkwxY974CO+krQrnhZAs/GvKb7DHCNnjtG+YtxBfhj7qtoGdOSkF/Cm2u1SRoV MfETyBv8ziCCTySj91aUcJrRJFl1TgXNyeKXnNR9lBKozTCtEgP+vWasvYS2GN6ElO dZ4MCJqnudM80CGPMBVJxYTyjPhEBXWQLiyY0LVXLK6RXtyRu0cgt2AUOMn8MWv6nz lRxKLVwP5Pr1Q== From: Mark Brown To: Catalin Marinas , Will Deacon , Shuah Khan , Shuah Khan Cc: Alan Hayward , Luis Machado , Szabolcs Nagy , linux-arm-kernel@lists.infradead.org, linux-kselftest@vger.kernel.org, Mark Brown Subject: [PATCH v2 01/21] arm64/sme: Rename za_state to sme_state Date: Tue, 1 Nov 2022 14:33:16 +0000 Message-Id: <20221101143336.254445-2-broonie@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20221101143336.254445-1-broonie@kernel.org> References: <20221101143336.254445-1-broonie@kernel.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=11078; i=broonie@kernel.org; h=from:subject; bh=feYAW/OZGfAMtc0rPHOMdt7oiYR1Iy5pxL7FHo9QLg8=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBjYS4pNMBxooaRDb1ycBASLIFJA7tavvWUdAK03CZn f8KfPC6JATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCY2EuKQAKCRAk1otyXVSH0L3NB/ 0TL+JPyg26OtiY8eTnTDlX5DXw172okeDQ3FKmepBhxkgZWG0Gup8puoMuGMv6tW5022o+dSdw6iD9 xZCjdsa2B165IIn8AYrMo4zDvbLc1uBn0tzwEtF2cvToRQe/Lgv7meKJ7ePv75NL/EnnjQWlqRnssd gYmgo8BmCX4QSlp9Q5ZZkSlrX7Qt5/OTWYizpMkhbPP8JChiVq+dCQwdrLGS1L5PCA//87/pup+9fO ckT4qe21obg7MyHNvQyp0dXK9Sy0FwvxhWwIhXo/lSqmVy7r5ny6x3cV26rHU/Zc7HZJGezR8uzGtf fJwtZdB8lrg095TyBidCxu1AWPEpqt X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB Precedence: bulk List-ID: X-Mailing-List: linux-kselftest@vger.kernel.org In preparation for adding support for storage for ZT0 to the thread_struct rename za_state to sme_state. Since ZT0 is accessible when PSTATE.ZA is set just like ZA itself we will extend the allocation done for ZA to cover it, avoiding the need to further expand task_struct for non-SME tasks. No functional changes. Signed-off-by: Mark Brown --- arch/arm64/include/asm/fpsimd.h | 13 ++++++---- arch/arm64/include/asm/processor.h | 2 +- arch/arm64/kernel/fpsimd.c | 40 +++++++++++++++--------------- arch/arm64/kernel/process.c | 11 ++++---- arch/arm64/kernel/ptrace.c | 6 ++--- arch/arm64/kernel/signal.c | 8 +++--- 6 files changed, 42 insertions(+), 38 deletions(-) diff --git a/arch/arm64/include/asm/fpsimd.h b/arch/arm64/include/asm/fpsimd.h index 6f86b7ab6c28..a18a86ccfd82 100644 --- a/arch/arm64/include/asm/fpsimd.h +++ b/arch/arm64/include/asm/fpsimd.h @@ -346,14 +346,17 @@ extern int sme_get_current_vl(void); /* * Return how many bytes of memory are required to store the full SME - * specific state (currently just ZA) for task, given task's currently - * configured vector length. + * specific state for task, given task's currently configured vector + * length. */ -static inline size_t za_state_size(struct task_struct const *task) +static inline size_t sme_state_size(struct task_struct const *task) { unsigned int vl = task_get_sme_vl(task); + size_t size; - return ZA_SIG_REGS_SIZE(sve_vq_from_vl(vl)); + size = ZA_SIG_REGS_SIZE(sve_vq_from_vl(vl)); + + return size; } #else @@ -373,7 +376,7 @@ static inline int sme_max_virtualisable_vl(void) { return 0; } static inline int sme_set_current_vl(unsigned long arg) { return -EINVAL; } static inline int sme_get_current_vl(void) { return -EINVAL; } -static inline size_t za_state_size(struct task_struct const *task) +static inline size_t sme_state_size(struct task_struct const *task) { return 0; } diff --git a/arch/arm64/include/asm/processor.h b/arch/arm64/include/asm/processor.h index 445aa3af3b76..923a896229c8 100644 --- a/arch/arm64/include/asm/processor.h +++ b/arch/arm64/include/asm/processor.h @@ -154,7 +154,7 @@ struct thread_struct { unsigned int fpsimd_cpu; void *sve_state; /* SVE registers, if any */ - void *za_state; /* ZA register, if any */ + void *sme_state; /* ZA and ZT state, if any */ unsigned int vl[ARM64_VEC_MAX]; /* vector length */ unsigned int vl_onexec[ARM64_VEC_MAX]; /* vl after next exec */ unsigned long fault_address; /* fault info */ diff --git a/arch/arm64/kernel/fpsimd.c b/arch/arm64/kernel/fpsimd.c index 23834d96d1e7..b677b5a3e0f6 100644 --- a/arch/arm64/kernel/fpsimd.c +++ b/arch/arm64/kernel/fpsimd.c @@ -121,7 +121,7 @@ struct fpsimd_last_state_struct { struct user_fpsimd_state *st; void *sve_state; - void *za_state; + void *sme_state; u64 *svcr; unsigned int sve_vl; unsigned int sme_vl; @@ -307,7 +307,7 @@ void task_set_vl_onexec(struct task_struct *task, enum vec_type type, /* * TIF_SME controls whether a task can use SME without trapping while * in userspace, when TIF_SME is set then we must have storage - * alocated in sve_state and za_state to store the contents of both ZA + * alocated in sve_state and sme_state to store the contents of both ZA * and the SVE registers for both streaming and non-streaming modes. * * If both SVCR.ZA and SVCR.SM are disabled then at any point we @@ -396,7 +396,7 @@ static void task_fpsimd_load(void) write_sysreg_s(current->thread.svcr, SYS_SVCR); if (thread_za_enabled(¤t->thread)) - za_load_state(current->thread.za_state); + za_load_state(current->thread.sme_state); if (thread_sm_enabled(¤t->thread)) { restore_sve_regs = true; @@ -449,7 +449,7 @@ static void fpsimd_save(void) *svcr = read_sysreg_s(SYS_SVCR); if (*svcr & SVCR_ZA_MASK) - za_save_state(last->za_state); + za_save_state(last->sme_state); /* If we are in streaming mode override regular SVE. */ if (*svcr & SVCR_SM_MASK) { @@ -1213,30 +1213,30 @@ void fpsimd_release_task(struct task_struct *dead_task) #ifdef CONFIG_ARM64_SME /* - * Ensure that task->thread.za_state is allocated and sufficiently large. + * Ensure that task->thread.sme_state is allocated and sufficiently large. * * This function should be used only in preparation for replacing - * task->thread.za_state with new data. The memory is always zeroed + * task->thread.sme_state with new data. The memory is always zeroed * here to prevent stale data from showing through: this is done in * the interest of testability and predictability, the architecture * guarantees that when ZA is enabled it will be zeroed. */ void sme_alloc(struct task_struct *task) { - if (task->thread.za_state) { - memset(task->thread.za_state, 0, za_state_size(task)); + if (task->thread.sme_state) { + memset(task->thread.sme_state, 0, sme_state_size(task)); return; } /* This could potentially be up to 64K. */ - task->thread.za_state = - kzalloc(za_state_size(task), GFP_KERNEL); + task->thread.sme_state = + kzalloc(sme_state_size(task), GFP_KERNEL); } static void sme_free(struct task_struct *task) { - kfree(task->thread.za_state); - task->thread.za_state = NULL; + kfree(task->thread.sme_state); + task->thread.sme_state = NULL; } void sme_kernel_enable(const struct arm64_cpu_capabilities *__always_unused p) @@ -1443,7 +1443,7 @@ void do_sme_acc(unsigned long esr, struct pt_regs *regs) sve_alloc(current, false); sme_alloc(current); - if (!current->thread.sve_state || !current->thread.za_state) { + if (!current->thread.sve_state || !current->thread.sme_state) { force_sig(SIGKILL); return; } @@ -1564,7 +1564,7 @@ static void fpsimd_flush_thread_vl(enum vec_type type) void fpsimd_flush_thread(void) { void *sve_state = NULL; - void *za_state = NULL; + void *sme_state = NULL; if (!system_supports_fpsimd()) return; @@ -1589,8 +1589,8 @@ void fpsimd_flush_thread(void) clear_thread_flag(TIF_SME); /* Defer kfree() while in atomic context */ - za_state = current->thread.za_state; - current->thread.za_state = NULL; + sme_state = current->thread.sme_state; + current->thread.sme_state = NULL; fpsimd_flush_thread_vl(ARM64_VEC_SME); current->thread.svcr = 0; @@ -1598,7 +1598,7 @@ void fpsimd_flush_thread(void) put_cpu_fpsimd_context(); kfree(sve_state); - kfree(za_state); + kfree(sme_state); } /* @@ -1640,7 +1640,7 @@ static void fpsimd_bind_task_to_cpu(void) WARN_ON(!system_supports_fpsimd()); last->st = ¤t->thread.uw.fpsimd_state; last->sve_state = current->thread.sve_state; - last->za_state = current->thread.za_state; + last->sme_state = current->thread.sme_state; last->sve_vl = task_get_sve_vl(current); last->sme_vl = task_get_sme_vl(current); last->svcr = ¤t->thread.svcr; @@ -1666,7 +1666,7 @@ static void fpsimd_bind_task_to_cpu(void) } void fpsimd_bind_state_to_cpu(struct user_fpsimd_state *st, void *sve_state, - unsigned int sve_vl, void *za_state, + unsigned int sve_vl, void *sme_state, unsigned int sme_vl, u64 *svcr) { struct fpsimd_last_state_struct *last = @@ -1678,7 +1678,7 @@ void fpsimd_bind_state_to_cpu(struct user_fpsimd_state *st, void *sve_state, last->st = st; last->svcr = svcr; last->sve_state = sve_state; - last->za_state = za_state; + last->sme_state = sme_state; last->sve_vl = sve_vl; last->sme_vl = sme_vl; } diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c index 044a7d7f1f6a..5cfb876c76ee 100644 --- a/arch/arm64/kernel/process.c +++ b/arch/arm64/kernel/process.c @@ -318,16 +318,17 @@ int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src) GFP_KERNEL); if (!dst->thread.sve_state) return -ENOMEM; - dst->thread.za_state = kmemdup(src->thread.za_state, - za_state_size(src), - GFP_KERNEL); - if (!dst->thread.za_state) { + + dst->thread.sme_state = kmemdup(src->thread.sme_state, + sme_state_size(src), + GFP_KERNEL); + if (!dst->thread.sme_state) { kfree(dst->thread.sve_state); dst->thread.sve_state = NULL; return -ENOMEM; } } else { - dst->thread.za_state = NULL; + dst->thread.sme_state = NULL; clear_tsk_thread_flag(dst, TIF_SME); } diff --git a/arch/arm64/kernel/ptrace.c b/arch/arm64/kernel/ptrace.c index c2fb5755bbec..85105375bea5 100644 --- a/arch/arm64/kernel/ptrace.c +++ b/arch/arm64/kernel/ptrace.c @@ -1052,7 +1052,7 @@ static int za_get(struct task_struct *target, if (thread_za_enabled(&target->thread)) { start = end; end = ZA_PT_SIZE(vq); - membuf_write(&to, target->thread.za_state, end - start); + membuf_write(&to, target->thread.sme_state, end - start); } /* Zero any trailing padding */ @@ -1106,7 +1106,7 @@ static int za_set(struct task_struct *target, /* Allocate/reinit ZA storage */ sme_alloc(target); - if (!target->thread.za_state) { + if (!target->thread.sme_state) { ret = -ENOMEM; goto out; } @@ -1131,7 +1131,7 @@ static int za_set(struct task_struct *target, start = ZA_PT_ZA_OFFSET; end = ZA_PT_SIZE(vq); ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, - target->thread.za_state, + target->thread.sme_state, start, end); if (ret) goto out; diff --git a/arch/arm64/kernel/signal.c b/arch/arm64/kernel/signal.c index 9ad911f1647c..335bc7294b3c 100644 --- a/arch/arm64/kernel/signal.c +++ b/arch/arm64/kernel/signal.c @@ -386,7 +386,7 @@ static int preserve_za_context(struct za_context __user *ctx) * fpsimd_signal_preserve_current_state(). */ err |= __copy_to_user((char __user *)ctx + ZA_SIG_REGS_OFFSET, - current->thread.za_state, + current->thread.sme_state, ZA_SIG_REGS_SIZE(vq)); } @@ -417,7 +417,7 @@ static int restore_za_context(struct user_ctxs *user) /* * Careful: we are about __copy_from_user() directly into - * thread.za_state with preemption enabled, so protection is + * thread.sme_state with preemption enabled, so protection is * needed to prevent a racing context switch from writing stale * registers back over the new data. */ @@ -426,13 +426,13 @@ static int restore_za_context(struct user_ctxs *user) /* From now, fpsimd_thread_switch() won't touch thread.sve_state */ sme_alloc(current); - if (!current->thread.za_state) { + if (!current->thread.sme_state) { current->thread.svcr &= ~SVCR_ZA_MASK; clear_thread_flag(TIF_SME); return -ENOMEM; } - err = __copy_from_user(current->thread.za_state, + err = __copy_from_user(current->thread.sme_state, (char __user const *)user->za + ZA_SIG_REGS_OFFSET, ZA_SIG_REGS_SIZE(vq)); From patchwork Tue Nov 1 14:33:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 13026981 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 31B24C433FE for ; Tue, 1 Nov 2022 14:39:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230298AbiKAOj1 (ORCPT ); Tue, 1 Nov 2022 10:39:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52872 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230347AbiKAOjW (ORCPT ); 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a=openpgp-sha256; l=1166; i=broonie@kernel.org; h=from:subject; bh=2WtYkfyqwfbzmrCrdKWnq9io6zKV9H6MzPUD6asynbg=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBjYS4qp/fnXI1ilfvmmnP6CxO7mMM9nfvM50hdIBdv A9TAH9+JATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCY2EuKgAKCRAk1otyXVSH0JiAB/ 9qBpKYFVHc8N/HI97CrKsnIMV9crK/IwLfzQV9lRi1wga7R8XDz1t5SEHKeurO9qxM5bvsVSEEpyWW 0wh4lZBlF3o2YdGb78jXFO88NHRLE9vzuLjpQCY2gDznAgr5Sg6tcISCVlH0JcJ1X1VXKV/sxrVlXX Ccov8AV27IF/2qkVKwELA1UMyMKc37bN+dOvzPTkWnK3gowKE30GRTfqBgyz1aAyE97O4pIrJ5gfBC cGDzNaP1TcjCT3874qWc+xECBhj7CjZRB0AZfZLFoAefflzvCl4SZK2Kjcqmr/Pw7xKzkBmk+u24et ZepAW2xhR/CNAeTunmKk+Utn7KRHS9 X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB Precedence: bulk List-ID: X-Mailing-List: linux-kselftest@vger.kernel.org SME 2 introduces the new ZT0 register, we require that access to this reigster is not trapped when we identify that the feature is supported. Signed-off-by: Mark Brown --- Documentation/arm64/booting.rst | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/arm64/booting.rst b/Documentation/arm64/booting.rst index 8aefa1001ae5..b69b5cb596e6 100644 --- a/Documentation/arm64/booting.rst +++ b/Documentation/arm64/booting.rst @@ -360,6 +360,16 @@ Before jumping into the kernel, the following conditions must be met: - HCR_EL2.ATA (bit 56) must be initialised to 0b1. + For CPUs with the Scalable Matrix Extension version 2 (FEAT_SME2): + + - If EL3 is present: + + - SMCR_EL3.EZT0 (bit 30) must be initialised to 0b1. + + - If the kernel is entered at EL1 and EL2 is present: + + - SMCR_EL2.EZT0 (bit 30) must be initialised to 0b1. + The requirements described above for CPU mode, caches, MMUs, architected timers, coherency and system registers apply to all CPUs. All CPUs must enter the kernel in the same exception level. Where the values documented From patchwork Tue Nov 1 14:33:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 13026982 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7CF2DC43217 for ; Tue, 1 Nov 2022 14:39:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230340AbiKAOj2 (ORCPT ); Tue, 1 Nov 2022 10:39:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52662 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230341AbiKAOjZ (ORCPT ); Tue, 1 Nov 2022 10:39:25 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CC927120B8 for ; Tue, 1 Nov 2022 07:39:24 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 8DD23B81CC4 for ; Tue, 1 Nov 2022 14:39:23 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 279DAC433D6; Tue, 1 Nov 2022 14:39:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1667313562; bh=lxN3b2FYRfYKa3rp4NRU1yWU1LTiLst+rtoiTHw401Y=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=b5A/A59y/17yYO9iJQ0qGNgeZxspAr2Edm+j9Ba9Vu+6i72PL+DY5EdjC4IVXtB3u RtVD03obZtGYTSfWVmKnMxmjS4aBjEL7S+mUFW9J18Ns0rgSc3PtdMJ2pFBDev/SIQ w2jjPZrDCIGqg0DzA7/t03yhWrl3UctxilHw1x8RpO/8i4m8NsO+fgkGlLh8eBnWc4 LEgwHAOxu+gu62cW30oan4hwNfDmouF8lMQVnjPYxfVKzzT25geqcXttOwJ7kwxLNn MMfN+xUfKDQV7FJKLUWuSlsaH+0JUOL3Xg+GMTOA1KrYgraJ/5W/FW8b7VkMYBlVAf wnJKy5PmoRfQA== From: Mark Brown To: Catalin Marinas , Will Deacon , Shuah Khan , Shuah Khan Cc: Alan Hayward , Luis Machado , Szabolcs Nagy , linux-arm-kernel@lists.infradead.org, linux-kselftest@vger.kernel.org, Mark Brown Subject: [PATCH v2 03/21] arm64/sysreg: Update system registers for SME 2 and 2.1 Date: Tue, 1 Nov 2022 14:33:18 +0000 Message-Id: <20221101143336.254445-4-broonie@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20221101143336.254445-1-broonie@kernel.org> References: <20221101143336.254445-1-broonie@kernel.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1367; i=broonie@kernel.org; h=from:subject; bh=lxN3b2FYRfYKa3rp4NRU1yWU1LTiLst+rtoiTHw401Y=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBjYS4szguQk5G1Wp1zJ9WFZbb4KEHHs3GtNYf6Duji o6VzzbyJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCY2EuLAAKCRAk1otyXVSH0Ow9B/ 9Q6gP/xJ7rQdx3ySv3ZKHglpq/MX1do3VttlBdQ3B74fHJ8L8zGhRU7Wbsh2UkQDm7ulJdNLsL9Kqo qlrKKywZpvkZ9waDWTyjPp+6Hs85gDcP2Gqd2Ysp3ItPXCQtqwn7RtBA2zyZPfI1pBHL/Krh9lDMp8 w3W4L34t56cvyAnhPM1WxBwenMyH1Hj43nZ2ATkZASwhhW6aFGaSOlxRfqUw/eCuFaeVuGpHXlRePi YoJMaqobppCORumljsRuQHjARVuVtZk0SDKjX/akpwBWUve4e71Y0iI4M8eq2EhRhhgO+E6tpsYJM4 b3iD2INlxozWKo53a3mBrajekEs/VD X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB Precedence: bulk List-ID: X-Mailing-List: linux-kselftest@vger.kernel.org FEAT_SME2 and FEAT_SME2P1 introduce several new SME features which can be enumerated via ID_AA64SMFR0_EL1 and a new register ZT0 access to which is controlled via SMCR_ELn, add the relevant register description. Signed-off-by: Mark Brown --- arch/arm64/tools/sysreg | 26 ++++++++++++++++++++++---- 1 file changed, 22 insertions(+), 4 deletions(-) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index b2782b8faa01..c8f259dbdfb8 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -221,7 +221,9 @@ Enum 63 FA64 EndEnum Res0 62:60 Enum 59:56 SMEver - 0b0000 IMP + 0b0000 SME + 0b0001 SME2 + 0b0010 SME2p1 EndEnum Enum 55:52 I16I64 0b0000 NI @@ -232,7 +234,19 @@ Enum 48 F64F64 0b0 NI 0b1 IMP EndEnum -Res0 47:40 +Enum 47:44 I16I32 + 0b0000 NI + 0b0101 IMP +EndEnum +Enum 43 B16B16 + 0b0 NI + 0b1 IMP +EndEnum +Enum 42 F16F16 + 0b0 NI + 0b1 IMP +EndEnum +Res0 41:40 Enum 39:36 I8I32 0b0000 NI 0b1111 IMP @@ -245,7 +259,10 @@ Enum 34 B16F32 0b0 NI 0b1 IMP EndEnum -Res0 33 +Enum 33 BI32I32 + 0b0 NI + 0b1 IMP +EndEnum Enum 32 F32F32 0b0 NI 0b1 IMP @@ -845,7 +862,8 @@ EndSysreg SysregFields SMCR_ELx Res0 63:32 Field 31 FA64 -Res0 30:9 +Field 30 EZT0 +Res0 29:9 Raz 8:4 Field 3:0 LEN EndSysregFields From patchwork Tue Nov 1 14:33:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 13026983 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C8C35C4321E for ; Tue, 1 Nov 2022 14:39:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230317AbiKAOja (ORCPT ); Tue, 1 Nov 2022 10:39:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52916 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230342AbiKAOj2 (ORCPT ); Tue, 1 Nov 2022 10:39:28 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 835BC120B8 for ; Tue, 1 Nov 2022 07:39:27 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 2E867B81DE7 for ; Tue, 1 Nov 2022 14:39:26 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id B77CCC4347C; Tue, 1 Nov 2022 14:39:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1667313564; bh=VcmEHzDZARMditkXtNN0tMYNsSRwIXTGJ6VV9XCNSRE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=iAXpIqyJIcJiBd7Czcch/OaxUBHbmS5Foy8SgLbYsdODQI2qZY/CIcIjuR/+7AvwF q4Jpy3Uuc7vS/sFu8kn+FQU0JWkAljnnE5o4dRw1kFa+B/5Fhr5PfIOmqp3KQeokvb KCXbqMmfBwOr382CHmeYtIUtlWV2GzGVdhyhFKYC4gZAGgfX3tQCm0dU5eKKRgFr8i +pVUusKXtL6U+RjtUi8rAjwYNkt2aVOxJuRK0UXuy1b2fBoAY1MEfDuFgEmuo7U4wH ssQJa8nJ83S1DfHHikg0lRkO61/81NBGrLtaYipOhAErFqBM2u7BWblKuzxsDlMn6q 4nN8tcLa7PzDQ== From: Mark Brown To: Catalin Marinas , Will Deacon , Shuah Khan , Shuah Khan Cc: Alan Hayward , Luis Machado , Szabolcs Nagy , linux-arm-kernel@lists.infradead.org, linux-kselftest@vger.kernel.org, Mark Brown Subject: [PATCH v2 04/21] arm64/sme: Document SME 2 and SME 2.1 ABI Date: Tue, 1 Nov 2022 14:33:19 +0000 Message-Id: <20221101143336.254445-5-broonie@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20221101143336.254445-1-broonie@kernel.org> References: <20221101143336.254445-1-broonie@kernel.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=6991; i=broonie@kernel.org; h=from:subject; bh=VcmEHzDZARMditkXtNN0tMYNsSRwIXTGJ6VV9XCNSRE=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBjYS4tPu9Y+fhztrfMumObod1N44XODOFZ8ak5D5Ek L3TXgq2JATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCY2EuLQAKCRAk1otyXVSH0OKQB/ 4mhSdThhhXnSA4EngMx9ZEN3L3+ncBEee+1B34IPWvezGY4aAtm20u1+waZR7kP0R2Wr8ONN566b2H FgBLA28N+hEEGU2ZYCv0/BjxdblNwWzn9NhPmUBfMpqNt8xt4PRvgi5ExnPQ3pzX36ubdsDAT6IYEb cjkoFPjtbFzTB4eVuUF2lGxH/Bp26dMJBJroWHzw60r2DJ9BgdoqZpcCm+SwooTQVpM23qZIjG6y6I 7PzxhcLHF4Ke+lygpi6KZd2AxGIcJATrHW1HU01XKNhBdNHRofxEGr5K2BOQzkGeP9A2zk30uOVVbb Twdd/J2Qego8ivvuCKygAM7Uhbu7V+ X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB Precedence: bulk List-ID: X-Mailing-List: linux-kselftest@vger.kernel.org As well as a number of simple features which only add new instructions and require corresponding hwcaps SME2 introduces a new register ZT0 for which we must define ABI. Fortunately this is a fixed size 512 bits and therefore much more straightforward than the base SME state, the only wrinkle is that it is only accessible when ZA is accessible. While there is only a single register the architecture is written with a view to exensibility, including a number in the name, so follow this in the ABI. Signed-off-by: Mark Brown --- Documentation/arm64/sme.rst | 52 ++++++++++++++++++++++++++++++------- 1 file changed, 43 insertions(+), 9 deletions(-) diff --git a/Documentation/arm64/sme.rst b/Documentation/arm64/sme.rst index 16d2db4c2e2e..5f7eabee4853 100644 --- a/Documentation/arm64/sme.rst +++ b/Documentation/arm64/sme.rst @@ -18,14 +18,19 @@ model features for SME is included in Appendix A. 1. General ----------- -* PSTATE.SM, PSTATE.ZA, the streaming mode vector length, the ZA - register state and TPIDR2_EL0 are tracked per thread. +* PSTATE.SM, PSTATE.ZA, the streaming mode vector length, the ZA and (when + present) ZT0 register state and TPIDR2_EL0 are tracked per thread. * The presence of SME is reported to userspace via HWCAP2_SME in the aux vector AT_HWCAP2 entry. Presence of this flag implies the presence of the SME instructions and registers, and the Linux-specific system interfaces described in this document. SME is reported in /proc/cpuinfo as "sme". +* The presence of SME2 is reported to userspace via HWCAP2_SME in the + aux vector AT_HWCAP2 entry. Presence of this flag implies the presence of + the SME2 instructions and ZT0, and the Linux-specific system interfaces + described in this document. SME2 is reported in /proc/cpuinfo as "sme2". + * Support for the execution of SME instructions in userspace can also be detected by reading the CPU ID register ID_AA64PFR1_EL1 using an MRS instruction, and checking that the value of the SME field is nonzero. [3] @@ -44,6 +49,7 @@ model features for SME is included in Appendix A. HWCAP2_SME_B16F32 HWCAP2_SME_F32F32 HWCAP2_SME_FA64 + HWCAP2_SME2 This list may be extended over time as the SME architecture evolves. @@ -52,8 +58,8 @@ model features for SME is included in Appendix A. cpu-feature-registers.txt for details. * Debuggers should restrict themselves to interacting with the target via the - NT_ARM_SVE, NT_ARM_SSVE and NT_ARM_ZA regsets. The recommended way - of detecting support for these regsets is to connect to a target process + NT_ARM_SVE, NT_ARM_SSVE, NT_ARM_ZA and NT_ARM_ZT regsets. The recommended + way of detecting support for these regsets is to connect to a target process first and then attempt a ptrace(PTRACE_GETREGSET, pid, NT_ARM_, &iov). @@ -89,13 +95,13 @@ be zeroed. ------------------------- * On syscall PSTATE.ZA is preserved, if PSTATE.ZA==1 then the contents of the - ZA matrix are preserved. + ZA matrix and ZT0 (if present) are preserved. * On syscall PSTATE.SM will be cleared and the SVE registers will be handled as per the standard SVE ABI. -* Neither the SVE registers nor ZA are used to pass arguments to or receive - results from any syscall. +* None of the SVE registers, ZA or ZT0 are used to pass arguments to + or receive results from any syscall. * On process creation (eg, clone()) the newly created process will have PSTATE.SM cleared. @@ -134,6 +140,14 @@ be zeroed. __reserved[] referencing this space. za_context is then written in the extra space. Refer to [1] for further details about this mechanism. +* If ZT is supported and PSTATE.ZA==1 then a signal frame record for ZT will + be generated. + +* The signal record for ZT has magic ZT_MAGIC (0x73d4e827) and consists of a + standard signal frame header followed by a struct zt_context specifying + the number of ZT registers supported by the system, then zt_contxt.nregs + blocks of 64 bytes of data per register. + 5. Signal return ----------------- @@ -151,6 +165,9 @@ When returning from a signal handler: the signal frame does not match the current vector length, the signal return attempt is treated as illegal, resulting in a forced SIGSEGV. +* If ZT is not supported or PSTATE.ZA==0 then it is illegal to have a + signal frame record for ZT, resulting in a forced SIGSEGV. + 6. prctl extensions -------------------- @@ -214,8 +231,8 @@ prctl(PR_SME_SET_VL, unsigned long arg) vector length that will be applied at the next execve() by the calling thread. - * Changing the vector length causes all of ZA, P0..P15, FFR and all bits of - Z0..Z31 except for Z0 bits [127:0] .. Z31 bits [127:0] to become + * Changing the vector length causes all of ZA, ZT, P0..P15, FFR and all + bits of Z0..Z31 except for Z0 bits [127:0] .. Z31 bits [127:0] to become unspecified, including both streaming and non-streaming SVE state. Calling PR_SME_SET_VL with vl equal to the thread's current vector length, or calling PR_SME_SET_VL with the PR_SVE_SET_VL_ONEXEC flag, @@ -317,6 +334,15 @@ The regset data starts with struct user_za_header, containing: * The effect of writing a partial, incomplete payload is unspecified. +* A new regset NT_ARM_ZT is defined for for access to ZT state via + PTRACE_GETREGSET and PTRACE_SETREGSET. + +* The NT_ARM_ZT regset consists of a single 512 bit register. + +* When PSTATE.ZA==0 reads of NT_ARM_ZT will report all bits of ZT as 0. + +* Writes to NT_ARM_ZT will set PSTATE.ZA to 1. + 8. ELF coredump extensions --------------------------- @@ -331,6 +357,11 @@ The regset data starts with struct user_za_header, containing: been read if a PTRACE_GETREGSET of NT_ARM_ZA were executed for each thread when the coredump was generated. +* A NT_ARM_ZT note will be added to each coredump for each thread of the + dumped process. The contents will be equivalent to the data that would have + been read if a PTRACE_GETREGSET of NT_ARM_ZT were executed for each thread + when the coredump was generated. + * The NT_ARM_TLS note will be extended to two registers, the second register will contain TPIDR2_EL0 on systems that support SME and will be read as zero with writes ignored otherwise. @@ -406,6 +437,9 @@ In A64 state, SME adds the following: For best system performance it is strongly encouraged for software to enable ZA only when it is actively being used. +* A new ZT0 register is introduced when SME2 is present. This is a 512 bit + register which is accessible PSTATE.ZA is set, as ZA itself is. + * Two new 1 bit fields in PSTATE which may be controlled via the SMSTART and SMSTOP instructions or by access to the SVCR system register: From patchwork Tue Nov 1 14:33:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 13026984 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 68D65C433FE for ; Tue, 1 Nov 2022 14:39:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230302AbiKAOja (ORCPT ); Tue, 1 Nov 2022 10:39:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52918 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230315AbiKAOj3 (ORCPT ); Tue, 1 Nov 2022 10:39:29 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 766591903C for ; Tue, 1 Nov 2022 07:39:28 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 138D3615ED for ; Tue, 1 Nov 2022 14:39:28 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4F1DAC433D7; Tue, 1 Nov 2022 14:39:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1667313567; bh=YKInprl0Z/WdYYYPuq/XXVfRQrNbgVz3ey4J2M/3SlI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=EeLJAfh53DSosVOk3rSRQUaUW8ErlZS8bWSDoSKNCe5pbOO40CasCAC4p30+LkEb+ tL2VtKyvGerDKnxAT82YvY5Nz3Jqaz6zVD5WlxS8TZlZqCr76V/bMT6r/snMpKE7vZ iGbUr+tdvZqYWrOe45EU42tUirQaDF0EkmNbrOCcqSUOGRfJZ5pxNa0VPc9QeR8hi6 fUaPVKygpYQsxI15DGRyNfuzog+kpWYLkn5fimULXa9VlYHkvf/Cb3wtG5MNV0OZD2 yImuw4jvK7oj1kPA2BOBrj52iK3OmUcUP1zKShHe5iyTdcI3rjuJz3+7Y5mX78JUSt 8qyydxtrqOyXg== From: Mark Brown To: Catalin Marinas , Will Deacon , Shuah Khan , Shuah Khan Cc: Alan Hayward , Luis Machado , Szabolcs Nagy , linux-arm-kernel@lists.infradead.org, linux-kselftest@vger.kernel.org, Mark Brown Subject: [PATCH v2 05/21] arm64/esr: Document ISS for ZT0 being disabled Date: Tue, 1 Nov 2022 14:33:20 +0000 Message-Id: <20221101143336.254445-6-broonie@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20221101143336.254445-1-broonie@kernel.org> References: <20221101143336.254445-1-broonie@kernel.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=645; i=broonie@kernel.org; h=from:subject; bh=YKInprl0Z/WdYYYPuq/XXVfRQrNbgVz3ey4J2M/3SlI=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBjYS4utC8ef3jGaowJXIFnq+Ms+yKnG+/t2cBH8Ug2 gL1ykRGJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCY2EuLgAKCRAk1otyXVSH0MPsB/ 9d2sFAonITHoPTNFnLA3oKF1bPJvnBWguMQf+1QtZo63o+D0dvqGoHTlzKBs2eqaWlLbFnKNpswith lCo6ac3g5SC0unHTuVmvKOhVsrEkm36rOb+kw7KjLG1RJiR3PduhGmMMQeaFDIoIak7aprq/rSGQ+5 eu49Lct9B96qvtOuF54J54VIlDdxh6VTFwR5DeE8ObZuh3AuaiH7mw9U+rj4lNd+qzw4MaFFKbaMJ8 bGt/yJleV6lED8vSPcZg53w7lGDZuhO4CQnos/JYLUB6CEdcHdRjxLSfLaC+c1VyUGV5Y48aQdec6c 0vVf3K6Vnzg9+redqHqSHEmE8j8JBR X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB Precedence: bulk List-ID: X-Mailing-List: linux-kselftest@vger.kernel.org SME2 defines a new ISS code for use when trapping acesses to ZT0, add a definition for it. Signed-off-by: Mark Brown --- arch/arm64/include/asm/esr.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/include/asm/esr.h b/arch/arm64/include/asm/esr.h index 15b34fbfca66..5f3271e9d5df 100644 --- a/arch/arm64/include/asm/esr.h +++ b/arch/arm64/include/asm/esr.h @@ -341,6 +341,7 @@ #define ESR_ELx_SME_ISS_ILL 1 #define ESR_ELx_SME_ISS_SM_DISABLED 2 #define ESR_ELx_SME_ISS_ZA_DISABLED 3 +#define ESR_ELx_SME_ISS_ZT_DISABLED 4 #ifndef __ASSEMBLY__ #include From patchwork Tue Nov 1 14:33:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 13026985 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B6FE0C433FE for ; Tue, 1 Nov 2022 14:39:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230315AbiKAOjf (ORCPT ); Tue, 1 Nov 2022 10:39:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52930 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230333AbiKAOjd (ORCPT ); Tue, 1 Nov 2022 10:39:33 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9892D12AFF for ; Tue, 1 Nov 2022 07:39:32 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 59C06B81DDF for ; Tue, 1 Nov 2022 14:39:31 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id E4173C4347C; Tue, 1 Nov 2022 14:39:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1667313570; bh=nNqQUwIlLlhNTh00NGbkWKb/ZzHhU7JuzVml+Agak8Y=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ooRgAoGkoMAzNXQfsm8pn/4sZFyfCKgPO4DTQ55jzjgnU1aBbi0BelIZOvXp6nV4l 3st9gG3x/zeH3y1NZc+ASerxZqc0aAgqE89qROvAdpReVxRdqjqHp7htt+Sk3vbrDt S72BL1Bz71hZp4AUHUMQo9tHwF4CDlbU3wLjhycLpnMRg/k0StzDYnR+cPDNDffCE7 +ckQF03mrgzQRM3ur4DbwZKjsl5V2LttqP0bKyRBcW6q95FCfrcOFMd7bRz5amGFOm DhzxlO3lDwc6DpH6KijxwmEO1+kUZ/kXTvpKvagAj5eq34sLcLpX7CudR/oFXUsIvD 0xa8omovETkVw== From: Mark Brown To: Catalin Marinas , Will Deacon , Shuah Khan , Shuah Khan Cc: Alan Hayward , Luis Machado , Szabolcs Nagy , linux-arm-kernel@lists.infradead.org, linux-kselftest@vger.kernel.org, Mark Brown Subject: [PATCH v2 06/21] arm64/sme: Manually encode ZT0 load and store instructions Date: Tue, 1 Nov 2022 14:33:21 +0000 Message-Id: <20221101143336.254445-7-broonie@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20221101143336.254445-1-broonie@kernel.org> References: <20221101143336.254445-1-broonie@kernel.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=909; i=broonie@kernel.org; h=from:subject; bh=nNqQUwIlLlhNTh00NGbkWKb/ZzHhU7JuzVml+Agak8Y=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBjYS4vnGSUPdo5XijQQVesN8LP48yDwYn+xoJHDLQF kPqnmJ6JATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCY2EuLwAKCRAk1otyXVSH0Fl/B/ 0faWBNOtatH8YELdjihsu7sT35RTc8WK8xytQPNTGIP2yRyOEoe/0hYGJlAj/K2HT1JjEpKw6yIXTU JtYPf0uTKrUYWNiWM7h8pAzfAryj2Z5caT5iqowMMBiQaC4Cad9FIvQ+au4WmFuAb3LtEawUPGA3mV h9u5UhIObQaVrpDv4Z1q6DU3eart15pSIe/LudZ+zkL/M/DR3Z0BSzi5kW9B0If9Xnu6ERGYalvsHo wyhyXAzIzOtWkihtAGUtMMK+LRgcPHMV0wW1sAFyTTro+G3piKVkjlYAAx1+tkGA/eOLk6AwpLsDdM 3El/1hOcUvgGmxXA/cYlvZE4FAOMd9 X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB Precedence: bulk List-ID: X-Mailing-List: linux-kselftest@vger.kernel.org In order to avoid unrealistic toolchain requirements we manually encode the instructions for loading and storing ZT0. Signed-off-by: Mark Brown --- arch/arm64/include/asm/fpsimdmacros.h | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/include/asm/fpsimdmacros.h b/arch/arm64/include/asm/fpsimdmacros.h index 5e0910cf4832..cd03819a3b68 100644 --- a/arch/arm64/include/asm/fpsimdmacros.h +++ b/arch/arm64/include/asm/fpsimdmacros.h @@ -220,6 +220,28 @@ | ((\offset) & 7) .endm +/* + * LDR (ZT0) + * + * LDR ZT0, nx + */ +.macro _ldr_zt nx + _check_general_reg \nx + .inst 0xe11f8000 \ + | (\nx << 5) +.endm + +/* + * STR (ZT0) + * + * STR ZT0, nx + */ +.macro _str_zt nx + _check_general_reg \nx + .inst 0xe13f8000 \ + | (\nx << 5) +.endm + /* * Zero the entire ZA array * ZERO ZA From patchwork Tue Nov 1 14:33:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 13026986 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 79D27C4332F for ; Tue, 1 Nov 2022 14:39:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230333AbiKAOjf (ORCPT ); Tue, 1 Nov 2022 10:39:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52940 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230335AbiKAOje (ORCPT ); Tue, 1 Nov 2022 10:39:34 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9EC1013F9A for ; Tue, 1 Nov 2022 07:39:33 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 3A966615ED for ; Tue, 1 Nov 2022 14:39:33 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7DE89C433C1; Tue, 1 Nov 2022 14:39:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1667313572; bh=80VeZpDH/AvqQz/7ZP/vlFhjGhDxdTuyQv5vjnhwMFE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=jeQjAS6Zwx/JwgO7i2KG7oPesOigwURaa43dNteZA0X5Luq/HEs80ZYvOoN27jzvM fRFN9g83MC2v+DImNQXMRSrZ+n+V7A5C7sCAWAuPMM9lioB/XpqVhn5jEiXSpjAftM TN5/BhnBJHKGkc6IsnSM0+Iyv7CQoKpFzQyz3AVhYcIl+L0kdxhf8rvhnwA/XhTRr6 iK+8eceLKr0g6ofpESuuk9cOH2/v4xenRGp/iYpZe+uyVZu779FBJbAMl/Q6naFWq3 0hlrvCnEhPyLTll9K/QkNS4DKbTBiKxeNrH/iiEweKbj2iLL6bUJ23YXZgzo0hJLEC zmB6AE6eUvwBQ== From: Mark Brown To: Catalin Marinas , Will Deacon , Shuah Khan , Shuah Khan Cc: Alan Hayward , Luis Machado , Szabolcs Nagy , linux-arm-kernel@lists.infradead.org, linux-kselftest@vger.kernel.org, Mark Brown Subject: [PATCH v2 07/21] arm64/sme: Enable host kernel to access ZT0 Date: Tue, 1 Nov 2022 14:33:22 +0000 Message-Id: <20221101143336.254445-8-broonie@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20221101143336.254445-1-broonie@kernel.org> References: <20221101143336.254445-1-broonie@kernel.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1458; i=broonie@kernel.org; h=from:subject; bh=80VeZpDH/AvqQz/7ZP/vlFhjGhDxdTuyQv5vjnhwMFE=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBjYS4wTbTmxCe8blM8BdTbg1P7SUXU+9mP/xRn2HGD MAaKabeJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCY2EuMAAKCRAk1otyXVSH0I7rB/ wLDuDyOPDInUuWeKBFciC6J4cJ4wIux/bFPEoPkc1AQKjuqpCPJLn9Rev4BQr32fIa7un3ZlqfTyht CTFMos5iQPUMaEJhDi2f1m6/hKCpgIGjPpherBVNGH/yTa7fSZA7iO4WsGWr+pG7Y1GH+EoRIFBrT7 Z5Bxq8C9XtYsiGyBgd+12yHThZzzOBy7vXDKhWLCtFDQFeO+J4qRXuE5SrnCTghGjg+3rvkTxXgDHu yfXiiv6e5sonTKTY+/o59dE0lpV7VS63kecBcduPO5S4jdL8o2/469vmBPVGZDR44qJFPRZxXEExt/ 99EPG4ZWSIeEIeYbANSlIEBBGWZ0y9 X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB Precedence: bulk List-ID: X-Mailing-List: linux-kselftest@vger.kernel.org The new register ZT0 introduced by SME2 comes with a new trap, disable it for the host kernel so that we can implement support for it. Signed-off-by: Mark Brown --- arch/arm64/kernel/hyp-stub.S | 6 ++++++ arch/arm64/kernel/idreg-override.c | 1 + 2 files changed, 7 insertions(+) diff --git a/arch/arm64/kernel/hyp-stub.S b/arch/arm64/kernel/hyp-stub.S index 2ee18c860f2a..d31d1acb170d 100644 --- a/arch/arm64/kernel/hyp-stub.S +++ b/arch/arm64/kernel/hyp-stub.S @@ -132,6 +132,12 @@ SYM_CODE_START_LOCAL(__finalise_el2) orr x0, x0, SMCR_ELx_FA64_MASK .Lskip_sme_fa64: + // ZT0 available? + __check_override id_aa64smfr0 ID_AA64SMFR0_EL1_SMEver_SHIFT 4 .Linit_sme_zt0 .Lskip_sme_zt0 +.Linit_sme_zt0: + orr x0, x0, SMCR_ELx_EZT0_MASK +.Lskip_sme_zt0: + orr x0, x0, #SMCR_ELx_LEN_MASK // Enable full SME vector msr_s SYS_SMCR_EL2, x0 // length for EL1. diff --git a/arch/arm64/kernel/idreg-override.c b/arch/arm64/kernel/idreg-override.c index 95133765ed29..d833d78a7f31 100644 --- a/arch/arm64/kernel/idreg-override.c +++ b/arch/arm64/kernel/idreg-override.c @@ -131,6 +131,7 @@ static const struct ftr_set_desc smfr0 __initconst = { .name = "id_aa64smfr0", .override = &id_aa64smfr0_override, .fields = { + FIELD("smever", ID_AA64SMFR0_EL1_SMEver_SHIFT, NULL), /* FA64 is a one bit field... :-/ */ { "fa64", ID_AA64SMFR0_EL1_FA64_SHIFT, 1, }, {} From patchwork Tue Nov 1 14:33:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 13026987 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 422FCC4332F for ; Tue, 1 Nov 2022 14:39:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230341AbiKAOjj (ORCPT ); Tue, 1 Nov 2022 10:39:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52986 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230335AbiKAOji (ORCPT ); Tue, 1 Nov 2022 10:39:38 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DD64C120B8 for ; Tue, 1 Nov 2022 07:39:37 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 8ECB9B81DE9 for ; Tue, 1 Nov 2022 14:39:36 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 19A97C433D7; Tue, 1 Nov 2022 14:39:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1667313575; bh=BSyGAKOSO0WbIOVL+wJlQnvdBXIuBCty+6/13InEecc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=S5OZanB0HojKRgjE1GwTyoKubtFZqxwVAo8qBvGt8aKmK5dmLszeSBuuCErpZODB6 gJ/ltzkbotFpP0U+bNzcGrmW/MqlpRifjP0lXG6/XsL67p3SD4w07X4rA3toIOrNGU 2CnM+iP84uCggMWl09g+FR97IxR+QxGRH8vnOJUhYC1DC/rAyHeJUvw6841l7VVJgI EBnZp0cNS2LvZsO0R3SGQuXG7fGE3xDYlGi4su5Cn4td6zms/3wN5Nltx1zg10cmOB x5/DZjgr9iZdNi2/YOHp4RcP/gTFDZiaNW+0os7q9s1drUV6tJtIVAlVx6zzi/8vZ5 YJQY4kRs+GTQQ== From: Mark Brown To: Catalin Marinas , Will Deacon , Shuah Khan , Shuah Khan Cc: Alan Hayward , Luis Machado , Szabolcs Nagy , linux-arm-kernel@lists.infradead.org, linux-kselftest@vger.kernel.org, Mark Brown Subject: [PATCH v2 08/21] arm64/sme: Add basic enumeration for SME2 Date: Tue, 1 Nov 2022 14:33:23 +0000 Message-Id: <20221101143336.254445-9-broonie@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20221101143336.254445-1-broonie@kernel.org> References: <20221101143336.254445-1-broonie@kernel.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=4162; i=broonie@kernel.org; h=from:subject; bh=BSyGAKOSO0WbIOVL+wJlQnvdBXIuBCty+6/13InEecc=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBjYS4x+GTOqkjCcFogoV8A1E6gb1xJeqE7gKHANrgO rXkTfpqJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCY2EuMQAKCRAk1otyXVSH0MFKB/ 4h0jn7E9AbZMAME+6KM2iFM/oeKHUFooaUjgNh9DnVOtUdQk2JtTqcbZfGCCPFGfmnBfGamj0kPIg4 kkjDUkGjCDA6OOAsicq0hzv221vRtLninqRhXIYvqx0W1oTAR3cgQpSMY2gJ3/5nNyTxaVhkySLtse X5C5JxDcAPh+ua07HhLsQ+Loc6tAC1zGxXYtGAcPShvuSYhd061OOqSdOokkoYFGxyZnKdYd+t3B3L 7R3AXB/irUkmkyAJgR6vOP1NUjQqPAQu1GBhBGFEhByVTo8KBsHwTfdFRsaG59TzI8db5OfD5bhlV/ biUsS5ZG4hRdFkbtQxDh4kJu2ggSPX X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB Precedence: bulk List-ID: X-Mailing-List: linux-kselftest@vger.kernel.org Add basic feature detection for SME2, detecting that the feature is present and disabling traps for ZT0. Signed-off-by: Mark Brown --- arch/arm64/include/asm/cpufeature.h | 6 ++++++ arch/arm64/include/asm/fpsimd.h | 1 + arch/arm64/kernel/cpufeature.c | 14 ++++++++++++++ arch/arm64/kernel/fpsimd.c | 11 +++++++++++ arch/arm64/tools/cpucaps | 1 + 5 files changed, 33 insertions(+) diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h index f73f11b55042..3ad41c26c9e7 100644 --- a/arch/arm64/include/asm/cpufeature.h +++ b/arch/arm64/include/asm/cpufeature.h @@ -769,6 +769,12 @@ static __always_inline bool system_supports_sme(void) cpus_have_const_cap(ARM64_SME); } +static __always_inline bool system_supports_sme2(void) +{ + return IS_ENABLED(CONFIG_ARM64_SME) && + cpus_have_const_cap(ARM64_SME2); +} + static __always_inline bool system_supports_fa64(void) { return IS_ENABLED(CONFIG_ARM64_SME) && diff --git a/arch/arm64/include/asm/fpsimd.h b/arch/arm64/include/asm/fpsimd.h index a18a86ccfd82..f2bda963cfe5 100644 --- a/arch/arm64/include/asm/fpsimd.h +++ b/arch/arm64/include/asm/fpsimd.h @@ -109,6 +109,7 @@ extern void za_load_state(void const *state); struct arm64_cpu_capabilities; extern void sve_kernel_enable(const struct arm64_cpu_capabilities *__unused); extern void sme_kernel_enable(const struct arm64_cpu_capabilities *__unused); +extern void sme2_kernel_enable(const struct arm64_cpu_capabilities *__unused); extern void fa64_kernel_enable(const struct arm64_cpu_capabilities *__unused); extern u64 read_zcr_features(void); diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index bb1ef8cf7d04..416785eeb512 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -282,6 +282,8 @@ static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = { static const struct arm64_ftr_bits ftr_id_aa64smfr0[] = { ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_FA64_SHIFT, 1, 0), + ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), + FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SMEver_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I16I64_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), @@ -2618,6 +2620,18 @@ static const struct arm64_cpu_capabilities arm64_features[] = { .matches = has_cpuid_feature, .cpu_enable = fa64_kernel_enable, }, + { + .desc = "SME2", + .type = ARM64_CPUCAP_SYSTEM_FEATURE, + .capability = ARM64_SME2, + .sys_reg = SYS_ID_AA64SMFR0_EL1, + .sign = FTR_UNSIGNED, + .field_pos = ID_AA64SMFR0_EL1_SMEver_SHIFT, + .field_width = ID_AA64SMFR0_EL1_SMEver_WIDTH, + .min_field_value = ID_AA64SMFR0_EL1_SMEver_SME2, + .matches = has_cpuid_feature, + .cpu_enable = sme2_kernel_enable, + }, #endif /* CONFIG_ARM64_SME */ { .desc = "WFx with timeout", diff --git a/arch/arm64/kernel/fpsimd.c b/arch/arm64/kernel/fpsimd.c index b677b5a3e0f6..73ec8850a402 100644 --- a/arch/arm64/kernel/fpsimd.c +++ b/arch/arm64/kernel/fpsimd.c @@ -1254,6 +1254,17 @@ void sme_kernel_enable(const struct arm64_cpu_capabilities *__always_unused p) isb(); } +/* + * This must be called after sme_kernel_enable(), we rely on the + * feature table being sorted to ensure this. + */ +void sme2_kernel_enable(const struct arm64_cpu_capabilities *__always_unused p) +{ + /* Allow use of ZT0 */ + write_sysreg_s(read_sysreg_s(SYS_SMCR_EL1) | SMCR_ELx_EZT0_MASK, + SYS_SMCR_EL1); +} + /* * This must be called after sme_kernel_enable(), we rely on the * feature table being sorted to ensure this. diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps index f1c0347ec31a..79f511ef3195 100644 --- a/arch/arm64/tools/cpucaps +++ b/arch/arm64/tools/cpucaps @@ -49,6 +49,7 @@ MTE MTE_ASYMM SME SME_FA64 +SME2 SPECTRE_V2 SPECTRE_V3A SPECTRE_V4 From patchwork Tue Nov 1 14:33:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 13026988 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 37E20C43217 for ; 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s=k20201202; t=1667313577; bh=WtLZskmj0qPo98o2L14apeeTu/h7b96ZNMltJ+zQPHo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=cTjyV/81DGsCax1YBvLPB1mDTZkpe2yPHjYicXsB8M5Z0SJ3n2d5k9rYVtM0TyPvI GYCW0mRYTVcVrmopebHLgb6/FqSfeKXru0v1wB6kph4n3T87A8jgu+cDpQ7LkSZVoD x8V3M6w7IWTXzr68/XnKZqCoLF2Chm6FhvMQJmSpsBKUEzgcvIDGF/Cavfup8z6ovf Xkby0gzwa7cFiOyhsOwCQx/BGhzRT8aLyVqrtyMmjUMOq43Cq6XdHWYBXmmiGW8cEx +u9v42T990oukUefN1lyDNpTXl6Oelyyp+FidZAgSPcDnVhCkItZ1UJvdW74vcRJTq o/4SxpG+lJofA== From: Mark Brown To: Catalin Marinas , Will Deacon , Shuah Khan , Shuah Khan Cc: Alan Hayward , Luis Machado , Szabolcs Nagy , linux-arm-kernel@lists.infradead.org, linux-kselftest@vger.kernel.org, Mark Brown Subject: [PATCH v2 09/21] arm64/sme: Provide storage for ZT0 Date: Tue, 1 Nov 2022 14:33:24 +0000 Message-Id: <20221101143336.254445-10-broonie@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20221101143336.254445-1-broonie@kernel.org> References: <20221101143336.254445-1-broonie@kernel.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=3004; i=broonie@kernel.org; h=from:subject; bh=WtLZskmj0qPo98o2L14apeeTu/h7b96ZNMltJ+zQPHo=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBjYS4yQsw2eFc36W6Nj2o/z05lO1c+jtujGyIEcwYm QWn+JCuJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCY2EuMgAKCRAk1otyXVSH0GT0CA CDgeib0V8bpeC2U5Wm52+G07etBIqOvvQO8A5iPLCugp6sKf2R6SuKT+iVBLyOqsjKnCgdmS7FhDJ+ NAZixiFw7ryQvTYC5fNhLtG8ILHvhJUTLoFL0FiEY8KO2358CxifvVcNEZtq+94itropg2huYOhAVc 7F2bb1Bx5Scb+ext5usFdCgi9hD9R6CkRXehWo+N0D33+mb+oq3rYKT9W1ds34oTCB399y+LD4A6pH sEAxmzQiKnVm+Ws/dRRaU/ZVvPw5lQ+irSjuZ8UecDroS8XO3P2cKUPwpTVszpm6qJmwqkXNcP7W6x D/WlYpnxq+1V9oOkcgHG9voHE0ScvR X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB Precedence: bulk List-ID: X-Mailing-List: linux-kselftest@vger.kernel.org When the system supports SME2 there is an additional register ZT0 which we must store when the task is using SME. Since ZT0 is accessible only when PSTATE.ZA is set just like ZA we allocate storage for it along with ZA, increasing the allocation size for the memory region where we store ZA and storing the data for ZT after that for ZA. Signed-off-by: Mark Brown --- arch/arm64/include/asm/fpsimd.h | 13 +++++++++++++ arch/arm64/kernel/process.c | 10 +++++----- 2 files changed, 18 insertions(+), 5 deletions(-) diff --git a/arch/arm64/include/asm/fpsimd.h b/arch/arm64/include/asm/fpsimd.h index f2bda963cfe5..2d7a69b49349 100644 --- a/arch/arm64/include/asm/fpsimd.h +++ b/arch/arm64/include/asm/fpsimd.h @@ -96,6 +96,13 @@ static inline void *sve_pffr(struct thread_struct *thread) return (char *)thread->sve_state + sve_ffr_offset(vl); } +static inline void *thread_zt_state(struct thread_struct *thread) +{ + /* The ZT register state is stored immediately after the ZA state */ + unsigned int sme_vq = sve_vq_from_vl(thread_get_sme_vl(thread)); + return thread->sme_state + ZA_SIG_REGS_SIZE(sme_vq); +} + extern void sve_save_state(void *state, u32 *pfpsr, int save_ffr); extern void sve_load_state(void const *state, u32 const *pfpsr, int restore_ffr); @@ -345,6 +352,9 @@ extern unsigned int sme_get_vl(void); extern int sme_set_current_vl(unsigned long arg); extern int sme_get_current_vl(void); +/* Will move with signal support */ +#define ZT_SIG_REG_SIZE 512 + /* * Return how many bytes of memory are required to store the full SME * specific state for task, given task's currently configured vector @@ -357,6 +367,9 @@ static inline size_t sme_state_size(struct task_struct const *task) size = ZA_SIG_REGS_SIZE(sve_vq_from_vl(vl)); + if (system_supports_sme2()) + size += ZT_SIG_REG_SIZE; + return size; } diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c index 5cfb876c76ee..b7919bf45e2e 100644 --- a/arch/arm64/kernel/process.c +++ b/arch/arm64/kernel/process.c @@ -307,11 +307,11 @@ int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src) /* * In the unlikely event that we create a new thread with ZA - * enabled we should retain the ZA state so duplicate it here. - * This may be shortly freed if we exec() or if CLONE_SETTLS - * but it's simpler to do it here. To avoid confusing the rest - * of the code ensure that we have a sve_state allocated - * whenever za_state is allocated. + * enabled we should retain the ZA and ZT state so duplicate + * it here. This may be shortly freed if we exec() or if + * CLONE_SETTLS but it's simpler to do it here. To avoid + * confusing the rest of the code ensure that we have a + * sve_state allocated whenever za_state is allocated. */ if (thread_za_enabled(&src->thread)) { dst->thread.sve_state = kzalloc(sve_state_size(src), From patchwork Tue Nov 1 14:33:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 13026989 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 44D85C4332F for ; Tue, 1 Nov 2022 14:39:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230336AbiKAOjo (ORCPT ); Tue, 1 Nov 2022 10:39:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53012 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230335AbiKAOjn (ORCPT ); Tue, 1 Nov 2022 10:39:43 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 07C61120B8 for ; Tue, 1 Nov 2022 07:39:43 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id A8A3EB81DE7 for ; Tue, 1 Nov 2022 14:39:41 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 445DAC43470; Tue, 1 Nov 2022 14:39:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1667313580; bh=mpO5Qxgy63SzKSm0Pa637DSx9B/LwRyQmrBGvfcgjI4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=uLPY8ISrAQM1IcwRt+e6glqWUD4UUhWhbIfjpBl7fu1hVoRp0auxf45pkcsIsfPV+ YuNBH7rLjoU1njZ3N5WF09uX6Uv0U5dvYgaIg+BsrQfWmnLuu3hy4HEOUk275yDy3p GIdBFV40FNfzrmrtiqvet2IIampGYnC0pu2iCfqb/+AGTabfHzstiGCCUaqR3i7kD2 UpqeW7pW3j1des7NTmgxnLH3WzexI+FmS6C5+zVxGpmwgxeaimnakAk7az1/li5eT4 zC9Oi+mjmeM56noZGYbos3u8oJX7Jkgg1MJSuCoLoQmAGKG4YSqzjHsijM54SxMiIv oF1yxJrg8Qqlg== From: Mark Brown To: Catalin Marinas , Will Deacon , Shuah Khan , Shuah Khan Cc: Alan Hayward , Luis Machado , Szabolcs Nagy , linux-arm-kernel@lists.infradead.org, linux-kselftest@vger.kernel.org, Mark Brown Subject: [PATCH v2 10/21] arm64/sme: Implement context switching for ZT0 Date: Tue, 1 Nov 2022 14:33:25 +0000 Message-Id: <20221101143336.254445-11-broonie@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20221101143336.254445-1-broonie@kernel.org> References: <20221101143336.254445-1-broonie@kernel.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=3458; i=broonie@kernel.org; h=from:subject; bh=mpO5Qxgy63SzKSm0Pa637DSx9B/LwRyQmrBGvfcgjI4=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBjYS4zdc/EIKP8qquj4JHn1sObOtN20Fi7cMiGER7Z YGdTDF+JATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCY2EuMwAKCRAk1otyXVSH0Hf9B/ sHUWBhFbCQTvgxgLRDQoO7uP6trnWCTyLZO0xGyJZitVcAyW2R7Cl7iOgTzSHb/4M7P1lLr45PFvjE 8ho8gFv1Wb2/pJKMz9JgkiI0xS8/Tsp/ab1cfxsSGVYKtPKjYCz9xnGbT+EhmrOehJJ2AeNt/dVqPY HNosuaKzdoPfua7xFrvsUXi6otS+pztyhURNBEuetf4vzsolyij0h4X/7CDjBatHjRW8M+Jcl5vhDS MJR5XTNdTQKvqSYcSnF7uSZhqj5YG9oq7bkmkmj1b86rCtoWQcxRzWW7qqvS/FCXDu9enol1E/mzIy SBdGSLufIdkXeYbwOpocSvtTHgxHWb X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB Precedence: bulk List-ID: X-Mailing-List: linux-kselftest@vger.kernel.org When the system supports SME2 the ZT0 register must be context switched as part of the floating point state. This register is stored immediately after ZA in memory and is only accessible when PSTATE.ZA is set so we handle it in the same functions we use to save and restore ZA. Signed-off-by: Mark Brown --- arch/arm64/include/asm/fpsimd.h | 4 ++-- arch/arm64/kernel/entry-fpsimd.S | 30 ++++++++++++++++++++---------- arch/arm64/kernel/fpsimd.c | 6 ++++-- 3 files changed, 26 insertions(+), 14 deletions(-) diff --git a/arch/arm64/include/asm/fpsimd.h b/arch/arm64/include/asm/fpsimd.h index 2d7a69b49349..42c019936dfd 100644 --- a/arch/arm64/include/asm/fpsimd.h +++ b/arch/arm64/include/asm/fpsimd.h @@ -110,8 +110,8 @@ extern void sve_flush_live(bool flush_ffr, unsigned long vq_minus_1); extern unsigned int sve_get_vl(void); extern void sve_set_vq(unsigned long vq_minus_1); extern void sme_set_vq(unsigned long vq_minus_1); -extern void za_save_state(void *state); -extern void za_load_state(void const *state); +extern void sme_save_state(void *state, int zt); +extern void sme_load_state(void const *state, int zt); struct arm64_cpu_capabilities; extern void sve_kernel_enable(const struct arm64_cpu_capabilities *__unused); diff --git a/arch/arm64/kernel/entry-fpsimd.S b/arch/arm64/kernel/entry-fpsimd.S index 229436f33df5..6325db1a2179 100644 --- a/arch/arm64/kernel/entry-fpsimd.S +++ b/arch/arm64/kernel/entry-fpsimd.S @@ -100,25 +100,35 @@ SYM_FUNC_START(sme_set_vq) SYM_FUNC_END(sme_set_vq) /* - * Save the SME state + * Save the ZA and ZT state * * x0 - pointer to buffer for state + * x1 - number of ZT registers to save */ -SYM_FUNC_START(za_save_state) - _sme_rdsvl 1, 1 // x1 = VL/8 - sme_save_za 0, x1, 12 +SYM_FUNC_START(sme_save_state) + _sme_rdsvl 2, 1 // x2 = VL/8 + sme_save_za 0, x2, 12 // Leaves x0 pointing to the end of ZA + + cbz x1, 1f + _str_zt 0 +1: ret -SYM_FUNC_END(za_save_state) +SYM_FUNC_END(sme_save_state) /* - * Load the SME state + * Load the ZA and ZT state * * x0 - pointer to buffer for state + * x1 - number of ZT registers to save */ -SYM_FUNC_START(za_load_state) - _sme_rdsvl 1, 1 // x1 = VL/8 - sme_load_za 0, x1, 12 +SYM_FUNC_START(sme_load_state) + _sme_rdsvl 2, 1 // x2 = VL/8 + sme_load_za 0, x2, 12 // Leaves x0 pointing to the end of ZA + + cbz x1, 1f + _ldr_zt 0 +1: ret -SYM_FUNC_END(za_load_state) +SYM_FUNC_END(sme_load_state) #endif /* CONFIG_ARM64_SME */ diff --git a/arch/arm64/kernel/fpsimd.c b/arch/arm64/kernel/fpsimd.c index 73ec8850a402..b7f4eef42f86 100644 --- a/arch/arm64/kernel/fpsimd.c +++ b/arch/arm64/kernel/fpsimd.c @@ -396,7 +396,8 @@ static void task_fpsimd_load(void) write_sysreg_s(current->thread.svcr, SYS_SVCR); if (thread_za_enabled(¤t->thread)) - za_load_state(current->thread.sme_state); + sme_load_state(current->thread.sme_state, + system_supports_sme2()); if (thread_sm_enabled(¤t->thread)) { restore_sve_regs = true; @@ -449,7 +450,8 @@ static void fpsimd_save(void) *svcr = read_sysreg_s(SYS_SVCR); if (*svcr & SVCR_ZA_MASK) - za_save_state(last->sme_state); + sme_save_state(last->sme_state, + system_supports_sme2()); /* If we are in streaming mode override regular SVE. */ if (*svcr & SVCR_SM_MASK) { From patchwork Tue Nov 1 14:33:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 13026990 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A9C9FC4332F for ; Tue, 1 Nov 2022 14:39:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230344AbiKAOjr (ORCPT ); Tue, 1 Nov 2022 10:39:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53028 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230335AbiKAOjq (ORCPT ); Tue, 1 Nov 2022 10:39:46 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C8D64120B8 for ; Tue, 1 Nov 2022 07:39:45 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 54028B81CC4 for ; Tue, 1 Nov 2022 14:39:44 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id D48B5C43142; Tue, 1 Nov 2022 14:39:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1667313583; bh=gqqU9mq6qOVcKT2rPaWnupV2Z7inErUAfg5WJJ3Pu+o=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=fiUiQGUjcvSds8Cinba4AnIlMCiX01Uib1RNGOwEVIuudI4zr0NXezYkPLoNPhs6F COWoCHO0OkXhqUb2EzzG1t5y6JLSi0W0n8EZOfaouvo08471AKnGe8U2COctygV/FH ZMFBjvmmPHCrAh5JjA64szBgpmpmuH2Dj2MdOU2CIEoc+ih+JSpC1cb17ZLfwnq5Hj xKwWqBQY3q6UV6DJ80tzOdh81G0/C/0KrdpuybybVCYpGW7YqH1/JMl0oTij/qq4zr oZY+lPnb1amryNFKUWJIoScLk9gR2yLmFIsX9VbyD8nfG682EMoiaJ/YpJIlochz36 AzfWel0zr7A2Q== From: Mark Brown To: Catalin Marinas , Will Deacon , Shuah Khan , Shuah Khan Cc: Alan Hayward , Luis Machado , Szabolcs Nagy , linux-arm-kernel@lists.infradead.org, linux-kselftest@vger.kernel.org, Mark Brown Subject: [PATCH v2 11/21] arm64/sme: Implement signal handling for ZT Date: Tue, 1 Nov 2022 14:33:26 +0000 Message-Id: <20221101143336.254445-12-broonie@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20221101143336.254445-1-broonie@kernel.org> References: <20221101143336.254445-1-broonie@kernel.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=7263; i=broonie@kernel.org; h=from:subject; bh=gqqU9mq6qOVcKT2rPaWnupV2Z7inErUAfg5WJJ3Pu+o=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBjYS40Bawn7KIyMoylCz7Pt9d+wpnURM7Al75/pdUm ZnSrM+iJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCY2EuNAAKCRAk1otyXVSH0IKmB/ 937SqwYsIxUjxGPQ/Yt4QDOnOTNID/Fd70QApFzwtLYW7tdUt/ov76LoZXOn5ueI21eHamiWgN9eXx aUwPwAYEdJTmhJax1VOzGtL6pN/keFGHKLCFPMH5EZzQrDbw3URe7KIMH5KhG6KZk+Ky3Ns4wNZjML Id+j2q0MbwDpPxMtiEYbjLvdCjvhBNXlZWIaX0E24le5qBOAHqT7G5GjmPK6QWUo2K0nZ5jevPAmHX 0DM8WPjo2mBFZeV9OxNAUWyN51XYmRY+hBBGPiY3AN9Op2UWuapElsxImSlULPIXXAVGBSZVVecHms SG6YQbeieGZctPfg9i48mEe+0evXhP X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB Precedence: bulk List-ID: X-Mailing-List: linux-kselftest@vger.kernel.org Add a new signal context type for ZT which is present in the signal frame when ZA is enabled and ZT is supported by the system. In order to account for the possible addition of further ZT registers in the future we make the number of registers variable in the ABI, though currently the only possible number is 1. We could just use a bare list head for the context since the number of registers can be inferred from the size of the context but for usability and future extensibility we define a header with the number of registers and some reserved fields in it. Signed-off-by: Mark Brown --- arch/arm64/include/asm/fpsimd.h | 3 - arch/arm64/include/uapi/asm/sigcontext.h | 19 ++++ arch/arm64/kernel/signal.c | 105 +++++++++++++++++++++++ 3 files changed, 124 insertions(+), 3 deletions(-) diff --git a/arch/arm64/include/asm/fpsimd.h b/arch/arm64/include/asm/fpsimd.h index 42c019936dfd..5c93cb5337c9 100644 --- a/arch/arm64/include/asm/fpsimd.h +++ b/arch/arm64/include/asm/fpsimd.h @@ -352,9 +352,6 @@ extern unsigned int sme_get_vl(void); extern int sme_set_current_vl(unsigned long arg); extern int sme_get_current_vl(void); -/* Will move with signal support */ -#define ZT_SIG_REG_SIZE 512 - /* * Return how many bytes of memory are required to store the full SME * specific state for task, given task's currently configured vector diff --git a/arch/arm64/include/uapi/asm/sigcontext.h b/arch/arm64/include/uapi/asm/sigcontext.h index 4aaf31e3bf16..177f16cc96b8 100644 --- a/arch/arm64/include/uapi/asm/sigcontext.h +++ b/arch/arm64/include/uapi/asm/sigcontext.h @@ -148,6 +148,14 @@ struct za_context { __u16 __reserved[3]; }; +#define ZT_MAGIC 0x5a544e01 + +struct zt_context { + struct _aarch64_ctx head; + __u16 nregs; + __u16 __reserved[3]; +}; + #endif /* !__ASSEMBLY__ */ #include @@ -300,4 +308,15 @@ struct za_context { #define ZA_SIG_CONTEXT_SIZE(vq) \ (ZA_SIG_REGS_OFFSET + ZA_SIG_REGS_SIZE(vq)) +#define ZT_SIG_REG_SIZE 512 + +#define ZT_SIG_REG_BYTES (ZT_SIG_REG_SIZE / 8) + +#define ZT_SIG_REGS_OFFSET sizeof(struct zt_context) + +#define ZT_SIG_REGS_SIZE(n) (ZT_SIG_REG_BYTES * n) + +#define ZT_SIG_CONTEXT_SIZE(n) \ + (sizeof(struct zt_context) + ZT_SIG_REGS_SIZE(n)) + #endif /* _UAPI__ASM_SIGCONTEXT_H */ diff --git a/arch/arm64/kernel/signal.c b/arch/arm64/kernel/signal.c index 335bc7294b3c..6e20f0b23d73 100644 --- a/arch/arm64/kernel/signal.c +++ b/arch/arm64/kernel/signal.c @@ -57,6 +57,7 @@ struct rt_sigframe_user_layout { unsigned long esr_offset; unsigned long sve_offset; unsigned long za_offset; + unsigned long zt_offset; unsigned long extra_offset; unsigned long end_offset; }; @@ -220,6 +221,7 @@ struct user_ctxs { struct fpsimd_context __user *fpsimd; struct sve_context __user *sve; struct za_context __user *za; + struct zt_context __user *zt; }; #ifdef CONFIG_ARM64_SVE @@ -444,11 +446,81 @@ static int restore_za_context(struct user_ctxs *user) return 0; } + +static int preserve_zt_context(struct zt_context __user *ctx) +{ + int err = 0; + u16 reserved[ARRAY_SIZE(ctx->__reserved)]; + + if (WARN_ON(!thread_za_enabled(¤t->thread))) + return -EINVAL; + + memset(reserved, 0, sizeof(reserved)); + + __put_user_error(ZT_MAGIC, &ctx->head.magic, err); + __put_user_error(round_up(ZT_SIG_CONTEXT_SIZE(1), 16), + &ctx->head.size, err); + __put_user_error(1, &ctx->nregs, err); + BUILD_BUG_ON(sizeof(ctx->__reserved) != sizeof(reserved)); + err |= __copy_to_user(&ctx->__reserved, reserved, sizeof(reserved)); + + /* + * This assumes that the ZT state has already been saved to + * the task struct by calling the function + * fpsimd_signal_preserve_current_state(). + */ + err |= __copy_to_user((char __user *)ctx + ZT_SIG_REGS_OFFSET, + thread_zt_state(¤t->thread), + ZT_SIG_REGS_SIZE(1)); + + return err ? -EFAULT : 0; +} + +static int restore_zt_context(struct user_ctxs *user) +{ + int err; + struct zt_context zt; + + /* ZA must be restored first for this check to be valid */ + if (!thread_za_enabled(¤t->thread)) + return -EINVAL; + + if (__copy_from_user(&zt, user->zt, sizeof(zt))) + return -EFAULT; + + if (zt.nregs != 1) + return -EINVAL; + + if (zt.head.size != ZT_SIG_CONTEXT_SIZE(zt.nregs)) + return -EINVAL; + + /* + * Careful: we are about __copy_from_user() directly into + * thread.zt_state with preemption enabled, so protection is + * needed to prevent a racing context switch from writing stale + * registers back over the new data. + */ + + fpsimd_flush_task_state(current); + /* From now, fpsimd_thread_switch() won't touch ZT in thread state */ + + err = __copy_from_user(thread_zt_state(¤t->thread), + (char __user const *)user->zt + + ZT_SIG_REGS_OFFSET, + ZT_SIG_REGS_SIZE(1)); + if (err) + return -EFAULT; + + return 0; +} + #else /* ! CONFIG_ARM64_SME */ /* Turn any non-optimised out attempts to use these into a link error: */ extern int preserve_za_context(void __user *ctx); extern int restore_za_context(struct user_ctxs *user); +extern int preserve_zt_context(void __user *ctx); +extern int restore_zt_context(struct user_ctxs *user); #endif /* ! CONFIG_ARM64_SME */ @@ -466,6 +538,7 @@ static int parse_user_sigframe(struct user_ctxs *user, user->fpsimd = NULL; user->sve = NULL; user->za = NULL; + user->zt = NULL; if (!IS_ALIGNED((unsigned long)base, 16)) goto invalid; @@ -544,6 +617,19 @@ static int parse_user_sigframe(struct user_ctxs *user, user->za = (struct za_context __user *)head; break; + case ZT_MAGIC: + if (!system_supports_sme2()) + goto invalid; + + if (user->zt) + goto invalid; + + if (size < sizeof(*user->zt)) + goto invalid; + + user->zt = (struct zt_context __user *)head; + break; + case EXTRA_MAGIC: if (have_extra_context) goto invalid; @@ -666,6 +752,9 @@ static int restore_sigframe(struct pt_regs *regs, if (err == 0 && system_supports_sme() && user.za) err = restore_za_context(&user); + if (err == 0 && system_supports_sme2() && user.zt) + err = restore_zt_context(&user); + return err; } @@ -766,6 +855,15 @@ static int setup_sigframe_layout(struct rt_sigframe_user_layout *user, return err; } + if (system_supports_sme2()) { + if (add_all || thread_za_enabled(¤t->thread)) { + err = sigframe_alloc(user, &user->zt_offset, + ZT_SIG_CONTEXT_SIZE(1)); + if (err) + return err; + } + } + return sigframe_alloc_end(user); } @@ -821,6 +919,13 @@ static int setup_sigframe(struct rt_sigframe_user_layout *user, err |= preserve_za_context(za_ctx); } + /* ZT state if present */ + if (system_supports_sme2() && err == 0 && user->zt_offset) { + struct zt_context __user *zt_ctx = + apply_user_offset(user, user->zt_offset); + err |= preserve_zt_context(zt_ctx); + } + if (err == 0 && user->extra_offset) { char __user *sfp = (char __user *)user->sigframe; char __user *userp = From patchwork Tue Nov 1 14:33:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 13026991 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EADC6C433FE for ; Tue, 1 Nov 2022 14:39:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230346AbiKAOju (ORCPT ); Tue, 1 Nov 2022 10:39:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53040 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230335AbiKAOjt (ORCPT ); Tue, 1 Nov 2022 10:39:49 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3FAE0120B8 for ; Tue, 1 Nov 2022 07:39:48 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id E5B60B81DE7 for ; Tue, 1 Nov 2022 14:39:46 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 74DEEC43470; Tue, 1 Nov 2022 14:39:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1667313585; bh=2yXo9o3hNxGIp4LEAKIBC5DAGZ6BWI4M1U6pYwioPZo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=tyMcw2K9JzmwNo3J1odk6gU5zq3jlKs/orxnJxvO13PlNKP2unS8IadnEJUbiJ9HU r8UX6Nbi0bCdONYHuEgudXFyhYi8y0xxjA6Ey3r0q2Kid6JVHBgCQamtgT7GKfBNUd zcbVW4y4IV0FBnt6Id9hE6PihqJ66GFEGxkrJaWtbSxFPOBNF/PMoudLalyGA4Xz86 h0xFOeSmw5HlbP5QTO7ltivwMRGFZzx0qxY5ujeqjKp3BVSL3zwHJitLMJMU4QZ+v8 WogOkb4oWWnaI5YcQOg9+Rw3myukkVviuu3/qvCahvvaJ4qVXIqSzL9YIjZPZS7hFL 7CoN3LUfeiYmA== From: Mark Brown To: Catalin Marinas , Will Deacon , Shuah Khan , Shuah Khan Cc: Alan Hayward , Luis Machado , Szabolcs Nagy , linux-arm-kernel@lists.infradead.org, linux-kselftest@vger.kernel.org, Mark Brown Subject: [PATCH v2 12/21] arm64/sme: Implement ZT0 ptrace support Date: Tue, 1 Nov 2022 14:33:27 +0000 Message-Id: <20221101143336.254445-13-broonie@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20221101143336.254445-1-broonie@kernel.org> References: <20221101143336.254445-1-broonie@kernel.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=3346; i=broonie@kernel.org; h=from:subject; bh=2yXo9o3hNxGIp4LEAKIBC5DAGZ6BWI4M1U6pYwioPZo=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBjYS42IHr+4F+T5foHYkSAPnY1aC9MVFsLFgrd/GU7 7tc4ET6JATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCY2EuNgAKCRAk1otyXVSH0EBPB/ 9FLZs7frO8oZEtnhw43SumYowLUmFtp/OfJ1OOe1DYVdBuDFfmn8EIk//uKkAVmdZwiZxVBBsJn1lp D8L0Bi9FtALLGlTF7ewUEECN9g4CJF3t2NmeayXs0h/x2v3II2UNwJ8Jl6sN4z2MEuT7W63bsbsLuH /omcyNe3iCzCcqAfPFzUUjatgSXetdbLnUShWitj3DC5Upk73IoNB3Lr49g8CR8jniysWdbRA0Ad1j e8aUCukVdfCNWjWIfMnIHW/g+FWQ8eyqcQH26LTjqeIhWjClLn/UOjgxLSMeJaMqtuBvDnInteWcpg S2RpbZyZbOPRBptQM/6Y0HdAn5MK4N X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB Precedence: bulk List-ID: X-Mailing-List: linux-kselftest@vger.kernel.org Implement support for a new note type NT_ARM64_ZT providing access to ZT0 when implemented. Since ZT0 is a register with constant size this is much simpler than for other SME state. As ZT0 is only accessible when PSTATE.ZA is set writes to ZT0 cause PSTATE.ZA to be set, the main alternative would be to return -EBUSY in this case but this seemed more constructive. Practical users are also going to be working with ZA anyway and have some understanding of the state. Signed-off-by: Mark Brown --- arch/arm64/kernel/ptrace.c | 54 ++++++++++++++++++++++++++++++++++++++ include/uapi/linux/elf.h | 1 + 2 files changed, 55 insertions(+) diff --git a/arch/arm64/kernel/ptrace.c b/arch/arm64/kernel/ptrace.c index 85105375bea5..a508f3a69d9f 100644 --- a/arch/arm64/kernel/ptrace.c +++ b/arch/arm64/kernel/ptrace.c @@ -1145,6 +1145,51 @@ static int za_set(struct task_struct *target, return ret; } +static int zt_get(struct task_struct *target, + const struct user_regset *regset, + struct membuf to) +{ + if (!system_supports_sme2()) + return -EINVAL; + + /* + * If PSTATE.ZA is not set then ZT will be zeroed when it is + * enabled so report the current register value as zero. + */ + if (thread_za_enabled(&target->thread)) + membuf_write(&to, thread_zt_state(&target->thread), + ZT_SIG_REG_BYTES); + else + membuf_zero(&to, ZT_SIG_REG_BYTES); + + return 0; +} + +static int zt_set(struct task_struct *target, + const struct user_regset *regset, + unsigned int pos, unsigned int count, + const void *kbuf, const void __user *ubuf) +{ + int ret; + + if (!system_supports_sme2()) + return -EINVAL; + + if (!thread_za_enabled(&target->thread)) { + sme_alloc(target); + if (!target->thread.sme_state) + return -ENOMEM; + } + + ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, + thread_zt_state(&target->thread), + 0, ZT_SIG_REG_BYTES); + if (ret == 0) + target->thread.svcr |= SVCR_ZA_MASK; + + return ret; +} + #endif /* CONFIG_ARM64_SME */ #ifdef CONFIG_ARM64_PTR_AUTH @@ -1367,6 +1412,7 @@ enum aarch64_regset { #ifdef CONFIG_ARM64_SVE REGSET_SSVE, REGSET_ZA, + REGSET_ZT, #endif #ifdef CONFIG_ARM64_PTR_AUTH REGSET_PAC_MASK, @@ -1474,6 +1520,14 @@ static const struct user_regset aarch64_regsets[] = { .regset_get = za_get, .set = za_set, }, + [REGSET_ZT] = { /* SME ZA */ + .core_note_type = NT_ARM_ZT, + .n = 1, + .size = ZT_SIG_REG_BYTES, + .align = sizeof(u64), + .regset_get = zt_get, + .set = zt_set, + }, #endif #ifdef CONFIG_ARM64_PTR_AUTH [REGSET_PAC_MASK] = { diff --git a/include/uapi/linux/elf.h b/include/uapi/linux/elf.h index c7b056af9ef0..3a73c853c537 100644 --- a/include/uapi/linux/elf.h +++ b/include/uapi/linux/elf.h @@ -434,6 +434,7 @@ typedef struct elf64_shdr { #define NT_ARM_PAC_ENABLED_KEYS 0x40a /* arm64 ptr auth enabled keys (prctl()) */ #define NT_ARM_SSVE 0x40b /* ARM Streaming SVE registers */ #define NT_ARM_ZA 0x40c /* ARM SME ZA registers */ +#define NT_ARM_ZT 0x40d /* ARM SME ZT registers */ #define NT_ARC_V2 0x600 /* ARCv2 accumulator/extra registers */ #define NT_VMCOREDD 0x700 /* Vmcore Device Dump Note */ #define NT_MIPS_DSP 0x800 /* MIPS DSP ASE registers */ From patchwork Tue Nov 1 14:33:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 13026992 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D7D04C4332F for ; Tue, 1 Nov 2022 14:39:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230347AbiKAOjx (ORCPT ); Tue, 1 Nov 2022 10:39:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53050 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230335AbiKAOjv (ORCPT ); Tue, 1 Nov 2022 10:39:51 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EB012120B8 for ; Tue, 1 Nov 2022 07:39:50 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 6FFB2B81DDF for ; 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a=openpgp-sha256; l=7092; i=broonie@kernel.org; h=from:subject; bh=EzLh9y/wWpOrmNDMdT1ovFCSwFhlQ56HhItuIoPkVgw=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBjYS42tXWhw3c5emwbCVSBcNlWm7BnECun0MgWc8Db mIn7X4CJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCY2EuNgAKCRAk1otyXVSH0KQCB/ 9iuOJ0+xC03W+EFw5J3xR0eBuHwjcpysfy098bbCLFGuH9I8pBKh5rAwrFEO4NhgvMemjF7bH4Z/rk vQ1vfLC4omUdzQrAB1cLukslOMpFRjXJQH0Nd5p6d2WHsLzbB5ex7bOjQ35Lw4ut/49uq7aZw4Qou4 VRxVcayfPD/B++KfwZAQDd+UAUxDq5XwufEj3U51XunDMa+2bv9cNCESPEk1mMhbRYiAAI3+Mq29tO TE6atB4DN6o3B9q25ajCD/G8zQHtmy4e6uuKvAgYmkg1WhtYfvjvCcW8DxbyzyHJ9470fW2Ap1SYZF +VTcKXrdCG5PJcudPy4rH/3ZtdBeZS X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB Precedence: bulk List-ID: X-Mailing-List: linux-kselftest@vger.kernel.org In order to allow userspace to discover the presence of the new SME features add hwcaps for them. Signed-off-by: Mark Brown --- Documentation/arm64/elf_hwcaps.rst | 18 ++++++++++++++++++ arch/arm64/include/asm/hwcap.h | 6 ++++++ arch/arm64/include/uapi/asm/hwcap.h | 6 ++++++ arch/arm64/kernel/cpufeature.c | 13 +++++++++++++ arch/arm64/kernel/cpuinfo.c | 6 ++++++ 5 files changed, 49 insertions(+) diff --git a/Documentation/arm64/elf_hwcaps.rst b/Documentation/arm64/elf_hwcaps.rst index 6fed84f935df..29a3dd1b8f5a 100644 --- a/Documentation/arm64/elf_hwcaps.rst +++ b/Documentation/arm64/elf_hwcaps.rst @@ -284,6 +284,24 @@ HWCAP2_RPRFM HWCAP2_SVE2P1 Functionality implied by ID_AA64ZFR0_EL1.SVEver == 0b0010. +HWCAP2_SME2 + Functionality implied by ID_AA64SMFR0_EL1.SMEver == 0b0001. + +HWCAP2_SME2P1 + Functionality implied by ID_AA64SMFR0_EL1.SMEver == 0b0010. + +HWCAP2_SMEI16I32 + Functionality implied by ID_AA64SMFR0_EL1.I16I32 == 0b0101 + +HWCAP2_SMEBI32I32 + Functionality implied by ID_AA64SMFR0_EL1.I32I32 == 0b1 + +HWCAP2_SMEB16B16 + Functionality implied by ID_AA64SMFR0_EL1.B16B16 == 0b1 + +HWCAP2_SMEF16F16 + Functionality implied by ID_AA64SMFR0_EL1.F16F16 == 0b1 + 4. Unused AT_HWCAP bits ----------------------- diff --git a/arch/arm64/include/asm/hwcap.h b/arch/arm64/include/asm/hwcap.h index 06dd12c514e6..475c803ecf42 100644 --- a/arch/arm64/include/asm/hwcap.h +++ b/arch/arm64/include/asm/hwcap.h @@ -123,6 +123,12 @@ #define KERNEL_HWCAP_CSSC __khwcap2_feature(CSSC) #define KERNEL_HWCAP_RPRFM __khwcap2_feature(RPRFM) #define KERNEL_HWCAP_SVE2P1 __khwcap2_feature(SVE2P1) +#define KERNEL_HWCAP_SME2 __khwcap2_feature(SME2) +#define KERNEL_HWCAP_SME2P1 __khwcap2_feature(SME2P1) +#define KERNEL_HWCAP_SME_I16I32 __khwcap2_feature(SME_I16I32) +#define KERNEL_HWCAP_SME_BI32I32 __khwcap2_feature(SME_BI32I32) +#define KERNEL_HWCAP_SME_B16B16 __khwcap2_feature(SME_B16B16) +#define KERNEL_HWCAP_SME_F16F16 __khwcap2_feature(SME_F16F16) /* * This yields a mask that user programs can use to figure out what diff --git a/arch/arm64/include/uapi/asm/hwcap.h b/arch/arm64/include/uapi/asm/hwcap.h index b713d30544f1..69a4fb749c65 100644 --- a/arch/arm64/include/uapi/asm/hwcap.h +++ b/arch/arm64/include/uapi/asm/hwcap.h @@ -96,5 +96,11 @@ #define HWCAP2_CSSC (1UL << 34) #define HWCAP2_RPRFM (1UL << 35) #define HWCAP2_SVE2P1 (1UL << 36) +#define HWCAP2_SME2 (1UL << 37) +#define HWCAP2_SME2P1 (1UL << 38) +#define HWCAP2_SME_I16I32 (1UL << 39) +#define HWCAP2_SME_BI32I32 (1UL << 40) +#define HWCAP2_SME_B16B16 (1UL << 41) +#define HWCAP2_SME_F16F16 (1UL << 42) #endif /* _UAPI__ASM_HWCAP_H */ diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 416785eeb512..fd517dfe909a 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -288,12 +288,20 @@ static const struct arm64_ftr_bits ftr_id_aa64smfr0[] = { FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I16I64_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F64F64_SHIFT, 1, 0), + ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), + FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I16I32_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), + FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_B16B16_SHIFT, 1, 0), + ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), + FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F16F16_SHIFT, 1, 0), ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I8I32_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F16F32_SHIFT, 1, 0), ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_B16F32_SHIFT, 1, 0), + ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), + FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_BI32I32_SHIFT, 1, 0), ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F32F32_SHIFT, 1, 0), ARM64_FTR_END, @@ -2798,11 +2806,16 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { #ifdef CONFIG_ARM64_SME HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_EL1_SME_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR1_EL1_SME_IMP, CAP_HWCAP, KERNEL_HWCAP_SME), HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_EL1_FA64_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_EL1_FA64_IMP, CAP_HWCAP, KERNEL_HWCAP_SME_FA64), + HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_EL1_SMEver_SHIFT, 4, FTR_UNSIGNED, ID_AA64SMFR0_EL1_SMEver_SME2p1, CAP_HWCAP, KERNEL_HWCAP_SME2P1), + HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_EL1_SMEver_SHIFT, 4, FTR_UNSIGNED, ID_AA64SMFR0_EL1_SMEver_SME2, CAP_HWCAP, KERNEL_HWCAP_SME2), HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_EL1_I16I64_SHIFT, 4, FTR_UNSIGNED, ID_AA64SMFR0_EL1_I16I64_IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I16I64), HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_EL1_F64F64_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_EL1_F64F64_IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F64F64), + HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_EL1_F64F64_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_EL1_B16B16_IMP, CAP_HWCAP, KERNEL_HWCAP_SME_B16B16), + HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_EL1_F64F64_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_EL1_F16F16_IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F16F16), HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_EL1_I8I32_SHIFT, 4, FTR_UNSIGNED, ID_AA64SMFR0_EL1_I8I32_IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I8I32), HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_EL1_F16F32_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_EL1_F16F32_IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F16F32), HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_EL1_B16F32_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_EL1_B16F32_IMP, CAP_HWCAP, KERNEL_HWCAP_SME_B16F32), + HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_EL1_B16F32_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_EL1_BI32I32_IMP, CAP_HWCAP, KERNEL_HWCAP_SME_BI32I32), HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_EL1_F32F32_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_EL1_F32F32_IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F32F32), #endif /* CONFIG_ARM64_SME */ {}, diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c index 379695262b77..85e54417d141 100644 --- a/arch/arm64/kernel/cpuinfo.c +++ b/arch/arm64/kernel/cpuinfo.c @@ -119,6 +119,12 @@ static const char *const hwcap_str[] = { [KERNEL_HWCAP_CSSC] = "cssc", [KERNEL_HWCAP_RPRFM] = "rprfm", [KERNEL_HWCAP_SVE2P1] = "sve2p1", + [KERNEL_HWCAP_SME2] = "sme2", + [KERNEL_HWCAP_SME2P1] = "sme2p1", + [KERNEL_HWCAP_SME_I16I32] = "smei16i32", + [KERNEL_HWCAP_SME_BI32I32] = "smebi32i32", + [KERNEL_HWCAP_SME_B16B16] = "smeb16b16", + [KERNEL_HWCAP_SME_F16F16] = "smef16f16", }; #ifdef CONFIG_COMPAT From patchwork Tue Nov 1 14:33:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 13026993 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 67608C43217 for ; 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d=kernel.org; s=k20201202; t=1667313590; bh=Jb6w8cU2zmWHyNyhoentTlAJFr6uil/U2XQxkdBpcoc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=dlbSJ2292zHkXAwwLs3DtE7lAeDYD7k0CO1GjjJVRvE5KMMmtNlNCSOVW04ig2sw1 5MTW39BYIGgqPIQYOS6mqjR5zcVyu+ZMm+AO9uAMCvNexgQtEhwYQxbpp4+UOP1BeY hN6VM/jTtdpuLW5LADpuJQfrk7gxYCA9O7Xr+7Wn/mOHpaAinmWYeVdATzZzopLWb3 zV1JHqP190uDPKp3xTYpLAR51JmzZVXjQer+dCZrqEG7TTgA326aaY3hmV9gOs93Ax xOdiClZ+UD9zX1rbeTv5wbVbOU8S9fyhhdxzPocAWZRwVs+AA+UrYI3k3jG8M4sGg5 Z/kSstVQgux6g== From: Mark Brown To: Catalin Marinas , Will Deacon , Shuah Khan , Shuah Khan Cc: Alan Hayward , Luis Machado , Szabolcs Nagy , linux-arm-kernel@lists.infradead.org, linux-kselftest@vger.kernel.org, Mark Brown Subject: [PATCH v2 14/21] kselftest/arm64: Add a stress test program for ZT0 Date: Tue, 1 Nov 2022 14:33:29 +0000 Message-Id: <20221101143336.254445-15-broonie@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20221101143336.254445-1-broonie@kernel.org> References: <20221101143336.254445-1-broonie@kernel.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=8809; i=broonie@kernel.org; h=from:subject; bh=Jb6w8cU2zmWHyNyhoentTlAJFr6uil/U2XQxkdBpcoc=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBjYS43lKs0d7YvIzSdvCHe1aOqaM1yrLnixzNUtMhB wIPMXtOJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCY2EuNwAKCRAk1otyXVSH0G44B/ 9u01LS+W2eD2wCEzyNb461lpX90H6XqINTW0LSOXguhtVn8f2qkx8SyMGTxHN/XIec5jt2Jt6GGZG0 iwbHkTA1ELB+gaJznz3VAWrkzebU2q3EjwvRyWRUAXtsH2+b1LjE9GbYinN2WSRhFmQbkBgQGIH79K SlWpf2rK5WKbyO4HoiVMc301jKuAiBantEw8KbaOKdUMpRI1MHPdNYQgORAmACU8B0gtpM0sBWmWqh A/azYnk8ULflAWtSoNu/x0Kmf/e58iXWQ4RoNkyGIihmgXaJdniArRb2IdT/o387HGdg8mpc+MoUMj A5rTceq1UKS3IJc5gT5WDbeyTIh8TB X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB Precedence: bulk List-ID: X-Mailing-List: linux-kselftest@vger.kernel.org Following the pattern for the other register sets add a stress test program for ZT0 which continually loads and verifies patterns in the register in an effort to discover context switching problems. Signed-off-by: Mark Brown --- tools/testing/selftests/arm64/fp/.gitignore | 1 + tools/testing/selftests/arm64/fp/Makefile | 3 + tools/testing/selftests/arm64/fp/sme-inst.h | 20 ++ tools/testing/selftests/arm64/fp/zt-test.S | 324 ++++++++++++++++++++ 4 files changed, 348 insertions(+) create mode 100644 tools/testing/selftests/arm64/fp/zt-test.S diff --git a/tools/testing/selftests/arm64/fp/.gitignore b/tools/testing/selftests/arm64/fp/.gitignore index df79d29664a1..41bde4c97d47 100644 --- a/tools/testing/selftests/arm64/fp/.gitignore +++ b/tools/testing/selftests/arm64/fp/.gitignore @@ -12,3 +12,4 @@ vlset za-fork za-ptrace za-test +zt-test diff --git a/tools/testing/selftests/arm64/fp/Makefile b/tools/testing/selftests/arm64/fp/Makefile index 36db61358ed5..aff3026d3dff 100644 --- a/tools/testing/selftests/arm64/fp/Makefile +++ b/tools/testing/selftests/arm64/fp/Makefile @@ -14,6 +14,7 @@ TEST_GEN_PROGS_EXTENDED := fp-pidbench fpsimd-test \ sve-test \ ssve-test \ za-test \ + zt-test \ vlset TEST_PROGS_EXTENDED := fpsimd-stress sve-stress ssve-stress za-stress @@ -41,5 +42,7 @@ $(OUTPUT)/za-fork: za-fork.c $(OUTPUT)/za-fork-asm.o $(OUTPUT)/za-ptrace: za-ptrace.c $(OUTPUT)/za-test: za-test.S $(OUTPUT)/asm-utils.o $(CC) -nostdlib $^ -o $@ +$(OUTPUT)/zt-test: zt-test.S $(OUTPUT)/asm-utils.o + $(CC) -nostdlib $^ -o $@ include ../../lib.mk diff --git a/tools/testing/selftests/arm64/fp/sme-inst.h b/tools/testing/selftests/arm64/fp/sme-inst.h index 7191e53ca1c0..9292bba5400b 100644 --- a/tools/testing/selftests/arm64/fp/sme-inst.h +++ b/tools/testing/selftests/arm64/fp/sme-inst.h @@ -48,4 +48,24 @@ | ((\offset) & 7) .endm +/* + * LDR (ZT0) + * + * LDR ZT0, nx + */ +.macro _ldr_zt nx + .inst 0xe11f8000 \ + | (((\nx) & 0x1f) << 5) +.endm + +/* + * STR (ZT0) + * + * STR ZT0, nx + */ +.macro _str_zt nx + .inst 0xe13f8000 \ + | (((\nx) & 0x1f) << 5) +.endm + #endif diff --git a/tools/testing/selftests/arm64/fp/zt-test.S b/tools/testing/selftests/arm64/fp/zt-test.S new file mode 100644 index 000000000000..6f04a8bf60f6 --- /dev/null +++ b/tools/testing/selftests/arm64/fp/zt-test.S @@ -0,0 +1,324 @@ +// SPDX-License-Identifier: GPL-2.0-only +// Copyright (C) 2021-2 ARM Limited. +// Original author: Mark Brown +// +// Scalable Matrix Extension ZT context switch test +// Repeatedly writes unique test patterns into ZT0 +// and reads them back to verify integrity. + +#include +#include "assembler.h" +#include "asm-offsets.h" +#include "sme-inst.h" + +.arch_extension sve + +#define ZT_SZ 512 +#define ZT_B (ZT_SZ / 8) + +// Declare some storage space to shadow ZT register contents and a +// scratch buffer. +.pushsection .text +.data +.align 4 +ztref: + .space ZT_B +scratch: + .space ZT_B +.popsection + +// Trivial memory copy: copy x2 bytes, starting at address x1, to address x0. +// Clobbers x0-x3 +function memcpy + cmp x2, #0 + b.eq 1f +0: ldrb w3, [x1], #1 + strb w3, [x0], #1 + subs x2, x2, #1 + b.ne 0b +1: ret +endfunction + +// Generate a test pattern for storage in ZT +// x0: pid +// x1: generation + +// These values are used to constuct a 32-bit pattern that is repeated in the +// scratch buffer as many times as will fit: +// bits 31:24 generation number (increments once per test_loop) +// bits 23: 8 pid +// bits 7: 0 32-bit lane index + +function pattern + mov w3, wzr + bfi w3, w0, #8, #16 // PID + bfi w3, w1, #24, #8 // Generation + + ldr x0, =scratch + mov w1, #ZT_B / 4 + +0: str w3, [x0], #4 + add w3, w3, #1 // Lane + subs w1, w1, #1 + b.ne 0b + + ret +endfunction + +// Set up test pattern in a ZT horizontal vector +// x0: pid +// x1: generation +function setup_zt + mov x4, x30 + + bl pattern // Get pattern in scratch buffer + ldr x0, =ztref + ldr x1, =scratch + mov x2, #ZT_B + bl memcpy + + _ldr_zt 0 // load zt0 from pointer x0 + + ret x4 +endfunction + +// Trivial memory compare: compare x2 bytes starting at address x0 with +// bytes starting at address x1. +// Returns only if all bytes match; otherwise, the program is aborted. +// Clobbers x0-x5. +function memcmp + cbz x2, 2f + + stp x0, x1, [sp, #-0x20]! + str x2, [sp, #0x10] + + mov x5, #0 +0: ldrb w3, [x0, x5] + ldrb w4, [x1, x5] + add x5, x5, #1 + cmp w3, w4 + b.ne 1f + subs x2, x2, #1 + b.ne 0b + +1: ldr x2, [sp, #0x10] + ldp x0, x1, [sp], #0x20 + b.ne barf + +2: ret +endfunction + +// Verify that a ZT vector matches its shadow in memory, else abort +// Clobbers x0-x7 and x12. +function check_zt + mov x3, x30 + + ldr x0, =scratch // Poison scratch + mov x1, #ZT_B + bl memfill_ae + + ldr x0, =scratch + _str_zt 0 + + ldr x0, =ztref + ldr x1, =scratch + mov x2, #ZT_B + mov x30, x3 + b memcmp +endfunction + +// Any SME register modified here can cause corruption in the main +// thread -- but *only* the locations modified here. +function irritator_handler + // Increment the irritation signal count (x23): + ldr x0, [x2, #ucontext_regs + 8 * 23] + add x0, x0, #1 + str x0, [x2, #ucontext_regs + 8 * 23] + + // Corrupt some random ZT data +#if 0 + adr x0, .text + (irritator_handler - .text) / 16 * 16 + movi v0.8b, #1 + movi v9.16b, #2 + movi v31.8b, #3 +#endif + + ret +endfunction + +function tickle_handler + // Increment the signal count (x23): + ldr x0, [x2, #ucontext_regs + 8 * 23] + add x0, x0, #1 + str x0, [x2, #ucontext_regs + 8 * 23] + + ret +endfunction + +function terminate_handler + mov w21, w0 + mov x20, x2 + + puts "Terminated by signal " + mov w0, w21 + bl putdec + puts ", no error, iterations=" + ldr x0, [x20, #ucontext_regs + 8 * 22] + bl putdec + puts ", signals=" + ldr x0, [x20, #ucontext_regs + 8 * 23] + bl putdecn + + mov x0, #0 + mov x8, #__NR_exit + svc #0 +endfunction + +// w0: signal number +// x1: sa_action +// w2: sa_flags +// Clobbers x0-x6,x8 +function setsignal + str x30, [sp, #-((sa_sz + 15) / 16 * 16 + 16)]! + + mov w4, w0 + mov x5, x1 + mov w6, w2 + + add x0, sp, #16 + mov x1, #sa_sz + bl memclr + + mov w0, w4 + add x1, sp, #16 + str w6, [x1, #sa_flags] + str x5, [x1, #sa_handler] + mov x2, #0 + mov x3, #sa_mask_sz + mov x8, #__NR_rt_sigaction + svc #0 + + cbz w0, 1f + + puts "sigaction failure\n" + b .Labort + +1: ldr x30, [sp], #((sa_sz + 15) / 16 * 16 + 16) + ret +endfunction + +// Main program entry point +.globl _start +function _start +_start: + mov x23, #0 // signal count + + mov w0, #SIGINT + adr x1, terminate_handler + mov w2, #SA_SIGINFO + bl setsignal + + mov w0, #SIGTERM + adr x1, terminate_handler + mov w2, #SA_SIGINFO + bl setsignal + + mov w0, #SIGUSR1 + adr x1, irritator_handler + mov w2, #SA_SIGINFO + orr w2, w2, #SA_NODEFER + bl setsignal + + mov w0, #SIGUSR2 + adr x1, tickle_handler + mov w2, #SA_SIGINFO + orr w2, w2, #SA_NODEFER + bl setsignal + + smstart_za + + // Obtain our PID, to ensure test pattern uniqueness between processes + mov x8, #__NR_getpid + svc #0 + mov x20, x0 + + puts "PID:\t" + mov x0, x20 + bl putdecn + + mov x22, #0 // generation number, increments per iteration +.Ltest_loop: + mov x0, x20 + mov x1, x22 + bl setup_zt + + mov x8, #__NR_sched_yield // Encourage preemption + svc #0 + + mov x0, x20 + mov x1, x22 + bl check_zt + + add x22, x22, #1 // Everything still working + b .Ltest_loop + +.Labort: + mov x0, #0 + mov x1, #SIGABRT + mov x8, #__NR_kill + svc #0 +endfunction + +function barf +// fpsimd.c acitivty log dump hack +// ldr w0, =0xdeadc0de +// mov w8, #__NR_exit +// svc #0 +// end hack + smstop + mov x10, x0 // expected data + mov x11, x1 // actual data + mov x12, x2 // data size + + puts "Mismatch: PID=" + mov x0, x20 + bl putdec + puts ", iteration=" + mov x0, x22 + bl putdec + puts "\tExpected [" + mov x0, x10 + mov x1, x12 + bl dumphex + puts "]\n\tGot [" + mov x0, x11 + mov x1, x12 + bl dumphex + puts "]\n" + + mov x8, #__NR_getpid + svc #0 +// fpsimd.c acitivty log dump hack +// ldr w0, =0xdeadc0de +// mov w8, #__NR_exit +// svc #0 +// ^ end of hack + mov x1, #SIGABRT + mov x8, #__NR_kill + svc #0 +// mov x8, #__NR_exit +// mov x1, #1 +// svc #0 +endfunction + +function svcr_barf + mov x10, x0 + + puts "Bad SVCR: " + mov x0, x10 + bl putdecn + + mov x8, #__NR_exit + mov x1, #1 + svc #0 +endfunction From patchwork Tue Nov 1 14:33:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 13026994 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6EE6CC4332F for ; Tue, 1 Nov 2022 14:39:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230354AbiKAOj4 (ORCPT ); Tue, 1 Nov 2022 10:39:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53068 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229496AbiKAOjz (ORCPT ); Tue, 1 Nov 2022 10:39:55 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6C91D12AFF for ; Tue, 1 Nov 2022 07:39:54 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 0981B615AF for ; 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Signed-off-by: Mark Brown --- tools/testing/selftests/arm64/fp/fp-stress.c | 29 ++++++++++++++++++-- 1 file changed, 27 insertions(+), 2 deletions(-) diff --git a/tools/testing/selftests/arm64/fp/fp-stress.c b/tools/testing/selftests/arm64/fp/fp-stress.c index 4e62a9199f97..7f4eef8717ad 100644 --- a/tools/testing/selftests/arm64/fp/fp-stress.c +++ b/tools/testing/selftests/arm64/fp/fp-stress.c @@ -350,6 +350,19 @@ static void start_za(struct child_data *child, int vl, int cpu) ksft_print_msg("Started %s\n", child->name); } +static void start_zt(struct child_data *child, int cpu) +{ + int ret; + + child_start(child, "./zt-test"); + + ret = asprintf(&child->name, "ZT-%d", cpu); + if (ret == -1) + ksft_exit_fail_msg("asprintf() failed\n"); + + ksft_print_msg("Started %s\n", child->name); +} + static void probe_vls(int vls[], int *vl_count, int set_vl) { unsigned int vq; @@ -404,6 +417,7 @@ int main(int argc, char **argv) int cpus, tests, i, j, c; int sve_vl_count, sme_vl_count, fpsimd_per_cpu; int sve_vls[MAX_VLS], sme_vls[MAX_VLS]; + bool have_sme2; struct epoll_event ev; struct sigaction sa; @@ -437,6 +451,13 @@ int main(int argc, char **argv) sme_vl_count = 0; } + if (getauxval(AT_HWCAP2) & HWCAP2_SME2) { + tests += cpus; + have_sme2 = true; + } else { + have_sme2 = false; + } + /* Force context switching if we only have FPSIMD */ if (!sve_vl_count && !sme_vl_count) fpsimd_per_cpu = 2; @@ -447,8 +468,9 @@ int main(int argc, char **argv) ksft_print_header(); ksft_set_plan(tests); - ksft_print_msg("%d CPUs, %d SVE VLs, %d SME VLs\n", - cpus, sve_vl_count, sme_vl_count); + ksft_print_msg("%d CPUs, %d SVE VLs, %d SME VLs, SME2 %s\n", + cpus, sve_vl_count, sme_vl_count, + have_sme2 ? "present" : "absent"); if (timeout > 0) ksft_print_msg("Will run for %ds\n", timeout); @@ -495,6 +517,9 @@ int main(int argc, char **argv) start_ssve(&children[num_children++], sme_vls[j], i); start_za(&children[num_children++], sme_vls[j], i); } + + if (have_sme2) + start_zt(&children[num_children++], i); } for (;;) { From patchwork Tue Nov 1 14:33:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 13026995 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6EA66C433FE for ; Tue, 1 Nov 2022 14:40:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230353AbiKAOkA (ORCPT ); Tue, 1 Nov 2022 10:40:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53096 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229496AbiKAOj7 (ORCPT ); Tue, 1 Nov 2022 10:39:59 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A0287120B8 for ; Tue, 1 Nov 2022 07:39:58 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 5B6E1B81DEC for ; Tue, 1 Nov 2022 14:39:57 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id DECB0C43144; Tue, 1 Nov 2022 14:39:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1667313596; bh=00PR8/nuJtujDDYwl13sEDj5zwVgbMN4OsknhAsrsH4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=FrShyTCS6BFlqhIudoVmx2ETzHReW2G6m4ATLyNs0y5l97nYxCACN3ej0o38yTylI HWRvegPL+NzUl1ZSuFuxsvJ+ulR6vI28242COepT6dBmefY9QhG+P4kL8+u4utRzy7 qRvLW5/gy4EKnTaxjLiENaOkPrdO+d5Dl2UDFF93GnRe6AIM1IxpjnW5yQWLBem/0y B4CoKdiGU84s76pauX6YrulisEwpKm9LtQr48bhlvRF8lLxSbVzNBs8S/iA9Xvu9s9 /WHzvy25IuBRYu/6iWnQzmIRGTRTadl/UKbPZEDpboj3u9ZBZhffMDKo2EuuzOsNK0 DXuhZM3k9eNQA== From: Mark Brown To: Catalin Marinas , Will Deacon , Shuah Khan , Shuah Khan Cc: Alan Hayward , Luis Machado , Szabolcs Nagy , linux-arm-kernel@lists.infradead.org, linux-kselftest@vger.kernel.org, Mark Brown Subject: [PATCH v2 16/21] kselftest/arm64: Enumerate SME2 in the signal test utility code Date: Tue, 1 Nov 2022 14:33:31 +0000 Message-Id: <20221101143336.254445-17-broonie@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20221101143336.254445-1-broonie@kernel.org> References: <20221101143336.254445-1-broonie@kernel.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1820; i=broonie@kernel.org; h=from:subject; bh=00PR8/nuJtujDDYwl13sEDj5zwVgbMN4OsknhAsrsH4=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBjYS46EwSHdJtxJHAjAf8Zfz1sC/cs1BTSXZAb2G1l y/UKikGJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCY2EuOgAKCRAk1otyXVSH0OlwB/ 9+hVBopJLDhiX4bXrMAHS1mYjUG+ZOoqvrO4y4SFxGpdKDgr4BZrK9z9q3mvqFgEBj6v00ku3Ir70L Edq7iXTJztUNqzx3496NNF6qAYoaCgr7vCKKdUCS6YHu6kWOM2y+GyO/kpej2Hbjs3UgrGwd2vgv59 mmlgLkcH0aZyclVSPatkUijv/x0Qzd9jk7R9aytlE4uOnN70P+ro750jQ2hOFJ+VfN4XB4n7Dj2Jyg fSdG5FrJ5rEm94SRS1lFfCKPRek3XJ1V5qND8gl2WpKZz97XPdRN8lq6nHeB0N4JajNXzhU5hgKzsC 73iJMbdqGFlTqFmKuuXuw3QUulsley X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB Precedence: bulk List-ID: X-Mailing-List: linux-kselftest@vger.kernel.org Support test cases for SME2 by adding it to the set of features that we enumerate so test cases can check for it. Signed-off-by: Mark Brown --- tools/testing/selftests/arm64/signal/test_signals.h | 2 ++ tools/testing/selftests/arm64/signal/test_signals_utils.c | 3 +++ 2 files changed, 5 insertions(+) diff --git a/tools/testing/selftests/arm64/signal/test_signals.h b/tools/testing/selftests/arm64/signal/test_signals.h index 0c645834ddc3..1e6273d81575 100644 --- a/tools/testing/selftests/arm64/signal/test_signals.h +++ b/tools/testing/selftests/arm64/signal/test_signals.h @@ -34,6 +34,7 @@ enum { FSVE_BIT, FSME_BIT, FSME_FA64_BIT, + FSME2_BIT, FMAX_END }; @@ -41,6 +42,7 @@ enum { #define FEAT_SVE (1UL << FSVE_BIT) #define FEAT_SME (1UL << FSME_BIT) #define FEAT_SME_FA64 (1UL << FSME_FA64_BIT) +#define FEAT_SME2 (1UL << FSME2_BIT) /* * A descriptor used to describe and configure a test case. diff --git a/tools/testing/selftests/arm64/signal/test_signals_utils.c b/tools/testing/selftests/arm64/signal/test_signals_utils.c index 308e229e58ab..07f518f0e58d 100644 --- a/tools/testing/selftests/arm64/signal/test_signals_utils.c +++ b/tools/testing/selftests/arm64/signal/test_signals_utils.c @@ -29,6 +29,7 @@ static char const *const feats_names[FMAX_END] = { " SVE ", " SME ", " FA64 ", + " SME2 ", }; #define MAX_FEATS_SZ 128 @@ -323,6 +324,8 @@ int test_init(struct tdescr *td) td->feats_supported |= FEAT_SME; if (getauxval(AT_HWCAP2) & HWCAP2_SME_FA64) td->feats_supported |= FEAT_SME_FA64; + if (getauxval(AT_HWCAP2) & HWCAP2_SME2) + td->feats_supported |= FEAT_SME2; if (feats_ok(td)) { if (td->feats_required & td->feats_supported) fprintf(stderr, From patchwork Tue Nov 1 14:33:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 13026996 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5D07AC4332F for ; Tue, 1 Nov 2022 14:40:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229496AbiKAOkB (ORCPT ); Tue, 1 Nov 2022 10:40:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53102 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230355AbiKAOkA (ORCPT ); Tue, 1 Nov 2022 10:40:00 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 97F5D12AFF for ; Tue, 1 Nov 2022 07:39:59 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 354D5615EF for ; Tue, 1 Nov 2022 14:39:59 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7BF4CC433D6; Tue, 1 Nov 2022 14:39:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1667313598; bh=aPsajbZlJ1Devthnun/HjJFRIhZ8YHh4Fs+22T7Mvjg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Skeks33py27UHT6zdPPUzCyjRtXiplx97z/X1FmXwzhm86JkRE1ECuQ9nC5bTHA5K 2/NlbZPck1BSTi14drdCMrX7EDl08GuCXticDObYYEiBevI4MO2eRzOrPJyj7i0oDC xY2NNaVZrtFDZdd9NUGCB6LFgQpT5ue9cm/bSPEcgB4iQfBLV+WBoJ/6F1W1wGf+HO OrBWGnnuBwAwNlzLWVVRlmEBsaJ2m08domNFsihjA4kAeukCy0MVIv5TFFDAXM6PpZ w2sE9ewHWPSVjR03MErvq6dS2AvgGKx7QhhVvkhessUrv0YIh+SdlMQxahdVcKos75 wiOM0Yl6SU6Kw== From: Mark Brown To: Catalin Marinas , Will Deacon , Shuah Khan , Shuah Khan Cc: Alan Hayward , Luis Machado , Szabolcs Nagy , linux-arm-kernel@lists.infradead.org, linux-kselftest@vger.kernel.org, Mark Brown Subject: [PATCH v2 17/21] kselftest/arm64: Teach the generic signal context validation about ZT Date: Tue, 1 Nov 2022 14:33:32 +0000 Message-Id: <20221101143336.254445-18-broonie@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20221101143336.254445-1-broonie@kernel.org> References: <20221101143336.254445-1-broonie@kernel.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=3158; i=broonie@kernel.org; h=from:subject; bh=aPsajbZlJ1Devthnun/HjJFRIhZ8YHh4Fs+22T7Mvjg=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBjYS47XpzWh18ZBwJu4MPVDW/1fV1ztVbBSwc1IDgW xTnzFKiJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCY2EuOwAKCRAk1otyXVSH0HpEB/ 4o/6Y4Pbp9sAYsSPdvvsQFwq+Z+KKME3zYQ1klnFUx0KZB2+FEQtmVOwp0zMQjM0xkVBmHlo1rg2Jg 1ZoHKcjltEHB7hzYzSzgcMBanjdFtvhdLanZ5vsjkhCTqU3rJgwLxp6CwgcI3HowxMTTC6QzzN+3pw rUw4dkHGnTyFqYFjPIHTE3h3W3KMUyKBBeyAMxVbbY/1CIXXZrBnftB+HpSvjrpjQ1hp/G4o6eY4Ee 3r4dWDBQttHrjg+JuEDFzlaFwbaSVf4t2iidVIGWbrcAZQhR8p5keXhCSeZynRIx4YimHuSKoNSg7u 8JJkiN38xVAHbZ5CEIO9DCmIjoDuoK X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB Precedence: bulk List-ID: X-Mailing-List: linux-kselftest@vger.kernel.org Add ZT to the set of signal contexts that the shared code understands and validates the form of. Signed-off-by: Mark Brown --- .../arm64/signal/testcases/testcases.c | 36 +++++++++++++++++++ .../arm64/signal/testcases/testcases.h | 1 + 2 files changed, 37 insertions(+) diff --git a/tools/testing/selftests/arm64/signal/testcases/testcases.c b/tools/testing/selftests/arm64/signal/testcases/testcases.c index e1c625b20ac4..9bee976aff55 100644 --- a/tools/testing/selftests/arm64/signal/testcases/testcases.c +++ b/tools/testing/selftests/arm64/signal/testcases/testcases.c @@ -104,6 +104,26 @@ bool validate_za_context(struct za_context *za, char **err) return true; } +bool validate_zt_context(struct zt_context *zt, char **err) +{ + if (!zt || !err) + return false; + + /* If the context is present there should be at least one register */ + if (zt->nregs == 0) { + *err = "no registers"; + return false; + } + + /* Size should agree with the number of registers */ + if (zt->head.size != ZT_SIG_CONTEXT_SIZE(zt->nregs)) { + *err = "register count does not match size"; + return false; + } + + return true; +} + bool validate_reserved(ucontext_t *uc, size_t resv_sz, char **err) { bool terminated = false; @@ -113,6 +133,7 @@ bool validate_reserved(ucontext_t *uc, size_t resv_sz, char **err) struct extra_context *extra = NULL; struct sve_context *sve = NULL; struct za_context *za = NULL; + struct zt_context *zt = NULL; struct _aarch64_ctx *head = (struct _aarch64_ctx *)uc->uc_mcontext.__reserved; void *extra_data = NULL; @@ -172,6 +193,13 @@ bool validate_reserved(ucontext_t *uc, size_t resv_sz, char **err) za = (struct za_context *)head; new_flags |= ZA_CTX; break; + case ZT_MAGIC: + if (flags & ZT_CTX) + *err = "Multiple ZT_MAGIC"; + /* Size is validated in validate_za_context() */ + zt = (struct zt_context *)head; + new_flags |= ZT_CTX; + break; case EXTRA_MAGIC: if (flags & EXTRA_CTX) *err = "Multiple EXTRA_MAGIC"; @@ -221,6 +249,9 @@ bool validate_reserved(ucontext_t *uc, size_t resv_sz, char **err) if (new_flags & ZA_CTX) if (!validate_za_context(za, err)) return false; + if (new_flags & ZT_CTX) + if (!validate_zt_context(zt, err)) + return false; flags |= new_flags; @@ -232,6 +263,11 @@ bool validate_reserved(ucontext_t *uc, size_t resv_sz, char **err) return false; } + if (terminated && (flags & ZT_CTX) && !(flags & ZA_CTX)) { + *err = "ZT context but no ZA context"; + return false; + } + return true; } diff --git a/tools/testing/selftests/arm64/signal/testcases/testcases.h b/tools/testing/selftests/arm64/signal/testcases/testcases.h index 040afded0b76..a08ab0d6207a 100644 --- a/tools/testing/selftests/arm64/signal/testcases/testcases.h +++ b/tools/testing/selftests/arm64/signal/testcases/testcases.h @@ -18,6 +18,7 @@ #define SVE_CTX (1 << 1) #define ZA_CTX (1 << 2) #define EXTRA_CTX (1 << 3) +#define ZT_CTX (1 << 4) #define KSFT_BAD_MAGIC 0xdeadbeef From patchwork Tue Nov 1 14:33:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 13026997 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 16EF8C4332F for ; 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d=kernel.org; s=k20201202; t=1667313601; bh=btqd+wxNRzbHiPozkH6Ho7qEjlMM8y1Ld49FHNxQVHA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Ma/LREcjN+QjKpjW+WdkMph0YqUkcGyxiTYwCRnnydyMgKwxaIA1+1SHiL7JpkuLZ u3HgXefflixeAITHUEqc1F2d5SNUqvt9jmEs9OIn+EQRtY/cN55cH/MQsfvbn33Qzx jbCPqXX24gKPIOobdA9ugLr+MtSo0K8l0Ui4ast6VU1bS4AP0K36QsWMU6HzV2rOJV OXr42DwcFGRWz+U77aomK2AzRddamWIF6jPCv4hP3xOswnhBGlb7D98yCInZB5SFfe 6AaJqSYxnryqN3tJVnFdMqIH1SosX32cL/lJVB1KFqJXGw3r6kY8AMq1KtocBw+zDn dlA+U0Daki0Gw== From: Mark Brown To: Catalin Marinas , Will Deacon , Shuah Khan , Shuah Khan Cc: Alan Hayward , Luis Machado , Szabolcs Nagy , linux-arm-kernel@lists.infradead.org, linux-kselftest@vger.kernel.org, Mark Brown Subject: [PATCH v2 18/21] kselftest/arm64: Add test coverage for ZT register signal frames Date: Tue, 1 Nov 2022 14:33:33 +0000 Message-Id: <20221101143336.254445-19-broonie@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20221101143336.254445-1-broonie@kernel.org> References: <20221101143336.254445-1-broonie@kernel.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=4843; i=broonie@kernel.org; h=from:subject; bh=btqd+wxNRzbHiPozkH6Ho7qEjlMM8y1Ld49FHNxQVHA=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBjYS4827wLUy8MmPY6StlaAnYEPtnbph52q+skWwFI XAVzRgeJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCY2EuPAAKCRAk1otyXVSH0JIJB/ oCrWd7+8lenSLrmEPaoT/GdLM97XyJJq8VrJcdwQzPX1EIWGZh+3g8DectglpXL3rg+D0OclhkiHsj 7ii6pUapRsUOXu/VsRMHXLbsG7/oF7QQd1W0dQCS52PUPud9z+u/INXHLHUHwsiRBExYbI2P3DPF6L Ef6kc6sy+doeINvxa92qDSKx1MzAkBEdUEdujXm70CanLC7uSzlVCXDvaZseQ+uAqqL+V7luupeIhI ZXka6wgVAGayDuaLPTyXqkuQzuC02A9CWTdnXSkkFsutoJO4NdjJhCREhpfSL/f5sFsI1WbuADdILZ ix74erHYkzBOA5TCjAdaozRianVP5j X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB Precedence: bulk List-ID: X-Mailing-List: linux-kselftest@vger.kernel.org We should have a ZT register frame with an expected size when ZA is enabled and have no ZT frame when ZA is disabled. Since we don't load any data into ZT we expect the data to all be zeros since the architecture guarantees it will be set to 0 as ZA is enabled. Signed-off-by: Mark Brown --- .../testing/selftests/arm64/signal/.gitignore | 1 + .../arm64/signal/testcases/zt_no_regs.c | 51 +++++++++++ .../arm64/signal/testcases/zt_regs.c | 85 +++++++++++++++++++ 3 files changed, 137 insertions(+) create mode 100644 tools/testing/selftests/arm64/signal/testcases/zt_no_regs.c create mode 100644 tools/testing/selftests/arm64/signal/testcases/zt_regs.c diff --git a/tools/testing/selftests/arm64/signal/.gitignore b/tools/testing/selftests/arm64/signal/.gitignore index e8d2b57f73ec..b7fbb65183e8 100644 --- a/tools/testing/selftests/arm64/signal/.gitignore +++ b/tools/testing/selftests/arm64/signal/.gitignore @@ -5,4 +5,5 @@ sme_* ssve_* sve_* za_* +zt_* !*.[ch] diff --git a/tools/testing/selftests/arm64/signal/testcases/zt_no_regs.c b/tools/testing/selftests/arm64/signal/testcases/zt_no_regs.c new file mode 100644 index 000000000000..34f69bcf821e --- /dev/null +++ b/tools/testing/selftests/arm64/signal/testcases/zt_no_regs.c @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021 ARM Limited + * + * Verify that using an instruction not supported in streaming mode + * traps when in streaming mode. + */ + +#include +#include +#include + +#include "test_signals_utils.h" +#include "testcases.h" + +static union { + ucontext_t uc; + char buf[1024 * 128]; +} context; + +int zt_no_regs_run(struct tdescr *td, siginfo_t *si, ucontext_t *uc) +{ + size_t offset; + struct _aarch64_ctx *head = GET_BUF_RESV_HEAD(context); + + /* + * Get a signal context which should not have a ZT frame and + * registers in it. + */ + if (!get_current_context(td, &context.uc, sizeof(context))) + return 1; + + head = get_header(head, ZT_MAGIC, GET_BUF_RESV_SIZE(context), &offset); + if (head) { + fprintf(stderr, "Got unexpected ZT context\n"); + return 1; + } + + td->pass = 1; + + return 0; +} + +struct tdescr tde = { + .name = "ZT register data not present", + .descr = "Validate that ZT is not present when ZA is disabled", + .feats_required = FEAT_SME2, + .timeout = 3, + .sanity_disabled = true, + .run = zt_no_regs_run, +}; diff --git a/tools/testing/selftests/arm64/signal/testcases/zt_regs.c b/tools/testing/selftests/arm64/signal/testcases/zt_regs.c new file mode 100644 index 000000000000..e1eb4d5c027a --- /dev/null +++ b/tools/testing/selftests/arm64/signal/testcases/zt_regs.c @@ -0,0 +1,85 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021 ARM Limited + * + * Verify that using an instruction not supported in streaming mode + * traps when in streaming mode. + */ + +#include +#include +#include + +#include "test_signals_utils.h" +#include "testcases.h" + +static union { + ucontext_t uc; + char buf[1024 * 128]; +} context; + +static void enable_za(void) +{ + /* smstart za; real data is TODO */ + asm volatile(".inst 0xd503457f" : : : ); +} + +int zt_regs_run(struct tdescr *td, siginfo_t *si, ucontext_t *uc) +{ + size_t offset; + struct _aarch64_ctx *head = GET_BUF_RESV_HEAD(context); + struct zt_context *zt; + char *zeros; + + /* + * Get a signal context which should have a ZT frame and registers + * in it. + */ + enable_za(); + if (!get_current_context(td, &context.uc, sizeof(context))) + return 1; + + head = get_header(head, ZT_MAGIC, GET_BUF_RESV_SIZE(context), &offset); + if (!head) { + fprintf(stderr, "No ZT context\n"); + return 1; + } + + zt = (struct zt_context *)head; + if (zt->nregs == 0) { + fprintf(stderr, "Got context with no registers\n"); + return 1; + } + + fprintf(stderr, "Got expected size %u for %d registers\n", + head->size, zt->nregs); + + /* We didn't load any data into ZT so it should be all zeros */ + zeros = malloc(ZT_SIG_REGS_SIZE(zt->nregs)); + if (!zeros) { + fprintf(stderr, "Out of memory, nregs=%u\n", zt->nregs); + return 1; + } + memset(zeros, 0, ZT_SIG_REGS_SIZE(zt->nregs)); + + if (memcmp(zeros, (char *)zt + ZT_SIG_REGS_OFFSET, + ZT_SIG_REGS_SIZE(zt->nregs)) != 0) { + fprintf(stderr, "ZT data invalid\n"); + return 1; + } + + free(zeros); + + td->pass = 1; + + return 0; +} + +struct tdescr tde = { + .name = "ZT register data", + .descr = "Validate that ZT is present and has data when ZA is enabled", + .feats_required = FEAT_SME2, + .timeout = 3, + .sanity_disabled = true, + .run = zt_regs_run, +}; From patchwork Tue Nov 1 14:33:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 13026998 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 32566C433FE for ; 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s=k20201202; t=1667313603; bh=27+llr53xtHHEMl2wSYoYx5Yhlq4fzr34gu5YztKp94=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=bfXSQICgwP/iQx4+nULxWweA3DoMFBvZBoBuAz8GgNozb830ziXRLSX5gvAnF6uwc 7xoQR4t7qkigDXPkncfFrVVm2QFpCMRvzmS6YCAIkMx88ALyK2JLq2lzfUzSxKZzt+ p/h8tQHCFexrXFXIgI63496bb51OW0RqXsIfmEoz3Q55zAeO7v+KVL89Lv9J5e7k7G RSgonU5OEwLhX+EltQjC0lyCa07MgO1mmE8t18WX3V6A0h4ZEg2IbqJMvlcsMHj1qX wlGV6/BBSCPFf5S+8AOqG+TjWQkqEFfbObUThsh8KHAWnXkYUF8Gs8FBSXxf7yJbqA ZyYPyaW41lw4Q== From: Mark Brown To: Catalin Marinas , Will Deacon , Shuah Khan , Shuah Khan Cc: Alan Hayward , Luis Machado , Szabolcs Nagy , linux-arm-kernel@lists.infradead.org, linux-kselftest@vger.kernel.org, Mark Brown Subject: [PATCH v2 19/21] kselftest/arm64: Add SME2 coverage to syscall-abi Date: Tue, 1 Nov 2022 14:33:34 +0000 Message-Id: <20221101143336.254445-20-broonie@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20221101143336.254445-1-broonie@kernel.org> References: <20221101143336.254445-1-broonie@kernel.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=4477; i=broonie@kernel.org; h=from:subject; bh=27+llr53xtHHEMl2wSYoYx5Yhlq4fzr34gu5YztKp94=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBjYS49gjBAz1913gNi8lUAWVdLkYEQKxRyR8+kD0xS TnxXF6mJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCY2EuPQAKCRAk1otyXVSH0OrKB/ 4jJrk4IQtr486Je9wxRGUG51Y7zYbfwal472RN+uKG9p7BA4O8v7dvn5FU9vRwm9pSh/eY271U1LJm uKVg0neTsIgbsS3LUqpjqWbCRAfSgPzJd+k+xmM30BY8L7Zwv744tUeXfNLnj2W1Vk+jkuY+rL0Ww3 vwz3TSSqJkKMIC48vuuQKvafaXCzTAm3uNU1iE02o4sG1eyRXLqUeC0oHO5XTrfG13ZlJTtQMK7ion udePfccr8dvRbR3OsZcqN+bxEeR35G4v/bq7GSe4QlntKnvmWDSwU8xS77f7PoksZeshkucV5QAF4v CJ678UpUcfCVGfiPzLVixOZ746qeZs X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB Precedence: bulk List-ID: X-Mailing-List: linux-kselftest@vger.kernel.org Verify that ZT0 is preserved over syscalls when it is present and PSTATE.ZA is set. Signed-off-by: Mark Brown --- .../selftests/arm64/abi/syscall-abi-asm.S | 43 ++++++++++++++++++- .../testing/selftests/arm64/abi/syscall-abi.c | 40 ++++++++++++++++- 2 files changed, 80 insertions(+), 3 deletions(-) diff --git a/tools/testing/selftests/arm64/abi/syscall-abi-asm.S b/tools/testing/selftests/arm64/abi/syscall-abi-asm.S index b523c21c2278..cca8f27900e9 100644 --- a/tools/testing/selftests/arm64/abi/syscall-abi-asm.S +++ b/tools/testing/selftests/arm64/abi/syscall-abi-asm.S @@ -23,6 +23,9 @@ .arch_extension sve +#define ID_AA64SMFR0_EL1_SMEver_SHIFT 56 +#define ID_AA64SMFR0_EL1_SMEver_WIDTH 4 + /* * LDR (vector to ZA array): * LDR ZA[\nw, #\offset], [X\nxbase, #\offset, MUL VL] @@ -45,6 +48,26 @@ | ((\offset) & 7) .endm +/* + * LDR (ZT0) + * + * LDR ZT0, nx + */ +.macro _ldr_zt nx + .inst 0xe11f8000 \ + | (((\nx) & 0x1f) << 5) +.endm + +/* + * STR (ZT0) + * + * STR ZT0, nx + */ +.macro _str_zt nx + .inst 0xe13f8000 \ + | (((\nx) & 0x1f) << 5) +.endm + .globl do_syscall do_syscall: // Store callee saved registers x19-x29 (80 bytes) plus x0 and x1 @@ -64,7 +87,7 @@ do_syscall: msr S3_3_C4_C2_2, x2 1: - // Load ZA if it's enabled - uses x12 as scratch due to SME LDR + // Load ZA and ZT0 if enabled - uses x12 as scratch due to SME LDR tbz x2, #SVCR_ZA_SHIFT, 1f mov w12, #0 ldr x2, =za_in @@ -73,6 +96,15 @@ do_syscall: add x12, x12, #1 cmp x1, x12 bne 2b + + // ZT0 + mrs x2, S3_0_C0_C4_5 // ID_AA64SMFR0_EL1 + ubfx x2, x2, #ID_AA64SMFR0_EL1_SMEver_SHIFT, \ + #ID_AA64SMFR0_EL1_SMEver_WIDTH + cbz x2, 1f + adrp x2, zt_in + add x2, x2, :lo12:zt_in + _ldr_zt 2 1: // Load GPRs x8-x28, and save our SP/FP for later comparison @@ -235,6 +267,15 @@ do_syscall: add x12, x12, #1 cmp x1, x12 bne 2b + + // ZT0 + mrs x2, S3_0_C0_C4_5 // ID_AA64SMFR0_EL1 + ubfx x2, x2, #ID_AA64SMFR0_EL1_SMEver_SHIFT, \ + #ID_AA64SMFR0_EL1_SMEver_WIDTH + cbz x2, 1f + adrp x2, zt_out + add x2, x2, :lo12:zt_out + _str_zt 2 1: // Save the SVE state if we have some diff --git a/tools/testing/selftests/arm64/abi/syscall-abi.c b/tools/testing/selftests/arm64/abi/syscall-abi.c index dd7ebe536d05..9800f9dc6b35 100644 --- a/tools/testing/selftests/arm64/abi/syscall-abi.c +++ b/tools/testing/selftests/arm64/abi/syscall-abi.c @@ -311,6 +311,35 @@ static int check_za(struct syscall_cfg *cfg, int sve_vl, int sme_vl, return errors; } +uint8_t zt_in[ZT_SIG_REG_BYTES] __attribute__((aligned(16))); +uint8_t zt_out[ZT_SIG_REG_BYTES] __attribute__((aligned(16))); + +static void setup_zt(struct syscall_cfg *cfg, int sve_vl, int sme_vl, + uint64_t svcr) +{ + fill_random(zt_in, sizeof(zt_in)); + memset(zt_out, 0, sizeof(zt_out)); +} + +static int check_zt(struct syscall_cfg *cfg, int sve_vl, int sme_vl, + uint64_t svcr) +{ + int errors = 0; + + if (!(getauxval(AT_HWCAP2) & HWCAP2_SME2)) + return 0; + + if (!(svcr & SVCR_ZA_MASK)) + return 0; + + if (memcmp(zt_in, zt_out, sizeof(zt_in)) != 0) { + ksft_print_msg("SME VL %d ZT does not match\n", sme_vl); + errors++; + } + + return errors; +} + typedef void (*setup_fn)(struct syscall_cfg *cfg, int sve_vl, int sme_vl, uint64_t svcr); typedef int (*check_fn)(struct syscall_cfg *cfg, int sve_vl, int sme_vl, @@ -334,6 +363,7 @@ static struct { { setup_ffr, check_ffr }, { setup_svcr, check_svcr }, { setup_za, check_za }, + { setup_zt, check_zt }, }; static bool do_test(struct syscall_cfg *cfg, int sve_vl, int sme_vl, @@ -474,6 +504,7 @@ int main(void) { int i; int tests = 1; /* FPSIMD */ + int sme_ver; srandom(getpid()); @@ -482,10 +513,15 @@ int main(void) tests += (sve_count_vls() * sme_count_vls()) * 3; ksft_set_plan(ARRAY_SIZE(syscalls) * tests); + if (getauxval(AT_HWCAP2) & HWCAP2_SME2) + sme_ver = 2; + else + sme_ver = 1; + if (getauxval(AT_HWCAP2) & HWCAP2_SME_FA64) - ksft_print_msg("SME with FA64\n"); + ksft_print_msg("SME%d with FA64\n", sme_ver); else if (getauxval(AT_HWCAP2) & HWCAP2_SME) - ksft_print_msg("SME without FA64\n"); + ksft_print_msg("SME%d without FA64\n", sme_ver); for (i = 0; i < ARRAY_SIZE(syscalls); i++) test_one_syscall(&syscalls[i]); From patchwork Tue Nov 1 14:33:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 13026999 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DB82FC4332F for ; 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s=k20201202; t=1667313606; bh=SmYshUMF+sA28bATA4EuOq9NVRA77C4hIqiO3DjravA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=dRh1LjVd2LFqyHxzXYOaemoLEv/UMQqGObARZPEEfzYvYisrRqoBTPS1cUV1saKt1 HU45iY4Ji+/n0W385domNfODH/4qVhBocJnP2SF74qFTEF1ukxjso6zrTKm0Br9NOa 1qXunJ8XE05/eoM6lQ75eju/F8lmbIGrkoxJ3q/tmyy8h4PtDIwSy2QH1nId6VeKhd hsvBgWrl9/ov9vextvmLiT9mRC/vizs6A3ynlxraZjuSJL6E2hw4iAoyCu3b/v6dG/ YpBT7Mx1yIamPVuiE/11/61Gewi6Hpy/xb7Tskz756gJkoSZHI7ckCgq/4J21hV+29 jl9v4iVJtmDdA== From: Mark Brown To: Catalin Marinas , Will Deacon , Shuah Khan , Shuah Khan Cc: Alan Hayward , Luis Machado , Szabolcs Nagy , linux-arm-kernel@lists.infradead.org, linux-kselftest@vger.kernel.org, Mark Brown Subject: [PATCH v2 20/21] kselftest/arm64: Add coverage of the ZT ptrace regset Date: Tue, 1 Nov 2022 14:33:35 +0000 Message-Id: <20221101143336.254445-21-broonie@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20221101143336.254445-1-broonie@kernel.org> References: <20221101143336.254445-1-broonie@kernel.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=9486; i=broonie@kernel.org; h=from:subject; bh=SmYshUMF+sA28bATA4EuOq9NVRA77C4hIqiO3DjravA=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBjYS4+sCanSCMakUgk22kBdfF2d1gzz01kvtnvlFOG BX4iIFOJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCY2EuPgAKCRAk1otyXVSH0PhkB/ 9ePNfcpXxKRSz+rGFDNTEcika0lW3jC8TtTNEGrVE743WUbmiHxzf7jDQpaK1sbgmYHYKYUDxqM/6t VDpxuK5Z+JQ8sH8g1s3aitlUA9UroPW/HNuomkboEJTJo6BdlDzebc+cN4kJ8nzTVuPVIhXj/6ptxw MsSb6kbQrn9ZvcZFSKsk5gH/oJrnGc1qWr/flDF/Ge1Q2VgIQMk3mWHrl+T2yxWfubFIqKvUwUJUCI jukr7y32PytL4gHRsIZKCCTAsJbCoOmDb4AfiSamUSB4lhfxfGRaYDXRPxNlYGk9rXTY4vhlQaFSok eNZxwnc+pA60m7ndMtHGhyZ6cH02K7 X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB Precedence: bulk List-ID: X-Mailing-List: linux-kselftest@vger.kernel.org Add coverage of the ZT ptrace interface. Signed-off-by: Mark Brown --- tools/testing/selftests/arm64/fp/.gitignore | 1 + tools/testing/selftests/arm64/fp/Makefile | 2 + tools/testing/selftests/arm64/fp/zt-ptrace.c | 365 +++++++++++++++++++ 3 files changed, 368 insertions(+) create mode 100644 tools/testing/selftests/arm64/fp/zt-ptrace.c diff --git a/tools/testing/selftests/arm64/fp/.gitignore b/tools/testing/selftests/arm64/fp/.gitignore index 41bde4c97d47..ebc86757bdd8 100644 --- a/tools/testing/selftests/arm64/fp/.gitignore +++ b/tools/testing/selftests/arm64/fp/.gitignore @@ -12,4 +12,5 @@ vlset za-fork za-ptrace za-test +zt-ptrace zt-test diff --git a/tools/testing/selftests/arm64/fp/Makefile b/tools/testing/selftests/arm64/fp/Makefile index aff3026d3dff..50a70220ba6c 100644 --- a/tools/testing/selftests/arm64/fp/Makefile +++ b/tools/testing/selftests/arm64/fp/Makefile @@ -14,6 +14,7 @@ TEST_GEN_PROGS_EXTENDED := fp-pidbench fpsimd-test \ sve-test \ ssve-test \ za-test \ + zt-ptrace \ zt-test \ vlset TEST_PROGS_EXTENDED := fpsimd-stress sve-stress ssve-stress za-stress @@ -42,6 +43,7 @@ $(OUTPUT)/za-fork: za-fork.c $(OUTPUT)/za-fork-asm.o $(OUTPUT)/za-ptrace: za-ptrace.c $(OUTPUT)/za-test: za-test.S $(OUTPUT)/asm-utils.o $(CC) -nostdlib $^ -o $@ +$(OUTPUT)/zt-ptrace: zt-ptrace.c $(OUTPUT)/zt-test: zt-test.S $(OUTPUT)/asm-utils.o $(CC) -nostdlib $^ -o $@ diff --git a/tools/testing/selftests/arm64/fp/zt-ptrace.c b/tools/testing/selftests/arm64/fp/zt-ptrace.c new file mode 100644 index 000000000000..996d9614a131 --- /dev/null +++ b/tools/testing/selftests/arm64/fp/zt-ptrace.c @@ -0,0 +1,365 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2021 ARM Limited. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../../kselftest.h" + +/* and don't like each other, so: */ +#ifndef NT_ARM_ZA +#define NT_ARM_ZA 0x40c +#endif +#ifndef NT_ARM_ZT +#define NT_ARM_ZT 0x40d +#endif + +#define EXPECTED_TESTS 3 + +static int sme_vl; + +static void fill_buf(char *buf, size_t size) +{ + int i; + + for (i = 0; i < size; i++) + buf[i] = random(); +} + +static int do_child(void) +{ + if (ptrace(PTRACE_TRACEME, -1, NULL, NULL)) + ksft_exit_fail_msg("PTRACE_TRACEME", strerror(errno)); + + if (raise(SIGSTOP)) + ksft_exit_fail_msg("raise(SIGSTOP)", strerror(errno)); + + return EXIT_SUCCESS; +} + +static struct user_za_header *get_za(pid_t pid, void **buf, size_t *size) +{ + struct user_za_header *za; + void *p; + size_t sz = sizeof(*za); + struct iovec iov; + + while (1) { + if (*size < sz) { + p = realloc(*buf, sz); + if (!p) { + errno = ENOMEM; + goto error; + } + + *buf = p; + *size = sz; + } + + iov.iov_base = *buf; + iov.iov_len = sz; + if (ptrace(PTRACE_GETREGSET, pid, NT_ARM_ZA, &iov)) + goto error; + + za = *buf; + if (za->size <= sz) + break; + + sz = za->size; + } + + return za; + +error: + return NULL; +} + +static int set_za(pid_t pid, const struct user_za_header *za) +{ + struct iovec iov; + + iov.iov_base = (void *)za; + iov.iov_len = za->size; + return ptrace(PTRACE_SETREGSET, pid, NT_ARM_ZA, &iov); +} + +static int get_zt(pid_t pid, char zt[ZT_SIG_REG_BYTES]) +{ + struct iovec iov; + + iov.iov_base = zt; + iov.iov_len = ZT_SIG_REG_BYTES; + return ptrace(PTRACE_GETREGSET, pid, NT_ARM_ZT, &iov); +} + + +static int set_zt(pid_t pid, const char zt[ZT_SIG_REG_BYTES]) +{ + struct iovec iov; + + iov.iov_base = (void *)zt; + iov.iov_len = ZT_SIG_REG_BYTES; + return ptrace(PTRACE_SETREGSET, pid, NT_ARM_ZT, &iov); +} + +/* Reading with ZA disabled returns all zeros */ +static void ptrace_za_disabled_read_zt(pid_t child) +{ + struct user_za_header za; + char zt[ZT_SIG_REG_BYTES]; + int ret, i; + bool fail = false; + + /* Disable PSTATE.ZA using the ZA interface */ + memset(&za, 0, sizeof(za)); + za.vl = sme_vl; + za.size = sizeof(za); + + ret = set_za(child, &za); + if (ret != 0) { + ksft_print_msg("Failed to disable ZA\n"); + fail = true; + } + + /* Read back ZT */ + ret = get_zt(child, zt); + if (ret != 0) { + ksft_print_msg("Failed to read ZT\n"); + fail = true; + } + + for (i = 0; i < ARRAY_SIZE(zt); i++) { + if (zt[i]) { + ksft_print_msg("zt[%d]: 0x%x != 0\n", i, zt[i]); + fail = true; + } + } + + ksft_test_result(!fail, "ptrace_za_disabled_read_zt\n"); +} + +/* Writing then reading ZT should return the data written */ +static void ptrace_set_get_zt(pid_t child) +{ + char zt_in[ZT_SIG_REG_BYTES]; + char zt_out[ZT_SIG_REG_BYTES]; + int ret, i; + bool fail = false; + + fill_buf(zt_in, sizeof(zt_in)); + + ret = set_zt(child, zt_in); + if (ret != 0) { + ksft_print_msg("Failed to set ZT\n"); + fail = true; + } + + ret = get_zt(child, zt_out); + if (ret != 0) { + ksft_print_msg("Failed to read ZT\n"); + fail = true; + } + + for (i = 0; i < ARRAY_SIZE(zt_in); i++) { + if (zt_in[i] != zt_out[i]) { + ksft_print_msg("zt[%d]: 0x%x != 0x%x\n", i, + zt_in[i], zt_out[i]); + fail = true; + } + } + + ksft_test_result(!fail, "ptrace_set_get_zt\n"); +} + +/* Writing ZT should set PSTATE.ZA */ +static void ptrace_enable_za_via_zt(pid_t child) +{ + struct user_za_header za_in; + struct user_za_header *za_out; + char zt[ZT_SIG_REG_BYTES]; + char *za_data; + size_t za_out_size; + int ret, i, vq; + bool fail = false; + + /* Disable PSTATE.ZA using the ZA interface */ + memset(&za_in, 0, sizeof(za_in)); + za_in.vl = sme_vl; + za_in.size = sizeof(za_in); + + ret = set_za(child, &za_in); + if (ret != 0) { + ksft_print_msg("Failed to disable ZA\n"); + fail = true; + } + + /* Write ZT */ + fill_buf(zt, sizeof(zt)); + ret = set_zt(child, zt); + if (ret != 0) { + ksft_print_msg("Failed to set ZT\n"); + fail = true; + } + + /* Read back ZA and check for register data */ + za_out = NULL; + za_out_size = 0; + if (get_za(child, (void **)&za_out, &za_out_size)) { + /* Should have an unchanged VL */ + if (za_out->vl != sme_vl) { + ksft_print_msg("VL changed from %d to %d\n", + sme_vl, za_out->vl); + fail = true; + } + vq = __sve_vq_from_vl(za_out->vl); + za_data = (char *)za_out + ZA_PT_ZA_OFFSET; + + /* Should have register data */ + if (za_out->size < ZA_PT_SIZE(vq)) { + ksft_print_msg("ZA data less than expected: %u < %u\n", + za_out->size, ZA_PT_SIZE(vq)); + fail = true; + vq = 0; + } + + /* That register data should be non-zero */ + for (i = 0; i < ZA_PT_ZA_SIZE(vq); i++) { + if (za_data[i]) { + ksft_print_msg("ZA byte %d is %x\n", + i, za_data[i]); + fail = true; + } + } + } else { + ksft_print_msg("Failed to read ZA\n"); + fail = true; + } + + ksft_test_result(!fail, "ptrace_enable_za_via_zt\n"); +} + +static int do_parent(pid_t child) +{ + int ret = EXIT_FAILURE; + pid_t pid; + int status; + siginfo_t si; + + /* Attach to the child */ + while (1) { + int sig; + + pid = wait(&status); + if (pid == -1) { + perror("wait"); + goto error; + } + + /* + * This should never happen but it's hard to flag in + * the framework. + */ + if (pid != child) + continue; + + if (WIFEXITED(status) || WIFSIGNALED(status)) + ksft_exit_fail_msg("Child died unexpectedly\n"); + + if (!WIFSTOPPED(status)) + goto error; + + sig = WSTOPSIG(status); + + if (ptrace(PTRACE_GETSIGINFO, pid, NULL, &si)) { + if (errno == ESRCH) + goto disappeared; + + if (errno == EINVAL) { + sig = 0; /* bust group-stop */ + goto cont; + } + + ksft_test_result_fail("PTRACE_GETSIGINFO: %s\n", + strerror(errno)); + goto error; + } + + if (sig == SIGSTOP && si.si_code == SI_TKILL && + si.si_pid == pid) + break; + + cont: + if (ptrace(PTRACE_CONT, pid, NULL, sig)) { + if (errno == ESRCH) + goto disappeared; + + ksft_test_result_fail("PTRACE_CONT: %s\n", + strerror(errno)); + goto error; + } + } + + ksft_print_msg("Parent is %d, child is %d\n", getpid(), child); + + ptrace_za_disabled_read_zt(child); + ptrace_set_get_zt(child); + ptrace_enable_za_via_zt(child); + + ret = EXIT_SUCCESS; + +error: + kill(child, SIGKILL); + +disappeared: + return ret; +} + +int main(void) +{ + int ret = EXIT_SUCCESS; + pid_t child; + + srandom(getpid()); + + ksft_print_header(); + + if (!(getauxval(AT_HWCAP2) & HWCAP2_SME2)) { + ksft_set_plan(1); + ksft_exit_skip("SME2 not available\n"); + } + + /* We need a valid SME VL to enable/disable ZA */ + sme_vl = prctl(PR_SME_GET_VL); + if (sme_vl == -1) { + ksft_set_plan(1); + ksft_exit_skip("Failed to read SME VL: %d (%s)\n", + errno, strerror(errno)); + } + + ksft_set_plan(EXPECTED_TESTS); + + child = fork(); + if (!child) + return do_child(); + + if (do_parent(child)) + ret = EXIT_FAILURE; + + ksft_print_cnts(); + + return ret; +} From patchwork Tue Nov 1 14:33:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 13027000 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5B8DFC433FE for ; Tue, 1 Nov 2022 14:40:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230358AbiKAOkO (ORCPT ); Tue, 1 Nov 2022 10:40:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53280 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229992AbiKAOkN (ORCPT ); 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a=openpgp-sha256; l=3403; i=broonie@kernel.org; h=from:subject; bh=XUlhSyM6tPYEzd0+yzz/l7oRBHYxosNeBw9c71QvHWc=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBjYS4/g9X6ib0ecYw1DQ9l67C7OI2vVG2uACZQB5k4 8ahxlbeJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCY2EuPwAKCRAk1otyXVSH0IbbB/ 40/0CCxUkoXK2fIoK3hrcDrCCkHGciL+SWt/1719NKZ0wvo7IQlzFPdmZi3UEEbdVd6yXpssG75UPh TgJb5hMJYGoZEUAlXNvHecpGf6xTSgEYmRtEyV7grqHAy3/w5b76KLjWYVPS3xABrRMtgenWn1nzZi 7pneNw7AWIRZEz+vu3usscV+XSHYs+N8d97pfVaXyjKNulS0PQdgPc9v4hvjKEkFOK649/lByucOH1 EYFsFSBBzxJ5S5LtMgZzRHQBVfSJrqA7zM1ZosB6PI1DNyWaYvrbzMfE19eEXKUAiqZI2OuH4Mbn93 0m2gfsx82/Sn3U912KVUqioOIhKtw+ X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB Precedence: bulk List-ID: X-Mailing-List: linux-kselftest@vger.kernel.org Add the hwcaps defined by SME 2 and 2.1 to the hwcaps test. Signed-off-by: Mark Brown --- tools/testing/selftests/arm64/abi/hwcap.c | 115 ++++++++++++++++++++++ 1 file changed, 115 insertions(+) diff --git a/tools/testing/selftests/arm64/abi/hwcap.c b/tools/testing/selftests/arm64/abi/hwcap.c index 9f255bc5f31c..832bb10d282c 100644 --- a/tools/testing/selftests/arm64/abi/hwcap.c +++ b/tools/testing/selftests/arm64/abi/hwcap.c @@ -50,6 +50,78 @@ static void sme_sigill(void) asm volatile(".inst 0x04bf5800" : : : "x0"); } +static void sme2_sigill(void) +{ + /* SMSTART ZA */ + asm volatile("msr S0_3_C4_C5_3, xzr" : : : ); + + /* ZERO ZT0 */ + asm volatile(".inst 0xc0480001" : : : ); + + /* SMSTOP */ + asm volatile("msr S0_3_C4_C6_3, xzr" : : : ); +} + +static void sme2p1_sigill(void) +{ + /* SMSTART SM */ + asm volatile("msr S0_3_C4_C3_3, xzr" : : : ); + + /* BFCLAMP { Z0.H - Z1.H }, Z0.H, Z0.H */ + asm volatile(".inst 0xc120C000" : : : ); + + /* SMSTOP */ + asm volatile("msr S0_3_C4_C6_3, xzr" : : : ); +} + +static void smei16i32_sigill(void) +{ + /* SMSTART SM */ + asm volatile("msr S0_3_C4_C3_3, xzr" : : : ); + + /* SMOPA ZA0.S, P0/M, P0/M, Z0.B, Z0.B */ + asm volatile(".inst 0xa0800000" : : : ); + + /* SMSTOP */ + asm volatile("msr S0_3_C4_C6_3, xzr" : : : ); +} + +static void smebi32i32_sigill(void) +{ + /* SMSTART SM */ + asm volatile("msr S0_3_C4_C3_3, xzr" : : : ); + + /* BMOPA ZA0.S, P0/M, P0/M, Z0.B, Z0.B */ + asm volatile(".inst 0x80800008" : : : ); + + /* SMSTOP */ + asm volatile("msr S0_3_C4_C6_3, xzr" : : : ); +} + +static void smeb16b16_sigill(void) +{ + /* SMSTART SM */ + asm volatile("msr S0_3_C4_C3_3, xzr" : : : ); + + /* BFADD ZA.H[W0, 0], {Z0.H-Z1.H} */ + asm volatile(".inst 0xC1E41C00" : : : ); + + /* SMSTOP */ + asm volatile("msr S0_3_C4_C6_3, xzr" : : : ); +} + +static void smef16f16_sigill(void) +{ + /* SMSTART SM */ + asm volatile("msr S0_3_C4_C3_3, xzr" : : : ); + + /* FADD ZA.H[W0, 0], { Z0.H-Z1.H } */ + asm volatile(".inst 0xc1a41C00" : : : ); + + /* SMSTOP */ + asm volatile("msr S0_3_C4_C6_3, xzr" : : : ); +} + static void sve_sigill(void) { /* RDVL x0, #0 */ @@ -158,6 +230,49 @@ static const struct hwcap_data { .sigill_fn = sme_sigill, .sigill_reliable = true, }, + { + .name = "SME2", + .at_hwcap = AT_HWCAP2, + .hwcap_bit = HWCAP2_SME2, + .cpuinfo = "sme2", + .sigill_fn = sme2_sigill, + .sigill_reliable = true, + }, + { + .name = "SME 2.1", + .at_hwcap = AT_HWCAP2, + .hwcap_bit = HWCAP2_SME2P1, + .cpuinfo = "sme2p1", + .sigill_fn = sme2p1_sigill, + }, + { + .name = "SME I16I32", + .at_hwcap = AT_HWCAP2, + .hwcap_bit = HWCAP2_SME_I16I32, + .cpuinfo = "smei16i32", + .sigill_fn = smei16i32_sigill, + }, + { + .name = "SME BI32I32", + .at_hwcap = AT_HWCAP2, + .hwcap_bit = HWCAP2_SME_BI32I32, + .cpuinfo = "smebi32i32", + .sigill_fn = smebi32i32_sigill, + }, + { + .name = "SME B16B16", + .at_hwcap = AT_HWCAP2, + .hwcap_bit = HWCAP2_SME_B16B16, + .cpuinfo = "smeb16b16", + .sigill_fn = smeb16b16_sigill, + }, + { + .name = "SME F16F16", + .at_hwcap = AT_HWCAP2, + .hwcap_bit = HWCAP2_SME_F16F16, + .cpuinfo = "smef16f16", + .sigill_fn = smef16f16_sigill, + }, { .name = "SVE", .at_hwcap = AT_HWCAP,