From patchwork Wed Nov 2 08:52:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lei Wang X-Patchwork-Id: 13027849 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 45F02C433FE for ; Wed, 2 Nov 2022 08:54:41 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oq9V4-0005P5-2G; Wed, 02 Nov 2022 04:53:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oq9Uv-0005Ne-CR for qemu-devel@nongnu.org; Wed, 02 Nov 2022 04:53:22 -0400 Received: from mga04.intel.com ([192.55.52.120]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oq9Ut-0008AD-JQ for qemu-devel@nongnu.org; Wed, 02 Nov 2022 04:53:21 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1667379199; x=1698915199; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=UyZWp1kELLoxMAnHvZybWFAVmfkD9Fko8h5Vk+D9uTQ=; b=bBkscSrwt9Ihpb8w6S0mlzZRntt8fn9J9SZQgf6zWL73iih38j5IhpQT AR7W+7prQNhSyr4H/0/yPE5prO5qg29MDJGdzMjejfKWgZMPUgdq4kT5N VlQcMOLoCjp+wZmf21NItTeXL32JaowjvFKvJyp2AV6Z0PJWmlnif09cg LF/88Y4B1gGHzUSAPrgEJ+AnObRZRDdKjt9oFfjGQhRF7dKjIzsif8GGO 8RKp2QEhtwg4+ZlvemCNPWHC6WkXkzuv6f15l91dMvPpoJ2VhmD5Vpoc1 5ChlNtnb8UZHccAOx55uNiMYN5XLAP1QbrlfqU7Zo1ZAGfmccUcEBqctr A==; X-IronPort-AV: E=McAfee;i="6500,9779,10518"; a="308072273" X-IronPort-AV: E=Sophos;i="5.95,232,1661842800"; d="scan'208";a="308072273" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Nov 2022 01:52:57 -0700 X-IronPort-AV: E=McAfee;i="6500,9779,10518"; a="963447212" X-IronPort-AV: E=Sophos;i="5.95,232,1661842800"; d="scan'208";a="963447212" Received: from b49691a74b20.jf.intel.com ([10.45.76.123]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Nov 2022 01:52:57 -0700 From: "Wang, Lei" To: pbonzini@redhat.com Cc: qemu-devel@nongnu.org, dgilbert@redhat.com, berrange@redhat.com, xiaoyao.li@intel.com, yang.zhong@linux.intel.com Subject: [PATCH v2 1/6] i386: Introduce FeatureWordInfo for AMX CPUID leaf 0x1D and 0x1E Date: Wed, 2 Nov 2022 01:52:51 -0700 Message-Id: <20221102085256.81139-2-lei4.wang@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221102085256.81139-1-lei4.wang@intel.com> References: <20221102085256.81139-1-lei4.wang@intel.com> MIME-Version: 1.0 Received-SPF: pass client-ip=192.55.52.120; envelope-from=lei4.wang@intel.com; helo=mga04.intel.com X-Spam_score_int: -53 X-Spam_score: -5.4 X-Spam_bar: ----- X-Spam_report: (-5.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1.051, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UPPERCASE_50_75=0.008 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org CPUID leaf 0x1D and 0x1E enumerate tile and TMUL information for AMX. Introduce FeatureWord FEAT_1D_1_EAX, FEAT_1D_1_EBX, FEAT_1D_1_ECX and FEAT_1E_0_EBX. Thus these features of AMX can be expanded when "-cpu host/max" and can be configured in named CPU model. Signed-off-by: Wang, Lei --- target/i386/cpu.c | 55 +++++++++++++++++++++++++++++++++++++++++++++++ target/i386/cpu.h | 12 +++++++++++ 2 files changed, 67 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 8a11470507..e98780773c 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1002,6 +1002,45 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = { }, .tcg_features = ~0U, }, + [FEAT_1D_1_EAX] = { + .type = CPUID_FEATURE_WORD, + .cpuid = { + .eax = 0x1D, + .needs_ecx = true, .ecx = 1, + .reg = R_EAX, + }, + .migratable_flags = CPUID_AMX_PALETTE_1_TOTAL_TILE_BYTES_MASK | + CPUID_AMX_PALETTE_1_BYTES_PER_TILE_MASK, + }, + [FEAT_1D_1_EBX] = { + .type = CPUID_FEATURE_WORD, + .cpuid = { + .eax = 0x1D, + .needs_ecx = true, .ecx = 1, + .reg = R_EBX, + }, + .migratable_flags = CPUID_AMX_PALETTE_1_BYTES_PER_ROW_MASK | + CPUID_AMX_PALETTE_1_MAX_NAMES_MASK, + }, + [FEAT_1D_1_ECX] = { + .type = CPUID_FEATURE_WORD, + .cpuid = { + .eax = 0x1D, + .needs_ecx = true, .ecx = 1, + .reg = R_ECX, + }, + .migratable_flags = CPUID_AMX_PALETTE_1_MAX_ROWS_MASK, + }, + [FEAT_1E_0_EBX] = { + .type = CPUID_FEATURE_WORD, + .cpuid = { + .eax = 0x1E, + .needs_ecx = true, .ecx = 0, + .reg = R_EBX, + }, + .migratable_flags = CPUID_AMX_TMUL_MAX_K_MASK | + CPUID_AMX_TMUL_MAX_N_MASK, + }, /*Below are MSR exposed features*/ [FEAT_ARCH_CAPABILITIES] = { .type = MSR_FEATURE_WORD, @@ -1371,6 +1410,22 @@ static FeatureDep feature_dependencies[] = { .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT }, .to = { FEAT_14_0_ECX, ~0ull }, }, + { + .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_AMX_TILE }, + .to = { FEAT_1D_1_EAX, ~0ull }, + }, + { + .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_AMX_TILE }, + .to = { FEAT_1D_1_EBX, ~0ull }, + }, + { + .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_AMX_TILE }, + .to = { FEAT_1D_1_ECX, ~0ull }, + }, + { + .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_AMX_TILE }, + .to = { FEAT_1E_0_EBX, ~0ull }, + }, { .from = { FEAT_8000_0001_EDX, CPUID_EXT2_RDTSCP }, .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDTSCP }, diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 7edf5dfac3..1c90fb6c9d 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -583,6 +583,14 @@ typedef enum X86Seg { XSTATE_Hi16_ZMM_MASK | XSTATE_PKRU_MASK | \ XSTATE_XTILE_CFG_MASK | XSTATE_XTILE_DATA_MASK) +#define CPUID_AMX_PALETTE_1_TOTAL_TILE_BYTES_MASK 0xffffU +#define CPUID_AMX_PALETTE_1_BYTES_PER_TILE_MASK (0xffffU << 16) +#define CPUID_AMX_PALETTE_1_BYTES_PER_ROW_MASK 0xffffU +#define CPUID_AMX_PALETTE_1_MAX_NAMES_MASK (0xffffU << 16) +#define CPUID_AMX_PALETTE_1_MAX_ROWS_MASK 0xffffU +#define CPUID_AMX_TMUL_MAX_K_MASK 0xffU +#define CPUID_AMX_TMUL_MAX_N_MASK (0xffffU << 8) + /* CPUID feature words */ typedef enum FeatureWord { FEAT_1_EDX, /* CPUID[1].EDX */ @@ -603,6 +611,10 @@ typedef enum FeatureWord { FEAT_6_EAX, /* CPUID[6].EAX */ FEAT_XSAVE_XCR0_LO, /* CPUID[EAX=0xd,ECX=0].EAX */ FEAT_XSAVE_XCR0_HI, /* CPUID[EAX=0xd,ECX=0].EDX */ + FEAT_1D_1_EAX, /* CPUID[EAX=0x1d,ECX=1].EAX */ + FEAT_1D_1_EBX, /* CPUID[EAX=0x1d,ECX=1].EBX */ + FEAT_1D_1_ECX, /* CPUID[EAX=0x1d,ECX=1].ECX */ + FEAT_1E_0_EBX, /* CPUID[EAX=0x1e,ECX=0].EBX */ FEAT_ARCH_CAPABILITIES, FEAT_CORE_CAPABILITY, FEAT_PERF_CAPABILITIES, From patchwork Wed Nov 2 08:52:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lei Wang X-Patchwork-Id: 13027853 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EDC71C43219 for ; Wed, 2 Nov 2022 08:55:15 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oq9V5-0005Pw-P9; Wed, 02 Nov 2022 04:53:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oq9Uw-0005OI-PI for qemu-devel@nongnu.org; Wed, 02 Nov 2022 04:53:24 -0400 Received: from mga04.intel.com ([192.55.52.120]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oq9Uv-0008Fg-7V for qemu-devel@nongnu.org; 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d="scan'208";a="963447215" Received: from b49691a74b20.jf.intel.com ([10.45.76.123]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Nov 2022 01:52:57 -0700 From: "Wang, Lei" To: pbonzini@redhat.com Cc: qemu-devel@nongnu.org, dgilbert@redhat.com, berrange@redhat.com, xiaoyao.li@intel.com, yang.zhong@linux.intel.com Subject: [PATCH v2 2/6] i386: Remove unused parameter "uint32_t bit" in feature_word_description() Date: Wed, 2 Nov 2022 01:52:52 -0700 Message-Id: <20221102085256.81139-3-lei4.wang@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221102085256.81139-1-lei4.wang@intel.com> References: <20221102085256.81139-1-lei4.wang@intel.com> MIME-Version: 1.0 Received-SPF: pass client-ip=192.55.52.120; envelope-from=lei4.wang@intel.com; helo=mga04.intel.com X-Spam_score_int: -54 X-Spam_score: -5.5 X-Spam_bar: ----- X-Spam_report: (-5.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1.051, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Parameter "uint32_t bit" is not used in function feature_word_description(), so remove it. Signed-off-by: Wang, Lei --- target/i386/cpu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index e98780773c..0083a2a7f7 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -4290,7 +4290,7 @@ static const TypeInfo max_x86_cpu_type_info = { .class_init = max_x86_cpu_class_init, }; -static char *feature_word_description(FeatureWordInfo *f, uint32_t bit) +static char *feature_word_description(FeatureWordInfo *f) { assert(f->type == CPUID_FEATURE_WORD || f->type == MSR_FEATURE_WORD); @@ -4329,6 +4329,7 @@ static void mark_unavailable_features(X86CPU *cpu, FeatureWord w, uint64_t mask, CPUX86State *env = &cpu->env; FeatureWordInfo *f = &feature_word_info[w]; int i; + g_autofree char *feat_word_str = feature_word_description(f); if (!cpu->force_features) { env->features[w] &= ~mask; @@ -4341,7 +4342,6 @@ static void mark_unavailable_features(X86CPU *cpu, FeatureWord w, uint64_t mask, for (i = 0; i < 64; ++i) { if ((1ULL << i) & mask) { - g_autofree char *feat_word_str = feature_word_description(f, i); warn_report("%s: %s%s%s [bit %d]", verbose_prefix, feat_word_str, From patchwork Wed Nov 2 08:52:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lei Wang X-Patchwork-Id: 13027854 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 18D06C4332F for ; Wed, 2 Nov 2022 08:55:41 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oq9V6-0005QV-A3; Wed, 02 Nov 2022 04:53:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oq9Ux-0005OJ-I1 for qemu-devel@nongnu.org; Wed, 02 Nov 2022 04:53:24 -0400 Received: from mga04.intel.com ([192.55.52.120]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oq9Uv-0008AD-QB for qemu-devel@nongnu.org; Wed, 02 Nov 2022 04:53:23 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1667379201; x=1698915201; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=r90dV8iF2ORg/n2SN9spjUCoFBK8wGi5ozVritK4IwE=; b=DhLjhAsciE5qastxmHzIxfpyEPLwi8+puV1eZ4AXyY8dpTACfPKdZIuQ mvOevYBu1k+YEFKVYtWkbq/do1kJNKKdJIt3p5/bszQQT+qjinz4d/fe2 Z3kTuAC0Cqhiks5b/UZaJHrcSOllciVBXp+ppYIoZMCYsRj+s6Gp6zOTL /gX+tyynL7mEBLOpIT8hQRaSBaPY9EFpBM5S24tXXkz8i8JXlZTDnA5bI kZZtTnZNrWwHZHmWTJ4kptuyd98zKONjG50czx6DV/LKIF7yfcnf1c8qz 4L9z4gKoKdOvkNA0F0t0CSAoa9uqTAPqF/MrlbF+knf2l+D5CpDLV+l2G A==; X-IronPort-AV: E=McAfee;i="6500,9779,10518"; a="308072277" X-IronPort-AV: E=Sophos;i="5.95,232,1661842800"; d="scan'208";a="308072277" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Nov 2022 01:52:58 -0700 X-IronPort-AV: E=McAfee;i="6500,9779,10518"; a="963447219" X-IronPort-AV: E=Sophos;i="5.95,232,1661842800"; d="scan'208";a="963447219" Received: from b49691a74b20.jf.intel.com ([10.45.76.123]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Nov 2022 01:52:58 -0700 From: "Wang, Lei" To: pbonzini@redhat.com Cc: qemu-devel@nongnu.org, dgilbert@redhat.com, berrange@redhat.com, xiaoyao.li@intel.com, yang.zhong@linux.intel.com Subject: [PATCH v2 3/6] i386: Introduce new struct "MultiBitFeatureInfo" for multi-bit features Date: Wed, 2 Nov 2022 01:52:53 -0700 Message-Id: <20221102085256.81139-4-lei4.wang@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221102085256.81139-1-lei4.wang@intel.com> References: <20221102085256.81139-1-lei4.wang@intel.com> MIME-Version: 1.0 Received-SPF: pass client-ip=192.55.52.120; envelope-from=lei4.wang@intel.com; helo=mga04.intel.com X-Spam_score_int: -54 X-Spam_score: -5.5 X-Spam_bar: ----- X-Spam_report: (-5.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1.051, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Some features use multiple CPUID bits to form a value to be used, e.g., CPUID(0x1E,0):EBX[23:08] is regarded as the tmul_maxn value for AMX. Introduce a new struct "MultiBitFeatureInfo" to hold the information for those features and create a corresponding member in struct FeatureWordInfo, so that the infomation can be assigned for each item in feature_word_info array and used in the future. Signed-off-by: Wang, Lei --- target/i386/cpu-internal.h | 9 +++++++ target/i386/cpu.c | 54 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 63 insertions(+) diff --git a/target/i386/cpu-internal.h b/target/i386/cpu-internal.h index 9baac5c0b4..66b3d66cb4 100644 --- a/target/i386/cpu-internal.h +++ b/target/i386/cpu-internal.h @@ -25,6 +25,13 @@ typedef enum FeatureWordType { MSR_FEATURE_WORD, } FeatureWordType; +typedef struct MultiBitFeatureInfo { + const char *feat_name; + uint64_t mask; + unsigned high_bit_position; + unsigned low_bit_position; +} MultiBitFeatureInfo; + typedef struct FeatureWordInfo { FeatureWordType type; /* feature flags names are taken from "Intel Processor Identification and @@ -51,6 +58,8 @@ typedef struct FeatureWordInfo { uint64_t migratable_flags; /* Feature flags known to be migratable */ /* Features that shouldn't be auto-enabled by "-cpu host" */ uint64_t no_autoenable_flags; + unsigned num_multi_bit_features; + MultiBitFeatureInfo *multi_bit_features; } FeatureWordInfo; extern FeatureWordInfo feature_word_info[]; diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 0083a2a7f7..7ae232ab18 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1011,6 +1011,21 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = { }, .migratable_flags = CPUID_AMX_PALETTE_1_TOTAL_TILE_BYTES_MASK | CPUID_AMX_PALETTE_1_BYTES_PER_TILE_MASK, + .num_multi_bit_features = 2, + .multi_bit_features = (MultiBitFeatureInfo[]){ + { + .feat_name = "total_tile_bytes", + .mask = CPUID_AMX_PALETTE_1_TOTAL_TILE_BYTES_MASK, + .high_bit_position = 15, + .low_bit_position = 0, + }, + { + .feat_name = "bytes_per_tile", + .mask = CPUID_AMX_PALETTE_1_BYTES_PER_TILE_MASK, + .high_bit_position = 31, + .low_bit_position = 16, + }, + }, }, [FEAT_1D_1_EBX] = { .type = CPUID_FEATURE_WORD, @@ -1021,6 +1036,21 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = { }, .migratable_flags = CPUID_AMX_PALETTE_1_BYTES_PER_ROW_MASK | CPUID_AMX_PALETTE_1_MAX_NAMES_MASK, + .num_multi_bit_features = 2, + .multi_bit_features = (MultiBitFeatureInfo[]){ + { + .feat_name = "bytes_per_row", + .mask = CPUID_AMX_PALETTE_1_BYTES_PER_ROW_MASK, + .high_bit_position = 15, + .low_bit_position = 0, + }, + { + .feat_name = "max_names", + .mask = CPUID_AMX_PALETTE_1_MAX_NAMES_MASK, + .high_bit_position = 31, + .low_bit_position = 16, + }, + }, }, [FEAT_1D_1_ECX] = { .type = CPUID_FEATURE_WORD, @@ -1030,6 +1060,15 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = { .reg = R_ECX, }, .migratable_flags = CPUID_AMX_PALETTE_1_MAX_ROWS_MASK, + .num_multi_bit_features = 1, + .multi_bit_features = (MultiBitFeatureInfo[]){ + { + .feat_name = "max_rows", + .mask = CPUID_AMX_PALETTE_1_MAX_ROWS_MASK, + .high_bit_position = 15, + .low_bit_position = 0, + }, + }, }, [FEAT_1E_0_EBX] = { .type = CPUID_FEATURE_WORD, @@ -1040,6 +1079,21 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = { }, .migratable_flags = CPUID_AMX_TMUL_MAX_K_MASK | CPUID_AMX_TMUL_MAX_N_MASK, + .num_multi_bit_features = 2, + .multi_bit_features = (MultiBitFeatureInfo[]){ + { + .feat_name = "tmul_maxk", + .mask = CPUID_AMX_TMUL_MAX_K_MASK, + .high_bit_position = 7, + .low_bit_position = 0, + }, + { + .feat_name = "tmul_maxn", + .mask = CPUID_AMX_TMUL_MAX_N_MASK, + .high_bit_position = 23, + .low_bit_position = 8, + }, + }, }, /*Below are MSR exposed features*/ [FEAT_ARCH_CAPABILITIES] = { From patchwork Wed Nov 2 08:52:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lei Wang X-Patchwork-Id: 13027850 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 793E1C4321E for ; Wed, 2 Nov 2022 08:54:41 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oq9V6-0005QX-UK; Wed, 02 Nov 2022 04:53:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oq9Uy-0005OY-T7 for qemu-devel@nongnu.org; Wed, 02 Nov 2022 04:53:26 -0400 Received: from mga04.intel.com ([192.55.52.120]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oq9Ux-0008Fg-4I for qemu-devel@nongnu.org; Wed, 02 Nov 2022 04:53:24 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1667379203; x=1698915203; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=DkvbW4konce0bxDTdajniQuAD892K9uSt/Jkb/vfhss=; b=D3w17V3sr+1G3aN1eHINJohtQq288P0ekgTIldAVa1dlsELWhv4uVbX+ aTUNcDNcQSsprZZNHqWJVUxtlOcGvND4u70fYfyVqEL7uygVW9O90BIq/ jeEj9gKxnOUq1Y6MlzQZEHfWPL2THOWNNdOPmlBFpnq1H6eu0K8pEBv3b 83pYRGPyh/Yt/tU53hxaMfbxNxAbaBtxi0Bnt4LWp8MK9HcdihVZFPWkQ 9zMWHDWB3rzqZzgbfnhNH4jhBvioNoJxPy4/f+f67d0/CA0n7k/MQgtGB d5H2D7/TNauq1rhjSWYGQ2DPSdhk71xY8P+Y2nqKZb8EaSF3SyrnkAItb w==; X-IronPort-AV: E=McAfee;i="6500,9779,10518"; a="308072278" X-IronPort-AV: E=Sophos;i="5.95,232,1661842800"; d="scan'208";a="308072278" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Nov 2022 01:52:58 -0700 X-IronPort-AV: E=McAfee;i="6500,9779,10518"; a="963447223" X-IronPort-AV: E=Sophos;i="5.95,232,1661842800"; d="scan'208";a="963447223" Received: from b49691a74b20.jf.intel.com ([10.45.76.123]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Nov 2022 01:52:58 -0700 From: "Wang, Lei" To: pbonzini@redhat.com Cc: qemu-devel@nongnu.org, dgilbert@redhat.com, berrange@redhat.com, xiaoyao.li@intel.com, yang.zhong@linux.intel.com Subject: [PATCH v2 4/6] i386: Mask and report unavailable multi-bit feature values Date: Wed, 2 Nov 2022 01:52:54 -0700 Message-Id: <20221102085256.81139-5-lei4.wang@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221102085256.81139-1-lei4.wang@intel.com> References: <20221102085256.81139-1-lei4.wang@intel.com> MIME-Version: 1.0 Received-SPF: pass client-ip=192.55.52.120; envelope-from=lei4.wang@intel.com; helo=mga04.intel.com X-Spam_score_int: -54 X-Spam_score: -5.5 X-Spam_bar: ----- X-Spam_report: (-5.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1.051, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Some feature words, e.g., feature words in AMX-related CPUID leaf 0x1D and 0x1E are not bit-wise but multiple bits represents one value. Handle this situation when the values specified are not the same as which are reported by KVM. The handling includes: - The responsibility of masking bits and giving warnings are delegated to the feature enabler. A framework is also provided to enable this. - To simplify the initialization, a default function is provided if the the function is not specified. The reason why delegating this responsibility rather than just marking them as zeros when they are not same is because different multi-bit features may have different logic, which is case by case, for example: 1. CPUID.0x14_0x1:EBX[15:0]. Even though it's multi-bits field, it's a bitmap and each bit represents a separate capability. 2. CPUID.0x14_0x1:EAX[2:0] represents the number of configurable Address Ranges. 3 bits as a whole to represent a integer value. It means the maximum capability of HW. If KVM reports M, then M to 0 is legal value to configure (because KVM can emulate each value correctly). 3. CPUID.0x1D_0x1:EAX[31:16] represents palette 1 bytes_per_tile. 16 bits as a whole represent an integer value. It's not like case 2 and SW needs to configure the same value as reported. Because it's not possible for SW to configure to a different value and KVM cannot emulate it. So marking them blindly as zeros is incorrect, and delegating this responsibility can let each multi-bit feature have its own way to mask bits. Signed-off-by: Wang, Lei --- target/i386/cpu-internal.h | 2 ++ target/i386/cpu.c | 36 ++++++++++++++++++++++++++++++++++++ 2 files changed, 38 insertions(+) diff --git a/target/i386/cpu-internal.h b/target/i386/cpu-internal.h index 66b3d66cb4..83c7b53926 100644 --- a/target/i386/cpu-internal.h +++ b/target/i386/cpu-internal.h @@ -30,6 +30,8 @@ typedef struct MultiBitFeatureInfo { uint64_t mask; unsigned high_bit_position; unsigned low_bit_position; + void (*mark_unavailable_multi_bit)(X86CPU *cpu, FeatureWord w, int index, + const char *verbose_prefix); } MultiBitFeatureInfo; typedef struct FeatureWordInfo { diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 7ae232ab18..53223857ba 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -4377,6 +4377,28 @@ static bool x86_cpu_have_filtered_features(X86CPU *cpu) return false; } +static void mark_unavailable_multi_bit_default(X86CPU *cpu, FeatureWord w, + int index, + const char *verbose_prefix) +{ + FeatureWordInfo *f = &feature_word_info[w]; + g_autofree char *feat_word_str = feature_word_description(f); + uint64_t host_feat = x86_cpu_get_supported_feature_word(w, false); + MultiBitFeatureInfo mf = f->multi_bit_features[index]; + + if ((cpu->env.features[w] & mf.mask) && + ((cpu->env.features[w] ^ host_feat) & mf.mask)) { + if (!cpu->force_features) { + cpu->env.features[w] &= ~mf.mask; + } + cpu->filtered_features[w] |= mf.mask; + if (verbose_prefix) + warn_report("%s: %s.%s [%u:%u]", verbose_prefix, feat_word_str, + mf.feat_name, mf.high_bit_position, + mf.low_bit_position); + } +} + static void mark_unavailable_features(X86CPU *cpu, FeatureWord w, uint64_t mask, const char *verbose_prefix) { @@ -6428,6 +6450,20 @@ static void x86_cpu_filter_features(X86CPU *cpu, bool verbose) x86_cpu_get_supported_feature_word(w, false); uint64_t requested_features = env->features[w]; uint64_t unavailable_features = requested_features & ~host_feat; + FeatureWordInfo f = feature_word_info[w]; + int i; + + for (i = 0; i < f.num_multi_bit_features; i++) { + MultiBitFeatureInfo mf = f.multi_bit_features[i]; + if (mf.mark_unavailable_multi_bit) { + mf.mark_unavailable_multi_bit(cpu, w, i, prefix); + } else { + mark_unavailable_multi_bit_default(cpu, w, i, prefix); + } + + unavailable_features &= ~mf.mask; + } + mark_unavailable_features(cpu, w, unavailable_features, prefix); } From patchwork Wed Nov 2 08:52:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lei Wang X-Patchwork-Id: 13027852 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 05D7CC43217 for ; Wed, 2 Nov 2022 08:55:15 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oq9V7-0005QY-FG; Wed, 02 Nov 2022 04:53:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oq9V0-0005OZ-26 for qemu-devel@nongnu.org; Wed, 02 Nov 2022 04:53:27 -0400 Received: from mga04.intel.com ([192.55.52.120]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oq9Ux-0008G6-O4 for qemu-devel@nongnu.org; Wed, 02 Nov 2022 04:53:25 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1667379203; x=1698915203; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=v7GPJAYTnIGoHNQV9oOiW8oLs3igAqh2m5HxrAubfgE=; b=FV8Yf7N9z1ZDyr4xUnlmLz4MsxwqbVGpplVi5U8KWlvhp6MROgImrL+B FjW0uKu0GBBaY8eiJB865+AXDekPSx+AYP30mCts5T0iYaTNKJO1ajSeO ug3n22puXxxTlmHsomwkzvGyUAwWJmYk8+uRk2rnaJL2h6ufTLchheFPC iF16bIqpDA897Ejn48nKdi9utp9OoVMOglkNm8uqptnuVnySkG4tVt5gX eJ1n9K88reNUaR1GqmXFnMoyMkrs27Bv+BYYOZBMbxCwwOx7yB/X95Z3h ASfyTTRaGJctwvHqTnRmcKb63tIrITQoxv6nJHwP7aeVrRGX5bPXRqcCg g==; X-IronPort-AV: E=McAfee;i="6500,9779,10518"; a="308072279" X-IronPort-AV: E=Sophos;i="5.95,232,1661842800"; d="scan'208";a="308072279" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Nov 2022 01:52:58 -0700 X-IronPort-AV: E=McAfee;i="6500,9779,10518"; a="963447227" X-IronPort-AV: E=Sophos;i="5.95,232,1661842800"; d="scan'208";a="963447227" Received: from b49691a74b20.jf.intel.com ([10.45.76.123]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Nov 2022 01:52:58 -0700 From: "Wang, Lei" To: pbonzini@redhat.com Cc: qemu-devel@nongnu.org, dgilbert@redhat.com, berrange@redhat.com, xiaoyao.li@intel.com, yang.zhong@linux.intel.com Subject: [PATCH v2 5/6] i386: Initialize AMX CPUID leaves with corresponding env->features[] leaves Date: Wed, 2 Nov 2022 01:52:55 -0700 Message-Id: <20221102085256.81139-6-lei4.wang@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221102085256.81139-1-lei4.wang@intel.com> References: <20221102085256.81139-1-lei4.wang@intel.com> MIME-Version: 1.0 Received-SPF: pass client-ip=192.55.52.120; envelope-from=lei4.wang@intel.com; helo=mga04.intel.com X-Spam_score_int: -54 X-Spam_score: -5.5 X-Spam_bar: ----- X-Spam_report: (-5.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1.051, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The AMX-related CPUID value, i.e., CPUID(0x1D,1):EAX, CPUID(0x1D,1):EBX, CPUID(0x1D,1):ECX and CPUID(0x1E,0):EBX are hard-coded to Sapphire Rapids without considering future platforms. Replace these hard-coded values with env->features[], so QEMU can pass the right value to KVM. Signed-off-by: Wang, Lei --- target/i386/cpu.c | 27 +++++++++++++-------------- 1 file changed, 13 insertions(+), 14 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 53223857ba..fce5a04be7 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -576,16 +576,16 @@ static CPUCacheInfo legacy_l3_cache = { #define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32K,64K */ /* CPUID Leaf 0x1D constants: */ -#define INTEL_AMX_TILE_MAX_SUBLEAF 0x1 -#define INTEL_AMX_TOTAL_TILE_BYTES 0x2000 -#define INTEL_AMX_BYTES_PER_TILE 0x400 -#define INTEL_AMX_BYTES_PER_ROW 0x40 -#define INTEL_AMX_TILE_MAX_NAMES 0x8 -#define INTEL_AMX_TILE_MAX_ROWS 0x10 +#define INTEL_SPR_AMX_TILE_MAX_SUBLEAF 0x1 +#define INTEL_SPR_AMX_TOTAL_TILE_BYTES 0x2000 +#define INTEL_SPR_AMX_BYTES_PER_TILE 0x400 +#define INTEL_SPR_AMX_BYTES_PER_ROW 0x40 +#define INTEL_SPR_AMX_TILE_MAX_NAMES 0x8 +#define INTEL_SPR_AMX_TILE_MAX_ROWS 0x10 /* CPUID Leaf 0x1E constants: */ -#define INTEL_AMX_TMUL_MAX_K 0x10 -#define INTEL_AMX_TMUL_MAX_N 0x40 +#define INTEL_SPR_AMX_TMUL_MAX_K 0x10 +#define INTEL_SPR_AMX_TMUL_MAX_N 0x40 void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1, uint32_t vendor2, uint32_t vendor3) @@ -5765,12 +5765,11 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, if (count == 0) { /* Highest numbered palette subleaf */ - *eax = INTEL_AMX_TILE_MAX_SUBLEAF; + *eax = INTEL_SPR_AMX_TILE_MAX_SUBLEAF; } else if (count == 1) { - *eax = INTEL_AMX_TOTAL_TILE_BYTES | - (INTEL_AMX_BYTES_PER_TILE << 16); - *ebx = INTEL_AMX_BYTES_PER_ROW | (INTEL_AMX_TILE_MAX_NAMES << 16); - *ecx = INTEL_AMX_TILE_MAX_ROWS; + *eax = env->features[FEAT_1D_1_EAX]; + *ebx = env->features[FEAT_1D_1_EBX]; + *ecx = env->features[FEAT_1D_1_ECX]; } break; } @@ -5786,7 +5785,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, if (count == 0) { /* Highest numbered palette subleaf */ - *ebx = INTEL_AMX_TMUL_MAX_K | (INTEL_AMX_TMUL_MAX_N << 8); + *ebx = env->features[FEAT_1E_0_EBX]; } break; } From patchwork Wed Nov 2 08:52:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lei Wang X-Patchwork-Id: 13027851 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 70F3DC43217 for ; Wed, 2 Nov 2022 08:54:41 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oq9V9-0005QZ-0p; Wed, 02 Nov 2022 04:53:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oq9V0-0005Oo-JY for qemu-devel@nongnu.org; Wed, 02 Nov 2022 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d="scan'208";a="308072280" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Nov 2022 01:52:59 -0700 X-IronPort-AV: E=McAfee;i="6500,9779,10518"; a="963447232" X-IronPort-AV: E=Sophos;i="5.95,232,1661842800"; d="scan'208";a="963447232" Received: from b49691a74b20.jf.intel.com ([10.45.76.123]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Nov 2022 01:52:58 -0700 From: "Wang, Lei" To: pbonzini@redhat.com Cc: qemu-devel@nongnu.org, dgilbert@redhat.com, berrange@redhat.com, xiaoyao.li@intel.com, yang.zhong@linux.intel.com Subject: [PATCH v2 6/6] i386: Add new CPU model SapphireRapids Date: Wed, 2 Nov 2022 01:52:56 -0700 Message-Id: <20221102085256.81139-7-lei4.wang@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221102085256.81139-1-lei4.wang@intel.com> References: <20221102085256.81139-1-lei4.wang@intel.com> MIME-Version: 1.0 Received-SPF: pass client-ip=192.55.52.120; envelope-from=lei4.wang@intel.com; helo=mga04.intel.com X-Spam_score_int: -53 X-Spam_score: -5.4 X-Spam_bar: ----- X-Spam_report: (-5.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1.051, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UPPERCASE_50_75=0.008 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The new CPU model mostly inherits features from Icelake-Server, while adding new features: - AMX (Advance Matrix eXtensions) - Bus Lock Debug Exception and new instructions: - AVX VNNI (Vector Neural Network Instruction): - VPDPBUS: Multiply and Add Unsigned and Signed Bytes - VPDPBUSDS: Multiply and Add Unsigned and Signed Bytes with Saturation - VPDPWSSD: Multiply and Add Signed Word Integers - VPDPWSSDS: Multiply and Add Signed Integers with Saturation - FP16: Replicates existing AVX512 computational SP (FP32) instructions using FP16 instead of FP32 for ~2X performance gain - SERIALIZE: Provide software with a simple way to force the processor to complete all modifications, faster, allowed in all privilege levels and not causing an unconditional VM exit - TSX Suspend Load Address Tracking: Allows programmers to choose which memory accesses do not need to be tracked in the TSX read set - AVX512_BF16: Vector Neural Network Instructions supporting BFLOAT16 inputs and conversion instructions from IEEE single precision Features may be added in future versions: - CET (virtualization support hasn't been merged) Instructions may be added in future versions: - fast zero-length MOVSB (KVM doesn't support yet) - fast short STOSB (KVM doesn't support yet) - fast short CMPSB, SCASB (KVM doesn't support yet) Signed-off-by: Wang, Lei Reviewed-by: Robert Hoo --- target/i386/cpu.c | 135 ++++++++++++++++++++++++++++++++++++++++++++++ target/i386/cpu.h | 4 ++ 2 files changed, 139 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index fce5a04be7..b4513742bd 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -3576,6 +3576,141 @@ static const X86CPUDefinition builtin_x86_defs[] = { { /* end of list */ } } }, + { + .name = "SapphireRapids", + .level = 0x20, + .vendor = CPUID_VENDOR_INTEL, + .family = 6, + .model = 143, + .stepping = 4, + /* + * please keep the ascending order so that we can have a clear view of + * bit position of each feature. + */ + .features[FEAT_1_EDX] = + CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | + CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | + CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | + CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | + CPUID_SSE | CPUID_SSE2, + .features[FEAT_1_ECX] = + CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 | + CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 | + CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | + CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | + CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND, + .features[FEAT_8000_0001_EDX] = + CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | + CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, + .features[FEAT_8000_0001_ECX] = + CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH, + .features[FEAT_8000_0008_EBX] = + CPUID_8000_0008_EBX_WBNOINVD, + .features[FEAT_7_0_EBX] = + CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_HLE | + CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | + CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_RTM | + CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | + CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | + CPUID_7_0_EBX_AVX512IFMA | CPUID_7_0_EBX_CLFLUSHOPT | + CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI | + CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL, + .features[FEAT_7_0_ECX] = + CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | + CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | + CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | + CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | + CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 | + CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT, + .features[FEAT_7_0_EDX] = + CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE | + CPUID_7_0_EDX_TSX_LDTRK | CPUID_7_0_EDX_AMX_BF16 | + CPUID_7_0_EDX_AVX512_FP16 | CPUID_7_0_EDX_AMX_TILE | + CPUID_7_0_EDX_AMX_INT8 | CPUID_7_0_EDX_SPEC_CTRL | + CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD, + .features[FEAT_ARCH_CAPABILITIES] = + MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | + MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | + MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO, + .features[FEAT_XSAVE] = + CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | + CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES | CPUID_D_1_EAX_XFD, + .features[FEAT_6_EAX] = + CPUID_6_EAX_ARAT, + .features[FEAT_7_1_EAX] = + CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_AVX512_BF16, + .features[FEAT_1D_1_EAX] = INTEL_SPR_AMX_TOTAL_TILE_BYTES | + (INTEL_SPR_AMX_BYTES_PER_TILE << 16), + .features[FEAT_1D_1_EBX] = INTEL_SPR_AMX_BYTES_PER_ROW | + (INTEL_SPR_AMX_TILE_MAX_NAMES << 16), + .features[FEAT_1D_1_ECX] = INTEL_SPR_AMX_TILE_MAX_ROWS, + .features[FEAT_1E_0_EBX] = INTEL_SPR_AMX_TMUL_MAX_K | + (INTEL_SPR_AMX_TMUL_MAX_N << 8), + .features[FEAT_VMX_BASIC] = + MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, + .features[FEAT_VMX_ENTRY_CTLS] = + VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE | + VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | + VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER, + .features[FEAT_VMX_EPT_VPID_CAPS] = + MSR_VMX_EPT_EXECONLY | + MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_PAGE_WALK_LENGTH_5 | + MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB | + MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS | + MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | + MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | + MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | + MSR_VMX_EPT_INVVPID_ALL_CONTEXT | + MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, + .features[FEAT_VMX_EXIT_CTLS] = + VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | + VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | + VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | + VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | + VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, + .features[FEAT_VMX_MISC] = + MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | + MSR_VMX_MISC_VMWRITE_VMEXIT, + .features[FEAT_VMX_PINBASED_CTLS] = + VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING | + VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER | + VMX_PIN_BASED_POSTED_INTR, + .features[FEAT_VMX_PROCBASED_CTLS] = + VMX_CPU_BASED_VIRTUAL_INTR_PENDING | + VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | + VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | + VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | + VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | + VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | + VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING | + VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | + VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG | + VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | + VMX_CPU_BASED_PAUSE_EXITING | + VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, + .features[FEAT_VMX_SECONDARY_CTLS] = + VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | + VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC | + VMX_SECONDARY_EXEC_RDTSCP | + VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | + VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXITING | + VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | + VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | + VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | + VMX_SECONDARY_EXEC_RDRAND_EXITING | + VMX_SECONDARY_EXEC_ENABLE_INVPCID | + VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | + VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML | + VMX_SECONDARY_EXEC_XSAVES, + .features[FEAT_VMX_VMFUNC] = + MSR_VMX_VMFUNC_EPT_SWITCHING, + .xlevel = 0x80000008, + .model_id = "Intel Xeon Processor (SapphireRapids)", + .versions = (X86CPUVersionDefinition[]) { + { .version = 1 }, + { /* end of list */ }, + }, + }, { .name = "Denverton", .level = 21, diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 1c90fb6c9d..2ea94b78b3 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -891,10 +891,14 @@ uint64_t x86_cpu_get_supported_feature_word(FeatureWord w, #define CPUID_7_0_EDX_TSX_LDTRK (1U << 16) /* Architectural LBRs */ #define CPUID_7_0_EDX_ARCH_LBR (1U << 19) +/* AMX_BF16 instruction */ +#define CPUID_7_0_EDX_AMX_BF16 (1U << 22) /* AVX512_FP16 instruction */ #define CPUID_7_0_EDX_AVX512_FP16 (1U << 23) /* AMX tile (two-dimensional register) */ #define CPUID_7_0_EDX_AMX_TILE (1U << 24) +/* AMX_INT8 instruction */ +#define CPUID_7_0_EDX_AMX_INT8 (1U << 25) /* Speculation Control */ #define CPUID_7_0_EDX_SPEC_CTRL (1U << 26) /* Single Thread Indirect Branch Predictors */