From patchwork Wed Nov 2 09:01:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Foss X-Patchwork-Id: 13027872 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E6295C4167B for ; Wed, 2 Nov 2022 09:02:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231328AbiKBJCk (ORCPT ); Wed, 2 Nov 2022 05:02:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34918 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231373AbiKBJCF (ORCPT ); Wed, 2 Nov 2022 05:02:05 -0400 Received: from mail-wr1-x434.google.com (mail-wr1-x434.google.com [IPv6:2a00:1450:4864:20::434]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3CE6B286DB for ; Wed, 2 Nov 2022 02:01:48 -0700 (PDT) Received: by mail-wr1-x434.google.com with SMTP id y16so23466814wrt.12 for ; Wed, 02 Nov 2022 02:01:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=sJwgXX3StBPw4KOENIV6+/ZT/9r64J3QECerjdiBj8E=; b=Nh+SlWGOhrAOk0lcCXZSQa0YEfcrlvree0Gav6U+2pP8gd56TYkqNw41fXA38eEpjK YF1vtvIT5gQkez+kPI2sEWZjspVXxle1b7ResvKq/Q/t5NLktRVQ5hFUlZ7joP2kg//g PFDLfwWLDxPutFXyQP7N3UOqN0w/WqrJJP90+rG7u9d/Js4h35DGVGG61dzSnEDKyPTr vIWGRyCz3wmfZl0QTiOo5CSr2wGm3uCDqHC+tOQo5jBApMST0EusZ3yHffl2jMOC+uzW hWB8nujMspCxOQw4/jAw4Mw1T2jYPv/HSuvSwNnuR1xAw3HPZ2mQaOtBrFNXPawWjCX8 B88w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=sJwgXX3StBPw4KOENIV6+/ZT/9r64J3QECerjdiBj8E=; b=AEmQNZxsYjsZ0boTGFXv7gtYaJHNAwhvxMTvGqxPRlxZcgEOkswFbnMca+ZN4P9VQS rRzrCWrxuRfVoyn/aVlwgg1H7l202c6Fyao6sDVTBqEx2DnAsPiwbxiafyJnfj2OHxBB Mqevt3vNPXsCuylfFyzqKUKGqQpjTWLpkSjiR9MkA6pUm9XNh7gkz4fq0CngdC8wZ1Ox tXpaTh/yx9Ui+CXVYrjFtU+VaoKWkqVlwuUkieb9Qs1DTDG3DPiWpnwNKvbWRYLcfc+K lx+XOYF00WEHSuVqUKGDfQkBmq47aZgrjtlr9OYY/g1+T6Ta4yYn5ehdDwW5LwA1ZogX 5Udg== X-Gm-Message-State: ACrzQf2Ip7VLH1JFC1ZMPXn6tfQydkpCCfcUgWOWHvF7C3FY3/wivHQl QbDkjt9W65YP3xKq4gBmOjkQRQ== X-Google-Smtp-Source: AMsMyM5oE9tRKYcIQVRx/Gbrtq5SbtR7Y78r/us6639SISCxrHNUtW+DU78PL7XVA5bXP+n85aRxTw== X-Received: by 2002:adf:e104:0:b0:236:dce2:35dc with SMTP id t4-20020adfe104000000b00236dce235dcmr7129994wrz.675.1667379706813; Wed, 02 Nov 2022 02:01:46 -0700 (PDT) Received: from prec5560.. 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[176.74.57.43]) by smtp.gmail.com with ESMTPSA id bd26-20020a05600c1f1a00b003cf6c2f9513sm1425322wmb.2.2022.11.02.02.01.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Nov 2022 02:01:46 -0700 (PDT) From: Robert Foss To: agross@kernel.org, bjorn.andersson@linaro.org, konrad.dybcio@somainline.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Bjorn Andersson , dmitry.baryshkov@linaro.org, Jonathan Marek Cc: Robert Foss Subject: [PATCH v2 1/5] clk: qcom: dispcc-sm8250: Disable EDP_GTC for sm8350 Date: Wed, 2 Nov 2022 10:01:36 +0100 Message-Id: <20221102090140.965450-2-robert.foss@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221102090140.965450-1-robert.foss@linaro.org> References: <20221102090140.965450-1-robert.foss@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org SM8350 does not have the EDP_GTC clock, so let's disable it for this SoC. Signed-off-by: Robert Foss Reviewed-by: Dmitry Baryshkov --- drivers/clk/qcom/dispcc-sm8250.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/clk/qcom/dispcc-sm8250.c b/drivers/clk/qcom/dispcc-sm8250.c index 709076f0f9d7..180ac2726f7e 100644 --- a/drivers/clk/qcom/dispcc-sm8250.c +++ b/drivers/clk/qcom/dispcc-sm8250.c @@ -1330,6 +1330,9 @@ static int disp_cc_sm8250_probe(struct platform_device *pdev) disp_cc_pll1_config.test_ctl_hi1_val = 0x01800000; disp_cc_pll1_init.ops = &clk_alpha_pll_lucid_5lpe_ops; disp_cc_pll1.vco_table = lucid_5lpe_vco; + + disp_cc_sm8250_clocks[DISP_CC_MDSS_EDP_GTC_CLK] = NULL; + disp_cc_sm8250_clocks[DISP_CC_MDSS_EDP_GTC_CLK_SRC] = NULL; } clk_lucid_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config); From patchwork Wed Nov 2 09:01:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Foss X-Patchwork-Id: 13027873 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 32D88C4332F for ; Wed, 2 Nov 2022 09:02:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229539AbiKBJCl (ORCPT ); Wed, 2 Nov 2022 05:02:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34464 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231376AbiKBJCF (ORCPT ); Wed, 2 Nov 2022 05:02:05 -0400 Received: from mail-wm1-x332.google.com (mail-wm1-x332.google.com [IPv6:2a00:1450:4864:20::332]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C765D27FF4 for ; Wed, 2 Nov 2022 02:01:49 -0700 (PDT) Received: by mail-wm1-x332.google.com with SMTP id v7so4452390wmn.0 for ; Wed, 02 Nov 2022 02:01:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=mzmAJH9YQHiTesc1z9ldOLJSqv+prtu196GqUJFfcRE=; b=ILs12tG7hkbdb+cHXkxKXea+I+frdKuFfWAEQBS/FUNC8M4BZz+TZIN6TdQWbIXBqB uWr1EoCMvueKuJXvqRVxJswPfnoUY5awGN/EBZGM27GsfzeCra3ziYie7SmsFzl5TcPG TNfy2wsop4uUUTkqXh0xvxIXs29baDgvE2Zk6csI6nq82z3Wydw9OPr2iIIRcSVQkgAG mG03T5lD2N+/SyrxE+/6lz1JjcaUvwEKgQA9BJRzd/84o27lzeNU40PCmrEfycndoEVk eb2Ev0kBptHDyknyxypIq2wShneh6WbC4nC5kF9LRzDyfmUFzEFE07MkwG2Ot5Sqh3Lu SlxQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mzmAJH9YQHiTesc1z9ldOLJSqv+prtu196GqUJFfcRE=; b=W32OAQu1Ei7wKsSXY7lT+kxKuOyC0h9LQBguIsRZy2EomSwCbqVqU7HIRs/UE0KZo+ H7JmbLKNo6wr3lA9p+zdCAa0MBQgfF/iD6biZ5et6Q1xdEI5DKSFbvZfuqK71QH1GgEv N6vH5kFdDVRMyxideHRC7shzbevBPqXaqTh7U9h/e25ebJS8P1JWn2Ip/7PFj5MCPgkP 3tE3Cm4SdvP5I6b3s1YDgOuEXTA46t1bkdB3aO+cLcjsfsM4qQuKio21lXtm1GPCrOfg peIVuME5SaZmpqLPKv/QhJIMb6eCAty/XgzCk1PDMD1JpKFMxogtjZoZVeL3e8E5vCP4 jA9A== X-Gm-Message-State: ACrzQf1BsSix5kPxN9YOIRq6K6t7i+/dhoM8x4FyawIpCbmPhfA6kpL4 VZhxniAcl1WGDl1IgURXQ2wJLQ== X-Google-Smtp-Source: AMsMyM7symkQrgKHjzoO57cPYLKB0VTs4nHaHnnnm9WbAAevST+d6XYEcpMQHfQ6g66VWM5OyjIxNA== X-Received: by 2002:a05:600c:1609:b0:3cf:4dc4:5a99 with SMTP id m9-20020a05600c160900b003cf4dc45a99mr14842484wmn.67.1667379708335; Wed, 02 Nov 2022 02:01:48 -0700 (PDT) Received: from prec5560.. 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[176.74.57.43]) by smtp.gmail.com with ESMTPSA id bd26-20020a05600c1f1a00b003cf6c2f9513sm1425322wmb.2.2022.11.02.02.01.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Nov 2022 02:01:47 -0700 (PDT) From: Robert Foss To: agross@kernel.org, bjorn.andersson@linaro.org, konrad.dybcio@somainline.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Bjorn Andersson , dmitry.baryshkov@linaro.org, Jonathan Marek Cc: Robert Foss Subject: [PATCH v2 2/5] clk: qcom: dispcc-sm8250: Add RETAIN_FF_ENABLE flag for mdss_gdsc Date: Wed, 2 Nov 2022 10:01:37 +0100 Message-Id: <20221102090140.965450-3-robert.foss@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221102090140.965450-1-robert.foss@linaro.org> References: <20221102090140.965450-1-robert.foss@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org All SoC supported by this driver supports the RETAIN_FF_ENABLE flag, so it should be enabled here. This feature enables registers to maintain their state after dis/re-enabling the GDSC. Signed-off-by: Robert Foss Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio --- drivers/clk/qcom/dispcc-sm8250.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/qcom/dispcc-sm8250.c b/drivers/clk/qcom/dispcc-sm8250.c index 180ac2726f7e..a7606580cf22 100644 --- a/drivers/clk/qcom/dispcc-sm8250.c +++ b/drivers/clk/qcom/dispcc-sm8250.c @@ -1137,7 +1137,7 @@ static struct gdsc mdss_gdsc = { .name = "mdss_gdsc", }, .pwrsts = PWRSTS_OFF_ON, - .flags = HW_CTRL, + .flags = HW_CTRL | RETAIN_FF_ENABLE, }; static struct clk_regmap *disp_cc_sm8250_clocks[] = { From patchwork Wed Nov 2 09:01:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Foss X-Patchwork-Id: 13027874 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E942EC4332F for ; Wed, 2 Nov 2022 09:02:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231343AbiKBJCy (ORCPT ); Wed, 2 Nov 2022 05:02:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34934 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230188AbiKBJCH (ORCPT ); Wed, 2 Nov 2022 05:02:07 -0400 Received: from mail-wm1-x329.google.com (mail-wm1-x329.google.com [IPv6:2a00:1450:4864:20::329]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 790DD27FD9 for ; Wed, 2 Nov 2022 02:01:51 -0700 (PDT) Received: by mail-wm1-x329.google.com with SMTP id c3-20020a1c3503000000b003bd21e3dd7aso840725wma.1 for ; Wed, 02 Nov 2022 02:01:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=QxLf9y7woLTGZWQ/1COhhq7B5uoXCRxWOXrKftkdqiQ=; b=o0jQjlRg6J1wa2XuGeOfg7m0FhkffKfSKeyrijbIT6CcU3cLCJC36MijXCtavSv/rs 2UonvwClMLIB7600BObtqyeSQIhUQadwTl2NAETYRdr1n+1Zn9B167NAEA5I/03UibPW FL9POj/23RC/cy8/Ajhxc2rQXY1dW4N1lBbtfbYXeMCZtj1kSxv1WmlmHaZd4+vDdN4h wnz+2wNCDZFyIVy6hJLqoa9rGAiE4j/7KhoyplqlUfFXqjHmdYNh346LYRoJS3ENt+lE xKwT4CgwShnxpP5DkiiZwKQD1IQQdmuMmoEyor23uLhT+17F5LARZWo4qoSuU8dvQRWv t0HQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QxLf9y7woLTGZWQ/1COhhq7B5uoXCRxWOXrKftkdqiQ=; b=fGp+5qF/WQKi8tIPp3W3uQmMHtT56HvNIYm81ZZSrg+uZsXnG9/44cqTvPgEX50mcE 88Xda5FILp5CNKvdIpPHDc3VVSjTcZCYvG0tydlJ0+JOvhmsHdmysxNIYT9zph9CO2gS Upae1t/GHanmOtJi2lwKmjQf3iuy31k1p66EqL+mT5dhwF3E8SawznqffKDrm2EhMx2G N2yY3i9UW4agLdsR8Ov+4m6/7pJBg50xthPIA/4oRjRKC57nEgxP1lDHrXf6ufSWe5sX 07QVBeFVv1J6sfZrn/HDC+6R1gHr1s423x+9eJME9exhNCqMuEouqISDLXl0RwM9g/v5 Xfqw== X-Gm-Message-State: ACrzQf3rGIhAu7ycjWROD5Qa4L6MUxDrnznikZ7jcITucvYHHrLzkrzI EjlKWNiZ24XoWAMsvQAAt/AkFQ== X-Google-Smtp-Source: AMsMyM7ayCKvyTqjAq7DvFb+MHshBo/YCnHNBlGdn3Z+Y0m0ln+f+/26P0G06KW0+1GcKvzdo+i0Gw== X-Received: by 2002:a05:600c:1987:b0:3c6:fd37:7776 with SMTP id t7-20020a05600c198700b003c6fd377776mr25389526wmq.72.1667379709992; Wed, 02 Nov 2022 02:01:49 -0700 (PDT) Received: from prec5560.. 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[176.74.57.43]) by smtp.gmail.com with ESMTPSA id bd26-20020a05600c1f1a00b003cf6c2f9513sm1425322wmb.2.2022.11.02.02.01.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Nov 2022 02:01:49 -0700 (PDT) From: Robert Foss To: agross@kernel.org, bjorn.andersson@linaro.org, konrad.dybcio@somainline.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Bjorn Andersson , dmitry.baryshkov@linaro.org, Jonathan Marek Cc: Robert Foss , Krzysztof Kozlowski Subject: [PATCH v2 3/5] dt-bindings: clock: dispcc-sm8250: Add EDP_LINK_DIV_CLK_SRC index Date: Wed, 2 Nov 2022 10:01:38 +0100 Message-Id: <20221102090140.965450-4-robert.foss@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221102090140.965450-1-robert.foss@linaro.org> References: <20221102090140.965450-1-robert.foss@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add this previously missing index, since it is supported by the SoCs targeted by the dispcc-sm8250 driver. Signed-off-by: Robert Foss Acked-by: Krzysztof Kozlowski --- include/dt-bindings/clock/qcom,dispcc-sm8250.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/clock/qcom,dispcc-sm8250.h b/include/dt-bindings/clock/qcom,dispcc-sm8250.h index ce001cbbc27f..767fdb27e514 100644 --- a/include/dt-bindings/clock/qcom,dispcc-sm8250.h +++ b/include/dt-bindings/clock/qcom,dispcc-sm8250.h @@ -64,6 +64,7 @@ #define DISP_CC_MDSS_EDP_LINK_INTF_CLK 54 #define DISP_CC_MDSS_EDP_PIXEL_CLK 55 #define DISP_CC_MDSS_EDP_PIXEL_CLK_SRC 56 +#define DISP_CC_MDSS_EDP_LINK_DIV_CLK_SRC 57 /* DISP_CC Reset */ #define DISP_CC_MDSS_CORE_BCR 0 From patchwork Wed Nov 2 09:01:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Foss X-Patchwork-Id: 13027875 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 44457C4321E for ; Wed, 2 Nov 2022 09:02:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230340AbiKBJC4 (ORCPT ); Wed, 2 Nov 2022 05:02:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34174 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231258AbiKBJCJ (ORCPT ); Wed, 2 Nov 2022 05:02:09 -0400 Received: from mail-wm1-x333.google.com (mail-wm1-x333.google.com [IPv6:2a00:1450:4864:20::333]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 63F7B286E5 for ; Wed, 2 Nov 2022 02:01:53 -0700 (PDT) Received: by mail-wm1-x333.google.com with SMTP id fn7-20020a05600c688700b003b4fb113b86so811164wmb.0 for ; Wed, 02 Nov 2022 02:01:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=pGxrVhiJog6cCrvFJyjRDALKwnKqI8styrZPsF0tpuc=; b=kjwpxsOgQwE9alprOtJ0BTkuMscZHfa0/qF8YpaFy718J9rnASNG8RqGiBb7tVuR+J +ntSZhm7Ehz6yCJm8Gog01fOFoCnqNr3LCYSpCPRkfubOlFMaOC5jqJRj6yKLbViAbDg gjoGQT1x1Ch4FSdz0aeC1X/TBV0wPW9wwMSBSIIdL365DhTWGe1oXxfy1sNjy4URkc9A r8o2L007YVyaLb6JoFrWL+AfRjjhY1bmlkmud26QsHSiJDKmhnc0HLQDeXn5oZDthqrN NoG7vg69uNQHfYoLUeiEYSZ7zOb2gF39qVUvv7xi5yq3pmbADF61zMDfG3EoNTQOYtBc tdJw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=pGxrVhiJog6cCrvFJyjRDALKwnKqI8styrZPsF0tpuc=; b=SECRSO3s47fOBRjlB3eao2ayVwNVBIs4N9e2bgy4ZuXr/dN9wqKEECfwRXTilSk2JU 9A1YU1WPPlur1nBZ+EjRqrXENsdEkUv5tnf2IndD2r0jZR3piPJmpkW7y2eZAt/rctWE OkLecs5xAydx4y/FU2fb15DWgZyTrceAMPNWiESaZSzRSbIJGnejJ8HwyJEvbRq/+GC1 IL3qbWkfnke7XB9TQjSYPzDar63EfXiEjuYUTpaTMtJl/zhBHHfqxREEMHw3FXx8m2qP 7l4PWmT1f+rJnY/R3Ytc0A1eOMQFekokAEUlRA+B9q+Eo5EwBwZUHuQuazxOSMR3RL4d TSFA== X-Gm-Message-State: ACrzQf18AY34UJM/VzUF7mGQNj8DxuPwB0VezJ3M1O9nb2AFvSUY9N5C gErpWBtnmbw9gf8uOez1zrMY2A== X-Google-Smtp-Source: AMsMyM4MC0JGcTklkwECadkBDppF5ZEhGBwjMvkfsMCRbvsYjvboD+bjpdL5KkOk74CFY7+IwmmORA== X-Received: by 2002:a05:600c:4618:b0:3cf:54ad:7bb3 with SMTP id m24-20020a05600c461800b003cf54ad7bb3mr20940293wmo.4.1667379711970; Wed, 02 Nov 2022 02:01:51 -0700 (PDT) Received: from prec5560.. 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[176.74.57.43]) by smtp.gmail.com with ESMTPSA id bd26-20020a05600c1f1a00b003cf6c2f9513sm1425322wmb.2.2022.11.02.02.01.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Nov 2022 02:01:51 -0700 (PDT) From: Robert Foss To: agross@kernel.org, bjorn.andersson@linaro.org, konrad.dybcio@somainline.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Bjorn Andersson , dmitry.baryshkov@linaro.org, Jonathan Marek Cc: Robert Foss Subject: [PATCH v2 4/5] clk: qcom: dispcc-sm8250: Add missing EDP clocks for sm8350 Date: Wed, 2 Nov 2022 10:01:39 +0100 Message-Id: <20221102090140.965450-5-robert.foss@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221102090140.965450-1-robert.foss@linaro.org> References: <20221102090140.965450-1-robert.foss@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org SM8350 supports embedded displayport, but the clocks for this were previously not accounted for. Signed-off-by: Robert Foss Reviewed-by: Dmitry Baryshkov --- drivers/clk/qcom/dispcc-sm8250.c | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/drivers/clk/qcom/dispcc-sm8250.c b/drivers/clk/qcom/dispcc-sm8250.c index a7606580cf22..d2aaa44ed3d4 100644 --- a/drivers/clk/qcom/dispcc-sm8250.c +++ b/drivers/clk/qcom/dispcc-sm8250.c @@ -462,6 +462,20 @@ static struct clk_branch disp_cc_mdss_edp_link_clk = { }, }; +static struct clk_regmap_div disp_cc_mdss_edp_link_div_clk_src = { + .reg = 0x2288, + .shift = 0, + .width = 2, + .clkr.hw.init = &(struct clk_init_data) { + .name = "disp_cc_mdss_edp_link_div_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_edp_link_clk_src.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_regmap_div_ro_ops, + }, +}; + static struct clk_branch disp_cc_mdss_edp_link_intf_clk = { .halt_reg = 0x2074, .halt_check = BRANCH_HALT, @@ -471,7 +485,7 @@ static struct clk_branch disp_cc_mdss_edp_link_intf_clk = { .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_edp_link_intf_clk", .parent_hws = (const struct clk_hw*[]){ - &disp_cc_mdss_edp_link_clk_src.clkr.hw, + &disp_cc_mdss_edp_link_div_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_GET_RATE_NOCACHE, @@ -1175,6 +1189,7 @@ static struct clk_regmap *disp_cc_sm8250_clocks[] = { [DISP_CC_MDSS_EDP_GTC_CLK_SRC] = &disp_cc_mdss_edp_gtc_clk_src.clkr, [DISP_CC_MDSS_EDP_LINK_CLK] = &disp_cc_mdss_edp_link_clk.clkr, [DISP_CC_MDSS_EDP_LINK_CLK_SRC] = &disp_cc_mdss_edp_link_clk_src.clkr, + [DISP_CC_MDSS_EDP_LINK_DIV_CLK_SRC] = &disp_cc_mdss_edp_link_div_clk_src.clkr, [DISP_CC_MDSS_EDP_LINK_INTF_CLK] = &disp_cc_mdss_edp_link_intf_clk.clkr, [DISP_CC_MDSS_EDP_PIXEL_CLK] = &disp_cc_mdss_edp_pixel_clk.clkr, [DISP_CC_MDSS_EDP_PIXEL_CLK_SRC] = &disp_cc_mdss_edp_pixel_clk_src.clkr, @@ -1285,7 +1300,11 @@ static int disp_cc_sm8250_probe(struct platform_device *pdev) &disp_cc_mdss_dp_pixel1_clk_src, &disp_cc_mdss_dp_pixel2_clk_src, &disp_cc_mdss_dp_pixel_clk_src, + &disp_cc_mdss_edp_aux_clk_src, + &disp_cc_mdss_edp_link_clk_src, + &disp_cc_mdss_edp_pixel_clk_src, &disp_cc_mdss_esc0_clk_src, + &disp_cc_mdss_esc1_clk_src, &disp_cc_mdss_mdp_clk_src, &disp_cc_mdss_pclk0_clk_src, &disp_cc_mdss_pclk1_clk_src, @@ -1297,6 +1316,7 @@ static int disp_cc_sm8250_probe(struct platform_device *pdev) &disp_cc_mdss_byte1_div_clk_src, &disp_cc_mdss_dp_link1_div_clk_src, &disp_cc_mdss_dp_link_div_clk_src, + &disp_cc_mdss_edp_link_div_clk_src, }; unsigned int i; static bool offset_applied; From patchwork Wed Nov 2 09:01:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Foss X-Patchwork-Id: 13027876 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CB2B8C4167D for ; Wed, 2 Nov 2022 09:02:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231364AbiKBJC5 (ORCPT ); Wed, 2 Nov 2022 05:02:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34150 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230304AbiKBJCN (ORCPT ); Wed, 2 Nov 2022 05:02:13 -0400 Received: from mail-wr1-x42b.google.com (mail-wr1-x42b.google.com [IPv6:2a00:1450:4864:20::42b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B8292286E8 for ; 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[176.74.57.43]) by smtp.gmail.com with ESMTPSA id bd26-20020a05600c1f1a00b003cf6c2f9513sm1425322wmb.2.2022.11.02.02.01.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Nov 2022 02:01:52 -0700 (PDT) From: Robert Foss To: agross@kernel.org, bjorn.andersson@linaro.org, konrad.dybcio@somainline.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Bjorn Andersson , dmitry.baryshkov@linaro.org, Jonathan Marek Cc: Robert Foss Subject: [PATCH v2 5/5] clk: qcom: dispcc-sm8250: Disable link_div_clk_src for sm8150 Date: Wed, 2 Nov 2022 10:01:40 +0100 Message-Id: <20221102090140.965450-6-robert.foss@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221102090140.965450-1-robert.foss@linaro.org> References: <20221102090140.965450-1-robert.foss@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org SM8150 does not have any of the link_div_clk_src clocks, so let's disable them for this SoC. Signed-off-by: Robert Foss Reviewed-by: Dmitry Baryshkov --- drivers/clk/qcom/dispcc-sm8250.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/clk/qcom/dispcc-sm8250.c b/drivers/clk/qcom/dispcc-sm8250.c index d2aaa44ed3d4..382dbd8ba250 100644 --- a/drivers/clk/qcom/dispcc-sm8250.c +++ b/drivers/clk/qcom/dispcc-sm8250.c @@ -1289,6 +1289,17 @@ static int disp_cc_sm8250_probe(struct platform_device *pdev) disp_cc_pll1_config.config_ctl_hi1_val = 0x00000024; disp_cc_pll1_config.user_ctl_hi1_val = 0x000000D0; disp_cc_pll1_init.ops = &clk_alpha_pll_trion_ops; + + disp_cc_mdss_dp_link_intf_clk.clkr.hw.init->parent_hws[0] = + &disp_cc_mdss_dp_link_clk_src.clkr.hw; + disp_cc_mdss_dp_link1_intf_clk.clkr.hw.init->parent_hws[0] = + &disp_cc_mdss_dp_link1_clk_src.clkr.hw; + disp_cc_mdss_edp_link_intf_clk.clkr.hw.init->parent_hws[0] = + &disp_cc_mdss_edp_link_clk_src.clkr.hw; + + disp_cc_sm8250_clocks[DISP_CC_MDSS_DP_LINK1_DIV_CLK_SRC] = NULL; + disp_cc_sm8250_clocks[DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC] = NULL; + disp_cc_sm8250_clocks[DISP_CC_MDSS_EDP_LINK_DIV_CLK_SRC] = NULL; } else if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8350-dispcc")) { static struct clk_rcg2 * const rcgs[] = { &disp_cc_mdss_byte0_clk_src,