From patchwork Wed Nov 2 12:46:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 13028087 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C5DD3C433FE for ; Wed, 2 Nov 2022 12:46:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=xamId2JebZ0z1sXxS/7PJcEVnAy4na52kqCjxRk7Sys=; b=jCVoYPeDwRb7Zw KsaesDb3EZYskSEpyymkVVa7DIVhtpAaXLOEF5qBLjt1K8yI5oMoFf0QK+YTudwikgMyFOHcKMjVN jnzaT5lVXJ1oo/mDYatZw7pzAuG3rzJQ9A3IkkDLmWeUrCora7nsCWeaLDVjeI1NsHQd3VFb53kFD DNMbYQ3u87h/3N+Dl5Nf4EAv1ZnHVLNzo4bBcOhjdnNn3DGn8pfsW+zsshqUc+jx1L0UijGH3hk1v EI8GCeC1cgLkbY6/z/JwZmRagzvUTwFsvaU094N5lPydC6pfcEjqc0HHECrn1CU1xQpEq8CD/w/bJ JBFV039/+xNFpcyEh97g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oqD8X-00B2rT-Dk; Wed, 02 Nov 2022 12:46:29 +0000 Received: from mail-pl1-x629.google.com ([2607:f8b0:4864:20::629]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oqD8T-00B2ou-EH for linux-rockchip@lists.infradead.org; Wed, 02 Nov 2022 12:46:27 +0000 Received: by mail-pl1-x629.google.com with SMTP id y4so16479867plb.2 for ; Wed, 02 Nov 2022 05:46:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=edgeble-ai.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=kO6+CnIeDGV1TT1m2dtttHbeeP5ee+5E/D067fCY9pY=; b=R4ymprkNzMdWNSWjsnePOPgdNqr6+axbObfeBWm1bPoRpdjHwSePgIJie3HD9Yt5gv YIKJSpthX4N1wHY0ml6jMTt6c0uzfkd2tuEbIiwQ4jxzwlsmKqB3h3njmZ0PHakYZKaz bfcf6/vAsDzWI+5kUgZ2PShznNBlPPIcwC4JGQBOqFlEpQV3oE4Gkwe6f7Zkd1pzXSIX LvAvc02wugHtm+hVLGxWY2GNBwCN78y0512idxABnuBtB0b8iMvSE+kMvYabaIBKNGBU 1R4yQXZFpm/2j0T5+t1HkfaZVFyyepdVuCc2+u3rgzvTC8Ia+7+VtWU86t4cwA5MeSAA azrw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=kO6+CnIeDGV1TT1m2dtttHbeeP5ee+5E/D067fCY9pY=; b=mlJJTLh0C60deWHEe7bDJgAhv7U4U+UCANfw1yjapshPMsdayMTofKQAU6d/BmEq1l YbahAqDbBykL7Zo1YFPfew8h7eMVer8c9vNjwZPDOX9OHxYSc0eIxnAeSeYnpsOoE9XT 94Gfb70xqDJEVY4J0EwyGT2znjaK/C92lwoIRmACnPQTD5iOFu0LWh3UE7sgBl3u7y83 nPipJm0KQOyKfaOk8i2fHcErYr12HuThv8N7Q5sEGorxoXjF2BPGRWF/hsYAUR3auR/n 4mE7bgywLehX4utYdLT0XRcPl3eAu06LQ42ElfLeWQOAIcQLbD8x4uI7WN0/gqMhddxZ fvxQ== X-Gm-Message-State: ACrzQf2pa1GP7Ui8l5Fx/1QJtUlezM7UT4sKL1IOpDzpTCIWXHjSEpmk YCUxN8TJvTV11U8usFfm8t8gpA== X-Google-Smtp-Source: AMsMyM7f5o5dkoKkL/hBc8xki/YP7nnqiLXIbcFkCsswbgmL4XwXxC3F40mRTJA4kDIaJigHz5z/rg== X-Received: by 2002:a17:902:7485:b0:17d:5176:fe6e with SMTP id h5-20020a170902748500b0017d5176fe6emr24850640pll.147.1667393181426; Wed, 02 Nov 2022 05:46:21 -0700 (PDT) Received: from localhost.localdomain ([2405:201:c00a:a809:aeff:563:9036:6729]) by smtp.gmail.com with ESMTPSA id g31-20020a63565f000000b00460fbe0d75esm7549533pgm.31.2022.11.02.05.46.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Nov 2022 05:46:21 -0700 (PDT) From: Jagan Teki To: Heiko Stuebner , Rob Herring , Krzysztof Kozlowski Cc: linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, Jagan Teki Subject: [PATCH v6 1/6] ARM: dts: rockchip: Add Rockchip RV1126 pinctrl Date: Wed, 2 Nov 2022 18:16:02 +0530 Message-Id: <20221102124607.297083-1-jagan@edgeble.ai> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221102_054625_761545_A6CDEFEE X-CRM114-Status: GOOD ( 17.92 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org Add pinctrl definitions for Rockchip RV1126. From RK3568 on-wards pinctrl configurations are maintained in common conf file rockchip-pinconf.dtsi and it is available in arm64 path (arch/arm64/boot/dts/rockchip/rockchip-pinconf.dtsi). So, include the same conf file to RV1126 pinctrl from arm64 path. Signed-off-by: Jagan Teki --- Changes for v6: - updated commit message Changes for v5: - none Changes for v4: - update i2c pins - rebase on -next Changes for v3: - none Changes for v2: - spilt pinctrl as separate patch MAINTAINERS | 2 +- arch/arm/boot/dts/rv1126-pinctrl.dtsi | 212 ++++++++++++++++++++++++++ 2 files changed, 213 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/rv1126-pinctrl.dtsi diff --git a/MAINTAINERS b/MAINTAINERS index 5f66378dcfb0..4fd0fa773209 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2750,7 +2750,7 @@ F: Documentation/devicetree/bindings/i2c/i2c-rk3x.yaml F: Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml F: Documentation/devicetree/bindings/spi/spi-rockchip.yaml F: arch/arm/boot/dts/rk3* -F: arch/arm/boot/dts/rv1108* +F: arch/arm/boot/dts/rv11* F: arch/arm/mach-rockchip/ F: drivers/*/*/*rockchip* F: drivers/*/*rockchip* diff --git a/arch/arm/boot/dts/rv1126-pinctrl.dtsi b/arch/arm/boot/dts/rv1126-pinctrl.dtsi new file mode 100644 index 000000000000..8d660d7c81ba --- /dev/null +++ b/arch/arm/boot/dts/rv1126-pinctrl.dtsi @@ -0,0 +1,212 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd + * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd. + */ + +#include +#include + +/* + * This file is auto generated by pin2dts tool, please keep these code + * by adding changes at end of this file. + */ +&pinctrl { + emmc { + /omit-if-no-ref/ + emmc_rstnout: emmc-rstnout { + rockchip,pins = + /* emmc_rstn */ + <1 RK_PA3 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + emmc_bus8: emmc-bus8 { + rockchip,pins = + /* emmc_d0 */ + <0 RK_PC4 2 &pcfg_pull_up_drv_level_2>, + /* emmc_d1 */ + <0 RK_PC5 2 &pcfg_pull_up_drv_level_2>, + /* emmc_d2 */ + <0 RK_PC6 2 &pcfg_pull_up_drv_level_2>, + /* emmc_d3 */ + <0 RK_PC7 2 &pcfg_pull_up_drv_level_2>, + /* emmc_d4 */ + <0 RK_PD0 2 &pcfg_pull_up_drv_level_2>, + /* emmc_d5 */ + <0 RK_PD1 2 &pcfg_pull_up_drv_level_2>, + /* emmc_d6 */ + <0 RK_PD2 2 &pcfg_pull_up_drv_level_2>, + /* emmc_d7 */ + <0 RK_PD3 2 &pcfg_pull_up_drv_level_2>; + }; + /omit-if-no-ref/ + emmc_clk: emmc-clk { + rockchip,pins = + /* emmc_clko */ + <0 RK_PD7 2 &pcfg_pull_up_drv_level_2>; + }; + /omit-if-no-ref/ + emmc_cmd: emmc-cmd { + rockchip,pins = + /* emmc_cmd */ + <0 RK_PD5 2 &pcfg_pull_up_drv_level_2>; + }; + }; + i2c0 { + /omit-if-no-ref/ + i2c0_xfer: i2c0-xfer { + rockchip,pins = + /* i2c0_scl */ + <0 RK_PB4 1 &pcfg_pull_none_drv_level_0_smt>, + /* i2c0_sda */ + <0 RK_PB5 1 &pcfg_pull_none_drv_level_0_smt>; + }; + }; + sdmmc0 { + /omit-if-no-ref/ + sdmmc0_bus4: sdmmc0-bus4 { + rockchip,pins = + /* sdmmc0_d0 */ + <1 RK_PA4 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc0_d1 */ + <1 RK_PA5 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc0_d2 */ + <1 RK_PA6 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc0_d3 */ + <1 RK_PA7 1 &pcfg_pull_up_drv_level_2>; + }; + /omit-if-no-ref/ + sdmmc0_clk: sdmmc0-clk { + rockchip,pins = + /* sdmmc0_clk */ + <1 RK_PB0 1 &pcfg_pull_up_drv_level_2>; + }; + /omit-if-no-ref/ + sdmmc0_cmd: sdmmc0-cmd { + rockchip,pins = + /* sdmmc0_cmd */ + <1 RK_PB1 1 &pcfg_pull_up_drv_level_2>; + }; + /omit-if-no-ref/ + sdmmc0_det: sdmmc0-det { + rockchip,pins = + <0 RK_PA3 1 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + sdmmc0_pwr: sdmmc0-pwr { + rockchip,pins = + <0 RK_PC0 1 &pcfg_pull_none>; + }; + }; + sdmmc1 { + /omit-if-no-ref/ + sdmmc1_bus4: sdmmc1-bus4 { + rockchip,pins = + /* sdmmc1_d0 */ + <1 RK_PB4 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc1_d1 */ + <1 RK_PB5 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc1_d2 */ + <1 RK_PB6 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc1_d3 */ + <1 RK_PB7 1 &pcfg_pull_up_drv_level_2>; + }; + /omit-if-no-ref/ + sdmmc1_clk: sdmmc1-clk { + rockchip,pins = + /* sdmmc1_clk */ + <1 RK_PB2 1 &pcfg_pull_up_drv_level_2>; + }; + /omit-if-no-ref/ + sdmmc1_cmd: sdmmc1-cmd { + rockchip,pins = + /* sdmmc1_cmd */ + <1 RK_PB3 1 &pcfg_pull_up_drv_level_2>; + }; + /omit-if-no-ref/ + sdmmc1_det: sdmmc1-det { + rockchip,pins = + <1 RK_PD0 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + sdmmc1_pwr: sdmmc1-pwr { + rockchip,pins = + <1 RK_PD1 2 &pcfg_pull_none>; + }; + }; + uart0 { + /omit-if-no-ref/ + uart0_xfer: uart0-xfer { + rockchip,pins = + /* uart0_rx */ + <1 RK_PC2 1 &pcfg_pull_up>, + /* uart0_tx */ + <1 RK_PC3 1 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + uart0_ctsn: uart0-ctsn { + rockchip,pins = + <1 RK_PC1 1 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart0_rtsn: uart0-rtsn { + rockchip,pins = + <1 RK_PC0 1 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart0_rtsn_gpio: uart0-rts-pin { + rockchip,pins = + <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + uart1 { + /omit-if-no-ref/ + uart1m0_xfer: uart1m0-xfer { + rockchip,pins = + /* uart1_rx_m0 */ + <0 RK_PB7 2 &pcfg_pull_up>, + /* uart1_tx_m0 */ + <0 RK_PB6 2 &pcfg_pull_up>; + }; + }; + uart2 { + /omit-if-no-ref/ + uart2m1_xfer: uart2m1-xfer { + rockchip,pins = + /* uart2_rx_m1 */ + <3 RK_PA3 1 &pcfg_pull_up>, + /* uart2_tx_m1 */ + <3 RK_PA2 1 &pcfg_pull_up>; + }; + }; + uart3 { + /omit-if-no-ref/ + uart3m0_xfer: uart3m0-xfer { + rockchip,pins = + /* uart3_rx_m0 */ + <3 RK_PC7 4 &pcfg_pull_up>, + /* uart3_tx_m0 */ + <3 RK_PC6 4 &pcfg_pull_up>; + }; + }; + uart4 { + /omit-if-no-ref/ + uart4m0_xfer: uart4m0-xfer { + rockchip,pins = + /* uart4_rx_m0 */ + <3 RK_PA5 4 &pcfg_pull_up>, + /* uart4_tx_m0 */ + <3 RK_PA4 4 &pcfg_pull_up>; + }; + }; + uart5 { + /omit-if-no-ref/ + uart5m0_xfer: uart5m0-xfer { + rockchip,pins = + /* uart5_rx_m0 */ + <3 RK_PA7 4 &pcfg_pull_up>, + /* uart5_tx_m0 */ + <3 RK_PA6 4 &pcfg_pull_up>; + }; + }; +}; From patchwork Wed Nov 2 12:46:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 13028088 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3A905C433FE for ; Wed, 2 Nov 2022 12:46:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=bgrg2jnJ8G104PwQSEBV738729zsc7u0sYNaE3U2oJ8=; b=uQPjmu1Y2vhuzL UYaxrwLBDQVbWd7osiJiUDE0XL28WyegvQM3F77uG4/Dw0GUe38/PdzVJUW0E2eAx3s63Agqxps5d w+3L3igqdM3ApONRDDaKzWKt1Sf93is44exEdpW5G9FiZ9dEFUT8Ayu8IHUdtoVPSLAVlvkJ6sw37 espbcMtymQb/n9ljn1tvVL0vHWHCCSaWM3iplzjMoKTggnViBLXuWB2VONetVparxHm38wsjtD6Ko mF/M82X2sYKgqJOCRCZrU8wqwMw3WzT1BNbLW5FsIPgjPg8c6dkUZJ6t/NyPdeLhLKhLEZ5ZEywrV MQYtoZCncOMahh6QMWjg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oqD8o-00B30N-UP; Wed, 02 Nov 2022 12:46:46 +0000 Received: from mail-pl1-x62f.google.com ([2607:f8b0:4864:20::62f]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oqD8X-00B2rN-W9 for linux-rockchip@lists.infradead.org; Wed, 02 Nov 2022 12:46:32 +0000 Received: by mail-pl1-x62f.google.com with SMTP id d24so16470312pls.4 for ; Wed, 02 Nov 2022 05:46:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=edgeble-ai.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=MODU6QQIqwHjWE5MCbmTHB7cfh8vTtswCxlSFwyg1ZU=; b=nLIDnBxICWb52I3dlL/koE3Kq+GsCh8S1urIk0eQWaHbH9hZ2YuJe/kaZ1yzTtt70+ 62FYfoFG8DbDG0XghSc8WUmNa/eEGk0ortFSoYBE3LL4gd8J6qCk42FwATyWBLOZMSEh 4v7hQx4wUjC6kEW7SLrkPBh4mLwEaS3U/wnr837jnxrYsgRYxLJFtGiHv85+t9ZzXWbl lA48HAqc9dlgbqFG2VNECarJlvrquhJ2Xw0nAPhaaAd5MZbMoDRS7veQ6zH1No1X0RoQ ow64tXMHtmBK66/PoXzaD0hOQXM5dINS53Ay9KT8mne6ZqSH6xkDqjhh9+ccytN2okYj q32g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=MODU6QQIqwHjWE5MCbmTHB7cfh8vTtswCxlSFwyg1ZU=; b=pe6eQJ6sC2ncvnOra4Yov1OttjXXbJARqMcmzIfR7YjLkPMcWkOEDjwbGSX9UksaHa HVOE/wlycDGymb+rVNSIIm//zpZf/MheT5cC5XFnRO5xUkEwuo4mHMX/mo4jqF+IpO7z Kb6Xy2jNhWKuLGtS0Z9Wpklc3u0IcIm9thnzDZX5XZP6f+e1l6DhY9VJJO8I1Goqkgt9 u+TYiTYwzaiFQs6aXuMfEpVa/MsYcF0bmoLecM55PtnY01oJ2XD6I+ndfxALA0XJj2i+ DpxlZmVtQHe3WJsvr8vbD2hS0Z4Mmjo/YVp4IHSlJrunNPMzvM6m0sywzW1xWpsUiggL vp4A== X-Gm-Message-State: ACrzQf3+UXrDRSeKRGOvBx0UHJu19JQ7QM2+zOdws7D/1egwLPpkbBeG neFaIuli9MHaZSWaoJ+LCbLmUA== X-Google-Smtp-Source: AMsMyM6VU/QuQww/A4AZR4TAK2XeRuUKbQeyWZkuARWWT6w5+oPh3ImZVtkQXuCqafMPlOpcsoLpyA== X-Received: by 2002:a17:903:110f:b0:178:ae31:ab2 with SMTP id n15-20020a170903110f00b00178ae310ab2mr24646599plh.89.1667393187712; Wed, 02 Nov 2022 05:46:27 -0700 (PDT) Received: from localhost.localdomain ([2405:201:c00a:a809:aeff:563:9036:6729]) by smtp.gmail.com with ESMTPSA id g31-20020a63565f000000b00460fbe0d75esm7549533pgm.31.2022.11.02.05.46.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Nov 2022 05:46:27 -0700 (PDT) From: Jagan Teki To: Heiko Stuebner , Rob Herring , Krzysztof Kozlowski Cc: linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, Jagan Teki , Jon Lin , Sugar Zhang Subject: [PATCH v6 2/6] ARM: dts: rockchip: Add Rockchip RV1126 SoC Date: Wed, 2 Nov 2022 18:16:03 +0530 Message-Id: <20221102124607.297083-2-jagan@edgeble.ai> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221102124607.297083-1-jagan@edgeble.ai> References: <20221102124607.297083-1-jagan@edgeble.ai> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221102_054630_067015_ADAB1064 X-CRM114-Status: GOOD ( 16.07 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org RV1126 is a high-performance vision processor SoC for IPC/CVR, especially for AI related application. It is based on quad-core ARM Cortex-A7 32-bit core which integrates NEON and FPU. There is a 32KB I-cache and 32KB D-cache for each core and 512KB unified L2 cache. It has build-in NPU supports INT8/INT16 hybrid operation and computing power is up to 2.0TOPs. This patch add basic core dtsi support. Signed-off-by: Jon Lin Signed-off-by: Sugar Zhang Signed-off-by: Jagan Teki --- Changes for v6: - add psci node Changes for v5: - none Changes for v4: - update i2c0 - rebase on -next Changes for v3: - update cru and power file names Changes for v2: - split pinctrl in separate patch arch/arm/boot/dts/rv1126.dtsi | 439 ++++++++++++++++++++++++++++++++++ 1 file changed, 439 insertions(+) create mode 100644 arch/arm/boot/dts/rv1126.dtsi diff --git a/arch/arm/boot/dts/rv1126.dtsi b/arch/arm/boot/dts/rv1126.dtsi new file mode 100644 index 000000000000..867f17ab0efd --- /dev/null +++ b/arch/arm/boot/dts/rv1126.dtsi @@ -0,0 +1,439 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd. + * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + + compatible = "rockchip,rv1126"; + + interrupt-parent = <&gic>; + + aliases { + i2c0 = &i2c0; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + serial5 = &uart5; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@f00 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf00>; + enable-method = "psci"; + clocks = <&cru ARMCLK>; + }; + + cpu1: cpu@f01 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf01>; + enable-method = "psci"; + clocks = <&cru ARMCLK>; + }; + + cpu2: cpu@f02 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf02>; + enable-method = "psci"; + clocks = <&cru ARMCLK>; + }; + + cpu3: cpu@f03 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf03>; + enable-method = "psci"; + clocks = <&cru ARMCLK>; + }; + }; + + arm-pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = , + , + , + ; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + clock-frequency = <24000000>; + }; + + xin24m: oscillator { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "xin24m"; + #clock-cells = <0>; + }; + + grf: syscon@fe000000 { + compatible = "rockchip,rv1126-grf", "syscon", "simple-mfd"; + reg = <0xfe000000 0x20000>; + }; + + pmugrf: syscon@fe020000 { + compatible = "rockchip,rv1126-pmugrf", "syscon", "simple-mfd"; + reg = <0xfe020000 0x1000>; + + pmu_io_domains: io-domains { + compatible = "rockchip,rv1126-pmu-io-voltage-domain"; + status = "disabled"; + }; + }; + + qos_emmc: qos@fe860000 { + compatible = "rockchip,rv1126-qos", "syscon"; + reg = <0xfe860000 0x20>; + }; + + qos_nandc: qos@fe860080 { + compatible = "rockchip,rv1126-qos", "syscon"; + reg = <0xfe860080 0x20>; + }; + + qos_sfc: qos@fe860200 { + compatible = "rockchip,rv1126-qos", "syscon"; + reg = <0xfe860200 0x20>; + }; + + qos_sdio: qos@fe86c000 { + compatible = "rockchip,rv1126-qos", "syscon"; + reg = <0xfe86c000 0x20>; + }; + + gic: interrupt-controller@feff0000 { + compatible = "arm,gic-400"; + interrupt-controller; + #interrupt-cells = <3>; + #address-cells = <0>; + + reg = <0xfeff1000 0x1000>, + <0xfeff2000 0x2000>, + <0xfeff4000 0x2000>, + <0xfeff6000 0x2000>; + interrupts = ; + }; + + pmu: power-management@ff3e0000 { + compatible = "rockchip,rv1126-pmu", "syscon", "simple-mfd"; + reg = <0xff3e0000 0x1000>; + + power: power-controller { + compatible = "rockchip,rv1126-power-controller"; + #power-domain-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + + power-domain@RV1126_PD_NVM { + reg = ; + clocks = <&cru HCLK_EMMC>, + <&cru CLK_EMMC>, + <&cru HCLK_NANDC>, + <&cru CLK_NANDC>, + <&cru HCLK_SFC>, + <&cru HCLK_SFCXIP>, + <&cru SCLK_SFC>; + pm_qos = <&qos_emmc>, + <&qos_nandc>, + <&qos_sfc>; + #power-domain-cells = <0>; + }; + + power-domain@RV1126_PD_SDIO { + reg = ; + clocks = <&cru HCLK_SDIO>, + <&cru CLK_SDIO>; + pm_qos = <&qos_sdio>; + #power-domain-cells = <0>; + }; + }; + }; + + i2c0: i2c@ff3f0000 { + compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c"; + reg = <0xff3f0000 0x1000>; + interrupts = ; + rockchip,grf = <&pmugrf>; + clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>; + clock-names = "i2c", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + dmac: dma-controller@ff4e0000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0xff4e0000 0x4000>; + interrupts = , + ; + #dma-cells = <1>; + arm,pl330-periph-burst; + clocks = <&cru ACLK_DMAC>; + clock-names = "apb_pclk"; + }; + + uart1: serial@ff410000 { + compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; + reg = <0xff410000 0x100>; + interrupts = ; + clock-frequency = <24000000>; + clocks = <&pmucru SCLK_UART1>, <&pmucru PCLK_UART1>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac 7>, <&dmac 6>; + pinctrl-names = "default"; + pinctrl-0 = <&uart1m0_xfer>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + pmucru: clock-controller@ff480000 { + compatible = "rockchip,rv1126-pmucru"; + reg = <0xff480000 0x1000>; + rockchip,grf = <&grf>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + cru: clock-controller@ff490000 { + compatible = "rockchip,rv1126-cru"; + reg = <0xff490000 0x1000>; + clocks = <&xin24m>; + clock-names = "xin24m"; + rockchip,grf = <&grf>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + uart0: serial@ff560000 { + compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; + reg = <0xff560000 0x100>; + interrupts = ; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac 5>, <&dmac 4>; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart2: serial@ff570000 { + compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; + reg = <0xff570000 0x100>; + interrupts = ; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac 9>, <&dmac 8>; + pinctrl-names = "default"; + pinctrl-0 = <&uart2m1_xfer>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart3: serial@ff580000 { + compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; + reg = <0xff580000 0x100>; + interrupts = ; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac 11>, <&dmac 10>; + pinctrl-names = "default"; + pinctrl-0 = <&uart3m0_xfer>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart4: serial@ff590000 { + compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; + reg = <0xff590000 0x100>; + interrupts = ; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac 13>, <&dmac 12>; + pinctrl-names = "default"; + pinctrl-0 = <&uart4m0_xfer>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart5: serial@ff5a0000 { + compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; + reg = <0xff5a0000 0x100>; + interrupts = ; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; + dmas = <&dmac 15>, <&dmac 14>; + clock-names = "baudclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart5m0_xfer>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + saradc: saradc@ff5e0000 { + compatible = "rockchip,rk3399-saradc"; + reg = <0xff5e0000 0x100>; + interrupts = ; + #io-channel-cells = <1>; + clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; + clock-names = "saradc", "apb_pclk"; + resets = <&cru SRST_SARADC_P>; + reset-names = "saradc-apb"; + status = "disabled"; + }; + + timer: timer@ff660000 { + compatible = "rockchip,rk3288-timer"; + reg = <0xff660000 0x20>; + interrupts = ; + clocks = <&cru PCLK_TIMER>, <&cru CLK_TIMER0>; + clock-names = "pclk", "timer"; + }; + + emmc: mmc@ffc50000 { + compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0xffc50000 0x4000>; + interrupts = ; + clocks = <&cru HCLK_EMMC>, <&cru CLK_EMMC>, + <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + max-frequency = <200000000>; + power-domains = <&power RV1126_PD_NVM>; + status = "disabled"; + }; + + sdmmc: mmc@ffc60000 { + compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0xffc60000 0x4000>; + interrupts = ; + clocks = <&cru HCLK_SDMMC>, <&cru CLK_SDMMC>, + <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + max-frequency = <200000000>; + status = "disabled"; + }; + + sdio: mmc@ffc70000 { + compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0xffc70000 0x4000>; + interrupts = ; + clocks = <&cru HCLK_SDIO>, <&cru CLK_SDIO>, + <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + max-frequency = <200000000>; + power-domains = <&power RV1126_PD_SDIO>; + status = "disabled"; + }; + + pinctrl: pinctrl { + compatible = "rockchip,rv1126-pinctrl"; + rockchip,grf = <&grf>; + rockchip,pmu = <&pmugrf>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gpio0: gpio0@ff460000 { + compatible = "rockchip,gpio-bank"; + reg = <0xff460000 0x100>; + interrupts = ; + clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio1@ff620000 { + compatible = "rockchip,gpio-bank"; + reg = <0xff620000 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio2@ff630000 { + compatible = "rockchip,gpio-bank"; + reg = <0xff630000 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio3@ff640000 { + compatible = "rockchip,gpio-bank"; + reg = <0xff640000 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio4@ff650000 { + compatible = "rockchip,gpio-bank"; + reg = <0xff650000 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; + +#include "rv1126-pinctrl.dtsi" From patchwork Wed Nov 2 12:46:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 13028089 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AD52CC4332F for ; Wed, 2 Nov 2022 12:46:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=BWhsLcU5OgH0YbjAWF8hTpfyhCXEgdEWcy9Uz44ANLg=; b=xgjX5Nx5kOJ4kS EVM2TPu4taKmFKt/XSbfLd1PTjta0KWJu3z0RrPrXbrCiKOQpS6TzB5zxdNID96TFtOP0TzTtJPrG GOc/IsnuhUS86kK5SoGxJKNkXH+9z0pckn/X44ZLOlGnQh/Yi0sZMhvXV/PPS5jRxcX1YcM/zIsad TWH+2bPSentwwQlT4MV+w9uwYY50hjW5K8pNRJp100jVUaw1AV8dYLYedpyL2HSAGCSxIfpVQQnfy wCP8ZiBqmx39vyUmeY6t/bVxafsiHJzzJx64o4hHisOoKtFTRQjMdTAVY0MFPC87OpVzXwApRbnB+ McvpbUXl+QGQi9q2lKvQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oqD8p-00B30x-J0; Wed, 02 Nov 2022 12:46:47 +0000 Received: from mail-pg1-x535.google.com ([2607:f8b0:4864:20::535]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oqD8i-00B2tq-1R for linux-rockchip@lists.infradead.org; Wed, 02 Nov 2022 12:46:41 +0000 Received: by mail-pg1-x535.google.com with SMTP id b62so5767163pgc.0 for ; Wed, 02 Nov 2022 05:46:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=edgeble-ai.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=hn4W0mxdUQJIGdxsbK9gur9SD5pGJjeIrIvUnQhsK84=; b=IupVzqalbZqJdIGX1SbOjqu0/LwJr5+P7EL8OAD8CScg0R0NDEv9nZ8KQrBBD+H19b crgHvfuKOgEA0j8cDVXfedfXk8rTk5vlKngfEsuR2lxtl8x2Vj54gbmmcFq9/amFvPjJ mfoBd6+7D4LlL3jzrA0rWqgu/TZrN9G+xegDFIysDkJLESh5rP2mNHprH62OMYSHD24d R0V+mFs0OlNPjh3ix3yaai+a3I9qBSGh0+5fmAc7jovFUB/JjBM4KTAnjxPF+kwmNsxs E9AuYz7+C66+sqJSGNmxyn7BoBa9GPRmaGfgRplQ9rY4u3e++yzA6donokHXouF/tQOs N7bw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hn4W0mxdUQJIGdxsbK9gur9SD5pGJjeIrIvUnQhsK84=; b=jUBeOMC+HLuMFDQHtK9ry0+RpeTvRWDLAw3xsvV+VfjfqrNtSnIT+TNth3XuN21aRi kS9RNa84W8FSXIemsJs7R2P7F1ZzkhSqXMzBywyPFU2e/03bLCWSTpBYDCF1kmbCtjtx 3mKtMhnmUC6yqKePDnf6lI+WYrBlQkxODdaVhPjXI14sCzFC8TJ2QMNN6rGuo4tO1tII ljqT4cNdE9CJpDXB+5szCiEu0Nq8Opuxqjfbbhjt/WhA+6QN2LPUhwjlSQ+ex43mNUDx HDv7zeD88kYC8n3bfmcL60sMCst7VJywe1cj4DGY1t8MqQw0CTJfzBetIHCkekkugAbO LfYw== X-Gm-Message-State: ACrzQf3eF8SK3KIlVMJkPcmXvV0r5BKFwzKbswks9RwD0rdMlVi7BTCp XmDJvZDmwrYNT1rqCw4gIC+B9w== X-Google-Smtp-Source: AMsMyM7M2bmEwza/mRoTgDbwvwShZdEoXQncRXzUgWn2KOIaCmhvl11lCbB6mz3IcHDZZcON+fOXHg== X-Received: by 2002:a05:6a00:1a0e:b0:547:1cf9:40e8 with SMTP id g14-20020a056a001a0e00b005471cf940e8mr24951716pfv.82.1667393196099; Wed, 02 Nov 2022 05:46:36 -0700 (PDT) Received: from localhost.localdomain ([2405:201:c00a:a809:aeff:563:9036:6729]) by smtp.gmail.com with ESMTPSA id g31-20020a63565f000000b00460fbe0d75esm7549533pgm.31.2022.11.02.05.46.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Nov 2022 05:46:35 -0700 (PDT) From: Jagan Teki To: Heiko Stuebner , Rob Herring , Krzysztof Kozlowski Cc: linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, Jagan Teki , Rob Herring Subject: [PATCH v6 3/6] dt-bindings: vendor-prefixes: Add Edgeble AI Technologies Pvt. Ltd. Date: Wed, 2 Nov 2022 18:16:04 +0530 Message-Id: <20221102124607.297083-3-jagan@edgeble.ai> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221102124607.297083-1-jagan@edgeble.ai> References: <20221102124607.297083-1-jagan@edgeble.ai> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221102_054640_105050_B8208645 X-CRM114-Status: UNSURE ( 9.41 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org Edgeble AI is an Artificial Intelligence company with a focus on deploying Neural Acceleration principles at the Edge. Add vendor prefix for it. Acked-by: Rob Herring Signed-off-by: Jagan Teki --- Changes for v6: - none Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 7f9ec8ef8749..6c81565af488 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -368,6 +368,8 @@ patternProperties: description: EBV Elektronik "^eckelmann,.*": description: Eckelmann AG + "^edgeble,.*": + description: Edgeble AI Technologies Pvt. Ltd. "^edimax,.*": description: EDIMAX Technology Co., Ltd "^edt,.*": From patchwork Wed Nov 2 12:46:05 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 13028090 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B9BC5C4332F for ; Wed, 2 Nov 2022 12:47:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=v4DG16bokjS5bQQNLYIFzHJ3xWxO7nVsmQt7HVuu7u0=; b=OsaOvU/ixrnRjq vubE7ofKoNdU0uMMfZsU8otInvOXLiVLfBjGe0LMlNvX2n8D2RX8oTBGi6zQAAUIDA0zg83/Hfms/ rwKswxz4cKT3cMgn3COJ4YJgdg+tiunIdku3N3T1EN5aHXmQ2cu+ILTFNJ81SL4J28fhyyTMFVXbW EYkcxqnusp9VVkzA1hYC+4QtUM+gw+EdSRYnw58ZVx4DHN4GSpIo60VkgTtyujGWH4PhgTpCU7DNg F5xVV7JW/5szrUw5+BUhdk7AjoKZAuNeVxL/fPzVxmK8w07sncKYsbjFO7VqdPFBhyIl+3nsgIRf+ AE6/Gtttua4z9SizIrEA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oqD94-00B3BD-D6; Wed, 02 Nov 2022 12:47:02 +0000 Received: from mail-pg1-x532.google.com ([2607:f8b0:4864:20::532]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oqD8l-00B2wl-EE for linux-rockchip@lists.infradead.org; Wed, 02 Nov 2022 12:46:44 +0000 Received: by mail-pg1-x532.google.com with SMTP id s196so16155689pgs.3 for ; Wed, 02 Nov 2022 05:46:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=edgeble-ai.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=C2JvjMqQ1T7iB6M7WJyLMMcTpJZI3Dgx1XMVy2FW2+s=; b=LHYEkP6/KqAkLzdExh8Dm18iD0YkeqKkY4hGgvg+S1N012xERhw+XQfymKgEInmdWH 77RtuWRZwHTgOoJuyNYli0PWio1paHvmc1mnzAqxxtKnkCLP/hwMR3BF1N+8jIfaTxU/ +0+RuGYpOkJuNpIFKWP7dpwXdaMJy+I7KDHcQPW0IQZKb4motDfFD7ZjzBKLeIvqgx8v GKktzF+yRCnjX1gNIwWYE95Juzjt/HxDMosQQ788vXGX5yWppex77DHw72DlqG0IU4cM jABHsaHdXQ/7Pz2pl8P8TKSBwlWYoYdRQBfMwHqcOOUQrp1uBzzbJZPLgFBPY8Q5vtyL F1wQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=C2JvjMqQ1T7iB6M7WJyLMMcTpJZI3Dgx1XMVy2FW2+s=; b=ti0/XvjqJFpko9W5DYeS0fgjsjtGdiCw0n7RwG2C8vlNZjZ1J5ybNO55+x5zNpp1D2 DceJFuaWaVdlL5ZClQJMPe34lCXiZHv3EvaDOcO9xhGrdA6pzfhIsmfMbUgOvVkRowhj V+LEsbVNUZepzBfK1GUaZGx4r0km7Sp8SQL/jx1TfkvwkkHMEATcq2D8qpxQLzFqkEXq frwxKScttIyMsqS0hL9ttYvA8yMXbiM7bxSG6afZlmKmXa/wAYspXiAlZHH9uZeGYYCd Akv0Q3NsWa1lKTfl16lH8sIDDPs6ONbsl9uCYaMcG6H9MbGAEgpZsPnBPTKdEl2lFl8B by9g== X-Gm-Message-State: ACrzQf2vbu0rkvTNdLf9IZV2Wt9gjAXQmUFnEidB1hNA+k24MiN+LKyb XfHEtSyJ9rT7gHZobV//CVGcqQ== X-Google-Smtp-Source: AMsMyM6RKg2jakUjZMbwj8Con6lsmVohWwDGkRZ1xaeaOOok0VVkEksIWCWbK/iKCVC783Mdux02eg== X-Received: by 2002:a63:e348:0:b0:46f:25cc:d554 with SMTP id o8-20020a63e348000000b0046f25ccd554mr22075489pgj.598.1667393200420; Wed, 02 Nov 2022 05:46:40 -0700 (PDT) Received: from localhost.localdomain ([2405:201:c00a:a809:aeff:563:9036:6729]) by smtp.gmail.com with ESMTPSA id g31-20020a63565f000000b00460fbe0d75esm7549533pgm.31.2022.11.02.05.46.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Nov 2022 05:46:40 -0700 (PDT) From: Jagan Teki To: Heiko Stuebner , Rob Herring , Krzysztof Kozlowski Cc: linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, Jagan Teki Subject: [PATCH v6 4/6] dt-bindings: arm: rockchip: Add Edgeble Neural Compute Module 2 Date: Wed, 2 Nov 2022 18:16:05 +0530 Message-Id: <20221102124607.297083-4-jagan@edgeble.ai> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221102124607.297083-1-jagan@edgeble.ai> References: <20221102124607.297083-1-jagan@edgeble.ai> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221102_054643_496748_7093EE02 X-CRM114-Status: GOOD ( 10.24 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org Neural Compute Module 2(Neu2) is a 96boards SoM-CB compute module based on Rockchip RV1126 from Edgeble AI. Edgeble Neural Compute Module 2(Neu2) IO board is an industrial form factor evaluation board from Edgeble AI. Neu2 needs to mount on top of this IO board in order to create complete Edgeble Neural Compute Module 2(Neu2) IO platform. Add dt-bindings for it. Signed-off-by: Jagan Teki Acked-by: Rob Herring --- Changes for v6: - updated SOM and Carrier name Documentation/devicetree/bindings/arm/rockchip.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index 244c42eaae8c..26fdd205a899 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -85,6 +85,12 @@ properties: - const: chipspark,rayeager-px2 - const: rockchip,rk3066a + - description: Edgeble Neural Compute Module 2(Neu2) SoM based boards + items: + - const: edgeble,neural-compute-module-2-io # Edgeble Neural Compute Module 2 IO Board + - const: edgeble,neural-compute-module-2 # Edgeble Neural Compute Module 2 SoM + - const: rockchip,rv1126 + - description: Elgin RV1108 R1 items: - const: elgin,rv1108-r1 From patchwork Wed Nov 2 12:46:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 13028092 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4D2F5C43219 for ; Wed, 2 Nov 2022 12:47:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=gOivRm4au1thtUBDtRAzGzFyhVWwlhCd7C8PlmbTeCY=; b=c7GMk5JPIh7QSC TGotxkAe+IkO5rQOV9SHlAIBheaa+3VFX0tIoFsZYZGlhFKTlIsZRP0e99L5lesHdNYsfj3yXrOzC tVNxTOgIHZfLLL/Ogo/2X/kVPdnxaGefpPK37j5cEB0Y6nPKmOqOsUnWgVDX7BhcsQqcTIEOmN1Rw HmfkJglTJyo9WDMenCqMQoGUkrYw05NytkkA0C70FfUmiXkR+jEKVmNi5Fn5RCEbcXdLuTfwc4sDz ztFbsRVj3NNCFora/R9ZX9uZaFtJhi2BcxmWkZt89NPcvu6SYQ2JA/DHdTUu5sh58n1bsC3iuzOfN 6Sd484foEU0hjU5UWZtg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oqD9h-00B3ZX-HG; Wed, 02 Nov 2022 12:47:41 +0000 Received: from mail-pl1-x633.google.com ([2607:f8b0:4864:20::633]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oqD8s-00B30p-Ht for linux-rockchip@lists.infradead.org; Wed, 02 Nov 2022 12:46:52 +0000 Received: by mail-pl1-x633.google.com with SMTP id k7so6744674pll.6 for ; Wed, 02 Nov 2022 05:46:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=edgeble-ai.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=6YskO7FhsJQtRFp62Vpf8qIa1NWpBFOPLOFenWcFItY=; b=6tTuPxB5kDfc9YfwdnJk6jGLWSyZoyRodLhYjSi90H5F1bueXWxugtVJCHMSBvddR1 Xw743QWQPNHvOOhRqwh8WQCTGAPMdWB7ekklMuv4Yv4Ak6l7VTYgbESKCSeeQPAwj8IG qKQ05g1A+4gSqV9Z7EuLNq9MCQomCBdJJLfOGEy5lOcc0Cjo4O0lsmJjtZ6AcH2UVQmH erhSEOV1VcGMxjj1kH9WElFB7IE6BNj0zsM82qZnsAVD24Uv/P4fmiQABdJ5IWM1v86Y RAy5PgbMh8kDbrYGzEHxjgP8Rp07qGVQZ+qKYqJXbwIdsV53CO04Lx/5nKmS9S/dJqcp z7IQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6YskO7FhsJQtRFp62Vpf8qIa1NWpBFOPLOFenWcFItY=; b=ysK8UVYqb+row7nzp+RFBbtzreyJ3TG25fILJaPQk7nErim3cCZ4KrR1Uvq+Cn4zN3 EkZGOARS64g3RJb1b/DaSE0A+RosBOqiHaQs2xRhF6aED0MJO1KV40zwvOVzqcfrZ25t w1o9hHmrwzdk7paISaiyWNQxIfhDK8EmVQ68s9lkvr37nu5meElKdyXqubWNpKYzi0/q ItXv8ufskTGdjSgtCPWHNQ+5HghqSCOEZVb1zDQ7q0x9U3pddn7fAxrV10qZpFkdErX3 n8PNzCLbn6tUOwN2t+HGyp63hWixpNgXEqceSqIDJ/L1oIweEvLQO8bZCQsNx9cwRdDR J46A== X-Gm-Message-State: ACrzQf1Ym3JXNXTRV/ZZQ17MIQoy3zXpaUz9u9B+i2u9LWn6zsHN4Lxo uyipSF4mEA3sj+XfUUCs8jz+Tw== X-Google-Smtp-Source: AMsMyM50XG42QgxHSPuVtcs98JQuXjyz3zmpyBGlDaIyX2dbXB3IeZHjHFQgiQD80bzWKsXGo98guQ== X-Received: by 2002:a17:90b:fc7:b0:213:d267:d490 with SMTP id gd7-20020a17090b0fc700b00213d267d490mr18675751pjb.239.1667393207079; Wed, 02 Nov 2022 05:46:47 -0700 (PDT) Received: from localhost.localdomain ([2405:201:c00a:a809:aeff:563:9036:6729]) by smtp.gmail.com with ESMTPSA id g31-20020a63565f000000b00460fbe0d75esm7549533pgm.31.2022.11.02.05.46.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Nov 2022 05:46:46 -0700 (PDT) From: Jagan Teki To: Heiko Stuebner , Rob Herring , Krzysztof Kozlowski Cc: linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, Jagan Teki Subject: [PATCH v6 5/6] ARM: dts: rockchip: rv1126: Add Edgeble Neural Compute Module 2(Neu2) Date: Wed, 2 Nov 2022 18:16:06 +0530 Message-Id: <20221102124607.297083-5-jagan@edgeble.ai> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221102124607.297083-1-jagan@edgeble.ai> References: <20221102124607.297083-1-jagan@edgeble.ai> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221102_054650_606704_3F7F4424 X-CRM114-Status: GOOD ( 15.40 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org Neural Compute Module 2(Neu2) is a 96boards SoM-CB compute module based on Rockchip RV1126 from Edgeble AI. General features: - Rockchip RV1126 - 2/4GB LPDDR4 - 8/16/32GB eMMC - 2x MIPI CSI2 FPC connector - Fn-link 8223A-SR WiFi/BT Industrial grade (-40 °C to +85 °C) version of the same class of module called Neu2k powered with Rockchip RV1126K. Neu2 needs to mount on top of Edgeble IO boards for creating complete platform solutions. Add support for it. Signed-off-by: Jagan Teki --- Changes for v6: - updated the SOM name arch/arm/boot/dts/rv1126-edgeble-neu2.dtsi | 353 +++++++++++++++++++++ 1 file changed, 353 insertions(+) create mode 100644 arch/arm/boot/dts/rv1126-edgeble-neu2.dtsi diff --git a/arch/arm/boot/dts/rv1126-edgeble-neu2.dtsi b/arch/arm/boot/dts/rv1126-edgeble-neu2.dtsi new file mode 100644 index 000000000000..6425ba5714ea --- /dev/null +++ b/arch/arm/boot/dts/rv1126-edgeble-neu2.dtsi @@ -0,0 +1,353 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd. + */ + +/ { + compatible = "edgeble,neural-compute-module-2", "rockchip,rv1126"; + + aliases { + mmc0 = &emmc; + }; + + vcc5v0_sys: vccsys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vccio_flash: vccio-flash { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&flash_vol_sel>; + regulator-name = "vccio_flash"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_3v3>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + reset-gpios = <&gpio1 RK_PD0 GPIO_ACTIVE_LOW>; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&emmc { + bus-width = <8>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 &emmc_cmd &emmc_clk &emmc_rstnout>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vccio_flash>; + rockchip,default-sample-phase = <90>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <400000>; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = ; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc_buck5>; + vcc6-supply = <&vcc_buck5>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc5v0_sys>; + + regulators { + vdd_npu_vepu: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <650000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_npu_vepu"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_arm: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_arm"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_ddr"; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc3v3_sys: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = <0x2>; + regulator-name = "vcc3v3_sys"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_buck5: DCDC_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2200000>; + regulator-max-microvolt = <2200000>; + regulator-name = "vcc_buck5"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2200000>; + }; + }; + + vcc_0v8: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-name = "vcc_0v8"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc1v8_pmu: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8_pmu"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd0v8_pmu: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-name = "vcc0v8_pmu"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <800000>; + }; + }; + + vcc_1v8: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_dovdd: LDO_REG5 { + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_dovdd"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_dvdd: LDO_REG6 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vcc_dvdd"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_avdd: LDO_REG7 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-name = "vcc_avdd"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: LDO_REG9 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_sd"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_5v0: SWITCH_REG1 { + regulator-name = "vcc_5v0"; + }; + + vcc_3v3: SWITCH_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_3v3"; + }; + }; + }; +}; + +&pinctrl { + bt { + bt_enable: bt-enable { + rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + flash { + flash_vol_sel: flash-vol-sel { + rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + wifi { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + pmuio0-supply = <&vcc1v8_pmu>; + pmuio1-supply = <&vcc3v3_sys>; + vccio1-supply = <&vccio_flash>; + vccio2-supply = <&vccio_sd>; + vccio3-supply = <&vcc_1v8>; + vccio4-supply = <&vcc_dovdd>; + vccio5-supply = <&vcc_1v8>; + vccio6-supply = <&vcc_1v8>; + vccio7-supply = <&vcc_dovdd>; + status = "okay"; +}; + +&saradc { + vref-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdio { + #address-cells = <1>; + #size-cells = <0>; + max-frequency = <100000000>; + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_clk &sdmmc1_cmd &sdmmc1_bus4>; + vmmc-supply = <&vcc3v3_sys>; + vqmmc-supply = <&vcc_1v8>; + rockchip,default-sample-phase = <90>; + sd-uhs-sdr104; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_ctsn &uart0_rtsn>; + status = "okay"; + + bluetooth { + compatible = "qcom,qca9377-bt"; + clocks = <&rk809 1>; + clock-names = "lpo"; + enable-gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>; /* BT_RST */ + max-speed = <2000000>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_enable>; + vddxo-supply = <&vcc3v3_sys>; + vddio-supply = <&vcc_1v8>; + }; +}; From patchwork Wed Nov 2 12:46:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 13028091 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0BE2CC433FE for ; Wed, 2 Nov 2022 12:47:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=1FsAFwKRfsc/qT6EBjqnJFeCFuBzM2STmjivTGodkwM=; b=w6MNUP/fRapQID VGNnJdg39IViPvMzxY7eseioynOias+jhUdqwiOs5qb3cjJ4NCVdUlxPedj/4goUjyNt9Fmc71H5Y N41m+Pgu0oI2b9bUhV2hTPj5GIMWJtYzAwCFRUK6+GckZdAvdB1qXcasY2FwuSLlfpHoR0AuufCjc fQNSC4udseGc3PCzcOQCNNjrNAXnZfFK7VpYEWvKcODSZQrePLp8EfzRXqalmJtna/AU0Ux/dhl6h HXAEciT4CUgke5GwvAb5i5nNOtQwevGvPUDbZ4cRDv5x42PtY3v0r2auf/JropHd/2+qUAkaUY+6V +Iiea2objJC5oXAM4mhA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oqD9i-00B3a2-5p; Wed, 02 Nov 2022 12:47:42 +0000 Received: from mail-pl1-x62f.google.com ([2607:f8b0:4864:20::62f]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oqD90-00B2rN-7W for linux-rockchip@lists.infradead.org; Wed, 02 Nov 2022 12:46:59 +0000 Received: by mail-pl1-x62f.google.com with SMTP id d24so16471518pls.4 for ; Wed, 02 Nov 2022 05:46:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=edgeble-ai.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=04A00wmc7ivq5c1HcZPDC2rBPvZBIFpcYtF6WjKRwqg=; b=5UyTJ6YySGqRc9UCiI+lvZh2KPPejSwVur4skyYw6Dowp5jJLy51KrGnJ2aXM9rxYz t9UzUd7NnQEWrP1O5cV6J4PPDNbqrLXXZG/FmJWrC8+ZIhbbT701B2R1j5NwWa/njRq7 kR8W7Rq+5fuE7k2Dkq1rqzwCA3ys/h6gQQzsizfudffP0LKSE6Z5UaI10w9XnB7dMlws UoWvArKtEWAvtqtyJ7pJES6r+HajCV9gHNdkUyOjDlq628PXAXos5dhppx0ODgaU35j/ 93uR7JSuCvpqf5DYThfNkNZstvwsfDyUhJnju7C17w0dnWfX/zuBvNBgkAuX+gqTXn3n HBwg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=04A00wmc7ivq5c1HcZPDC2rBPvZBIFpcYtF6WjKRwqg=; b=1FuYe6s9HjLDiap4WP4WysekUQ+l3JlrlNz12WGpnSz9Sf0whYERctWRDbhcWxsAgE vdL04bckASt03KIZnkctqUkRUJqieJDc1As34ApgtTkjJ9YptG4xA5qJ9iVoKqft7+Ml KVDJkuaLKhfnHQRwD6mb/f3akmO2FkLosJuq/I7i+TowHT8AMo18/D8Yk381Irht7T0L 5amUlX+BmqRGbaj70K/h53mmg/R7bL+OKeDOmpTcTn1eyxwwu7kCSt2i7E0TW2IjeOM5 IBlcxkwI2LsPvqDfJ9reoyscC4qM8R8+TmioCYTIHOq7opqHJ3ouu8ke1WqqFj2+tmHS 6+zw== X-Gm-Message-State: ACrzQf37jhdJNlCkHmnY89CZDV5iAALauuBjFkEgvZhQO4A2ne+XY/+D j3vdj3v/JUIPSTw9n0B2+GyNTA== X-Google-Smtp-Source: AMsMyM6+hxj1asTrKWMS4QSnSpR+achyLNm5DhZ+F4u9ixal1cweAWmCJVIEy41U3WzMm8YvX2ePFw== X-Received: by 2002:a17:90b:1b50:b0:213:c304:1d2f with SMTP id nv16-20020a17090b1b5000b00213c3041d2fmr20774685pjb.64.1667393217762; Wed, 02 Nov 2022 05:46:57 -0700 (PDT) Received: from localhost.localdomain ([2405:201:c00a:a809:aeff:563:9036:6729]) by smtp.gmail.com with ESMTPSA id g31-20020a63565f000000b00460fbe0d75esm7549533pgm.31.2022.11.02.05.46.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Nov 2022 05:46:57 -0700 (PDT) From: Jagan Teki To: Heiko Stuebner , Rob Herring , Krzysztof Kozlowski Cc: linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, Jagan Teki Subject: [PATCH v6 6/6] ARM: dts: rockchip: rv1126: Add Edgeble Neural Compute Module 2(Neu2) IO Date: Wed, 2 Nov 2022 18:16:07 +0530 Message-Id: <20221102124607.297083-6-jagan@edgeble.ai> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221102124607.297083-1-jagan@edgeble.ai> References: <20221102124607.297083-1-jagan@edgeble.ai> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221102_054658_301569_0C61C9F2 X-CRM114-Status: GOOD ( 16.10 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org Neural Compute Module 2(Neu2) IO board is an industrial form factor evaluation board from Edgeble AI. General features: - microSD slot - MIPI DSI connector - 2x USB Host - 1x USB OTG - Ethernet - mini PCIe - Onboard PoE - RS485, RS232, CAN - Micro Phone array - Speaker - RTC battery slot - 40-pin expansion Neu2 needs to mount on top of this IO board in order to create complete Edgeble Neural Compute Module 2(Neu2) IO platform. Add support for it. Signed-off-by: Jagan Teki --- Changes for v6: - update the carrier name. arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/rv1126-edgeble-neu2-io.dts | 38 ++++++++++++++++++++ 2 files changed, 39 insertions(+) create mode 100644 arch/arm/boot/dts/rv1126-edgeble-neu2-io.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index e48cfbc4e8e4..40cc34bd4945 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1122,6 +1122,7 @@ dtb-$(CONFIG_ARCH_RENESAS) += \ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rv1108-elgin-r1.dtb \ rv1108-evb.dtb \ + rv1126-edgeble-neu2-io.dtb \ rk3036-evb.dtb \ rk3036-kylin.dtb \ rk3066a-bqcurie2.dtb \ diff --git a/arch/arm/boot/dts/rv1126-edgeble-neu2-io.dts b/arch/arm/boot/dts/rv1126-edgeble-neu2-io.dts new file mode 100644 index 000000000000..ae1cf344239b --- /dev/null +++ b/arch/arm/boot/dts/rv1126-edgeble-neu2-io.dts @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd. + */ + +/dts-v1/; +#include "rv1126.dtsi" +#include "rv1126-edgeble-neu2.dtsi" + +/ { + model = "Edgeble Neu2 IO Board"; + compatible = "edgeble,neural-compute-module-2-io", + "edgeble,neural-compute-module-2", "rockchip,rv1126"; + + chosen { + stdout-path = "serial2:1500000n8"; + }; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + card-detect-delay = <200>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_bus4 &sdmmc0_det>; + rockchip,default-sample-phase = <90>; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr104; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +};