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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Nov 2022 04:39:10.1617 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: dafdc173-8727-4487-e8e3-08dabd5559c8 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT019.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4068 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org In order to fully make use of the !IOMMU_API stub functions, make the struct iommu_fwspec always available so that users of the stubs can keep using the structure's internals without causing compile failures. Signed-off-by: Thierry Reding Reviewed-by: Ulf Hansson --- include/linux/iommu.h | 39 +++++++++++++++++++-------------------- 1 file changed, 19 insertions(+), 20 deletions(-) diff --git a/include/linux/iommu.h b/include/linux/iommu.h index ea30f00dc145..afa829bc4356 100644 --- a/include/linux/iommu.h +++ b/include/linux/iommu.h @@ -173,6 +173,25 @@ enum iommu_dev_features { #define IOMMU_PASID_INVALID (-1U) +/** + * struct iommu_fwspec - per-device IOMMU instance data + * @ops: ops for this device's IOMMU + * @iommu_fwnode: firmware handle for this device's IOMMU + * @flags: IOMMU_FWSPEC_* flags + * @num_ids: number of associated device IDs + * @ids: IDs which this device may present to the IOMMU + */ +struct iommu_fwspec { + const struct iommu_ops *ops; + struct fwnode_handle *iommu_fwnode; + u32 flags; + unsigned int num_ids; + u32 ids[]; +}; + +/* ATS is supported */ +#define IOMMU_FWSPEC_PCI_RC_ATS (1 << 0) + #ifdef CONFIG_IOMMU_API /** @@ -600,25 +619,6 @@ extern struct iommu_group *generic_device_group(struct device *dev); /* FSL-MC device grouping function */ struct iommu_group *fsl_mc_device_group(struct device *dev); -/** - * struct iommu_fwspec - per-device IOMMU instance data - * @ops: ops for this device's IOMMU - * @iommu_fwnode: firmware handle for this device's IOMMU - * @flags: IOMMU_FWSPEC_* flags - * @num_ids: number of associated device IDs - * @ids: IDs which this device may present to the IOMMU - */ -struct iommu_fwspec { - const struct iommu_ops *ops; - struct fwnode_handle *iommu_fwnode; - u32 flags; - unsigned int num_ids; - u32 ids[]; -}; - -/* ATS is supported */ -#define IOMMU_FWSPEC_PCI_RC_ATS (1 << 0) - /** * struct iommu_sva - handle to a device-mm bond */ @@ -682,7 +682,6 @@ bool iommu_group_dma_owner_claimed(struct iommu_group *group); struct iommu_ops {}; struct iommu_group {}; -struct iommu_fwspec {}; struct iommu_device {}; struct iommu_fault_param {}; struct iommu_iotlb_gather {}; From patchwork Thu Nov 3 04:38:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Prathamesh Shete X-Patchwork-Id: 13029525 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5FF2DC4332F for ; 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Wed, 2 Nov 2022 21:39:00 -0700 From: Prathamesh Shete To: , , , , , , , , CC: , , , , , , Subject: [PATCH v10 2/4] mmc: sdhci-tegra: Separate Tegra194 and Tegra234 SoC data Date: Thu, 3 Nov 2022 10:08:50 +0530 Message-ID: <20221103043852.24718-2-pshete@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221103043852.24718-1-pshete@nvidia.com> References: <20221103043852.24718-1-pshete@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT063:EE_|SN7PR12MB6766:EE_ X-MS-Office365-Filtering-Correlation-Id: 9bb1e026-b703-4ce8-c8db-08dabd555b54 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: kYmjK55TxOWCgPnhIP4XVjquE2W8FLuSzcGccxngxMtnUg6V9oVjvzhbkXKon+C1yq2btOxpsJNeHK5tQUT5ac7B2XnYCgSsnEtX4J8OibtGQNjZrC3uLgLcOIrdKZGpTqIJcvXrare+RY4xfdNOz1lJ3FPLY/SilXsFqQXGI/5Ac7AfClL0ad0d/eFNBvi5vOZmGVU0yG3KEiS3UKq1dYNRZfOEE82kQGRYGXd8EU/Jx5Nexi6ZNlVJkSjlp6GXuUL6pNkfSHe6V+kwYAP6ziolm0ANF/Wg4Y9fRlr1IgxmTGgAACo4XJrRyEIoYgy1mma3USz/w443cWutZEA8EJlm2p8O8nf2STjD7qFPqxgqN5tM8b6zHVezXvN/rsxscS+kB9sp31auccau+UwWO7V5j6YNuXyRPujGsAOLiaF/O8O/q5mGuf7bYbZda1fycLapIsDt3E5MyzhSwjbVtqlqPDAHVL7/Cr8Jc4kaTslNFZU1edrjyF4uMySoKBlpIHMWZNT8m8EhgBuOs1EEsSkjWTp1RNzTBwkNNJ3OB/PakLRtAd/9J2Da+ZXcfNGYDK4b+/v5gme4jxqxIbHrksi2zJ8K55mFf4FAyOTxjl4DX1FbjqZUdDa6GgXuynphSALa7voEG5Bqp/rcPGqLAV6iksrp6mTQDN0UqQT2ailvA9grLwo4sG52qVXaA7LcLqGEMQTq29cGfCpheSji6o2RXdoTQmH+oDnBYBNMqzy33aSr1Q4Ex7f+W1vC0PnlN80i3ePtxY496lFxGb2Ytg== X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230022)(4636009)(136003)(376002)(396003)(346002)(39860400002)(451199015)(40470700004)(36840700001)(46966006)(47076005)(316002)(2616005)(83380400001)(426003)(186003)(336012)(1076003)(86362001)(8676002)(40480700001)(4326008)(36756003)(82310400005)(356005)(82740400003)(36860700001)(70206006)(7636003)(26005)(8936002)(2906002)(40460700003)(107886003)(6666004)(110136005)(5660300002)(41300700001)(54906003)(7696005)(70586007)(478600001)(7416002);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Nov 2022 04:39:12.6468 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9bb1e026-b703-4ce8-c8db-08dabd555b54 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT063.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB6766 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Create new SoC data structure for Tegra234 platforms. Additional features, tap value configurations are added/ updated for Tegra234 platform hence separate Tegra194 and Tegra234 SoC data. Signed-off-by: Aniruddha Tvs Rao Signed-off-by: Prathamesh Shete Acked-by: Adrian Hunter Acked-by: Thierry Reding --- drivers/mmc/host/sdhci-tegra.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c index 2d2d8260c681..a6c5bbae77b4 100644 --- a/drivers/mmc/host/sdhci-tegra.c +++ b/drivers/mmc/host/sdhci-tegra.c @@ -1556,7 +1556,21 @@ static const struct sdhci_tegra_soc_data soc_data_tegra194 = { .max_tap_delay = 139, }; +static const struct sdhci_tegra_soc_data soc_data_tegra234 = { + .pdata = &sdhci_tegra186_pdata, + .dma_mask = DMA_BIT_MASK(39), + .nvquirks = NVQUIRK_NEEDS_PAD_CONTROL | + NVQUIRK_HAS_PADCALIB | + NVQUIRK_DIS_CARD_CLK_CONFIG_TAP | + NVQUIRK_ENABLE_SDR50 | + NVQUIRK_ENABLE_SDR104 | + NVQUIRK_HAS_TMCLK, + .min_tap_delay = 95, + .max_tap_delay = 111, +}; + static const struct of_device_id sdhci_tegra_dt_match[] = { + { .compatible = "nvidia,tegra234-sdhci", .data = &soc_data_tegra234 }, { .compatible = "nvidia,tegra194-sdhci", .data = &soc_data_tegra194 }, { .compatible = "nvidia,tegra186-sdhci", .data = &soc_data_tegra186 }, { .compatible = "nvidia,tegra210-sdhci", .data = &soc_data_tegra210 }, From patchwork Thu Nov 3 04:38:51 2022 Content-Type: text/plain; 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Wed, 2 Nov 2022 21:39:13 -0700 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail203.nvidia.com (10.126.190.182) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Wed, 2 Nov 2022 21:39:13 -0700 Received: from pshete-ubuntu.nvidia.com (10.127.8.14) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.986.29 via Frontend Transport; Wed, 2 Nov 2022 21:39:08 -0700 From: Prathamesh Shete To: , , , , , , , , CC: , , , , , , Subject: [PATCH v10 3/4] mmc: sdhci-tegra: Add support to program MC stream ID Date: Thu, 3 Nov 2022 10:08:51 +0530 Message-ID: <20221103043852.24718-3-pshete@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221103043852.24718-1-pshete@nvidia.com> References: <20221103043852.24718-1-pshete@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT032:EE_|PH7PR12MB5733:EE_ X-MS-Office365-Filtering-Correlation-Id: 22699bfd-5f53-406d-4c09-08dabd5561f2 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Nov 2022 04:39:23.8548 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 22699bfd-5f53-406d-4c09-08dabd5561f2 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT032.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB5733 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org SMMU clients are supposed to program stream ID from their respective address spaces instead of MC override. Define NVQUIRK_PROGRAM_STREAMID and use it to program SMMU stream ID from the SDMMC client address space. Signed-off-by: Aniruddha TVS Rao Signed-off-by: Prathamesh Shete Acked-by: Adrian Hunter Acked-by: Thierry Reding --- drivers/mmc/host/sdhci-tegra.c | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c index a6c5bbae77b4..e44060cceb68 100644 --- a/drivers/mmc/host/sdhci-tegra.c +++ b/drivers/mmc/host/sdhci-tegra.c @@ -25,6 +25,8 @@ #include #include #include +#include +#include #include @@ -94,6 +96,8 @@ #define SDHCI_TEGRA_AUTO_CAL_STATUS 0x1ec #define SDHCI_TEGRA_AUTO_CAL_ACTIVE BIT(31) +#define SDHCI_TEGRA_CIF2AXI_CTRL_0 0x1fc + #define NVQUIRK_FORCE_SDHCI_SPEC_200 BIT(0) #define NVQUIRK_ENABLE_BLOCK_GAP_DET BIT(1) #define NVQUIRK_ENABLE_SDHCI_SPEC_300 BIT(2) @@ -121,6 +125,7 @@ #define NVQUIRK_HAS_TMCLK BIT(10) #define NVQUIRK_HAS_ANDROID_GPT_SECTOR BIT(11) +#define NVQUIRK_PROGRAM_STREAMID BIT(12) /* SDMMC CQE Base Address for Tegra Host Ver 4.1 and Higher */ #define SDHCI_TEGRA_CQE_BASE_ADDR 0xF000 @@ -177,6 +182,7 @@ struct sdhci_tegra { bool enable_hwcq; unsigned long curr_clk_rate; u8 tuned_tap_delay; + u32 streamid; }; static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg) @@ -1564,6 +1570,7 @@ static const struct sdhci_tegra_soc_data soc_data_tegra234 = { NVQUIRK_DIS_CARD_CLK_CONFIG_TAP | NVQUIRK_ENABLE_SDR50 | NVQUIRK_ENABLE_SDR104 | + NVQUIRK_PROGRAM_STREAMID | NVQUIRK_HAS_TMCLK, .min_tap_delay = 95, .max_tap_delay = 111, @@ -1630,6 +1637,29 @@ static int sdhci_tegra_add_host(struct sdhci_host *host) return ret; } +/* Program MC streamID for DMA transfers */ +static void program_stream_id(struct device *dev) +{ + struct sdhci_host *host = dev_get_drvdata(dev); + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); + struct iommu_fwspec *fwspec; + + if (tegra_host->soc_data->nvquirks & NVQUIRK_PROGRAM_STREAMID) { + fwspec = dev_iommu_fwspec_get(dev); + if (!fwspec) { + dev_warn(mmc_dev(host->mmc), + "iommu fwspec is NULL, continue without stream ID\n"); + } else { + tegra_host->streamid = fwspec->ids[0] & 0xff; + tegra_sdhci_writel(host, tegra_host->streamid | + FIELD_PREP(GENMASK(15, 8), + tegra_host->streamid), + SDHCI_TEGRA_CIF2AXI_CTRL_0); + } + } +} + static int sdhci_tegra_probe(struct platform_device *pdev) { const struct sdhci_tegra_soc_data *soc_data; @@ -1775,6 +1805,8 @@ static int sdhci_tegra_probe(struct platform_device *pdev) if (rc) goto err_add_host; + program_stream_id(&pdev->dev); + return 0; err_add_host: @@ -1871,6 +1903,8 @@ static int sdhci_tegra_resume(struct device *dev) if (ret) return ret; + program_stream_id(dev); + ret = sdhci_resume_host(host); if (ret) goto disable_clk; From patchwork Thu Nov 3 04:38:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Prathamesh Shete X-Patchwork-Id: 13029527 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AEB3AC4332F for ; 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Wed, 2 Nov 2022 21:39:14 -0700 From: Prathamesh Shete To: , , , , , , , , CC: , , , , , , Subject: [PATCH v10 4/4] mmc: sdhci-tegra: Issue CMD and DAT resets together Date: Thu, 3 Nov 2022 10:08:52 +0530 Message-ID: <20221103043852.24718-4-pshete@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221103043852.24718-1-pshete@nvidia.com> References: <20221103043852.24718-1-pshete@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT057:EE_|BL1PR12MB5970:EE_ X-MS-Office365-Filtering-Correlation-Id: 145f2f1d-eb54-46f6-7234-08dabd5569a4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: L0JnOLDUlALpyaJKgaBReVaQ1VHMFEy5WvspdC+OUVKkD6xU3RfgFT7fs6rCSbIRvl0ZcVZyVnoMnF7UI3tZEoLzKbcDDxlhDA7ZMxh73Plsg50jfuZ+6v4x0Y4mLeJzUZug4fk2EDtGQI0yTCbS70vDRVv/nB3FOUb2o3xFYcVOO10klmen0CMnOZAfr3/6NPrZP3Eu4awZxscXHd8/BU5sAPoCHvqrraPe9tArVIFer/rKMAWhaVxRN+taeMTybSlkH92xtnnHKy1fhY7e6fsP1bg+vJXRyygoAnXTLEMDcgKKYF1JMEXAKkB/nUVwlF+zyYHBP/JhkVOOe2t2bxm8e0noD4sKnvV8pW0X0qjqKzJlP+iCXz5B766r37kFl4W9CtE0w3FZuBWako5yLtI+Pr1ixiIb1gE5CL60mN4D6vq1rVrQ89jRARuajAkO/f/OgRy0uaW2pv0A0xEbsZlOaJTu38rYYEU1LWiyT3epDO9sjfqYXGaBkE4vkkBMB0iSh/d4VyX2Yd+zBA/msH5lflqcwlFoJs+qsQ1hSq9erW9hfzssu5SP+iC7YB8EAa4EcpsyEK5FvysbF3ZKoWkJn3alDTgoS93yekzafA/TKDDIE50YGOv92GTu5A8QD6kVrj9GtSgn/dYlCGyrPztMWHez0OLeLaBWmYTJQLH6avW/zZQ6g6r8DDP3zDlnvYcpflUR+D+bQBBlcN3YP7cJiaPPfo6T7FGYGiIUdS32VoaM2ac/dLrN9gGjlE/qcDqJDFVFKQmYCoblRjUPkQ== X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230022)(4636009)(376002)(346002)(136003)(396003)(39860400002)(451199015)(40470700004)(36840700001)(46966006)(26005)(186003)(86362001)(4326008)(70206006)(316002)(8676002)(82310400005)(8936002)(70586007)(478600001)(41300700001)(110136005)(54906003)(40480700001)(7636003)(356005)(6666004)(36860700001)(82740400003)(7696005)(83380400001)(40460700003)(107886003)(2616005)(426003)(47076005)(336012)(2906002)(1076003)(36756003)(5660300002)(7416002);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Nov 2022 04:39:36.6726 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 145f2f1d-eb54-46f6-7234-08dabd5569a4 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT057.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5970 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org In case of error condition to avoid system crash Tegra SDMMC controller requires CMD and DAT resets issued together. SDHCI controller FSM goes into bad state due to rapid SD card hot-plug event. Issuing reset on the CMD FSM before DATA FSM results in kernel panic, hence add support to issue CMD and DAT resets together. This is applicable to Tegra186 and later chips. Signed-off-by: Aniruddha TVS Rao Signed-off-by: Prathamesh Shete Acked-by: Adrian Hunter Acked-by: Thierry Reding --- drivers/mmc/host/sdhci-tegra.c | 3 ++- drivers/mmc/host/sdhci.c | 5 +++++ drivers/mmc/host/sdhci.h | 2 ++ 3 files changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c index e44060cceb68..7cb3bf34a176 100644 --- a/drivers/mmc/host/sdhci-tegra.c +++ b/drivers/mmc/host/sdhci-tegra.c @@ -1531,7 +1531,8 @@ static const struct sdhci_pltfm_data sdhci_tegra186_pdata = { SDHCI_QUIRK_NO_HISPD_BIT | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, - .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, + .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | + SDHCI_QUIRK2_ISSUE_CMD_DAT_RESET_TOGETHER, .ops = &tegra186_sdhci_ops, }; diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 2b5dda521b0e..8512a69f1aae 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -270,6 +270,11 @@ enum sdhci_reset_reason { static void sdhci_reset_for_reason(struct sdhci_host *host, enum sdhci_reset_reason reason) { + if (host->quirks2 & + SDHCI_QUIRK2_ISSUE_CMD_DAT_RESET_TOGETHER) { + sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); + return; + } switch (reason) { case SDHCI_RESET_FOR_INIT: sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index d750c464bd1e..6a5766774b05 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -478,6 +478,8 @@ struct sdhci_host { * block count. */ #define SDHCI_QUIRK2_USE_32BIT_BLK_CNT (1<<18) +/* Issue CMD and DATA reset together */ +#define SDHCI_QUIRK2_ISSUE_CMD_DAT_RESET_TOGETHER (1<<19) int irq; /* Device IRQ */ void __iomem *ioaddr; /* Mapped address */