From patchwork Fri Nov 4 11:35:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13031657 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D9363C43219 for ; Fri, 4 Nov 2022 11:36:24 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oquyr-0001A8-Iv; Fri, 04 Nov 2022 07:35:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oquyp-00018q-PO for qemu-devel@nongnu.org; Fri, 04 Nov 2022 07:35:23 -0400 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oquym-00084y-Vy for qemu-devel@nongnu.org; Fri, 04 Nov 2022 07:35:23 -0400 Received: by mail-wm1-x336.google.com with SMTP id o30so2862781wms.2 for ; Fri, 04 Nov 2022 04:35:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=nHWSJ+DS7zWi4CyAI29TJeB0bJ7NNMFTP3CfxToiYuk=; b=jDlzL+hr4/8FeN+SSwQdFCjCO/yzF9FDEwRxWBVrGnsNA8l70VtCjHwJH5WWlL3gFn A/PIVllWV+CYAza9um2JHZJCPeXnw/eH/UuaynhjDEV7xnC/GG8x+77c89yEBWkNoplO QejDHSHnH47ZvkZUj8fRcbPZDJbotu+bSSYbbMLUQPiCL3CMiUwIEuoTJCwGurAKGGgw AC7PpJpGJ0DLDh4qseZWvo29umuhT1hLbkRubAHvrW4w27LkGqNr1ZiUaix8UbfTqmDB d+aCpaPdsPfO96e4fJjdthnVcsWehuH0laNZDo3QzqZJVVo6LTjwVxml5mBPTqsC9Jno P1ng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=nHWSJ+DS7zWi4CyAI29TJeB0bJ7NNMFTP3CfxToiYuk=; b=Hl0TPUg0W0PYJqFekA04x6RlyJ2l19ZAghnQdbGeGe8M6ugJwpcF7RgrOLZjcwdGfM AyoCOaV9QVWEJQeX7phnBzsbOdSXbs/sjJTJOgdkcJ5OGc1oKRRCiy/tukJMIgzEwJze Q3LmUSuknKICqhhU47G8sBwEh28uvPTW+4BKe+MH6PNQB8qNXSuhWKmJeAvlUmgddaoh 3kE+yKsAML43hcj5vI3d6LfjnaN5IRI5CI2NSuXks17ViL7WKc9XKtJuFvHFTEfoIhPh ttoal7xeTe4deE7iIGOWJvYrIa2uP7gh8yzqY2c+z1luWLUOKjbGHCwrLZrqfVt4OKzm j7qQ== X-Gm-Message-State: ACrzQf3Yx/rFK1frXt5Ns4lnXRw+6I5U3NetpCKpPDoieudYvtm43EXn QfgxAw1Ms2DevVAPVrzucfybIPbKN23c4w== X-Google-Smtp-Source: AMsMyM50U9ulJBcuL2KW7WkksjBoQDh+CfrSHeHYoFuPHbkRXzKOHREj4XxONeb+mfBSiiQYH7BP4g== X-Received: by 2002:a05:600c:18a3:b0:3cf:8df1:ce6e with SMTP id x35-20020a05600c18a300b003cf8df1ce6emr5735723wmp.5.1667561719384; Fri, 04 Nov 2022 04:35:19 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id g17-20020a5d4891000000b0023655e51c33sm3255743wrq.4.2022.11.04.04.35.18 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Nov 2022 04:35:18 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 1/7] hw/arm/boot: Set SME and SVE EL3 vector lengths when booting kernel Date: Fri, 4 Nov 2022 11:35:09 +0000 Message-Id: <20221104113515.2278508-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221104113515.2278508-1-peter.maydell@linaro.org> References: <20221104113515.2278508-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org When we direct boot a kernel on a CPU which emulates EL3, we need to set up the EL3 system registers as the Linux kernel documentation specifies: https://www.kernel.org/doc/Documentation/arm64/booting.rst For SVE and SME this includes: - ZCR_EL3.LEN must be initialised to the same value for all CPUs the kernel is executed on. - SMCR_EL3.LEN must be initialised to the same value for all CPUs the kernel will execute on. Although we are technically compliant with this, the "same value" we currently use by default is the reset value of 0. This will end up forcing the guest kernel's SVE and SME vector length to be only the smallest supported length. Initialize the vector length fields to their maximum possible value, which is 0xf. If the implementation doesn't actually support that vector length then the effective vector length will be constrained down to the maximum supported value at point of use. This allows the guest to use all the vector lengths the emulated CPU supports (by programming the _EL2 and _EL1 versions of these registers.) Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20221027140207.413084-2-peter.maydell@linaro.org --- hw/arm/boot.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/arm/boot.c b/hw/arm/boot.c index b106f314685..17d38260faf 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -764,10 +764,12 @@ static void do_cpu_reset(void *opaque) } if (cpu_isar_feature(aa64_sve, cpu)) { env->cp15.cptr_el[3] |= R_CPTR_EL3_EZ_MASK; + env->vfp.zcr_el[3] = 0xf; } if (cpu_isar_feature(aa64_sme, cpu)) { env->cp15.cptr_el[3] |= R_CPTR_EL3_ESM_MASK; env->cp15.scr_el3 |= SCR_ENTP2; + env->vfp.smcr_el[3] = 0xf; } /* AArch64 kernels never boot in secure mode */ assert(!info->secure_boot); From patchwork Fri Nov 4 11:35:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13031662 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E5A41C433FE for ; Fri, 4 Nov 2022 11:37:18 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oquys-0001BN-8t; Fri, 04 Nov 2022 07:35:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oquyq-00019j-QN for qemu-devel@nongnu.org; Fri, 04 Nov 2022 07:35:24 -0400 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oquyn-000853-V6 for qemu-devel@nongnu.org; Fri, 04 Nov 2022 07:35:24 -0400 Received: by mail-wm1-x32a.google.com with SMTP id v124-20020a1cac82000000b003cf7a4ea2caso5219255wme.5 for ; Fri, 04 Nov 2022 04:35:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=ZILEcs7gVrun3BhktEfyfWSQRQlvBxIa2XjRbb6boco=; b=iD3fAoPTGLh3TphSZZzBhNHW3zz8BkXFBr6bVIHYeERsPs8gyJ59y4vZHcWsYlDGml LMidq15o7khNMGznCtKGQnW8jPSntoiJx02Wk/m82G9bF0doKmXIPvmhoKjfyNY34k/9 FpQ9r8vAw7+kIfvqWL6QZUr0Xku90GDwtuONEjRAssYXiAPjd41eFZJ8EU8y3psDrDA8 YYUT3FKE9XZ8ziqHZwFHwZRY5uee5Pe4EP8EgJfXJ5ide9+85KVn/oQ+ao/wdXsbl7B5 AumouZBD467AlkQNv986/LOvbVcZorhy9NtS+9SkVsv64qPa7W3vy7Imyn57/rZEvRcL 3z/w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ZILEcs7gVrun3BhktEfyfWSQRQlvBxIa2XjRbb6boco=; b=U3QgwwoXTFSYIpfHxJbbjzyWdjKNTEJhUQqrmX6M+4yeZGUYlUQWgqyilDsZWWSCXy /MRLL2azXR/067Uczx+8Vq7kUS8dbGGubIwlBJ/4ESgNy/tqvMrfEy3I4qD8GVNayvb+ SqyOgtvw6ww9rB9g3WDKrcQsYJm7o/IDZNMRgz7tdUEulWZ8oExA1KR95VipWbdJpDYo 9pzFs/6b0CXORwtk/cHWKuRF1TRDedZvgTARArwPz3RGVxWpbJzmcgFe0NVeMvtUNVPX Qo9teKPJaMqsK0GfN6EJrEhXuW446q78T52qo3DuOMxu0knnVVqXCBcqVcfixIo6hsGg ENoQ== X-Gm-Message-State: ACrzQf2t0CrwJYJZWSnmR/jDpRm71qHRms08/nsEuaartbIySVqobrfo gH7XDQXqQqqotwSBqMcmNEN2jK1859gUeQ== X-Google-Smtp-Source: AMsMyM7vqoDJpZ/+Wre1f95hb81WMxMSy1g4lY2OaYJYGtfjsA0mGtnNNYpgHLexHnehXqliTVsw3w== X-Received: by 2002:a05:600c:1ca1:b0:3cf:7aa1:c682 with SMTP id k33-20020a05600c1ca100b003cf7aa1c682mr15565474wms.135.1667561720352; Fri, 04 Nov 2022 04:35:20 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id g17-20020a5d4891000000b0023655e51c33sm3255743wrq.4.2022.11.04.04.35.19 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Nov 2022 04:35:19 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 2/7] hw/arm/boot: Set SCR_EL3.HXEn when booting kernel Date: Fri, 4 Nov 2022 11:35:10 +0000 Message-Id: <20221104113515.2278508-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221104113515.2278508-1-peter.maydell@linaro.org> References: <20221104113515.2278508-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org When we direct boot a kernel on a CPU which emulates EL3, we need to set up the EL3 system registers as the Linux kernel documentation specifies: https://www.kernel.org/doc/Documentation/arm64/booting.rst For CPUs with FEAT_HCX support this includes: - SCR_EL3.HXEn (bit 38) must be initialised to 0b1. but we forgot to do this when implementing FEAT_HCX, which would mean that a guest trying to access the HCRX_EL2 register would crash. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20221027140207.413084-3-peter.maydell@linaro.org --- hw/arm/boot.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/hw/arm/boot.c b/hw/arm/boot.c index 17d38260faf..15c2bf1867f 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -771,6 +771,9 @@ static void do_cpu_reset(void *opaque) env->cp15.scr_el3 |= SCR_ENTP2; env->vfp.smcr_el[3] = 0xf; } + if (cpu_isar_feature(aa64_hcx, cpu)) { + env->cp15.scr_el3 |= SCR_HXEN; + } /* AArch64 kernels never boot in secure mode */ assert(!info->secure_boot); /* This hook is only supported for AArch32 currently: From patchwork Fri Nov 4 11:35:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13031656 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8AD2EC43217 for ; Fri, 4 Nov 2022 11:36:24 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oquyt-0001Bz-Vo; Fri, 04 Nov 2022 07:35:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oquyr-0001Af-NC for qemu-devel@nongnu.org; Fri, 04 Nov 2022 07:35:25 -0400 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oquyp-000858-Tf for qemu-devel@nongnu.org; Fri, 04 Nov 2022 07:35:25 -0400 Received: by mail-wr1-x42d.google.com with SMTP id v1so6629999wrt.11 for ; Fri, 04 Nov 2022 04:35:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=rEqx4pUAyvcNCFw109Z//pIeNENb6Z5peeqvuKyFDlg=; b=GO4S1Crt0+leZ3f2QF5c7B6Mtn03OXb9a3Rd89djx/6cdOk08SrGN0immgDh+FqoTD QIB11iDi8MRJdvw4zyoVO5Vfpd8MtI9BeE0ddKl/IR3aVjz14VyJlNmPP4fizCZSJkcf imXM59/IO/Gdk7WFRE3TABld9Qbzgqy7RbZnd3x9PhL0VD39f4mIRyNzsN8T6bRpKu8f mCGCAUm1gbvwpi7kgHcHusW/qp4gv/23iJZ24hidL0Jyi3zYxDBEcfVcE+k/Oienn1JW R9pz9Tvvql+6LJeIvzbTEK1BSbDb5zEnj7gwXLBxFfILG3HD9Fx0JL6W04jPWM65R/GC TQ/w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rEqx4pUAyvcNCFw109Z//pIeNENb6Z5peeqvuKyFDlg=; b=dnX5OFYcIsctNSU/K1A2kdmK1cY5aY7r+Bcq7wrIqg3RplAgWJg1a5KgFMVbxeeKgx ceensm6R2rBzqG2HvxPa8BgQl3H1gn7lWRA2ZiUOmYmO0KEBQf74qKpul613mNDic2Se Ooh7Q1JdZdo95B+91vvOaUH+y/AQMyAh78DPwFoYP9eKMj4iEW/iBKMSEjWyLBah9mPe YFSBM6mgakPjPtQdEOEaN44mReDKtvzQlx4uPcM8Q/BH2HMO+5wDdPqVHgAuG+QdXgKP vERv9XlvmICiwwSJYSS0LJrGZGDM2wp0EgncVc0uffHg5ZeoQLOH9dMvKV7XfX2AQ9uN eaVA== X-Gm-Message-State: ACrzQf3THxET0kcL34R3sD2M+mBphvXw4/X4xO9jA+1gjOMHhK0p1eDQ w82eissjbnm7MHywMOh3JADwBZhg0tzAdQ== X-Google-Smtp-Source: AMsMyM6I+d9DosjM0zqIFL452k15FZxHssemXD1WfmSOz8MTmtbNdfFTqM00zKHjYEKSb8XpHdSeKg== X-Received: by 2002:a5d:4f8d:0:b0:236:714b:29f0 with SMTP id d13-20020a5d4f8d000000b00236714b29f0mr21052319wru.145.1667561721325; Fri, 04 Nov 2022 04:35:21 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id g17-20020a5d4891000000b0023655e51c33sm3255743wrq.4.2022.11.04.04.35.20 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Nov 2022 04:35:20 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 3/7] target/arm: Make TLBIOS and TLBIRANGE ops trap on HCR_EL2.TTLB Date: Fri, 4 Nov 2022 11:35:11 +0000 Message-Id: <20221104113515.2278508-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221104113515.2278508-1-peter.maydell@linaro.org> References: <20221104113515.2278508-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The HCR_EL2.TTLB bit is supposed to trap all EL1 execution of TLB maintenance instructions. However we have added new TLB insns for FEAT_TLBIOS and FEAT_TLBIRANGE, and forgot to set their accessfn to access_ttlb. Add the missing accessfns. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper.c | 36 ++++++++++++++++++------------------ 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index b070a20f1ad..efbdc657a2d 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6717,51 +6717,51 @@ static const ARMCPRegInfo pauth_reginfo[] = { static const ARMCPRegInfo tlbirange_reginfo[] = { { .name = "TLBI_RVAE1IS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 1, - .access = PL1_W, .type = ARM_CP_NO_RAW, + .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, .writefn = tlbi_aa64_rvae1is_write }, { .name = "TLBI_RVAAE1IS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 3, - .access = PL1_W, .type = ARM_CP_NO_RAW, + .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, .writefn = tlbi_aa64_rvae1is_write }, { .name = "TLBI_RVALE1IS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 5, - .access = PL1_W, .type = ARM_CP_NO_RAW, + .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, .writefn = tlbi_aa64_rvae1is_write }, { .name = "TLBI_RVAALE1IS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 7, - .access = PL1_W, .type = ARM_CP_NO_RAW, + .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, .writefn = tlbi_aa64_rvae1is_write }, { .name = "TLBI_RVAE1OS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 1, - .access = PL1_W, .type = ARM_CP_NO_RAW, + .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, .writefn = tlbi_aa64_rvae1is_write }, { .name = "TLBI_RVAAE1OS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 3, - .access = PL1_W, .type = ARM_CP_NO_RAW, + .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, .writefn = tlbi_aa64_rvae1is_write }, { .name = "TLBI_RVALE1OS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 5, - .access = PL1_W, .type = ARM_CP_NO_RAW, + .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, .writefn = tlbi_aa64_rvae1is_write }, { .name = "TLBI_RVAALE1OS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 7, - .access = PL1_W, .type = ARM_CP_NO_RAW, + .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, .writefn = tlbi_aa64_rvae1is_write }, { .name = "TLBI_RVAE1", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 1, - .access = PL1_W, .type = ARM_CP_NO_RAW, + .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, .writefn = tlbi_aa64_rvae1_write }, { .name = "TLBI_RVAAE1", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 3, - .access = PL1_W, .type = ARM_CP_NO_RAW, + .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, .writefn = tlbi_aa64_rvae1_write }, { .name = "TLBI_RVALE1", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 5, - .access = PL1_W, .type = ARM_CP_NO_RAW, + .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, .writefn = tlbi_aa64_rvae1_write }, { .name = "TLBI_RVAALE1", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 7, - .access = PL1_W, .type = ARM_CP_NO_RAW, + .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, .writefn = tlbi_aa64_rvae1_write }, { .name = "TLBI_RIPAS2E1IS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 2, @@ -6832,27 +6832,27 @@ static const ARMCPRegInfo tlbirange_reginfo[] = { static const ARMCPRegInfo tlbios_reginfo[] = { { .name = "TLBI_VMALLE1OS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 0, - .access = PL1_W, .type = ARM_CP_NO_RAW, + .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, .writefn = tlbi_aa64_vmalle1is_write }, { .name = "TLBI_VAE1OS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 1, - .access = PL1_W, .type = ARM_CP_NO_RAW, + .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, .writefn = tlbi_aa64_vae1is_write }, { .name = "TLBI_ASIDE1OS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 2, - .access = PL1_W, .type = ARM_CP_NO_RAW, + .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, .writefn = tlbi_aa64_vmalle1is_write }, { .name = "TLBI_VAAE1OS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 3, - .access = PL1_W, .type = ARM_CP_NO_RAW, + .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, .writefn = tlbi_aa64_vae1is_write }, { .name = "TLBI_VALE1OS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 5, - .access = PL1_W, .type = ARM_CP_NO_RAW, + .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, .writefn = tlbi_aa64_vae1is_write }, { .name = "TLBI_VAALE1OS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 7, - .access = PL1_W, .type = ARM_CP_NO_RAW, + .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, .writefn = tlbi_aa64_vae1is_write }, { .name = "TLBI_ALLE2OS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 0, From patchwork Fri Nov 4 11:35:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13031660 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D953BC43219 for ; Fri, 4 Nov 2022 11:36:48 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oquyw-0001F3-Ea; Fri, 04 Nov 2022 07:35:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oquys-0001BP-AR for qemu-devel@nongnu.org; Fri, 04 Nov 2022 07:35:26 -0400 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oquyq-00086G-4g for qemu-devel@nongnu.org; Fri, 04 Nov 2022 07:35:26 -0400 Received: by mail-wr1-x430.google.com with SMTP id v1so6630064wrt.11 for ; Fri, 04 Nov 2022 04:35:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=gsbbbX/qa9xmeVzw5HZUsZ9ZpD/YYuH0dDHJDSfXWZQ=; b=ZeOHCQRrtNzIKgpELT9ADoKjafjVr+WCyoXI8lZ7l/sxpIfTL+3xnIFQQ2wUnYoVmV fuxV1NQ24BuM25YBsEEDr8BM8jcSq7UJYXO+3v3URbmkD1eFi4BYsXytzScstpTaXMgx GE22Cq2eaqRpBOPms5KSETdDeu7cfg5+VN372yWfyKNvgGXhp3Tf95ZBxGWpYs+VeYqo tMQOsvXkZD2815b7WuZezoI8AfIdVQoYKiuISqRZs1AATqyT48XPWu98ixLfFLV6FXsH aumtmfsV6TLR6E116WSMrGUe4zippnPnfLODP3VVa10GoK44uX+1BLCPez8kG3a7Y82A nMAg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gsbbbX/qa9xmeVzw5HZUsZ9ZpD/YYuH0dDHJDSfXWZQ=; b=h693VYy/Cbr4IglNEG93KtbqCn/1RqV9da8ktEIYz4fCAH5gZswGD9fyJaUcxHra23 OicSMHtVMNAF0+aeGbsLO2Y9q1+jp4rdf6Gj/s41Ub6NhHf6WwtMqqY/uJuZfw8MzAXw RPpwJtfVZtr9vnxRJg64+qARUWL/oSXb40mieDsdyVdg7z2LOr11gMZ5W6Zum7IO6BPT cWH4LshrQxCPFdteUoHE8HHKs+REySMuaLDikupT1LCHSmB475r6OvmfZmkavCvZyBtQ wAHi3ZhQPaaqQxym5MEyPm1nfgTvubcYQnR3e5Ki8YA/nti+JfUZZVUlx6biuH+r2286 3ffw== X-Gm-Message-State: ANoB5pkd0RHRpavz1RkA+AoYG7YIjTHKMuJCGGfRrEkkzRYy5jcKE296 nwJgwSDzUtrlJLiWrFJoFRh5/rE/FE6m6w== X-Google-Smtp-Source: AA0mqf4s/FUqKF9myTrYg05tSzQ9bXp75jlQQv7akJ+/EFqUe5daqLKnIzDNZ1crC1qfOq8boYxFGA== X-Received: by 2002:adf:f60f:0:b0:23a:d94d:40d1 with SMTP id t15-20020adff60f000000b0023ad94d40d1mr1581875wrp.18.1667561722499; Fri, 04 Nov 2022 04:35:22 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id g17-20020a5d4891000000b0023655e51c33sm3255743wrq.4.2022.11.04.04.35.21 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Nov 2022 04:35:21 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 4/7] target/arm: Fix Privileged Access Never (PAN) for aarch32 Date: Fri, 4 Nov 2022 11:35:12 +0000 Message-Id: <20221104113515.2278508-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221104113515.2278508-1-peter.maydell@linaro.org> References: <20221104113515.2278508-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Timofey Kutergin When we implemented the PAN support we theoretically wanted to support it for both AArch32 and AArch64, but in practice several bugs made it essentially unusable with an AArch32 guest. Fix all those problems: - Use CPSR.PAN to check for PAN state in aarch32 mode - throw permission fault during address translation when PAN is enabled and kernel tries to access user acessible page - ignore SCTLR_XP bit for armv7 and armv8 (conflicts with SCTLR_SPAN). Signed-off-by: Timofey Kutergin Reviewed-by: Peter Maydell Message-id: 20221027112619.2205229-1-tkutergin@gmail.com [PMM: tweak commit message] Signed-off-by: Peter Maydell --- target/arm/helper.c | 13 +++++++++++-- target/arm/ptw.c | 35 ++++++++++++++++++++++++++++++----- 2 files changed, 41 insertions(+), 7 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index efbdc657a2d..077581187e7 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11003,6 +11003,15 @@ ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) } #endif +static bool arm_pan_enabled(CPUARMState *env) +{ + if (is_a64(env)) { + return env->pstate & PSTATE_PAN; + } else { + return env->uncached_cpsr & CPSR_PAN; + } +} + ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el) { ARMMMUIdx idx; @@ -11023,7 +11032,7 @@ ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el) } break; case 1: - if (env->pstate & PSTATE_PAN) { + if (arm_pan_enabled(env)) { idx = ARMMMUIdx_E10_1_PAN; } else { idx = ARMMMUIdx_E10_1; @@ -11032,7 +11041,7 @@ ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el) case 2: /* Note that TGE does not apply at EL2. */ if (arm_hcr_el2_eff(env) & HCR_E2H) { - if (env->pstate & PSTATE_PAN) { + if (arm_pan_enabled(env)) { idx = ARMMMUIdx_E20_2_PAN; } else { idx = ARMMMUIdx_E20_2; diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 58a7bbda505..e04dccff44f 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -503,12 +503,11 @@ static bool get_level1_table_address(CPUARMState *env, ARMMMUIdx mmu_idx, * @mmu_idx: MMU index indicating required translation regime * @ap: The 3-bit access permissions (AP[2:0]) * @domain_prot: The 2-bit domain access permissions + * @is_user: TRUE if accessing from PL0 */ -static int ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, - int ap, int domain_prot) +static int ap_to_rw_prot_is_user(CPUARMState *env, ARMMMUIdx mmu_idx, + int ap, int domain_prot, bool is_user) { - bool is_user = regime_is_user(env, mmu_idx); - if (domain_prot == 3) { return PAGE_READ | PAGE_WRITE; } @@ -552,6 +551,20 @@ static int ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, } } +/* + * Translate section/page access permissions to page R/W protection flags + * @env: CPUARMState + * @mmu_idx: MMU index indicating required translation regime + * @ap: The 3-bit access permissions (AP[2:0]) + * @domain_prot: The 2-bit domain access permissions + */ +static int ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, + int ap, int domain_prot) +{ + return ap_to_rw_prot_is_user(env, mmu_idx, ap, domain_prot, + regime_is_user(env, mmu_idx)); +} + /* * Translate section/page access permissions to page R/W protection flags. * @ap: The 2-bit simple AP (AP[2:1]) @@ -720,6 +733,7 @@ static bool get_phys_addr_v6(CPUARMState *env, S1Translate *ptw, hwaddr phys_addr; uint32_t dacr; bool ns; + int user_prot; /* Pagetable walk. */ /* Lookup l1 descriptor. */ @@ -831,8 +845,10 @@ static bool get_phys_addr_v6(CPUARMState *env, S1Translate *ptw, goto do_fault; } result->f.prot = simple_ap_to_rw_prot(env, mmu_idx, ap >> 1); + user_prot = simple_ap_to_rw_prot_is_user(ap >> 1, 1); } else { result->f.prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot); + user_prot = ap_to_rw_prot_is_user(env, mmu_idx, ap, domain_prot, 1); } if (result->f.prot && !xn) { result->f.prot |= PAGE_EXEC; @@ -842,6 +858,14 @@ static bool get_phys_addr_v6(CPUARMState *env, S1Translate *ptw, fi->type = ARMFault_Permission; goto do_fault; } + if (regime_is_pan(env, mmu_idx) && + !regime_is_user(env, mmu_idx) && + user_prot && + access_type != MMU_INST_FETCH) { + /* Privileged Access Never fault */ + fi->type = ARMFault_Permission; + goto do_fault; + } } if (ns) { /* The NS bit will (as required by the architecture) have no effect if @@ -2773,7 +2797,8 @@ static bool get_phys_addr_with_struct(CPUARMState *env, S1Translate *ptw, if (regime_using_lpae_format(env, mmu_idx)) { return get_phys_addr_lpae(env, ptw, address, access_type, false, result, fi); - } else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) { + } else if (arm_feature(env, ARM_FEATURE_V7) || + regime_sctlr(env, mmu_idx) & SCTLR_XP) { return get_phys_addr_v6(env, ptw, address, access_type, result, fi); } else { return get_phys_addr_v5(env, ptw, address, access_type, result, fi); From patchwork Fri Nov 4 11:35:13 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13031661 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9763CC4332F for ; Fri, 4 Nov 2022 11:37:07 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oquyx-0001Fh-1T; Fri, 04 Nov 2022 07:35:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oquys-0001Bd-Im for qemu-devel@nongnu.org; Fri, 04 Nov 2022 07:35:26 -0400 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oquyq-00086U-Ua for qemu-devel@nongnu.org; Fri, 04 Nov 2022 07:35:26 -0400 Received: by mail-wm1-x335.google.com with SMTP id p16so2857896wmc.3 for ; Fri, 04 Nov 2022 04:35:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=OaH3AJ6++HqpYB2gMwyPaC+oyNj5p0BkbapcfI5PAjg=; b=dNaPdlqvrfIYhdca05Z+nNHc25pxVkN2v9HdKE+VNT0Jpv+paH0gxGBZFKs01wfqKB PBKTDgR1Dkuzjz3kNMUm8N8uMQXyXBfwj8p5KGGRzRA1GPs29xuh/Uqzoh8Dqv0xqW0D pUi08KNzXD9pMcenhot5nui/SIg3xqZinCU0Vy6K3kZr6nBWLilW3p6HkUe9wMWH51VO VgJzQF9EHuBu3RFjIg7c1F2Z8wXmAD2nPwZDoI+3tMyI8eXUzAytk+d6RUNip21QZ5Ns tCM9JKat1yky6bm7mNVIrPutF/fnolPzA24diEFGjmX28qEIwftxhQAPUh72P6t4ZHN7 VA0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=OaH3AJ6++HqpYB2gMwyPaC+oyNj5p0BkbapcfI5PAjg=; b=aXVo6FhpbDsXt4lAvHpAF9dle5bkq0iwEE020z95rjZLcIpMdM3lOVB8hEjar+sAur PhsVdJawNwbsRf5rHnKx4UBn1ISV4BCnDxxwoCbB+tONjegM7JzBsI/zgyWDNkijOzJv NsFRAyDKrBJMdayT5Mq9/m87NKT3ZkEqNKl4Fzoyhkh2BpVpilIdr7WsKbBzyRgw2cCM d9rRp/cszY7U0szzWIYhkwY3y1SC27crnpRmHFmidu0oeqoBI9PbWOX/K0EYeVzytgF/ ltF64bcBqcrTNwj2g2e0W3W3NZl0beMZFLqtcJ1/dC58u1cXi5N57VM7Xlufj9Zl6Sjf yt8Q== X-Gm-Message-State: ACrzQf03LEEmC68eCmwCT6FaGi0pP9zd2lIHxFBOPb557Og3+ldQ9O/e j9PXUwauo0HODx3H9bXFdqd11dFkga4jSg== X-Google-Smtp-Source: AMsMyM6qf6Ugnn344TEx5XKTSVON1pPQCaeCWTWUmKjCYGMIfihudr0wrmRD4Evbtndl6G/qf2siSQ== X-Received: by 2002:a05:600c:2242:b0:3cf:4ccc:7418 with SMTP id a2-20020a05600c224200b003cf4ccc7418mr32804125wmm.191.1667561723499; Fri, 04 Nov 2022 04:35:23 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id g17-20020a5d4891000000b0023655e51c33sm3255743wrq.4.2022.11.04.04.35.22 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Nov 2022 04:35:22 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 5/7] target/arm: Copy the entire vector in DO_ZIP Date: Fri, 4 Nov 2022 11:35:13 +0000 Message-Id: <20221104113515.2278508-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221104113515.2278508-1-peter.maydell@linaro.org> References: <20221104113515.2278508-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Richard Henderson With odd_ofs set, we weren't copying enough data. Fixes: 09eb6d7025d1 ("target/arm: Move sve zip high_ofs into simd_data") Reported-by: Idan Horowitz Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-id: 20221031054144.3574-1-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/sve_helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index 3d0d2987cd0..1afeadf9c85 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -3366,10 +3366,10 @@ void HELPER(NAME)(void *vd, void *vn, void *vm, uint32_t desc) \ /* We produce output faster than we consume input. \ Therefore we must be mindful of possible overlap. */ \ if (unlikely((vn - vd) < (uintptr_t)oprsz)) { \ - vn = memcpy(&tmp_n, vn, oprsz_2); \ + vn = memcpy(&tmp_n, vn, oprsz); \ } \ if (unlikely((vm - vd) < (uintptr_t)oprsz)) { \ - vm = memcpy(&tmp_m, vm, oprsz_2); \ + vm = memcpy(&tmp_m, vm, oprsz); \ } \ for (i = 0; i < oprsz_2; i += sizeof(TYPE)) { \ *(TYPE *)(vd + H(2 * i + 0)) = *(TYPE *)(vn + odd_ofs + H(i)); \ From patchwork Fri Nov 4 11:35:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13031658 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3164EC433FE for ; Fri, 4 Nov 2022 11:36:34 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oquyv-0001Ee-PY; Fri, 04 Nov 2022 07:35:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oquyt-0001D8-Ou for qemu-devel@nongnu.org; Fri, 04 Nov 2022 07:35:27 -0400 Received: from mail-wr1-x42e.google.com ([2a00:1450:4864:20::42e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oquys-00087F-3F for qemu-devel@nongnu.org; Fri, 04 Nov 2022 07:35:27 -0400 Received: by mail-wr1-x42e.google.com with SMTP id z14so6655568wrn.7 for ; Fri, 04 Nov 2022 04:35:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=B0i2dCHDu9lWZFqlFLWm0pVGENdI0RfMEclSaPXpBTU=; b=Ilwq2q2nEtKKOaBDN9UJvFQY7Ae5thrM+vvIn1kyQYQimvgo6jigHPqe6xZ34dUXKE fDr58CRsVR1ZU/l31dyWEZ4ZrWQOzPj1806Xp1WgJwVhQlb0IBjRZkEcYU03WoEu+1QT z6Kxdh/1X5osRfjIfnvK8Czk6gcEsPV9+uxW1+qe0j3gdftB253T+dFEXuKMVeW5SXVx fhmEXv65tJdy5e10SkxjOh30tYN3WRmfSvSWlkY6lF2BRN/pm4K74f2NHoeG7AKoUxvr yXtr9GsChzMEiYWXLVodWiPaH7ujc3bXilWHryui9HmuH8kvb1vJT5WTyWWMTMy6jK4Q 4UNg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=B0i2dCHDu9lWZFqlFLWm0pVGENdI0RfMEclSaPXpBTU=; b=PUXpDQd+aouP+s+N8bX7ocE6ZSiaxMpGyY95ByhsdjyrGoB/j045orZFoeFoErgcSE a83wRBAJF0ePEoheDStoRUEv5KPbkTpkTVY84aIbjDpimeL/i+BIC8Zpv6bwtqX2si1T K80j9OKhBmBL+caBHrCAst6ENtP5JEF1X3jhHUSmz5i09Ibw5Qhqed8ekYQrRz7w6eX1 /+Ajh+kmQVbRK15PcyjVKoVKGnLILiXiDOehrwKLGw/pqWp8pEFAY5jMAMVmpZjYTb9T +pvs5FG+tBK0xMIWJdwEg3TbvJ+8qHCHrmuIW2gq+9vM9dQusxHBLSsk9JPZ1JkeU3tp KiQA== X-Gm-Message-State: ACrzQf2CKFLrpwt50uqie8UyE9pIJL04640XpUBzTKVUerRciH/E3LwH yF+jrNRZvI7pS4EYCy164D23ralXmRcyWA== X-Google-Smtp-Source: AMsMyM5lZ/gqW2jrFRm5Z/UOwk6atRhDKoNsBZUplDjI9uWi5kTS+kLln7F0nmEcDCcFxNKyuPamrA== X-Received: by 2002:adf:e30f:0:b0:236:d8ef:9ede with SMTP id b15-20020adfe30f000000b00236d8ef9edemr15922883wrj.170.1667561724422; Fri, 04 Nov 2022 04:35:24 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id g17-20020a5d4891000000b0023655e51c33sm3255743wrq.4.2022.11.04.04.35.23 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Nov 2022 04:35:23 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 6/7] target/arm: Honor HCR_E2H and HCR_TGE in ats_write64() Date: Fri, 4 Nov 2022 11:35:14 +0000 Message-Id: <20221104113515.2278508-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221104113515.2278508-1-peter.maydell@linaro.org> References: <20221104113515.2278508-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Ake Koomsin We need to check HCR_E2H and HCR_TGE to select the right MMU index for the correct translation regime. To check for EL2&0 translation regime: - For S1E0*, S1E1* and S12E* ops, check both HCR_E2H and HCR_TGE - For S1E2* ops, check only HCR_E2H Signed-off-by: Ake Koomsin Message-id: 20221101064250.12444-1-ake@igel.co.jp Reviewed-by: Richard Henderson Signed-off-by: Peter Maydell --- target/arm/helper.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 077581187e7..d8c8223ec38 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3501,19 +3501,22 @@ static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri, MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD; ARMMMUIdx mmu_idx; int secure = arm_is_secure_below_el3(env); + uint64_t hcr_el2 = arm_hcr_el2_eff(env); + bool regime_e20 = (hcr_el2 & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE); switch (ri->opc2 & 6) { case 0: switch (ri->opc1) { case 0: /* AT S1E1R, AT S1E1W, AT S1E1RP, AT S1E1WP */ if (ri->crm == 9 && (env->pstate & PSTATE_PAN)) { - mmu_idx = ARMMMUIdx_Stage1_E1_PAN; + mmu_idx = regime_e20 ? + ARMMMUIdx_E20_2_PAN : ARMMMUIdx_Stage1_E1_PAN; } else { - mmu_idx = ARMMMUIdx_Stage1_E1; + mmu_idx = regime_e20 ? ARMMMUIdx_E20_2 : ARMMMUIdx_Stage1_E1; } break; case 4: /* AT S1E2R, AT S1E2W */ - mmu_idx = ARMMMUIdx_E2; + mmu_idx = hcr_el2 & HCR_E2H ? ARMMMUIdx_E20_2 : ARMMMUIdx_E2; break; case 6: /* AT S1E3R, AT S1E3W */ mmu_idx = ARMMMUIdx_E3; @@ -3524,13 +3527,13 @@ static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri, } break; case 2: /* AT S1E0R, AT S1E0W */ - mmu_idx = ARMMMUIdx_Stage1_E0; + mmu_idx = regime_e20 ? ARMMMUIdx_E20_0 : ARMMMUIdx_Stage1_E0; break; case 4: /* AT S12E1R, AT S12E1W */ - mmu_idx = ARMMMUIdx_E10_1; + mmu_idx = regime_e20 ? ARMMMUIdx_E20_2 : ARMMMUIdx_E10_1; break; case 6: /* AT S12E0R, AT S12E0W */ - mmu_idx = ARMMMUIdx_E10_0; + mmu_idx = regime_e20 ? ARMMMUIdx_E20_0 : ARMMMUIdx_E10_0; break; default: g_assert_not_reached(); From patchwork Fri Nov 4 11:35:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13031659 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8F37BC4332F for ; Fri, 4 Nov 2022 11:36:42 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oquzA-0001NU-HR; Fri, 04 Nov 2022 07:35:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oquz8-0001NC-44 for qemu-devel@nongnu.org; Fri, 04 Nov 2022 07:35:42 -0400 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oquys-00087O-Lu for qemu-devel@nongnu.org; Fri, 04 Nov 2022 07:35:40 -0400 Received: by mail-wr1-x434.google.com with SMTP id o4so6667669wrq.6 for ; Fri, 04 Nov 2022 04:35:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=TK36xDI/Bedr+1cIQUf9pmiyP0CsOopzktqKeVg1tdc=; b=CwgSab0DFfsNtlJTI3tyOh6Q2Yt3Hycy0QO1Gk9H2QplJOUjDyll6ASKg54J+JedCN Ygo0meKrsfqZt16gg+X00/JRwCLNFB0E+VqgY6P0SQrnP8B4SBGz0sN0exiZUgIDpsjB mY4gjQ4Ou4tcOdCOpQb4q70vri9KlDIdokoQdDLY1Y6pslYNWZFLoWE1b5+MYbnsrpBI 85ahl9x+IQPDqHOwQFBG0Nt2FPNrPg4XG3sjoinlmP+0GXl2yTbaYtVcTai5eKb3oRLh 6jQo2G4mPz/o+LLKCHag7KxOG4VP9MgBjq2L0KClJRmPZPK0nYsGUNKgcJvSdrM3N/xf Gt7g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TK36xDI/Bedr+1cIQUf9pmiyP0CsOopzktqKeVg1tdc=; b=b4yWSCJSTcJJB9MbMwCYZAS0q5Ufb0krLcCLopku8fEWGwV13zXiTqvsSa/0Ax+KjX H3d+YpS+UNHtfk53ibLqmgI8w9Bew3tb7CXGwwRPCz6VyvKglr9ZwVkoZ1V1durgIzPK BapzLJToa+9B1gcFrteSflyK3taiCXE3fs1jnGPZ6GBY1V1HjryBCz2XgR5QnfrIVV2V VoGg0y2qEAb++QuKJgHIWYAtI+haByOMI0UUihlyq87f6XZoan/UHnTW+4gGUrt8bxRY o1t2hAb5QyC5D8XZK1BhE+bnOXiAzgJx48ZHFz5LrEolZRUNWmuITdtZ0UUg+cmpN/Gg +8Kg== X-Gm-Message-State: ACrzQf3f63VdeUC91ilWui6M7HVEFc1+jquDAcixdVpI9peek3jJF3fT TETItsn9c3jeD/1nXAX0V9OG3Ex0e4H3Ew== X-Google-Smtp-Source: AMsMyM4Iyu4dLZ9Gjv1j1Sk/w9Qq7sQ/r8ubxFpHj/znyRef8wgKapl+AJMEPEfvYub9P5/W4wcmhg== X-Received: by 2002:a5d:45d0:0:b0:236:8201:1cb7 with SMTP id b16-20020a5d45d0000000b0023682011cb7mr21817787wrs.417.1667561725365; Fri, 04 Nov 2022 04:35:25 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id g17-20020a5d4891000000b0023655e51c33sm3255743wrq.4.2022.11.04.04.35.24 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Nov 2022 04:35:24 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 7/7] target/arm: Two fixes for secure ptw Date: Fri, 4 Nov 2022 11:35:15 +0000 Message-Id: <20221104113515.2278508-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221104113515.2278508-1-peter.maydell@linaro.org> References: <20221104113515.2278508-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Richard Henderson Reversed the sense of non-secure in get_phys_addr_lpae, and failed to initialize attrs.secure for ARMMMUIdx_Phys_S. Fixes: 48da29e4 ("target/arm: Add ptw_idx to S1Translate") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1293 Signed-off-by: Richard Henderson Tested-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/ptw.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index e04dccff44f..3745ac97234 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1381,7 +1381,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, descaddr |= (address >> (stride * (4 - level))) & indexmask; descaddr &= ~7ULL; nstable = extract32(tableattrs, 4, 1); - if (!nstable) { + if (nstable) { /* * Stage2_S -> Stage2 or Phys_S -> Phys_NS * Assert that the non-secure idx are even, and relative order. @@ -2695,6 +2695,13 @@ static bool get_phys_addr_with_struct(CPUARMState *env, S1Translate *ptw, bool is_secure = ptw->in_secure; ARMMMUIdx s1_mmu_idx; + /* + * The page table entries may downgrade secure to non-secure, but + * cannot upgrade an non-secure translation regime's attributes + * to secure. + */ + result->f.attrs.secure = is_secure; + switch (mmu_idx) { case ARMMMUIdx_Phys_S: case ARMMMUIdx_Phys_NS: @@ -2736,12 +2743,6 @@ static bool get_phys_addr_with_struct(CPUARMState *env, S1Translate *ptw, break; } - /* - * The page table entries may downgrade secure to non-secure, but - * cannot upgrade an non-secure translation regime's attributes - * to secure. - */ - result->f.attrs.secure = is_secure; result->f.attrs.user = regime_is_user(env, mmu_idx); /*