From patchwork Fri Nov 4 15:55:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Rob Herring (Arm)" X-Patchwork-Id: 13032239 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 904B6C4332F for ; Fri, 4 Nov 2022 15:57:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References:Message-Id :MIME-Version:Subject:Date:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=/aDgCDdo2GOmmWwFtm3fSJk3B/+IHJwPc26oktriI80=; b=HoFzg7G9NtPDhj ME7R0Vc04vI9o3/vd09EAvy0URYaBsWsh5vBkNMpDyMVoQFYKMzJHf6/yCcG660KpqiwVw1luUIWS SXerSL7WrT5QzaeNEpC1QieBkQcWSCzCxoYAOzEJqbkT4F1Bfweh3HNkS7gLuvbHdoKUlMm6X0aYs 1hAaGxdElYaPRrfD8OkwUk9xEBLtSW4/BdJuWBVIDUlRWOWF5zE/2NtOAVQdPOWGPTq1xBZHrOW1U Bd1TLapFWvigCr35ule5RzTHciQoWkkFvUdZJwbrMUhIi/EKIbaq0uyid/fvOigMziB77NFKQNo5Z L+wXPkJfyY887GkzcQyg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oqz35-004LZ9-G9; Fri, 04 Nov 2022 15:56:03 +0000 Received: from mail-oi1-f182.google.com ([209.85.167.182]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oqz2T-004LL4-Ap for linux-arm-kernel@lists.infradead.org; Fri, 04 Nov 2022 15:55:27 +0000 Received: by mail-oi1-f182.google.com with SMTP id p127so5573928oih.9 for ; Fri, 04 Nov 2022 08:55:25 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=nbh4kYtAszd2WFH06dmd+kkJjoRcl20JJM5emroag08=; b=rZIF2TU1flP/FFrP0BbMJm8tsAgDmFo86AboPwYg7qneA+FJeQjcyJkFWFnU+ieiTU 0g+e2F5vxMCUcy/V1Voj7EznYTS+Gdf/9eoupk+zvVpaoWffdc/kMHJBMSTIIAsBewfG W7HZds759s4DujwWVUnGHjiNhf/NyPfl801xVxGzSdhbasKQvklRES0CZCHjYR61wrUW 9oACK+wwNCl5HwK7VJvzTAjgmFW8isxoEB/7EdQ1ZIhSTUlOzaVXuQo4HmbqJilmzoHe +SAJmrkifKt7KbX4qfsMjRuw9gUFSFem+pQNry1015jVI+VheSVYMtsgDcWjgC1wlaSY qDnw== X-Gm-Message-State: ACrzQf2H5FP44IDnnd/22MU5uYluM+vhb3WeVAuzrJEMJJdLMkNFSJyX IAuISl4SvNzanSb7wmjanCcUBLKdUw== X-Google-Smtp-Source: AMsMyM6XCGOxDkWp/KDtlfrAH+Z735zS9ydDsev6tHg8eM+cXyEV7Ga+K7IZqgQFpv3gP3gCDvvgow== X-Received: by 2002:a05:6808:11c1:b0:353:f1a5:207a with SMTP id p1-20020a05680811c100b00353f1a5207amr27451988oiv.183.1667577324586; Fri, 04 Nov 2022 08:55:24 -0700 (PDT) Received: from robh_at_kernel.org (66-90-144-107.dyn.grandenetworks.net. [66.90.144.107]) by smtp.gmail.com with ESMTPSA id cg27-20020a056830631b00b00661b019accbsm1588176otb.3.2022.11.04.08.55.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Nov 2022 08:55:24 -0700 (PDT) Received: (nullmailer pid 1880410 invoked by uid 1000); Fri, 04 Nov 2022 15:55:18 -0000 From: Rob Herring Date: Fri, 04 Nov 2022 10:55:01 -0500 Subject: [PATCH v3 1/8] perf: arm_spe: Use feature numbering for PMSEVFR_EL1 defines MIME-Version: 1.0 Message-Id: <20220825-arm-spe-v8-7-v3-1-87682f78caac@kernel.org> References: <20220825-arm-spe-v8-7-v3-0-87682f78caac@kernel.org> In-Reply-To: <20220825-arm-spe-v8-7-v3-0-87682f78caac@kernel.org> To: Namhyung Kim , Will Deacon , Arnaldo Carvalho de Melo , Jiri Olsa , Peter Zijlstra , Alexander Shishkin , Mark Rutland , Catalin Marinas , Marc Zyngier , Oliver Upton , Ingo Molnar , Suzuki K Poulose , James Morse , Alexandru Elisei Cc: kvmarm@lists.linux.dev, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, James Clark , Mark Brown , linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu X-Mailer: b4 0.11.0-dev X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221104_085525_414555_443F21DE X-CRM114-Status: GOOD ( 13.79 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Similar to commit 121a8fc088f1 ("arm64/sysreg: Use feature numbering for PMU and SPE revisions") use feature numbering instead of architecture versions for the PMSEVFR_EL1 Res0 defines. Tested-by: James Clark Signed-off-by: Rob Herring --- v3: - No change v2: - New patch --- arch/arm64/include/asm/sysreg.h | 6 +++--- drivers/perf/arm_spe_pmu.c | 4 ++-- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 7d301700d1a9..9a4cf12e3e16 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -294,11 +294,11 @@ #define SYS_PMSFCR_EL1_ST_SHIFT 18 #define SYS_PMSEVFR_EL1 sys_reg(3, 0, 9, 9, 5) -#define SYS_PMSEVFR_EL1_RES0_8_2 \ +#define PMSEVFR_EL1_RES0_IMP \ (GENMASK_ULL(47, 32) | GENMASK_ULL(23, 16) | GENMASK_ULL(11, 8) |\ BIT_ULL(6) | BIT_ULL(4) | BIT_ULL(2) | BIT_ULL(0)) -#define SYS_PMSEVFR_EL1_RES0_8_3 \ - (SYS_PMSEVFR_EL1_RES0_8_2 & ~(BIT_ULL(18) | BIT_ULL(17) | BIT_ULL(11))) +#define PMSEVFR_EL1_RES0_V1P1 \ + (PMSEVFR_EL1_RES0_IMP & ~(BIT_ULL(18) | BIT_ULL(17) | BIT_ULL(11))) #define SYS_PMSLATFR_EL1 sys_reg(3, 0, 9, 9, 6) #define SYS_PMSLATFR_EL1_MINLAT_SHIFT 0 diff --git a/drivers/perf/arm_spe_pmu.c b/drivers/perf/arm_spe_pmu.c index 00e3a637f7b6..65cf93dcc8ee 100644 --- a/drivers/perf/arm_spe_pmu.c +++ b/drivers/perf/arm_spe_pmu.c @@ -677,11 +677,11 @@ static u64 arm_spe_pmsevfr_res0(u16 pmsver) { switch (pmsver) { case ID_AA64DFR0_EL1_PMSVer_IMP: - return SYS_PMSEVFR_EL1_RES0_8_2; + return PMSEVFR_EL1_RES0_IMP; case ID_AA64DFR0_EL1_PMSVer_V1P1: /* Return the highest version we support in default */ default: - return SYS_PMSEVFR_EL1_RES0_8_3; + return PMSEVFR_EL1_RES0_V1P1; } } From patchwork Fri Nov 4 15:55:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Rob Herring (Arm)" X-Patchwork-Id: 13032237 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8321DC433FE for ; Fri, 4 Nov 2022 15:56:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References:Message-Id :MIME-Version:Subject:Date:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=DRh2U4jtZkOqspPzsvPO2aKdP2huuciZOTHA8FALa5Y=; b=RR98tGSrnqcYma HhQ/XY+HgrV/osGF/kzzvZyJrzjZnqlBNufpAWzGort/uDtLoVcBd9VsyD86ugepIDSNrXA3gC0Vw 2y5+51qjOeyIxzUY9JawUfES/zNSTlwRRCCUYrE8sVY35RzwqgO75RB7lSLmwJWYutS2TBkCjXCTs HId7Yo/HItxjvV3XqyuTRH9WWJ5NJ7G3O0KjkRk9jd6rHQqDafudGwbIkYh6bBFfCgbP6clFlLTBg rXHfaFQGps0PqfX6PW5KtgpAMqnhnTCDm3FIscHgCgKTzupFkOYu/rR7nNVOIA4hvriA2F1sHH9/t km+h+B+xr9qSzJLTmlug==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oqz2m-004LSC-1C; Fri, 04 Nov 2022 15:55:44 +0000 Received: from mail-oo1-f54.google.com ([209.85.161.54]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oqz2Q-004LJP-Le for linux-arm-kernel@lists.infradead.org; Fri, 04 Nov 2022 15:55:26 +0000 Received: by mail-oo1-f54.google.com with SMTP id z127-20020a4a4985000000b0049ea7fbfb74so226314ooa.11 for ; Fri, 04 Nov 2022 08:55:21 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vXHN85rGi/sHJxkCh/EJ6+8yFyKV7jY1RaGb4FopPeo=; b=qHkf3gDhB19HSV1Z3I8M1+bD0/1CYpmLvUp9GqS/PSEJnRPe+JPq+2Ev4Sj3gsvR4/ 1Refyt+p42BmAN7k/qaGz41suL2ToP3Cf8lckUW+cMJs0KX17JtaodXmQDYcWushnkA1 DMpS9X5LmuznF7EaYJUib7/Fg/HkloLzfl5f2C5YY+wU4BK4vsBBz1MROcTt/0X29MR2 G7SBT9BWYjUSUjD9UB1WKcMfRZGDSk8x3yerA0usxdErz1yw8yThIXsUgv7QvsCR/XkK 3xKYIGZOjx6Incte65QomwD8/yWFWF6mKHNExxiD7z1OW8lAerOVf1KQUfH0j3d/prdW Co7Q== X-Gm-Message-State: ACrzQf11kOtwCuqO0N9jDa4Wvnj1VG5QOwBdEgO3UZNYrpLnz564VuqF 1b/K5Zv6TW2HMrOUg08dvw== X-Google-Smtp-Source: AMsMyM7pCwyPgb66JWSqAhyJT2Zy19MfmfLvn4n0Iy5I5SMyodx/qFkxvUx6vK81mIjTcgeM6iIZtg== X-Received: by 2002:a4a:8e81:0:b0:475:811f:3f9e with SMTP id p1-20020a4a8e81000000b00475811f3f9emr15376005ook.35.1667577320918; Fri, 04 Nov 2022 08:55:20 -0700 (PDT) Received: from robh_at_kernel.org (66-90-144-107.dyn.grandenetworks.net. [66.90.144.107]) by smtp.gmail.com with ESMTPSA id l8-20020a056870218800b0013669485016sm1884406oae.37.2022.11.04.08.55.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Nov 2022 08:55:20 -0700 (PDT) Received: (nullmailer pid 1880412 invoked by uid 1000); Fri, 04 Nov 2022 15:55:18 -0000 From: Rob Herring Date: Fri, 04 Nov 2022 10:55:02 -0500 Subject: [PATCH v3 2/8] arm64: Drop SYS_ from SPE register defines MIME-Version: 1.0 Message-Id: <20220825-arm-spe-v8-7-v3-2-87682f78caac@kernel.org> References: <20220825-arm-spe-v8-7-v3-0-87682f78caac@kernel.org> In-Reply-To: <20220825-arm-spe-v8-7-v3-0-87682f78caac@kernel.org> To: Namhyung Kim , Will Deacon , Arnaldo Carvalho de Melo , Jiri Olsa , Peter Zijlstra , Alexander Shishkin , Mark Rutland , Catalin Marinas , Marc Zyngier , Oliver Upton , Ingo Molnar , Suzuki K Poulose , James Morse , Alexandru Elisei Cc: kvmarm@lists.linux.dev, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, James Clark , Mark Brown , linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu X-Mailer: b4 0.11.0-dev X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221104_085522_763515_65D63197 X-CRM114-Status: GOOD ( 21.04 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org We currently have a non-standard SYS_ prefix in the constants generated for the SPE register bitfields. Drop this in preparation for automatic register definition generation. The SPE mask defines were unshifted, and the SPE register field enumerations were shifted. The autogenerated defines are the opposite, so make the necessary adjustments. No functional changes. Tested-by: James Clark Signed-off-by: Rob Herring --- v3: - No change v2: - New patch --- arch/arm64/include/asm/el2_setup.h | 6 +- arch/arm64/include/asm/sysreg.h | 112 ++++++++++++++++++------------------- arch/arm64/kvm/debug.c | 2 +- arch/arm64/kvm/hyp/nvhe/debug-sr.c | 2 +- drivers/perf/arm_spe_pmu.c | 85 ++++++++++++++-------------- 5 files changed, 103 insertions(+), 104 deletions(-) diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el2_setup.h index 668569adf4d3..f9da43e53cdb 100644 --- a/arch/arm64/include/asm/el2_setup.h +++ b/arch/arm64/include/asm/el2_setup.h @@ -53,10 +53,10 @@ cbz x0, .Lskip_spe_\@ // Skip if SPE not present mrs_s x0, SYS_PMBIDR_EL1 // If SPE available at EL2, - and x0, x0, #(1 << SYS_PMBIDR_EL1_P_SHIFT) + and x0, x0, #(1 << PMBIDR_EL1_P_SHIFT) cbnz x0, .Lskip_spe_el2_\@ // then permit sampling of physical - mov x0, #(1 << SYS_PMSCR_EL2_PCT_SHIFT | \ - 1 << SYS_PMSCR_EL2_PA_SHIFT) + mov x0, #(1 << PMSCR_EL2_PCT_SHIFT | \ + 1 << PMSCR_EL2_PA_SHIFT) msr_s SYS_PMSCR_EL2, x0 // addresses and physical counter .Lskip_spe_el2_\@: mov x0, #(MDCR_EL2_E2PB_MASK << MDCR_EL2_E2PB_SHIFT) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 9a4cf12e3e16..8df8a0a51273 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -239,59 +239,59 @@ /*** Statistical Profiling Extension ***/ /* ID registers */ #define SYS_PMSIDR_EL1 sys_reg(3, 0, 9, 9, 7) -#define SYS_PMSIDR_EL1_FE_SHIFT 0 -#define SYS_PMSIDR_EL1_FT_SHIFT 1 -#define SYS_PMSIDR_EL1_FL_SHIFT 2 -#define SYS_PMSIDR_EL1_ARCHINST_SHIFT 3 -#define SYS_PMSIDR_EL1_LDS_SHIFT 4 -#define SYS_PMSIDR_EL1_ERND_SHIFT 5 -#define SYS_PMSIDR_EL1_INTERVAL_SHIFT 8 -#define SYS_PMSIDR_EL1_INTERVAL_MASK 0xfUL -#define SYS_PMSIDR_EL1_MAXSIZE_SHIFT 12 -#define SYS_PMSIDR_EL1_MAXSIZE_MASK 0xfUL -#define SYS_PMSIDR_EL1_COUNTSIZE_SHIFT 16 -#define SYS_PMSIDR_EL1_COUNTSIZE_MASK 0xfUL +#define PMSIDR_EL1_FE_SHIFT 0 +#define PMSIDR_EL1_FT_SHIFT 1 +#define PMSIDR_EL1_FL_SHIFT 2 +#define PMSIDR_EL1_ARCHINST_SHIFT 3 +#define PMSIDR_EL1_LDS_SHIFT 4 +#define PMSIDR_EL1_ERND_SHIFT 5 +#define PMSIDR_EL1_INTERVAL_SHIFT 8 +#define PMSIDR_EL1_INTERVAL_MASK GENMASK_ULL(11, 8) +#define PMSIDR_EL1_MAXSIZE_SHIFT 12 +#define PMSIDR_EL1_MAXSIZE_MASK GENMASK_ULL(15, 12) +#define PMSIDR_EL1_COUNTSIZE_SHIFT 16 +#define PMSIDR_EL1_COUNTSIZE_MASK GENMASK_ULL(19, 16) #define SYS_PMBIDR_EL1 sys_reg(3, 0, 9, 10, 7) -#define SYS_PMBIDR_EL1_ALIGN_SHIFT 0 -#define SYS_PMBIDR_EL1_ALIGN_MASK 0xfU -#define SYS_PMBIDR_EL1_P_SHIFT 4 -#define SYS_PMBIDR_EL1_F_SHIFT 5 +#define PMBIDR_EL1_ALIGN_SHIFT 0 +#define PMBIDR_EL1_ALIGN_MASK 0xfU +#define PMBIDR_EL1_P_SHIFT 4 +#define PMBIDR_EL1_F_SHIFT 5 /* Sampling controls */ #define SYS_PMSCR_EL1 sys_reg(3, 0, 9, 9, 0) -#define SYS_PMSCR_EL1_E0SPE_SHIFT 0 -#define SYS_PMSCR_EL1_E1SPE_SHIFT 1 -#define SYS_PMSCR_EL1_CX_SHIFT 3 -#define SYS_PMSCR_EL1_PA_SHIFT 4 -#define SYS_PMSCR_EL1_TS_SHIFT 5 -#define SYS_PMSCR_EL1_PCT_SHIFT 6 +#define PMSCR_EL1_E0SPE_SHIFT 0 +#define PMSCR_EL1_E1SPE_SHIFT 1 +#define PMSCR_EL1_CX_SHIFT 3 +#define PMSCR_EL1_PA_SHIFT 4 +#define PMSCR_EL1_TS_SHIFT 5 +#define PMSCR_EL1_PCT_SHIFT 6 #define SYS_PMSCR_EL2 sys_reg(3, 4, 9, 9, 0) -#define SYS_PMSCR_EL2_E0HSPE_SHIFT 0 -#define SYS_PMSCR_EL2_E2SPE_SHIFT 1 -#define SYS_PMSCR_EL2_CX_SHIFT 3 -#define SYS_PMSCR_EL2_PA_SHIFT 4 -#define SYS_PMSCR_EL2_TS_SHIFT 5 -#define SYS_PMSCR_EL2_PCT_SHIFT 6 +#define PMSCR_EL2_E0HSPE_SHIFT 0 +#define PMSCR_EL2_E2SPE_SHIFT 1 +#define PMSCR_EL2_CX_SHIFT 3 +#define PMSCR_EL2_PA_SHIFT 4 +#define PMSCR_EL2_TS_SHIFT 5 +#define PMSCR_EL2_PCT_SHIFT 6 #define SYS_PMSICR_EL1 sys_reg(3, 0, 9, 9, 2) #define SYS_PMSIRR_EL1 sys_reg(3, 0, 9, 9, 3) -#define SYS_PMSIRR_EL1_RND_SHIFT 0 -#define SYS_PMSIRR_EL1_INTERVAL_SHIFT 8 -#define SYS_PMSIRR_EL1_INTERVAL_MASK 0xffffffUL +#define PMSIRR_EL1_RND_SHIFT 0 +#define PMSIRR_EL1_INTERVAL_SHIFT 8 +#define PMSIRR_EL1_INTERVAL_MASK GENMASK_ULL(31, 8) /* Filtering controls */ #define SYS_PMSNEVFR_EL1 sys_reg(3, 0, 9, 9, 1) #define SYS_PMSFCR_EL1 sys_reg(3, 0, 9, 9, 4) -#define SYS_PMSFCR_EL1_FE_SHIFT 0 -#define SYS_PMSFCR_EL1_FT_SHIFT 1 -#define SYS_PMSFCR_EL1_FL_SHIFT 2 -#define SYS_PMSFCR_EL1_B_SHIFT 16 -#define SYS_PMSFCR_EL1_LD_SHIFT 17 -#define SYS_PMSFCR_EL1_ST_SHIFT 18 +#define PMSFCR_EL1_FE_SHIFT 0 +#define PMSFCR_EL1_FT_SHIFT 1 +#define PMSFCR_EL1_FL_SHIFT 2 +#define PMSFCR_EL1_B_SHIFT 16 +#define PMSFCR_EL1_LD_SHIFT 17 +#define PMSFCR_EL1_ST_SHIFT 18 #define SYS_PMSEVFR_EL1 sys_reg(3, 0, 9, 9, 5) #define PMSEVFR_EL1_RES0_IMP \ @@ -301,37 +301,37 @@ (PMSEVFR_EL1_RES0_IMP & ~(BIT_ULL(18) | BIT_ULL(17) | BIT_ULL(11))) #define SYS_PMSLATFR_EL1 sys_reg(3, 0, 9, 9, 6) -#define SYS_PMSLATFR_EL1_MINLAT_SHIFT 0 +#define PMSLATFR_EL1_MINLAT_SHIFT 0 /* Buffer controls */ #define SYS_PMBLIMITR_EL1 sys_reg(3, 0, 9, 10, 0) -#define SYS_PMBLIMITR_EL1_E_SHIFT 0 -#define SYS_PMBLIMITR_EL1_FM_SHIFT 1 -#define SYS_PMBLIMITR_EL1_FM_MASK 0x3UL -#define SYS_PMBLIMITR_EL1_FM_STOP_IRQ (0 << SYS_PMBLIMITR_EL1_FM_SHIFT) +#define PMBLIMITR_EL1_E_SHIFT 0 +#define PMBLIMITR_EL1_FM_SHIFT 1 +#define PMBLIMITR_EL1_FM_MASK GENMASK_ULL(2, 1) +#define PMBLIMITR_EL1_FM_STOP_IRQ 0 #define SYS_PMBPTR_EL1 sys_reg(3, 0, 9, 10, 1) /* Buffer error reporting */ #define SYS_PMBSR_EL1 sys_reg(3, 0, 9, 10, 3) -#define SYS_PMBSR_EL1_COLL_SHIFT 16 -#define SYS_PMBSR_EL1_S_SHIFT 17 -#define SYS_PMBSR_EL1_EA_SHIFT 18 -#define SYS_PMBSR_EL1_DL_SHIFT 19 -#define SYS_PMBSR_EL1_EC_SHIFT 26 -#define SYS_PMBSR_EL1_EC_MASK 0x3fUL +#define PMBSR_EL1_COLL_SHIFT 16 +#define PMBSR_EL1_S_SHIFT 17 +#define PMBSR_EL1_EA_SHIFT 18 +#define PMBSR_EL1_DL_SHIFT 19 +#define PMBSR_EL1_EC_SHIFT 26 +#define PMBSR_EL1_EC_MASK GENMASK_ULL(31, 26) -#define SYS_PMBSR_EL1_EC_BUF (0x0UL << SYS_PMBSR_EL1_EC_SHIFT) -#define SYS_PMBSR_EL1_EC_FAULT_S1 (0x24UL << SYS_PMBSR_EL1_EC_SHIFT) -#define SYS_PMBSR_EL1_EC_FAULT_S2 (0x25UL << SYS_PMBSR_EL1_EC_SHIFT) +#define PMBSR_EL1_EC_BUF 0x0UL +#define PMBSR_EL1_EC_FAULT_S1 0x24UL +#define PMBSR_EL1_EC_FAULT_S2 0x25UL -#define SYS_PMBSR_EL1_FAULT_FSC_SHIFT 0 -#define SYS_PMBSR_EL1_FAULT_FSC_MASK 0x3fUL +#define PMBSR_EL1_FAULT_FSC_SHIFT 0 +#define PMBSR_EL1_FAULT_FSC_MASK 0x3fUL -#define SYS_PMBSR_EL1_BUF_BSC_SHIFT 0 -#define SYS_PMBSR_EL1_BUF_BSC_MASK 0x3fUL +#define PMBSR_EL1_BUF_BSC_SHIFT 0 +#define PMBSR_EL1_BUF_BSC_MASK 0x3fUL -#define SYS_PMBSR_EL1_BUF_BSC_FULL (0x1UL << SYS_PMBSR_EL1_BUF_BSC_SHIFT) +#define PMBSR_EL1_BUF_BSC_FULL 0x1UL /*** End of Statistical Profiling Extension ***/ diff --git a/arch/arm64/kvm/debug.c b/arch/arm64/kvm/debug.c index fccf9ec01813..55f80fb93925 100644 --- a/arch/arm64/kvm/debug.c +++ b/arch/arm64/kvm/debug.c @@ -328,7 +328,7 @@ void kvm_arch_vcpu_load_debug_state_flags(struct kvm_vcpu *vcpu) * we may need to check if the host state needs to be saved. */ if (cpuid_feature_extract_unsigned_field(dfr0, ID_AA64DFR0_EL1_PMSVer_SHIFT) && - !(read_sysreg_s(SYS_PMBIDR_EL1) & BIT(SYS_PMBIDR_EL1_P_SHIFT))) + !(read_sysreg_s(SYS_PMBIDR_EL1) & BIT(PMBIDR_EL1_P_SHIFT))) vcpu_set_flag(vcpu, DEBUG_STATE_SAVE_SPE); /* Check if we have TRBE implemented and available at the host */ diff --git a/arch/arm64/kvm/hyp/nvhe/debug-sr.c b/arch/arm64/kvm/hyp/nvhe/debug-sr.c index e17455773b98..2673bde62fad 100644 --- a/arch/arm64/kvm/hyp/nvhe/debug-sr.c +++ b/arch/arm64/kvm/hyp/nvhe/debug-sr.c @@ -27,7 +27,7 @@ static void __debug_save_spe(u64 *pmscr_el1) * Check if the host is actually using it ? */ reg = read_sysreg_s(SYS_PMBLIMITR_EL1); - if (!(reg & BIT(SYS_PMBLIMITR_EL1_E_SHIFT))) + if (!(reg & BIT(PMBLIMITR_EL1_E_SHIFT))) return; /* Yes; save the control register and disable data generation */ diff --git a/drivers/perf/arm_spe_pmu.c b/drivers/perf/arm_spe_pmu.c index 65cf93dcc8ee..814ed18346b6 100644 --- a/drivers/perf/arm_spe_pmu.c +++ b/drivers/perf/arm_spe_pmu.c @@ -12,6 +12,7 @@ #define DRVNAME PMUNAME "_pmu" #define pr_fmt(fmt) DRVNAME ": " fmt +#include #include #include #include @@ -282,18 +283,18 @@ static u64 arm_spe_event_to_pmscr(struct perf_event *event) struct perf_event_attr *attr = &event->attr; u64 reg = 0; - reg |= ATTR_CFG_GET_FLD(attr, ts_enable) << SYS_PMSCR_EL1_TS_SHIFT; - reg |= ATTR_CFG_GET_FLD(attr, pa_enable) << SYS_PMSCR_EL1_PA_SHIFT; - reg |= ATTR_CFG_GET_FLD(attr, pct_enable) << SYS_PMSCR_EL1_PCT_SHIFT; + reg |= ATTR_CFG_GET_FLD(attr, ts_enable) << PMSCR_EL1_TS_SHIFT; + reg |= ATTR_CFG_GET_FLD(attr, pa_enable) << PMSCR_EL1_PA_SHIFT; + reg |= ATTR_CFG_GET_FLD(attr, pct_enable) << PMSCR_EL1_PCT_SHIFT; if (!attr->exclude_user) - reg |= BIT(SYS_PMSCR_EL1_E0SPE_SHIFT); + reg |= BIT(PMSCR_EL1_E0SPE_SHIFT); if (!attr->exclude_kernel) - reg |= BIT(SYS_PMSCR_EL1_E1SPE_SHIFT); + reg |= BIT(PMSCR_EL1_E1SPE_SHIFT); if (get_spe_event_has_cx(event)) - reg |= BIT(SYS_PMSCR_EL1_CX_SHIFT); + reg |= BIT(PMSCR_EL1_CX_SHIFT); return reg; } @@ -302,8 +303,7 @@ static void arm_spe_event_sanitise_period(struct perf_event *event) { struct arm_spe_pmu *spe_pmu = to_spe_pmu(event->pmu); u64 period = event->hw.sample_period; - u64 max_period = SYS_PMSIRR_EL1_INTERVAL_MASK - << SYS_PMSIRR_EL1_INTERVAL_SHIFT; + u64 max_period = PMSIRR_EL1_INTERVAL_MASK; if (period < spe_pmu->min_period) period = spe_pmu->min_period; @@ -322,7 +322,7 @@ static u64 arm_spe_event_to_pmsirr(struct perf_event *event) arm_spe_event_sanitise_period(event); - reg |= ATTR_CFG_GET_FLD(attr, jitter) << SYS_PMSIRR_EL1_RND_SHIFT; + reg |= ATTR_CFG_GET_FLD(attr, jitter) << PMSIRR_EL1_RND_SHIFT; reg |= event->hw.sample_period; return reg; @@ -333,18 +333,18 @@ static u64 arm_spe_event_to_pmsfcr(struct perf_event *event) struct perf_event_attr *attr = &event->attr; u64 reg = 0; - reg |= ATTR_CFG_GET_FLD(attr, load_filter) << SYS_PMSFCR_EL1_LD_SHIFT; - reg |= ATTR_CFG_GET_FLD(attr, store_filter) << SYS_PMSFCR_EL1_ST_SHIFT; - reg |= ATTR_CFG_GET_FLD(attr, branch_filter) << SYS_PMSFCR_EL1_B_SHIFT; + reg |= ATTR_CFG_GET_FLD(attr, load_filter) << PMSFCR_EL1_LD_SHIFT; + reg |= ATTR_CFG_GET_FLD(attr, store_filter) << PMSFCR_EL1_ST_SHIFT; + reg |= ATTR_CFG_GET_FLD(attr, branch_filter) << PMSFCR_EL1_B_SHIFT; if (reg) - reg |= BIT(SYS_PMSFCR_EL1_FT_SHIFT); + reg |= BIT(PMSFCR_EL1_FT_SHIFT); if (ATTR_CFG_GET_FLD(attr, event_filter)) - reg |= BIT(SYS_PMSFCR_EL1_FE_SHIFT); + reg |= BIT(PMSFCR_EL1_FE_SHIFT); if (ATTR_CFG_GET_FLD(attr, min_latency)) - reg |= BIT(SYS_PMSFCR_EL1_FL_SHIFT); + reg |= BIT(PMSFCR_EL1_FL_SHIFT); return reg; } @@ -359,7 +359,7 @@ static u64 arm_spe_event_to_pmslatfr(struct perf_event *event) { struct perf_event_attr *attr = &event->attr; return ATTR_CFG_GET_FLD(attr, min_latency) - << SYS_PMSLATFR_EL1_MINLAT_SHIFT; + << PMSLATFR_EL1_MINLAT_SHIFT; } static void arm_spe_pmu_pad_buf(struct perf_output_handle *handle, int len) @@ -511,7 +511,7 @@ static void arm_spe_perf_aux_output_begin(struct perf_output_handle *handle, limit = buf->snapshot ? arm_spe_pmu_next_snapshot_off(handle) : arm_spe_pmu_next_off(handle); if (limit) - limit |= BIT(SYS_PMBLIMITR_EL1_E_SHIFT); + limit |= BIT(PMBLIMITR_EL1_E_SHIFT); limit += (u64)buf->base; base = (u64)buf->base + PERF_IDX2OFF(handle->head, buf); @@ -570,28 +570,28 @@ arm_spe_pmu_buf_get_fault_act(struct perf_output_handle *handle) /* Service required? */ pmbsr = read_sysreg_s(SYS_PMBSR_EL1); - if (!(pmbsr & BIT(SYS_PMBSR_EL1_S_SHIFT))) + if (!(pmbsr & BIT(PMBSR_EL1_S_SHIFT))) return SPE_PMU_BUF_FAULT_ACT_SPURIOUS; /* * If we've lost data, disable profiling and also set the PARTIAL * flag to indicate that the last record is corrupted. */ - if (pmbsr & BIT(SYS_PMBSR_EL1_DL_SHIFT)) + if (pmbsr & BIT(PMBSR_EL1_DL_SHIFT)) perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED | PERF_AUX_FLAG_PARTIAL); /* Report collisions to userspace so that it can up the period */ - if (pmbsr & BIT(SYS_PMBSR_EL1_COLL_SHIFT)) + if (pmbsr & BIT(PMBSR_EL1_COLL_SHIFT)) perf_aux_output_flag(handle, PERF_AUX_FLAG_COLLISION); /* We only expect buffer management events */ - switch (pmbsr & (SYS_PMBSR_EL1_EC_MASK << SYS_PMBSR_EL1_EC_SHIFT)) { - case SYS_PMBSR_EL1_EC_BUF: + switch (FIELD_GET(PMBSR_EL1_EC_MASK, pmbsr)) { + case PMBSR_EL1_EC_BUF: /* Handled below */ break; - case SYS_PMBSR_EL1_EC_FAULT_S1: - case SYS_PMBSR_EL1_EC_FAULT_S2: + case PMBSR_EL1_EC_FAULT_S1: + case PMBSR_EL1_EC_FAULT_S2: err_str = "Unexpected buffer fault"; goto out_err; default: @@ -600,9 +600,8 @@ arm_spe_pmu_buf_get_fault_act(struct perf_output_handle *handle) } /* Buffer management event */ - switch (pmbsr & - (SYS_PMBSR_EL1_BUF_BSC_MASK << SYS_PMBSR_EL1_BUF_BSC_SHIFT)) { - case SYS_PMBSR_EL1_BUF_BSC_FULL: + switch (FIELD_GET(PMBSR_EL1_BUF_BSC_MASK, pmbsr)) { + case PMBSR_EL1_BUF_BSC_FULL: ret = SPE_PMU_BUF_FAULT_ACT_OK; goto out_stop; default: @@ -717,23 +716,23 @@ static int arm_spe_pmu_event_init(struct perf_event *event) return -EINVAL; reg = arm_spe_event_to_pmsfcr(event); - if ((reg & BIT(SYS_PMSFCR_EL1_FE_SHIFT)) && + if ((reg & BIT(PMSFCR_EL1_FE_SHIFT)) && !(spe_pmu->features & SPE_PMU_FEAT_FILT_EVT)) return -EOPNOTSUPP; - if ((reg & BIT(SYS_PMSFCR_EL1_FT_SHIFT)) && + if ((reg & BIT(PMSFCR_EL1_FT_SHIFT)) && !(spe_pmu->features & SPE_PMU_FEAT_FILT_TYP)) return -EOPNOTSUPP; - if ((reg & BIT(SYS_PMSFCR_EL1_FL_SHIFT)) && + if ((reg & BIT(PMSFCR_EL1_FL_SHIFT)) && !(spe_pmu->features & SPE_PMU_FEAT_FILT_LAT)) return -EOPNOTSUPP; set_spe_event_has_cx(event); reg = arm_spe_event_to_pmscr(event); if (!perfmon_capable() && - (reg & (BIT(SYS_PMSCR_EL1_PA_SHIFT) | - BIT(SYS_PMSCR_EL1_PCT_SHIFT)))) + (reg & (BIT(PMSCR_EL1_PA_SHIFT) | + BIT(PMSCR_EL1_PCT_SHIFT)))) return -EACCES; return 0; @@ -971,14 +970,14 @@ static void __arm_spe_pmu_dev_probe(void *info) /* Read PMBIDR first to determine whether or not we have access */ reg = read_sysreg_s(SYS_PMBIDR_EL1); - if (reg & BIT(SYS_PMBIDR_EL1_P_SHIFT)) { + if (reg & BIT(PMBIDR_EL1_P_SHIFT)) { dev_err(dev, "profiling buffer owned by higher exception level\n"); return; } /* Minimum alignment. If it's out-of-range, then fail the probe */ - fld = reg >> SYS_PMBIDR_EL1_ALIGN_SHIFT & SYS_PMBIDR_EL1_ALIGN_MASK; + fld = (reg & PMBIDR_EL1_ALIGN_MASK) >> PMBIDR_EL1_ALIGN_SHIFT; spe_pmu->align = 1 << fld; if (spe_pmu->align > SZ_2K) { dev_err(dev, "unsupported PMBIDR.Align [%d] on CPU %d\n", @@ -988,26 +987,26 @@ static void __arm_spe_pmu_dev_probe(void *info) /* It's now safe to read PMSIDR and figure out what we've got */ reg = read_sysreg_s(SYS_PMSIDR_EL1); - if (reg & BIT(SYS_PMSIDR_EL1_FE_SHIFT)) + if (reg & BIT(PMSIDR_EL1_FE_SHIFT)) spe_pmu->features |= SPE_PMU_FEAT_FILT_EVT; - if (reg & BIT(SYS_PMSIDR_EL1_FT_SHIFT)) + if (reg & BIT(PMSIDR_EL1_FT_SHIFT)) spe_pmu->features |= SPE_PMU_FEAT_FILT_TYP; - if (reg & BIT(SYS_PMSIDR_EL1_FL_SHIFT)) + if (reg & BIT(PMSIDR_EL1_FL_SHIFT)) spe_pmu->features |= SPE_PMU_FEAT_FILT_LAT; - if (reg & BIT(SYS_PMSIDR_EL1_ARCHINST_SHIFT)) + if (reg & BIT(PMSIDR_EL1_ARCHINST_SHIFT)) spe_pmu->features |= SPE_PMU_FEAT_ARCH_INST; - if (reg & BIT(SYS_PMSIDR_EL1_LDS_SHIFT)) + if (reg & BIT(PMSIDR_EL1_LDS_SHIFT)) spe_pmu->features |= SPE_PMU_FEAT_LDS; - if (reg & BIT(SYS_PMSIDR_EL1_ERND_SHIFT)) + if (reg & BIT(PMSIDR_EL1_ERND_SHIFT)) spe_pmu->features |= SPE_PMU_FEAT_ERND; /* This field has a spaced out encoding, so just use a look-up */ - fld = reg >> SYS_PMSIDR_EL1_INTERVAL_SHIFT & SYS_PMSIDR_EL1_INTERVAL_MASK; + fld = (reg & PMSIDR_EL1_INTERVAL_MASK) >> PMSIDR_EL1_INTERVAL_SHIFT; switch (fld) { case 0: spe_pmu->min_period = 256; @@ -1039,7 +1038,7 @@ static void __arm_spe_pmu_dev_probe(void *info) } /* Maximum record size. If it's out-of-range, then fail the probe */ - fld = reg >> SYS_PMSIDR_EL1_MAXSIZE_SHIFT & SYS_PMSIDR_EL1_MAXSIZE_MASK; + fld = (reg & PMSIDR_EL1_MAXSIZE_MASK) >> PMSIDR_EL1_MAXSIZE_SHIFT; spe_pmu->max_record_sz = 1 << fld; if (spe_pmu->max_record_sz > SZ_2K || spe_pmu->max_record_sz < 16) { dev_err(dev, "unsupported PMSIDR_EL1.MaxSize [%d] on CPU %d\n", @@ -1047,7 +1046,7 @@ static void __arm_spe_pmu_dev_probe(void *info) return; } - fld = reg >> SYS_PMSIDR_EL1_COUNTSIZE_SHIFT & SYS_PMSIDR_EL1_COUNTSIZE_MASK; + fld = (reg & PMSIDR_EL1_COUNTSIZE_MASK) >> PMSIDR_EL1_COUNTSIZE_SHIFT; switch (fld) { default: dev_warn(dev, "unknown PMSIDR_EL1.CountSize [%d]; assuming 2\n", From patchwork Fri Nov 4 15:55:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Rob Herring (Arm)" X-Patchwork-Id: 13032228 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DA9F3C433FE for ; Fri, 4 Nov 2022 15:56:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References:Message-Id :MIME-Version:Subject:Date:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=kC3IB1khDU4Lxke4xxknFM19V9zO0cKNAqARMMMbd6g=; b=uRSEcOl9bpgmFU lJ4JI+hoQtAvUBPT6tUVixiIGG4CVBg07VcK0uulYpnG1Vd2dMqUpwtdxFNHGUZbU1HNQmNHjexQp PcDcAxMlSu7AAeG3tDIvepMzYfjq1Gbu/SispNfzt/HA7yaIbkBKTJ+SPxZ8ug72WLQIwAycJGyxs uo7EpU+/zb/RHcqqUAKFbsl40dXYUF5qsdiQ1XS+tYtb4lhZJJFOtxFp+6AKugfGwTEBlJSL54F88 BUXDwi7lZwH8SMsome4seW+/QQWaxomKr/a5IYLYrux7DG5TGUo449pNwYR3bRD9pXRXbDtMjbFQC VACAF8V8m+Xhx52HPXKg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oqz2c-004LPY-83; Fri, 04 Nov 2022 15:55:34 +0000 Received: from mail-oa1-f49.google.com ([209.85.160.49]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oqz2O-004LIi-Qp for linux-arm-kernel@lists.infradead.org; Fri, 04 Nov 2022 15:55:22 +0000 Received: by mail-oa1-f49.google.com with SMTP id 586e51a60fabf-13b23e29e36so5949220fac.8 for ; Fri, 04 Nov 2022 08:55:19 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UEANOaGnOLKPIxD2FErExSJrTxX7DU5rJvRw0e3bF80=; b=wvi5mCsySjraUeRHk1BplrwHyxJ3+juGC50YVgINkcapTzQpDtlLi1GNQr3OhGZkmZ TxZGyrR+F4HRfZaIX3Ja5ibFWyjUutdtA2FtBhJ82Tn1tOpt+XZx0EpWQTcpLO6Tvvi+ dMJOVtv7Na0OuN8RYgPPVH+Wj7m7h1i2TAzKTqGlLpBfN72Mk0XXIgZwhmYJwEw8oKMD NMzukpOMSyBfGJwH17Te4hRotBMlaIMmfilJT6ivumI3woVM+6KbHqXlcIn5sCpMyTOa L/CNP2v8TX9PiJufh0PjvAI2gOT6Bylgz/aJYIo+d8hFlFJA+91TspQSm8/w6LlZEsTp hp8A== X-Gm-Message-State: ACrzQf1R69rp1DIDkVIxyoGQQAMG+OvZTOUVjmYEo+YRoc9aMedUPbZu 4umyaHQrO17izQE3A4Bgkw== X-Google-Smtp-Source: AMsMyM6WrFtmkapT1UrpNl2ZQAkfrsboc6K0XV+rMZwF1lg79gRvh93AF4KLZSe+/QOGuXp3fJ0Wbw== X-Received: by 2002:a05:6870:e2d6:b0:13c:a47a:c477 with SMTP id w22-20020a056870e2d600b0013ca47ac477mr22216403oad.269.1667577319209; Fri, 04 Nov 2022 08:55:19 -0700 (PDT) Received: from robh_at_kernel.org (66-90-144-107.dyn.grandenetworks.net. [66.90.144.107]) by smtp.gmail.com with ESMTPSA id x19-20020a056808145300b0034fc91dbd7bsm1608088oiv.58.2022.11.04.08.55.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Nov 2022 08:55:18 -0700 (PDT) Received: (nullmailer pid 1880414 invoked by uid 1000); Fri, 04 Nov 2022 15:55:18 -0000 From: Rob Herring Date: Fri, 04 Nov 2022 10:55:03 -0500 Subject: [PATCH v3 3/8] arm64/sysreg: Convert SPE registers to automatic generation MIME-Version: 1.0 Message-Id: <20220825-arm-spe-v8-7-v3-3-87682f78caac@kernel.org> References: <20220825-arm-spe-v8-7-v3-0-87682f78caac@kernel.org> In-Reply-To: <20220825-arm-spe-v8-7-v3-0-87682f78caac@kernel.org> To: Namhyung Kim , Will Deacon , Arnaldo Carvalho de Melo , Jiri Olsa , Peter Zijlstra , Alexander Shishkin , Mark Rutland , Catalin Marinas , Marc Zyngier , Oliver Upton , Ingo Molnar , Suzuki K Poulose , James Morse , Alexandru Elisei Cc: kvmarm@lists.linux.dev, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, James Clark , Mark Brown , linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu X-Mailer: b4 0.11.0-dev X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221104_085520_889622_221C3FBD X-CRM114-Status: GOOD ( 12.83 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Convert all the SPE register defines to automatic generation. No functional changes. New registers and fields for SPEv1.2 are added with the conversion. Some of the PMBSR MSS field defines are kept as the automatic generation has no way to create multiple names for the same register bits. The meaning of the MSS field depends on other bits. Tested-by: James Clark Signed-off-by: Rob Herring Reviewed-by: Mark Brown --- v3: - Make some fields enums and add some missing fields v2: - New patch --- arch/arm64/include/asm/sysreg.h | 91 ++------------------------ arch/arm64/tools/sysreg | 139 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 144 insertions(+), 86 deletions(-) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 8df8a0a51273..d002dd00e53e 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -237,99 +237,18 @@ #define SYS_PAR_EL1_FST GENMASK(6, 1) /*** Statistical Profiling Extension ***/ -/* ID registers */ -#define SYS_PMSIDR_EL1 sys_reg(3, 0, 9, 9, 7) -#define PMSIDR_EL1_FE_SHIFT 0 -#define PMSIDR_EL1_FT_SHIFT 1 -#define PMSIDR_EL1_FL_SHIFT 2 -#define PMSIDR_EL1_ARCHINST_SHIFT 3 -#define PMSIDR_EL1_LDS_SHIFT 4 -#define PMSIDR_EL1_ERND_SHIFT 5 -#define PMSIDR_EL1_INTERVAL_SHIFT 8 -#define PMSIDR_EL1_INTERVAL_MASK GENMASK_ULL(11, 8) -#define PMSIDR_EL1_MAXSIZE_SHIFT 12 -#define PMSIDR_EL1_MAXSIZE_MASK GENMASK_ULL(15, 12) -#define PMSIDR_EL1_COUNTSIZE_SHIFT 16 -#define PMSIDR_EL1_COUNTSIZE_MASK GENMASK_ULL(19, 16) - -#define SYS_PMBIDR_EL1 sys_reg(3, 0, 9, 10, 7) -#define PMBIDR_EL1_ALIGN_SHIFT 0 -#define PMBIDR_EL1_ALIGN_MASK 0xfU -#define PMBIDR_EL1_P_SHIFT 4 -#define PMBIDR_EL1_F_SHIFT 5 - -/* Sampling controls */ -#define SYS_PMSCR_EL1 sys_reg(3, 0, 9, 9, 0) -#define PMSCR_EL1_E0SPE_SHIFT 0 -#define PMSCR_EL1_E1SPE_SHIFT 1 -#define PMSCR_EL1_CX_SHIFT 3 -#define PMSCR_EL1_PA_SHIFT 4 -#define PMSCR_EL1_TS_SHIFT 5 -#define PMSCR_EL1_PCT_SHIFT 6 - -#define SYS_PMSCR_EL2 sys_reg(3, 4, 9, 9, 0) -#define PMSCR_EL2_E0HSPE_SHIFT 0 -#define PMSCR_EL2_E2SPE_SHIFT 1 -#define PMSCR_EL2_CX_SHIFT 3 -#define PMSCR_EL2_PA_SHIFT 4 -#define PMSCR_EL2_TS_SHIFT 5 -#define PMSCR_EL2_PCT_SHIFT 6 - -#define SYS_PMSICR_EL1 sys_reg(3, 0, 9, 9, 2) - -#define SYS_PMSIRR_EL1 sys_reg(3, 0, 9, 9, 3) -#define PMSIRR_EL1_RND_SHIFT 0 -#define PMSIRR_EL1_INTERVAL_SHIFT 8 -#define PMSIRR_EL1_INTERVAL_MASK GENMASK_ULL(31, 8) - -/* Filtering controls */ -#define SYS_PMSNEVFR_EL1 sys_reg(3, 0, 9, 9, 1) - -#define SYS_PMSFCR_EL1 sys_reg(3, 0, 9, 9, 4) -#define PMSFCR_EL1_FE_SHIFT 0 -#define PMSFCR_EL1_FT_SHIFT 1 -#define PMSFCR_EL1_FL_SHIFT 2 -#define PMSFCR_EL1_B_SHIFT 16 -#define PMSFCR_EL1_LD_SHIFT 17 -#define PMSFCR_EL1_ST_SHIFT 18 - -#define SYS_PMSEVFR_EL1 sys_reg(3, 0, 9, 9, 5) #define PMSEVFR_EL1_RES0_IMP \ (GENMASK_ULL(47, 32) | GENMASK_ULL(23, 16) | GENMASK_ULL(11, 8) |\ BIT_ULL(6) | BIT_ULL(4) | BIT_ULL(2) | BIT_ULL(0)) #define PMSEVFR_EL1_RES0_V1P1 \ (PMSEVFR_EL1_RES0_IMP & ~(BIT_ULL(18) | BIT_ULL(17) | BIT_ULL(11))) -#define SYS_PMSLATFR_EL1 sys_reg(3, 0, 9, 9, 6) -#define PMSLATFR_EL1_MINLAT_SHIFT 0 - -/* Buffer controls */ -#define SYS_PMBLIMITR_EL1 sys_reg(3, 0, 9, 10, 0) -#define PMBLIMITR_EL1_E_SHIFT 0 -#define PMBLIMITR_EL1_FM_SHIFT 1 -#define PMBLIMITR_EL1_FM_MASK GENMASK_ULL(2, 1) -#define PMBLIMITR_EL1_FM_STOP_IRQ 0 - -#define SYS_PMBPTR_EL1 sys_reg(3, 0, 9, 10, 1) - /* Buffer error reporting */ -#define SYS_PMBSR_EL1 sys_reg(3, 0, 9, 10, 3) -#define PMBSR_EL1_COLL_SHIFT 16 -#define PMBSR_EL1_S_SHIFT 17 -#define PMBSR_EL1_EA_SHIFT 18 -#define PMBSR_EL1_DL_SHIFT 19 -#define PMBSR_EL1_EC_SHIFT 26 -#define PMBSR_EL1_EC_MASK GENMASK_ULL(31, 26) - -#define PMBSR_EL1_EC_BUF 0x0UL -#define PMBSR_EL1_EC_FAULT_S1 0x24UL -#define PMBSR_EL1_EC_FAULT_S2 0x25UL - -#define PMBSR_EL1_FAULT_FSC_SHIFT 0 -#define PMBSR_EL1_FAULT_FSC_MASK 0x3fUL - -#define PMBSR_EL1_BUF_BSC_SHIFT 0 -#define PMBSR_EL1_BUF_BSC_MASK 0x3fUL +#define PMBSR_EL1_FAULT_FSC_SHIFT PMBSR_EL1_MSS_SHIFT +#define PMBSR_EL1_FAULT_FSC_MASK PMBSR_EL1_MSS_MASK + +#define PMBSR_EL1_BUF_BSC_SHIFT PMBSR_EL1_MSS_SHIFT +#define PMBSR_EL1_BUF_BSC_MASK PMBSR_EL1_MSS_MASK #define PMBSR_EL1_BUF_BSC_FULL 0x1UL diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 384757a7eda9..04741f446c46 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -854,6 +854,130 @@ Sysreg FAR_EL1 3 0 6 0 0 Field 63:0 ADDR EndSysreg +Sysreg PMSCR_EL1 3 0 9 9 0 +Res0 63:8 +Field 7:6 PCT +Field 5 TS +Field 4 PA +Field 3 CX +Res0 2 +Field 1 E1SPE +Field 0 E0SPE +EndSysreg + +Sysreg PMSNEVFR_EL1 3 0 9 9 1 +Field 63:0 E +EndSysreg + +Sysreg PMSICR_EL1 3 0 9 9 2 +Field 63:56 ECOUNT +Res0 55:32 +Field 31:0 COUNT +EndSysreg + +Sysreg PMSIRR_EL1 3 0 9 9 3 +Res0 63:32 +Field 31:8 INTERVAL +Res0 7:1 +Field 0 RND +EndSysreg + +Sysreg PMSFCR_EL1 3 0 9 9 4 +Res0 63:19 +Field 18 ST +Field 17 LD +Field 16 B +Res0 15:4 +Field 3 FnE +Field 2 FL +Field 1 FT +Field 0 FE +EndSysreg + +Sysreg PMSEVFR_EL1 3 0 9 9 5 +Field 63:0 E +EndSysreg + +Sysreg PMSLATFR_EL1 3 0 9 9 6 +Res0 63:16 +Field 15:0 MINLAT +EndSysreg + +Sysreg PMSIDR_EL1 3 0 9 9 7 +Res0 63:25 +Field 24 PBT +Field 23:20 FORMAT +Enum 19:16 COUNTSIZE + 0b0010 12_BIT_SAT + 0b0011 16_BIT_SAT +EndEnum +Field 15:12 MAXSIZE +Enum 11:8 INTERVAL + 0b0000 256 + 0b0010 512 + 0b0011 768 + 0b0100 1024 + 0b0101 1536 + 0b0110 2048 + 0b0111 3072 + 0b1000 4096 +EndEnum +Res0 7 +Field 6 FnE +Field 5 ERND +Field 4 LDS +Field 3 ARCHINST +Field 2 FL +Field 1 FT +Field 0 FE +EndSysreg + +Sysreg PMBLIMITR_EL1 3 0 9 10 0 +Field 63:12 LIMIT +Res0 11:6 +Field 5 PMFZ +Res0 4:3 +Enum 2:1 FM + 0b00 FILL + 0b10 DISCARD +EndEnum +Field 0 E +EndSysreg + +Sysreg PMBPTR_EL1 3 0 9 10 1 +Field 63:0 PTR +EndSysreg + +Sysreg PMBSR_EL1 3 0 9 10 3 +Res0 63:32 +Enum 31:26 EC + 0b000000 BUF + 0b100100 FAULT_S1 + 0b100101 FAULT_S2 + 0b011110 FAULT_GPC + 0b011111 IMP_DEF +EndEnum +Res0 25:20 +Field 19 DL +Field 18 EA +Field 17 S +Field 16 COLL +Field 15:0 MSS +EndSysreg + +Sysreg PMBIDR_EL1 3 0 9 10 7 +Res0 63:12 +Enum 11:8 EA + 0b0000 NotDescribed + 0b0001 Ignored + 0b0010 SError +EndEnum +Res0 7:6 +Field 5 F +Field 4 P +Field 3:0 ALIGN +EndSysreg + SysregFields CONTEXTIDR_ELx Res0 63:32 Field 31:0 PROCID @@ -1008,6 +1132,21 @@ Sysreg FAR_EL2 3 4 6 0 0 Field 63:0 ADDR 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[66.90.144.107]) by smtp.gmail.com with ESMTPSA id v20-20020a4ac014000000b0049052c66126sm1278110oop.2.2022.11.04.08.55.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Nov 2022 08:55:25 -0700 (PDT) Received: (nullmailer pid 1880416 invoked by uid 1000); Fri, 04 Nov 2022 15:55:18 -0000 From: Rob Herring Date: Fri, 04 Nov 2022 10:55:04 -0500 Subject: [PATCH v3 4/8] perf: arm_spe: Drop BIT() and use FIELD_GET/PREP accessors MIME-Version: 1.0 Message-Id: <20220825-arm-spe-v8-7-v3-4-87682f78caac@kernel.org> References: <20220825-arm-spe-v8-7-v3-0-87682f78caac@kernel.org> In-Reply-To: <20220825-arm-spe-v8-7-v3-0-87682f78caac@kernel.org> To: Namhyung Kim , Will Deacon , Arnaldo Carvalho de Melo , Jiri Olsa , Peter Zijlstra , Alexander Shishkin , Mark Rutland , Catalin Marinas , Marc Zyngier , Oliver Upton , Ingo Molnar , Suzuki K Poulose , James Morse , Alexandru Elisei Cc: kvmarm@lists.linux.dev, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, James Clark , Mark Brown , linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu X-Mailer: b4 0.11.0-dev X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221104_085528_314092_5A77B1FD X-CRM114-Status: GOOD ( 18.56 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Now that generated sysregs are in place, update the register field accesses. The use of BIT() is no longer needed with the new defines. Use FIELD_GET and FIELD_PREP instead of open coding masking and shifting. No functional change. Tested-by: James Clark Signed-off-by: Rob Herring --- v3: - no change --- drivers/perf/arm_spe_pmu.c | 70 ++++++++++++++++++++++------------------------ 1 file changed, 34 insertions(+), 36 deletions(-) diff --git a/drivers/perf/arm_spe_pmu.c b/drivers/perf/arm_spe_pmu.c index 814ed18346b6..9b4bd72087ea 100644 --- a/drivers/perf/arm_spe_pmu.c +++ b/drivers/perf/arm_spe_pmu.c @@ -283,18 +283,18 @@ static u64 arm_spe_event_to_pmscr(struct perf_event *event) struct perf_event_attr *attr = &event->attr; u64 reg = 0; - reg |= ATTR_CFG_GET_FLD(attr, ts_enable) << PMSCR_EL1_TS_SHIFT; - reg |= ATTR_CFG_GET_FLD(attr, pa_enable) << PMSCR_EL1_PA_SHIFT; - reg |= ATTR_CFG_GET_FLD(attr, pct_enable) << PMSCR_EL1_PCT_SHIFT; + reg |= FIELD_PREP(PMSCR_EL1_TS, ATTR_CFG_GET_FLD(attr, ts_enable)); + reg |= FIELD_PREP(PMSCR_EL1_PA, ATTR_CFG_GET_FLD(attr, pa_enable)); + reg |= FIELD_PREP(PMSCR_EL1_PCT, ATTR_CFG_GET_FLD(attr, pct_enable)); if (!attr->exclude_user) - reg |= BIT(PMSCR_EL1_E0SPE_SHIFT); + reg |= PMSCR_EL1_E0SPE; if (!attr->exclude_kernel) - reg |= BIT(PMSCR_EL1_E1SPE_SHIFT); + reg |= PMSCR_EL1_E1SPE; if (get_spe_event_has_cx(event)) - reg |= BIT(PMSCR_EL1_CX_SHIFT); + reg |= PMSCR_EL1_CX; return reg; } @@ -322,7 +322,7 @@ static u64 arm_spe_event_to_pmsirr(struct perf_event *event) arm_spe_event_sanitise_period(event); - reg |= ATTR_CFG_GET_FLD(attr, jitter) << PMSIRR_EL1_RND_SHIFT; + reg |= FIELD_PREP(PMSIRR_EL1_RND, ATTR_CFG_GET_FLD(attr, jitter)); reg |= event->hw.sample_period; return reg; @@ -333,18 +333,18 @@ static u64 arm_spe_event_to_pmsfcr(struct perf_event *event) struct perf_event_attr *attr = &event->attr; u64 reg = 0; - reg |= ATTR_CFG_GET_FLD(attr, load_filter) << PMSFCR_EL1_LD_SHIFT; - reg |= ATTR_CFG_GET_FLD(attr, store_filter) << PMSFCR_EL1_ST_SHIFT; - reg |= ATTR_CFG_GET_FLD(attr, branch_filter) << PMSFCR_EL1_B_SHIFT; + reg |= FIELD_PREP(PMSFCR_EL1_LD, ATTR_CFG_GET_FLD(attr, load_filter)); + reg |= FIELD_PREP(PMSFCR_EL1_ST, ATTR_CFG_GET_FLD(attr, store_filter)); + reg |= FIELD_PREP(PMSFCR_EL1_B, ATTR_CFG_GET_FLD(attr, branch_filter)); if (reg) - reg |= BIT(PMSFCR_EL1_FT_SHIFT); + reg |= PMSFCR_EL1_FT; if (ATTR_CFG_GET_FLD(attr, event_filter)) - reg |= BIT(PMSFCR_EL1_FE_SHIFT); + reg |= PMSFCR_EL1_FE; if (ATTR_CFG_GET_FLD(attr, min_latency)) - reg |= BIT(PMSFCR_EL1_FL_SHIFT); + reg |= PMSFCR_EL1_FL; return reg; } @@ -358,8 +358,7 @@ static u64 arm_spe_event_to_pmsevfr(struct perf_event *event) static u64 arm_spe_event_to_pmslatfr(struct perf_event *event) { struct perf_event_attr *attr = &event->attr; - return ATTR_CFG_GET_FLD(attr, min_latency) - << PMSLATFR_EL1_MINLAT_SHIFT; + return FIELD_PREP(PMSLATFR_EL1_MINLAT, ATTR_CFG_GET_FLD(attr, min_latency)); } static void arm_spe_pmu_pad_buf(struct perf_output_handle *handle, int len) @@ -511,7 +510,7 @@ static void arm_spe_perf_aux_output_begin(struct perf_output_handle *handle, limit = buf->snapshot ? arm_spe_pmu_next_snapshot_off(handle) : arm_spe_pmu_next_off(handle); if (limit) - limit |= BIT(PMBLIMITR_EL1_E_SHIFT); + limit |= PMBLIMITR_EL1_E; limit += (u64)buf->base; base = (u64)buf->base + PERF_IDX2OFF(handle->head, buf); @@ -570,23 +569,23 @@ arm_spe_pmu_buf_get_fault_act(struct perf_output_handle *handle) /* Service required? */ pmbsr = read_sysreg_s(SYS_PMBSR_EL1); - if (!(pmbsr & BIT(PMBSR_EL1_S_SHIFT))) + if (!FIELD_GET(PMBSR_EL1_S, pmbsr)) return SPE_PMU_BUF_FAULT_ACT_SPURIOUS; /* * If we've lost data, disable profiling and also set the PARTIAL * flag to indicate that the last record is corrupted. */ - if (pmbsr & BIT(PMBSR_EL1_DL_SHIFT)) + if (FIELD_GET(PMBSR_EL1_DL, pmbsr)) perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED | PERF_AUX_FLAG_PARTIAL); /* Report collisions to userspace so that it can up the period */ - if (pmbsr & BIT(PMBSR_EL1_COLL_SHIFT)) + if (FIELD_GET(PMBSR_EL1_COLL, pmbsr)) perf_aux_output_flag(handle, PERF_AUX_FLAG_COLLISION); /* We only expect buffer management events */ - switch (FIELD_GET(PMBSR_EL1_EC_MASK, pmbsr)) { + switch (FIELD_GET(PMBSR_EL1_EC, pmbsr)) { case PMBSR_EL1_EC_BUF: /* Handled below */ break; @@ -716,23 +715,22 @@ static int arm_spe_pmu_event_init(struct perf_event *event) return -EINVAL; reg = arm_spe_event_to_pmsfcr(event); - if ((reg & BIT(PMSFCR_EL1_FE_SHIFT)) && + if ((FIELD_GET(PMSFCR_EL1_FE, reg)) && !(spe_pmu->features & SPE_PMU_FEAT_FILT_EVT)) return -EOPNOTSUPP; - if ((reg & BIT(PMSFCR_EL1_FT_SHIFT)) && + if ((FIELD_GET(PMSFCR_EL1_FT, reg)) && !(spe_pmu->features & SPE_PMU_FEAT_FILT_TYP)) return -EOPNOTSUPP; - if ((reg & BIT(PMSFCR_EL1_FL_SHIFT)) && + if ((FIELD_GET(PMSFCR_EL1_FL, reg)) && !(spe_pmu->features & SPE_PMU_FEAT_FILT_LAT)) return -EOPNOTSUPP; set_spe_event_has_cx(event); reg = arm_spe_event_to_pmscr(event); if (!perfmon_capable() && - (reg & (BIT(PMSCR_EL1_PA_SHIFT) | - BIT(PMSCR_EL1_PCT_SHIFT)))) + (reg & (PMSCR_EL1_PA | PMSCR_EL1_PCT))) return -EACCES; return 0; @@ -970,14 +968,14 @@ static void __arm_spe_pmu_dev_probe(void *info) /* Read PMBIDR first to determine whether or not we have access */ reg = read_sysreg_s(SYS_PMBIDR_EL1); - if (reg & BIT(PMBIDR_EL1_P_SHIFT)) { + if (FIELD_GET(PMBIDR_EL1_P, reg)) { dev_err(dev, "profiling buffer owned by higher exception level\n"); return; } /* Minimum alignment. If it's out-of-range, then fail the probe */ - fld = (reg & PMBIDR_EL1_ALIGN_MASK) >> PMBIDR_EL1_ALIGN_SHIFT; + fld = FIELD_GET(PMBIDR_EL1_ALIGN, reg); spe_pmu->align = 1 << fld; if (spe_pmu->align > SZ_2K) { dev_err(dev, "unsupported PMBIDR.Align [%d] on CPU %d\n", @@ -987,26 +985,26 @@ static void __arm_spe_pmu_dev_probe(void *info) /* It's now safe to read PMSIDR and figure out what we've got */ reg = read_sysreg_s(SYS_PMSIDR_EL1); - if (reg & BIT(PMSIDR_EL1_FE_SHIFT)) + if (FIELD_GET(PMSIDR_EL1_FE, reg)) spe_pmu->features |= SPE_PMU_FEAT_FILT_EVT; - if (reg & BIT(PMSIDR_EL1_FT_SHIFT)) + if (FIELD_GET(PMSIDR_EL1_FT, reg)) spe_pmu->features |= SPE_PMU_FEAT_FILT_TYP; - if (reg & BIT(PMSIDR_EL1_FL_SHIFT)) + if (FIELD_GET(PMSIDR_EL1_FL, reg)) spe_pmu->features |= SPE_PMU_FEAT_FILT_LAT; - if (reg & BIT(PMSIDR_EL1_ARCHINST_SHIFT)) + if (FIELD_GET(PMSIDR_EL1_ARCHINST, reg)) spe_pmu->features |= SPE_PMU_FEAT_ARCH_INST; - if (reg & BIT(PMSIDR_EL1_LDS_SHIFT)) + if (FIELD_GET(PMSIDR_EL1_LDS, reg)) spe_pmu->features |= SPE_PMU_FEAT_LDS; - if (reg & BIT(PMSIDR_EL1_ERND_SHIFT)) + if (FIELD_GET(PMSIDR_EL1_ERND, reg)) spe_pmu->features |= SPE_PMU_FEAT_ERND; /* This field has a spaced out encoding, so just use a look-up */ - fld = (reg & PMSIDR_EL1_INTERVAL_MASK) >> PMSIDR_EL1_INTERVAL_SHIFT; + fld = FIELD_GET(PMSIDR_EL1_INTERVAL, reg); switch (fld) { case 0: spe_pmu->min_period = 256; @@ -1038,7 +1036,7 @@ static void __arm_spe_pmu_dev_probe(void *info) } /* Maximum record size. If it's out-of-range, then fail the probe */ - fld = (reg & PMSIDR_EL1_MAXSIZE_MASK) >> PMSIDR_EL1_MAXSIZE_SHIFT; + fld = FIELD_GET(PMSIDR_EL1_MAXSIZE, reg); spe_pmu->max_record_sz = 1 << fld; if (spe_pmu->max_record_sz > SZ_2K || spe_pmu->max_record_sz < 16) { dev_err(dev, "unsupported PMSIDR_EL1.MaxSize [%d] on CPU %d\n", @@ -1046,7 +1044,7 @@ static void __arm_spe_pmu_dev_probe(void *info) return; } - fld = (reg & PMSIDR_EL1_COUNTSIZE_MASK) >> PMSIDR_EL1_COUNTSIZE_SHIFT; + fld = FIELD_GET(PMSIDR_EL1_COUNTSIZE, reg); switch (fld) { default: dev_warn(dev, "unknown PMSIDR_EL1.CountSize [%d]; assuming 2\n", From patchwork Fri Nov 4 15:55:05 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Rob Herring (Arm)" X-Patchwork-Id: 13032242 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4601EC433FE for ; Fri, 4 Nov 2022 15:58:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References:Message-Id :MIME-Version:Subject:Date:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=AXt9Xe1qojjA19e5GOkmgDH71mqa9rUyVp8qGVIdvbo=; b=uoQcH+385kf3Jq 9ZLSdmhqcPiHQHXhfNRdwH4zfIDJuxfTOjrFPiLvcNSUQf2POEJ/uu9abM/mxo3H2g3ufvOIwIll5 QBj6Wd0ALEPnM3s7Kc3IOaZbBrueNkWE4h33UJhQOgYR0UYzvmrnXFhEptq0AhN+9gUuzxCRPjSjd yB5OrRqUXvRx/lUN47cKUH0/hVUyR9J/mmtMrTa3YJljT5DUzQYRext35hMSEu3Zb/AEoo+xpDnrg ySN3cN2iQmPs9mQKhtjVSJkQ5jNAZlXHok4I9S5dJARxJoHFtsXIHk/p5jeLJe1hhaHoUfG1VLznz CBpJNKSVbh6jQXwbHibg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oqz3y-004LxH-Td; Fri, 04 Nov 2022 15:56:59 +0000 Received: from mail-oi1-f173.google.com ([209.85.167.173]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oqz2Y-004LNE-MF for linux-arm-kernel@lists.infradead.org; Fri, 04 Nov 2022 15:55:34 +0000 Received: by mail-oi1-f173.google.com with SMTP id s206so5608843oie.3 for ; Fri, 04 Nov 2022 08:55:28 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YXxvA5Cmwe9nSMxNL2yH3Amn9qhEZ+Ppqa0CVXQahDM=; b=39ktqM7/HeVwYeNIBM4wx5zrTnW+A7JfszF79gayK2PAd3jKjm9w3owVxLcNRyApBL CqTWMV9600O4f2vZikTt1qshXdpybbLPq+8qjT3Z0WaaXjQ9tpZ+KZ0bzjCA9YA8r6AD Lg0k7ZRwUNKC11NSa+p24qQiiO6I/mb8VQCiRZM1M+JvURWXZocLTzLnsNqeJamU5n/A sk/1AdhfKAsTaEmdhC/e+pCLWHAIZrj6LN+0dOhtjBaObsTWom9KqFp3FyuQxbROkKTQ Z8ajy7TaVG485eaxUNOF8RkeV68DiNoo4TSKQMOZNwdsUeTHguIGsByY0wq0gu/8x3Cv fFQw== X-Gm-Message-State: ACrzQf27LWoCP442Zu1kvbyLY42J1M4obKToHGqCgD2vawQBhXVfJ/Nd iC50VJLaRQhWRO+CMRKtUw== X-Google-Smtp-Source: AMsMyM7j75hsQAjfZIMDag+E+uxVO086sbySFKGpZQmxBHGiFVlWgpE6vfapy3lhNwjdU+847kbdBg== X-Received: by 2002:a05:6808:2023:b0:359:c826:8085 with SMTP id q35-20020a056808202300b00359c8268085mr19906327oiw.156.1667577328221; Fri, 04 Nov 2022 08:55:28 -0700 (PDT) Received: from robh_at_kernel.org (66-90-144-107.dyn.grandenetworks.net. [66.90.144.107]) by smtp.gmail.com with ESMTPSA id h4-20020a9d2f04000000b00661a3f4113bsm1532860otb.64.2022.11.04.08.55.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Nov 2022 08:55:27 -0700 (PDT) Received: (nullmailer pid 1880418 invoked by uid 1000); Fri, 04 Nov 2022 15:55:18 -0000 From: Rob Herring Date: Fri, 04 Nov 2022 10:55:05 -0500 Subject: [PATCH v3 5/8] perf: arm_spe: Use new PMSIDR_EL1 register enums MIME-Version: 1.0 Message-Id: <20220825-arm-spe-v8-7-v3-5-87682f78caac@kernel.org> References: <20220825-arm-spe-v8-7-v3-0-87682f78caac@kernel.org> In-Reply-To: <20220825-arm-spe-v8-7-v3-0-87682f78caac@kernel.org> To: Namhyung Kim , Will Deacon , Arnaldo Carvalho de Melo , Jiri Olsa , Peter Zijlstra , Alexander Shishkin , Mark Rutland , Catalin Marinas , Marc Zyngier , Oliver Upton , Ingo Molnar , Suzuki K Poulose , James Morse , Alexandru Elisei Cc: kvmarm@lists.linux.dev, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, James Clark , Mark Brown , linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu X-Mailer: b4 0.11.0-dev X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221104_085530_762551_F826C429 X-CRM114-Status: GOOD ( 11.77 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Now that the SPE register definitions include enums for some PMSIDR_EL1 fields, use them in the driver in place of magic values. Signed-off-by: Rob Herring --- v3: New patch --- drivers/perf/arm_spe_pmu.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/perf/arm_spe_pmu.c b/drivers/perf/arm_spe_pmu.c index 9b4bd72087ea..af6d3867c3e7 100644 --- a/drivers/perf/arm_spe_pmu.c +++ b/drivers/perf/arm_spe_pmu.c @@ -1006,32 +1006,32 @@ static void __arm_spe_pmu_dev_probe(void *info) /* This field has a spaced out encoding, so just use a look-up */ fld = FIELD_GET(PMSIDR_EL1_INTERVAL, reg); switch (fld) { - case 0: + case PMSIDR_EL1_INTERVAL_256: spe_pmu->min_period = 256; break; - case 2: + case PMSIDR_EL1_INTERVAL_512: spe_pmu->min_period = 512; break; - case 3: + case PMSIDR_EL1_INTERVAL_768: spe_pmu->min_period = 768; break; - case 4: + case PMSIDR_EL1_INTERVAL_1024: spe_pmu->min_period = 1024; break; - case 5: + case PMSIDR_EL1_INTERVAL_1536: spe_pmu->min_period = 1536; break; - case 6: + case PMSIDR_EL1_INTERVAL_2048: spe_pmu->min_period = 2048; break; - case 7: + case PMSIDR_EL1_INTERVAL_3072: spe_pmu->min_period = 3072; break; default: dev_warn(dev, "unknown PMSIDR_EL1.Interval [%d]; assuming 8\n", fld); fallthrough; - case 8: + case PMSIDR_EL1_INTERVAL_4096: spe_pmu->min_period = 4096; } @@ -1050,10 +1050,10 @@ static void __arm_spe_pmu_dev_probe(void *info) dev_warn(dev, "unknown PMSIDR_EL1.CountSize [%d]; assuming 2\n", fld); fallthrough; - case 2: + case PMSIDR_EL1_COUNTSIZE_12_BIT_SAT: spe_pmu->counter_sz = 12; break; - case 3: + case PMSIDR_EL1_COUNTSIZE_16_BIT_SAT: spe_pmu->counter_sz = 16; } From patchwork Fri Nov 4 15:55:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Rob Herring (Arm)" X-Patchwork-Id: 13032238 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 82B75C433FE for ; Fri, 4 Nov 2022 15:57:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References:Message-Id :MIME-Version:Subject:Date:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=vnneGgUUi6GzOw6+NU/AwXiSZwfUPl1xJKohNBg9Ts4=; b=KyN0dlnI2Qlfux PYdXedNvTyb/QS6Nwg7iQbNjBJlxQlyZzoiJCdlVkIW9da7OAGEFJ6FIoL6nxICqSpPrfdRZqX3uQ bAUZQI2eOUi1uV2B2XWftDaUquDvtpLb33oObTzSnQhoJLuD4Bu5S3fTkJFHTimchXvj0vt2SNyd8 y3OMoSutUcD8ICKSTh5h0baEXV5ZCsFGvdkXqXuL+ypjxqUG1O5+uCBvnioxWp+mj6Av8/3Ee12nA DLyIJr+Whe4bpgz/nmmiP5lINBEb22aA+43rB8JNULB+1RrxA0lBtX09Nu49xjQ9H/dCrs154bE6W 1DnQMKQPj1V5QIZKd6KQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oqz2v-004LVL-M5; Fri, 04 Nov 2022 15:55:53 +0000 Received: from mail-oi1-f182.google.com ([209.85.167.182]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oqz2S-004LKK-6W for linux-arm-kernel@lists.infradead.org; Fri, 04 Nov 2022 15:55:27 +0000 Received: by mail-oi1-f182.google.com with SMTP id m204so5595888oib.6 for ; Fri, 04 Nov 2022 08:55:23 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1LuRWZ+uGAhH28zFK+adTPuM2Aq0aZSCcYB6eJqAff0=; b=xFr7QX4ynCbHGD+L5BrYjBHEJDr+VPZNBSc+r1anjLH2eGLVAJLvfM5uIes3lYIjG4 V31LQDUzX4w26GmOqOS6qz9TxZS8K7CVXpjGgs3brkfwtQYs3WZStwB7Pwj0yvOqRuLN DTToZNURFP+vRE60ZqP4g3sz6+5uemcyN6jDVkvMEg5Fdib+rR1BXIPw7ASzXOUXk42G buMgbUap//hlmnXGR8H/vl6urgKFwVe6RkXGRMIkjn74HV/7wNSXDEVZY51cL8kGQweM 4zmLUOkQOi0oPP73pQRTACKjKoDq7uci+LpeTMlnMZtX2GgaxM2jTV4jRKU6zSRCSF83 cN6g== X-Gm-Message-State: ACrzQf16CqG/2FMj5GOTdpIQPu6hijzyoK4DEg/0YRtZ6coEoTPIad1l Vbncn+tnPb7kNupJ5p5pzw== X-Google-Smtp-Source: AMsMyM4d6TDw2T7GbRam3QWG/Wa4RT72PM5DQk1E8uYmT91uYVnx3slmlmbYjUyO46tJ6RiQPcimSQ== X-Received: by 2002:a05:6808:1492:b0:353:f28f:6fb with SMTP id e18-20020a056808149200b00353f28f06fbmr258038oiw.246.1667577322632; Fri, 04 Nov 2022 08:55:22 -0700 (PDT) Received: from robh_at_kernel.org (66-90-144-107.dyn.grandenetworks.net. [66.90.144.107]) by smtp.gmail.com with ESMTPSA id z15-20020a056870e30f00b00136a0143de8sm1876818oad.40.2022.11.04.08.55.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Nov 2022 08:55:22 -0700 (PDT) Received: (nullmailer pid 1880420 invoked by uid 1000); Fri, 04 Nov 2022 15:55:18 -0000 From: Rob Herring Date: Fri, 04 Nov 2022 10:55:06 -0500 Subject: [PATCH v3 6/8] perf: arm_spe: Support new SPEv1.2/v8.7 'not taken' event MIME-Version: 1.0 Message-Id: <20220825-arm-spe-v8-7-v3-6-87682f78caac@kernel.org> References: <20220825-arm-spe-v8-7-v3-0-87682f78caac@kernel.org> In-Reply-To: <20220825-arm-spe-v8-7-v3-0-87682f78caac@kernel.org> To: Namhyung Kim , Will Deacon , Arnaldo Carvalho de Melo , Jiri Olsa , Peter Zijlstra , Alexander Shishkin , Mark Rutland , Catalin Marinas , Marc Zyngier , Oliver Upton , Ingo Molnar , Suzuki K Poulose , James Morse , Alexandru Elisei Cc: kvmarm@lists.linux.dev, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, James Clark , Mark Brown , linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu X-Mailer: b4 0.11.0-dev X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221104_085524_264130_4D345A26 X-CRM114-Status: GOOD ( 13.73 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Arm SPEv1.2 (Armv8.7/v9.2) adds a new event, 'not taken', in bit 6 of the PMSEVFR_EL1 register. Update arm_spe_pmsevfr_res0() to support the additional event. Tested-by: James Clark Signed-off-by: Rob Herring --- v3: - No change v2: - Update for v6.1 sysreg generated header changes --- arch/arm64/include/asm/sysreg.h | 2 ++ drivers/perf/arm_spe_pmu.c | 4 +++- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index d002dd00e53e..06231e896832 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -242,6 +242,8 @@ BIT_ULL(6) | BIT_ULL(4) | BIT_ULL(2) | BIT_ULL(0)) #define PMSEVFR_EL1_RES0_V1P1 \ (PMSEVFR_EL1_RES0_IMP & ~(BIT_ULL(18) | BIT_ULL(17) | BIT_ULL(11))) +#define PMSEVFR_EL1_RES0_V1P2 \ + (PMSEVFR_EL1_RES0_V1P1 & ~BIT_ULL(6)) /* Buffer error reporting */ #define PMBSR_EL1_FAULT_FSC_SHIFT PMBSR_EL1_MSS_SHIFT diff --git a/drivers/perf/arm_spe_pmu.c b/drivers/perf/arm_spe_pmu.c index af6d3867c3e7..82f67e941bc4 100644 --- a/drivers/perf/arm_spe_pmu.c +++ b/drivers/perf/arm_spe_pmu.c @@ -677,9 +677,11 @@ static u64 arm_spe_pmsevfr_res0(u16 pmsver) case ID_AA64DFR0_EL1_PMSVer_IMP: return PMSEVFR_EL1_RES0_IMP; case ID_AA64DFR0_EL1_PMSVer_V1P1: + return PMSEVFR_EL1_RES0_V1P1; + case ID_AA64DFR0_EL1_PMSVer_V1P2: /* Return the highest version we support in default */ default: - return PMSEVFR_EL1_RES0_V1P1; + return PMSEVFR_EL1_RES0_V1P2; } } From patchwork Fri Nov 4 15:55:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Rob Herring (Arm)" X-Patchwork-Id: 13032243 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 37D2FC4332F for ; Fri, 4 Nov 2022 15:58:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References:Message-Id :MIME-Version:Subject:Date:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=0DyFfTltXm26KJSNRStK+pziLq+9mXBWLmbB2ejutso=; b=qvsA91l0DcVzxz OmysHz1xB3L89On2KVetz6qGtqPjhBajG9zZ9yd/OuMa8v/52dLdXb30nLSv2qoJoQIz47l96wdj6 rpKVrvzMnxky+3xZaqDinvYrQ6WiAEKi5qRoQbkBe1AMEL7JKphGNZsvEscJzEfBdu9jxt1/LxZdD zQVJJK0wHAvd+E/UOtX+JoSRkxAN6zVhzzPPQGMSJQP351FamYLlpW3+nLNHN1BaVIMjyc+/GARz9 W2qiox6RHApJvicRe0TuUJRaRFovFOYLxmZ2gcqCHrEY2ujxpFYw2EvSLnhC+Ma1Z8YejWsV0Hxsz qeVRkwhMMEfMO0FaqToA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oqz4X-004MBP-1H; Fri, 04 Nov 2022 15:57:33 +0000 Received: from mail-ot1-f49.google.com ([209.85.210.49]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oqz2b-004LOy-0V for linux-arm-kernel@lists.infradead.org; Fri, 04 Nov 2022 15:55:34 +0000 Received: by mail-ot1-f49.google.com with SMTP id k59-20020a9d19c1000000b0066c45cdfca5so2877484otk.10 for ; Fri, 04 Nov 2022 08:55:32 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rdANC8NrUTH0lQipJQx568c5Das7/Cs95kVjxC07YnA=; b=uvdCvyoHXVxyvdGivjBG8otgYjI/EptDlmLdgbpj42PDcsfK3zxlcMo21VvQ7EsUxO ikDg4ra5pvTBr5bXsSQuYsYExcHottd0nnKeS1+a8DwE5aIhaAfXwx1Qs+fdoCPxodKV KQvSElGTNtjonob08o34h8WXp6D1kmaQzyXU/QKv+sdFmKe1DMLaQ8DP1JvUN1y4apkM xEQZAji4OTLoDxWeMjIjxHzkS0KF2crh6IdaDT4zJZZvpBwhe612Q7OsWk9tSo8+Yc9T v4EVXnVQALAE3+H6A6H44LuEN3+wyyu9ZgsDdnm68Dh4aaWCAgDJjPyaD58ARV0l6gsZ pphw== X-Gm-Message-State: ACrzQf3tH51fTnljX2hxIRDuC7cgKHSw82QwN/Icas740OjYzXHGKJxG 5vOR9XfXqLVcJdm9wZ5IvQ== X-Google-Smtp-Source: AMsMyM59dgaW5KOcOiwYnuILFe/BJR9IA6bPecpfclxA2KHdZ3Eq+UoizXI26yxdMDvL0GyieiOjSA== X-Received: by 2002:a05:6830:1241:b0:66c:3bc2:f919 with SMTP id s1-20020a056830124100b0066c3bc2f919mr16838358otp.33.1667577331662; Fri, 04 Nov 2022 08:55:31 -0700 (PDT) Received: from robh_at_kernel.org (66-90-144-107.dyn.grandenetworks.net. [66.90.144.107]) by smtp.gmail.com with ESMTPSA id l21-20020a05687040d500b0013d9bd4ad2esm1906311oal.12.2022.11.04.08.55.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Nov 2022 08:55:31 -0700 (PDT) Received: (nullmailer pid 1880422 invoked by uid 1000); Fri, 04 Nov 2022 15:55:18 -0000 From: Rob Herring Date: Fri, 04 Nov 2022 10:55:07 -0500 Subject: [PATCH v3 7/8] perf: Add perf_event_attr::config3 MIME-Version: 1.0 Message-Id: <20220825-arm-spe-v8-7-v3-7-87682f78caac@kernel.org> References: <20220825-arm-spe-v8-7-v3-0-87682f78caac@kernel.org> In-Reply-To: <20220825-arm-spe-v8-7-v3-0-87682f78caac@kernel.org> To: Namhyung Kim , Will Deacon , Arnaldo Carvalho de Melo , Jiri Olsa , Peter Zijlstra , Alexander Shishkin , Mark Rutland , Catalin Marinas , Marc Zyngier , Oliver Upton , Ingo Molnar , Suzuki K Poulose , James Morse , Alexandru Elisei Cc: kvmarm@lists.linux.dev, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, James Clark , Mark Brown , linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu X-Mailer: b4 0.11.0-dev X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221104_085533_071340_8B2FFBB7 X-CRM114-Status: GOOD ( 12.30 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Arm SPEv1.2 adds another 64-bits of event filtering control. As the existing perf_event_attr::configN fields are all used up for SPE PMU, an additional field is needed. Add a new 'config3' field. Tested-by: James Clark Signed-off-by: Rob Herring --- v3: - No change v2: - Drop tools/ side update --- include/uapi/linux/perf_event.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/uapi/linux/perf_event.h b/include/uapi/linux/perf_event.h index 85be78e0e7f6..b2b1d7b54097 100644 --- a/include/uapi/linux/perf_event.h +++ b/include/uapi/linux/perf_event.h @@ -374,6 +374,7 @@ enum perf_event_read_format { #define PERF_ATTR_SIZE_VER5 112 /* add: aux_watermark */ #define PERF_ATTR_SIZE_VER6 120 /* add: aux_sample_size */ #define PERF_ATTR_SIZE_VER7 128 /* add: sig_data */ +#define PERF_ATTR_SIZE_VER8 136 /* add: config3 */ /* * Hardware event_id to monitor via a performance monitoring event: @@ -515,6 +516,8 @@ struct perf_event_attr { * truncated accordingly on 32 bit architectures. */ __u64 sig_data; + + __u64 config3; /* extension of config2 */ }; /* From patchwork Fri Nov 4 15:55:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Rob Herring (Arm)" X-Patchwork-Id: 13032241 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A1EADC433FE for ; Fri, 4 Nov 2022 15:57:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References:Message-Id :MIME-Version:Subject:Date:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=lzuy5NQPt/2y8LLFHi9GRi6NfYPkWpGfoET0se4MjVQ=; b=17idjaq4ufjLIi 55htSKj/X6pwp7qlwYXFcF4bLY6gpyC+Y212kF1TwFEVRAsxJ2KEg3Nw5PtVwGzcKEbHmNlunwaXX L5wj6Xf1pVj4ZqUW66+AW0wKNKeZydXtf7k2P/VkGhnP8byxm8qqlbu5aAEdunQXMVf1AkMIBdlsh R6xpc2T8v6AbO03Sqif+k9UGsaQ3QvqFgR+n3yuUItEJjNlLr0wghEIyxP8zVjHz1Z+stPlR0HTxx MZbq/d89E7MUSz7jwM97xRHOeyvFyaWTjuq3hx3bviX9l8sWS//S24otQvLLnn4Xdo1JsVgRk/cnu nGuEyCFJ4hqw8cgexojQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oqz3e-004Lnl-0r; Fri, 04 Nov 2022 15:56:38 +0000 Received: from mail-oa1-f49.google.com ([209.85.160.49]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oqz2Y-004LIi-Id for linux-arm-kernel@lists.infradead.org; Fri, 04 Nov 2022 15:55:32 +0000 Received: by mail-oa1-f49.google.com with SMTP id 586e51a60fabf-13b23e29e36so5949757fac.8 for ; Fri, 04 Nov 2022 08:55:30 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fY5WLVvBtjin9otYHyxvqw7D/OBaUkyJnRUdtIxFHiA=; b=kUmtG+3AcRBfImXT+dgKsvv9SAQz3eQOqlTbhps4rIPqFZhVGrzm3USsYA6kmZNgQW 3DR3lczmInr74f5KJj0+OJobR049Pdjlk2bmE9K6fwvWTq2t8CceUufF+DlQeG9ahNDe X/U8CUYBjGrudj2SUl6uBgXqVn8jDLAzZsK9muQsonFCPSHPYVAJeJkqzARUyOuq6NC9 vBwo6XfTdFPQVeuZME2nmNIIUgR7RR0AQT+EQnnsiUQNA3t5z8L6wiNy0b0BIdPbjU0R 7bDTMXDD6t/iG5r/uhQWr2bSFLFnTegiPel4Bb3Kwp7dTkP1eAuwIy1oewcNxQBYiDMO ZYAg== X-Gm-Message-State: ACrzQf1hJ2i1IEl7zd78SPdHXKJBxCzAOkaGUM5WvZyxYrLAJQ4+6IUn NO0NIUZ9TlKMAT8uJ/HKAA== X-Google-Smtp-Source: AMsMyM4hNP3YtD1AjfgdVy7Wwt0avfUZHLw8qObIfSKL9fYTqIcOZIAAguh8sEaoNEPCMLo5eWKqXA== X-Received: by 2002:a05:6871:20c:b0:13c:12cf:1fee with SMTP id t12-20020a056871020c00b0013c12cf1feemr22484223oad.120.1667577329944; Fri, 04 Nov 2022 08:55:29 -0700 (PDT) Received: from robh_at_kernel.org (66-90-144-107.dyn.grandenetworks.net. [66.90.144.107]) by smtp.gmail.com with ESMTPSA id p36-20020a05687056a400b0013b1301ce42sm1871096oao.47.2022.11.04.08.55.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Nov 2022 08:55:29 -0700 (PDT) Received: (nullmailer pid 1880424 invoked by uid 1000); Fri, 04 Nov 2022 15:55:18 -0000 From: Rob Herring Date: Fri, 04 Nov 2022 10:55:08 -0500 Subject: [PATCH v3 8/8] perf: arm_spe: Add support for SPEv1.2 inverted event filtering MIME-Version: 1.0 Message-Id: <20220825-arm-spe-v8-7-v3-8-87682f78caac@kernel.org> References: <20220825-arm-spe-v8-7-v3-0-87682f78caac@kernel.org> In-Reply-To: <20220825-arm-spe-v8-7-v3-0-87682f78caac@kernel.org> To: Namhyung Kim , Will Deacon , Arnaldo Carvalho de Melo , Jiri Olsa , Peter Zijlstra , Alexander Shishkin , Mark Rutland , Catalin Marinas , Marc Zyngier , Oliver Upton , Ingo Molnar , Suzuki K Poulose , James Morse , Alexandru Elisei Cc: kvmarm@lists.linux.dev, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, James Clark , Mark Brown , linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu X-Mailer: b4 0.11.0-dev X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221104_085530_671876_44982520 X-CRM114-Status: GOOD ( 18.75 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Arm SPEv1.2 (Arm v8.7/v9.2) adds a new feature called Inverted Event Filter which excludes samples matching the event filter. The feature mirrors the existing event filter in PMSEVFR_EL1 adding a new register, PMSNEVFR_EL1, which has the same event bit assignments. Tested-by: James Clark Signed-off-by: Rob Herring --- v3: - No change v2: - Update for auto generated register defines - Avoid accessing SYS_PMSNEVFR_EL1 on < v8.7 --- drivers/perf/arm_spe_pmu.c | 45 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/drivers/perf/arm_spe_pmu.c b/drivers/perf/arm_spe_pmu.c index 82f67e941bc4..573db4211acd 100644 --- a/drivers/perf/arm_spe_pmu.c +++ b/drivers/perf/arm_spe_pmu.c @@ -85,6 +85,7 @@ struct arm_spe_pmu { #define SPE_PMU_FEAT_ARCH_INST (1UL << 3) #define SPE_PMU_FEAT_LDS (1UL << 4) #define SPE_PMU_FEAT_ERND (1UL << 5) +#define SPE_PMU_FEAT_INV_FILT_EVT (1UL << 6) #define SPE_PMU_FEAT_DEV_PROBED (1UL << 63) u64 features; @@ -202,6 +203,10 @@ static const struct attribute_group arm_spe_pmu_cap_group = { #define ATTR_CFG_FLD_min_latency_LO 0 #define ATTR_CFG_FLD_min_latency_HI 11 +#define ATTR_CFG_FLD_inv_event_filter_CFG config3 /* PMSNEVFR_EL1 */ +#define ATTR_CFG_FLD_inv_event_filter_LO 0 +#define ATTR_CFG_FLD_inv_event_filter_HI 63 + /* Why does everything I do descend into this? */ #define __GEN_PMU_FORMAT_ATTR(cfg, lo, hi) \ (lo) == (hi) ? #cfg ":" #lo "\n" : #cfg ":" #lo "-" #hi @@ -232,6 +237,7 @@ GEN_PMU_FORMAT_ATTR(branch_filter); GEN_PMU_FORMAT_ATTR(load_filter); GEN_PMU_FORMAT_ATTR(store_filter); GEN_PMU_FORMAT_ATTR(event_filter); +GEN_PMU_FORMAT_ATTR(inv_event_filter); GEN_PMU_FORMAT_ATTR(min_latency); static struct attribute *arm_spe_pmu_formats_attr[] = { @@ -243,12 +249,27 @@ static struct attribute *arm_spe_pmu_formats_attr[] = { &format_attr_load_filter.attr, &format_attr_store_filter.attr, &format_attr_event_filter.attr, + &format_attr_inv_event_filter.attr, &format_attr_min_latency.attr, NULL, }; +static umode_t arm_spe_pmu_format_attr_is_visible(struct kobject *kobj, + struct attribute *attr, + int unused) + { + struct device *dev = kobj_to_dev(kobj); + struct arm_spe_pmu *spe_pmu = dev_get_drvdata(dev); + + if (attr == &format_attr_inv_event_filter.attr && !(spe_pmu->features & SPE_PMU_FEAT_INV_FILT_EVT)) + return 0; + + return attr->mode; +} + static const struct attribute_group arm_spe_pmu_format_group = { .name = "format", + .is_visible = arm_spe_pmu_format_attr_is_visible, .attrs = arm_spe_pmu_formats_attr, }; @@ -343,6 +364,9 @@ static u64 arm_spe_event_to_pmsfcr(struct perf_event *event) if (ATTR_CFG_GET_FLD(attr, event_filter)) reg |= PMSFCR_EL1_FE; + if (ATTR_CFG_GET_FLD(attr, inv_event_filter)) + reg |= PMSFCR_EL1_FnE; + if (ATTR_CFG_GET_FLD(attr, min_latency)) reg |= PMSFCR_EL1_FL; @@ -355,6 +379,12 @@ static u64 arm_spe_event_to_pmsevfr(struct perf_event *event) return ATTR_CFG_GET_FLD(attr, event_filter); } +static u64 arm_spe_event_to_pmsnevfr(struct perf_event *event) +{ + struct perf_event_attr *attr = &event->attr; + return ATTR_CFG_GET_FLD(attr, inv_event_filter); +} + static u64 arm_spe_event_to_pmslatfr(struct perf_event *event) { struct perf_event_attr *attr = &event->attr; @@ -703,6 +733,9 @@ static int arm_spe_pmu_event_init(struct perf_event *event) if (arm_spe_event_to_pmsevfr(event) & arm_spe_pmsevfr_res0(spe_pmu->pmsver)) return -EOPNOTSUPP; + if (arm_spe_event_to_pmsnevfr(event) & arm_spe_pmsevfr_res0(spe_pmu->pmsver)) + return -EOPNOTSUPP; + if (attr->exclude_idle) return -EOPNOTSUPP; @@ -721,6 +754,10 @@ static int arm_spe_pmu_event_init(struct perf_event *event) !(spe_pmu->features & SPE_PMU_FEAT_FILT_EVT)) return -EOPNOTSUPP; + if ((FIELD_GET(PMSFCR_EL1_FnE, reg)) && + !(spe_pmu->features & SPE_PMU_FEAT_INV_FILT_EVT)) + return -EOPNOTSUPP; + if ((FIELD_GET(PMSFCR_EL1_FT, reg)) && !(spe_pmu->features & SPE_PMU_FEAT_FILT_TYP)) return -EOPNOTSUPP; @@ -756,6 +793,11 @@ static void arm_spe_pmu_start(struct perf_event *event, int flags) reg = arm_spe_event_to_pmsevfr(event); write_sysreg_s(reg, SYS_PMSEVFR_EL1); + if (spe_pmu->features & SPE_PMU_FEAT_INV_FILT_EVT) { + reg = arm_spe_event_to_pmsnevfr(event); + write_sysreg_s(reg, SYS_PMSNEVFR_EL1); + } + reg = arm_spe_event_to_pmslatfr(event); write_sysreg_s(reg, SYS_PMSLATFR_EL1); @@ -990,6 +1032,9 @@ static void __arm_spe_pmu_dev_probe(void *info) if (FIELD_GET(PMSIDR_EL1_FE, reg)) spe_pmu->features |= SPE_PMU_FEAT_FILT_EVT; + if (FIELD_GET(PMSIDR_EL1_FnE, reg)) + spe_pmu->features |= SPE_PMU_FEAT_INV_FILT_EVT; + if (FIELD_GET(PMSIDR_EL1_FT, reg)) spe_pmu->features |= SPE_PMU_FEAT_FILT_TYP;