From patchwork Fri Nov 4 17:21:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 13032411 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 994BBC433FE for ; Fri, 4 Nov 2022 17:22:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231674AbiKDRWH (ORCPT ); Fri, 4 Nov 2022 13:22:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34478 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231206AbiKDRWF (ORCPT ); Fri, 4 Nov 2022 13:22:05 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EF3ED41997; Fri, 4 Nov 2022 10:22:00 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 7046F660298A; Fri, 4 Nov 2022 17:21:56 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1667582517; bh=x44V5BqHSx5e6HeGtp/eVZ6L8gSCZl4R10NBZVoCgpw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=b6e0gfwBwlEAMhjbq8jU8shjCKQzd0cMmcE6Z2S8y6NlsJpy72lUolyRH1S4qrAGS /JaNUkZztWmVEGxL5wJy6gmlPz0WWc4wkAndeqoEKGXhGlHN6iT2jOMJSsjUsxbI/5 /l0F0AKjR1LGxyBwF6oRBwqkjr9il5FkTahIoZDcWOQIpu9iMra8O8nInZx0f8DJMr jnefQ/qkvTBYcMFik9TvoaSYqK9d6q3tRs7RhTrPHbLwZjnIo6M+x5QmMcQvWvzRS9 q917rpFVBii+5og6N2oe+Ax6N6iWkZFMqB1Sdkd/NhbLR9V0p551Zf1oTQRLcDIZ4G Ywcf2lwhPgR8g== From: AngeloGioacchino Del Regno To: agross@kernel.org Cc: andersson@kernel.org, konrad.dybcio@somainline.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee@kernel.org, ulf.hansson@linaro.org, srinivas.kandagatla@linaro.org, jic23@kernel.org, lars@metafoo.de, keescook@chromium.org, tony.luck@intel.com, gpiccoli@igalia.com, bhupesh.sharma@linaro.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, linux-iio@vger.kernel.org, linux-hardening@vger.kernel.org, marijn.suijten@somainline.org, kernel@collabora.com, luca@z3ntu.xyz, a39.skl@gmail.com, AngeloGioacchino Del Regno , AngeloGioacchino Del Regno Subject: [PATCH 1/9] dt-bindings: iio: qcom-spmi-vadc: Add definitions for USB DP/DM VADCs Date: Fri, 4 Nov 2022 18:21:14 +0100 Message-Id: <20221104172122.252761-2-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20221104172122.252761-1-angelogioacchino.delregno@collabora.com> References: <20221104172122.252761-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-hardening@vger.kernel.org From: AngeloGioacchino Del Regno Some SoCs do have a USB DP/DM ADC at 0x43, 0x44. Signed-off-by: AngeloGioacchino Del Regno Signed-off-by: Konrad Dybcio Signed-off-by: Marijn Suijten Signed-off-by: AngeloGioacchino Del Regno Acked-by: Krzysztof Kozlowski Acked-by: Jonathan Cameron --- include/dt-bindings/iio/qcom,spmi-vadc.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/dt-bindings/iio/qcom,spmi-vadc.h b/include/dt-bindings/iio/qcom,spmi-vadc.h index 08adfe25964c..c7bb9ef1f9ed 100644 --- a/include/dt-bindings/iio/qcom,spmi-vadc.h +++ b/include/dt-bindings/iio/qcom,spmi-vadc.h @@ -72,6 +72,9 @@ #define VADC_AMUX_PU2 0x3b #define VADC_LR_MUX3_BUF_XO_THERM 0x3c +#define VADC_USB_DP 0x43 +#define VADC_USB_DM 0x44 + #define VADC_LR_MUX1_PU1_BAT_THERM 0x70 #define VADC_LR_MUX2_PU1_BAT_ID 0x71 #define VADC_LR_MUX3_PU1_XO_THERM 0x72 From patchwork Fri Nov 4 17:21:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 13032405 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0F5A6C4332F for ; Fri, 4 Nov 2022 17:22:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230254AbiKDRWG (ORCPT ); Fri, 4 Nov 2022 13:22:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34470 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230205AbiKDRWE (ORCPT ); Fri, 4 Nov 2022 13:22:04 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 90DF141996; Fri, 4 Nov 2022 10:22:00 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id D83E36602997; Fri, 4 Nov 2022 17:21:57 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1667582519; bh=yJVjQ3f9FOfr69ZHuU0UhqtUyjhf5Eq1urXR3HU4CjI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Z1bTd1lU9vjJE0IarBtqRsIxTwqkqlAwOMPE5uFrbe1SS1UbVFOdWlEd85HjUE9sf +UDT1jZQJ7L65SGUKX0WzFmTs3jxi4N25cz9/6fL0FprZWrHjR3GDRJTDSSUU/GTbX q7a/RUKKu5Pdr0WjIq72GPKL+jKIxZ4eA6DIZqxGPhmidpJST8uLy+Xbql9nMUiF5S i82OSiZuGheARFBukjdPkg4oo6BjRV9nWXNn/IulmKWY2q7SslO/UCp+sEjdFBeUzK Sk3nq1hO1Erapkb0P8Cd0H7sLmDKaJ3GhWUCQpzayPwWmankYvwhDiWIBisIvgUChg GFp1MDBkRjTSA== From: AngeloGioacchino Del Regno To: agross@kernel.org Cc: andersson@kernel.org, konrad.dybcio@somainline.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee@kernel.org, ulf.hansson@linaro.org, srinivas.kandagatla@linaro.org, jic23@kernel.org, lars@metafoo.de, keescook@chromium.org, tony.luck@intel.com, gpiccoli@igalia.com, bhupesh.sharma@linaro.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, linux-iio@vger.kernel.org, linux-hardening@vger.kernel.org, marijn.suijten@somainline.org, kernel@collabora.com, luca@z3ntu.xyz, a39.skl@gmail.com, AngeloGioacchino Del Regno Subject: [PATCH 2/9] dt-bindings: nvmem: Add compatible for MSM8976 Date: Fri, 4 Nov 2022 18:21:15 +0100 Message-Id: <20221104172122.252761-3-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20221104172122.252761-1-angelogioacchino.delregno@collabora.com> References: <20221104172122.252761-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-hardening@vger.kernel.org From: Marijn Suijten Document generic QFPROM compatibility on MSM8976. Signed-off-by: Marijn Suijten Signed-off-by: AngeloGioacchino Del Regno --- Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml b/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml index 2eab2f46cb65..cac7be59c3cd 100644 --- a/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml +++ b/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml @@ -22,6 +22,7 @@ properties: - qcom,msm8974-qfprom - qcom,msm8916-qfprom - qcom,msm8996-qfprom + - qcom,msm8976-qfprom - qcom,msm8998-qfprom - qcom,qcs404-qfprom - qcom,sc7180-qfprom From patchwork Fri Nov 4 17:21:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 13032407 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6B995C43219 for ; Fri, 4 Nov 2022 17:22:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231625AbiKDRWL (ORCPT ); Fri, 4 Nov 2022 13:22:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34532 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231621AbiKDRWH (ORCPT ); Fri, 4 Nov 2022 13:22:07 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5E7E64199E; Fri, 4 Nov 2022 10:22:03 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 476846602995; Fri, 4 Nov 2022 17:21:59 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1667582520; bh=xk85JL4r9GN8347TeRxdMBc6hGdnmcfNXzfRU+FDXVg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Ddq/w482hg/tM55H/d0BFH7R1PAvyrQ0w2EwwewOT5DRLLqg0sugFU2+LlzfgiuXQ Kq+tM1GNN3xFARPOGrWS4U7v1sDuaS0Ty39D+6lx0iTplwb4tFTpj+/C3z4ZpbdxPt 1xftY2hdw8OOMfVLoI61SBSE25CjqpdbxBbVpyfCrRl2wS00lF+d8/kkyTGEZ9kVsx Kzg7BH6qo4LlZ5STDwntBiSc8XceM/6sJBG5YW+mGavDt7RP2EzqYgAoHUI5mn5ZsF 8dCpbqGS8734ALrTi1HHoYihjNK7qijTiFDhRWe3rfvLcGobpbqQ15vIYPLOXbk2Xv nZkDfego7zhIQ== From: AngeloGioacchino Del Regno To: agross@kernel.org Cc: andersson@kernel.org, konrad.dybcio@somainline.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee@kernel.org, ulf.hansson@linaro.org, srinivas.kandagatla@linaro.org, jic23@kernel.org, lars@metafoo.de, keescook@chromium.org, tony.luck@intel.com, gpiccoli@igalia.com, bhupesh.sharma@linaro.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, linux-iio@vger.kernel.org, linux-hardening@vger.kernel.org, marijn.suijten@somainline.org, kernel@collabora.com, luca@z3ntu.xyz, a39.skl@gmail.com, AngeloGioacchino Del Regno Subject: [PATCH 3/9] dt-bindings: arm: qcom: Document msm8956 and msm8976 SoC and devices Date: Fri, 4 Nov 2022 18:21:16 +0100 Message-Id: <20221104172122.252761-4-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20221104172122.252761-1-angelogioacchino.delregno@collabora.com> References: <20221104172122.252761-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-hardening@vger.kernel.org From: Marijn Suijten Note that msm8976 is omitted as a compatible, since there are currently no boards/devices using it. Signed-off-by: Marijn Suijten Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/qcom.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 207e28260206..bd1d5164938a 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -34,7 +34,9 @@ description: | mdm9615 msm8226 msm8916 + msm8956 msm8974 + msm8976 msm8992 msm8994 msm8996 @@ -149,6 +151,12 @@ properties: - samsung,s3ve3g - const: qcom,msm8226 + - items: + - enum: + - sony,kugo-row + - sony,suzu-row + - const: qcom,msm8956 + - items: - enum: - qcom,msm8960-cdp @@ -834,6 +842,8 @@ allOf: - qcom,apq8026 - qcom,apq8094 - qcom,apq8096 + - qcom,msm8956 + - qcom,msm8976 - qcom,msm8992 - qcom,msm8994 - qcom,msm8996 From patchwork Fri Nov 4 17:21:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 13032406 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A9211C4167E for ; Fri, 4 Nov 2022 17:22:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231756AbiKDRWI (ORCPT ); Fri, 4 Nov 2022 13:22:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34520 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230008AbiKDRWG (ORCPT ); Fri, 4 Nov 2022 13:22:06 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 492A74199D; Fri, 4 Nov 2022 10:22:03 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id A5DA2660299E; Fri, 4 Nov 2022 17:22:00 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1667582521; bh=ah3iLCOsM4WqktW76W9/Jw9aCMvs/EiM65WkIIXTGE0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=CD3By9lHSHlN885jyaYWtT2AOSe/3EXd6A249e4p5EBy2uxwP78s6g/rYBI7EWd1E AanCDy9g4jyKBjfGeI5pbaT8Nu3Ab66uN9G4+c+cCr3UoFqWpK+yXgm9wujEQjwYRf 4aLxPcv3GkEkk8GJRL1y9vae9JRglgH1IoAQ9J+U4yBV2kQr9cpQPcbTSuW2MSxY4N nuO0dAdAXOIbtZ1xKN2u2MEdxMi72aFvkBz0/bu2ZepEhRRqvIpRDisNUIuren4U1V Y5o5XwCZlwmS9nFgn7yzdyg04I3lWjybxx46EUFglmVtVKfptzF+5/CCQtacBFyUNB u6wBTlXn87HHQ== From: AngeloGioacchino Del Regno To: agross@kernel.org Cc: andersson@kernel.org, konrad.dybcio@somainline.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee@kernel.org, ulf.hansson@linaro.org, srinivas.kandagatla@linaro.org, jic23@kernel.org, lars@metafoo.de, keescook@chromium.org, tony.luck@intel.com, gpiccoli@igalia.com, bhupesh.sharma@linaro.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, linux-iio@vger.kernel.org, linux-hardening@vger.kernel.org, marijn.suijten@somainline.org, kernel@collabora.com, luca@z3ntu.xyz, a39.skl@gmail.com, AngeloGioacchino Del Regno Subject: [PATCH 4/9] dt-bindings: soc: qcom: qcom,smd-rpm: Use qcom,smd-channels on MSM8976 Date: Fri, 4 Nov 2022 18:21:17 +0100 Message-Id: <20221104172122.252761-5-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20221104172122.252761-1-angelogioacchino.delregno@collabora.com> References: <20221104172122.252761-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-hardening@vger.kernel.org Like MSM8916 and some others, MSM8976 uses qcom,smd-channels and not qcom,glink-channels. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml index fef7f29d44ba..11c0f4dd797c 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml @@ -81,6 +81,7 @@ if: - qcom,rpm-apq8084 - qcom,rpm-msm8916 - qcom,rpm-msm8974 + - qcom,rpm-msm8976 - qcom,rpm-msm8953 then: properties: From patchwork Fri Nov 4 17:21:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 13032408 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 18369C43217 for ; Fri, 4 Nov 2022 17:22:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230111AbiKDRWN (ORCPT ); Fri, 4 Nov 2022 13:22:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34580 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231891AbiKDRWK (ORCPT ); Fri, 4 Nov 2022 13:22:10 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 09E46419B2; Fri, 4 Nov 2022 10:22:05 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 16DDD66029A1; Fri, 4 Nov 2022 17:22:02 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1667582523; bh=bJJKGQIUdKlBSLPJiUpn9VKFemzRIMtNb7tKeJ4IU10=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=kuL8zpOjdB4/NlSWNrQpyJ2nE/geAifVIVY8Uwub101TNz4CPKGaC5/cDllTv3z1y HOQa8iVDWwRkzaZ2zFpQGlVshkMDaXmTVZ26Rz1jrjAVF+9kkjHSIE/jZYKVdslySX Yq8l4asF5ICszatrEg16pUlkgGNYHWf/byAa1TbQ2UEZffJOnEh0B6lcfM2eRxB/yu WHsL6qkX44hS6d5zB2gkah4B/l9qyTnt05uGY1Flx5+H+tT4n08GxsZNEJ0M22Evx8 xgsX4X0VK8ybGdwxFdy5rsGxMWPePdqLnsxvN7LqBCYjA0+1SVVr8nEMbwxH+lYXk2 nM7KxvSvrDZpQ== From: AngeloGioacchino Del Regno To: agross@kernel.org Cc: andersson@kernel.org, konrad.dybcio@somainline.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee@kernel.org, ulf.hansson@linaro.org, srinivas.kandagatla@linaro.org, jic23@kernel.org, lars@metafoo.de, keescook@chromium.org, tony.luck@intel.com, gpiccoli@igalia.com, bhupesh.sharma@linaro.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, linux-iio@vger.kernel.org, linux-hardening@vger.kernel.org, marijn.suijten@somainline.org, kernel@collabora.com, luca@z3ntu.xyz, a39.skl@gmail.com, AngeloGioacchino Del Regno Subject: [PATCH 5/9] dt-bindings: mmc: sdhci-msm: Document compatible for MSM8976 Date: Fri, 4 Nov 2022 18:21:18 +0100 Message-Id: <20221104172122.252761-6-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20221104172122.252761-1-angelogioacchino.delregno@collabora.com> References: <20221104172122.252761-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-hardening@vger.kernel.org Document the compatible for the SDHCI controller(s) found on MSM8976. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/mmc/sdhci-msm.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml index a96f143479c7..fc8a6b345d97 100644 --- a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml +++ b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml @@ -26,6 +26,7 @@ properties: - qcom,msm8226-sdhci - qcom,msm8953-sdhci - qcom,msm8974-sdhci + - qcom,msm8976-sdhci - qcom,msm8916-sdhci - qcom,msm8992-sdhci - qcom,msm8994-sdhci From patchwork Fri Nov 4 17:21:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 13032409 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C4791C41535 for ; Fri, 4 Nov 2022 17:22:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231313AbiKDRWQ (ORCPT ); Fri, 4 Nov 2022 13:22:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34552 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231889AbiKDRWJ (ORCPT ); Fri, 4 Nov 2022 13:22:09 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 23A4F419B5; Fri, 4 Nov 2022 10:22:06 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 7D63466029AE; Fri, 4 Nov 2022 17:22:03 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1667582524; bh=Tqj4UxRl+lyaeuF2LxgMqzCLs7oyv7xzXjHhz4lrVH0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=I4eNS4SEq61yHqhIBXWBPxK0fMuNvTXs5nbxuKOQiuP166POK6wKW8jacwxz9h4uf k54FJjOT8lggkGeqmonpqBr/YwEZLlbwe/JaBXX6TvPYNREsJHbaPJb6S174XFlD1j 1jxWUbeaoq20ytL96aVVih9EAnaMUcWv19dKUr0n3K32oJ9OZmCU1fujNB2yCxzLUs 9azzBe+WbLZ5tZ3KyHdK55hvo3IVCTkRnMToQ/EhOLL9Cm1x9ixRg9zb8lrzKZuLf2 Y1AMc9VrRlecLyKN9hOI9VYdHn0aZ7g86Crs9bI7SRsN9KQ9/eB1ytRyWggFYNPp3c +CuLRNqS3pJeg== From: AngeloGioacchino Del Regno To: agross@kernel.org Cc: andersson@kernel.org, konrad.dybcio@somainline.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee@kernel.org, ulf.hansson@linaro.org, srinivas.kandagatla@linaro.org, jic23@kernel.org, lars@metafoo.de, keescook@chromium.org, tony.luck@intel.com, gpiccoli@igalia.com, bhupesh.sharma@linaro.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, linux-iio@vger.kernel.org, linux-hardening@vger.kernel.org, marijn.suijten@somainline.org, kernel@collabora.com, luca@z3ntu.xyz, a39.skl@gmail.com, AngeloGioacchino Del Regno Subject: [PATCH 6/9] dt-bindings: mfd: qcom,tcsr: Add compatible for MSM8976 Date: Fri, 4 Nov 2022 18:21:19 +0100 Message-Id: <20221104172122.252761-7-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20221104172122.252761-1-angelogioacchino.delregno@collabora.com> References: <20221104172122.252761-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-hardening@vger.kernel.org Document the qcom,msm8976-tcsr compatible. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml b/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml index cb0ae38a777f..adcae6c007d9 100644 --- a/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml +++ b/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml @@ -17,6 +17,7 @@ properties: compatible: items: - enum: + - qcom,msm8976-tcsr - qcom,msm8998-tcsr - qcom,qcs404-tcsr - qcom,sc7180-tcsr From patchwork Fri Nov 4 17:21:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 13032410 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 08624C43219 for ; Fri, 4 Nov 2022 17:22:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231938AbiKDRWW (ORCPT ); Fri, 4 Nov 2022 13:22:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34592 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231869AbiKDRWM (ORCPT ); Fri, 4 Nov 2022 13:22:12 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A7858419AF; Fri, 4 Nov 2022 10:22:08 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id DF52466029BC; Fri, 4 Nov 2022 17:22:04 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1667582526; bh=UwbBWlIfKJJvEVD6FdOydMwJ+myG0v8FtTKG+u1//w0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=eKx8ztoA7fAwCPju/E30tTBUizvUJ0lc9/MHURn8tHvNLkUxWx1ubygySdTBcoK/8 tb/DueFnVVsZS2LdOj9vYuuAsCAPtuIBTZ8iOZ13vwxczY4lU/qbXUljTcfGRtPCJB 2G/6QhR+TJ6228AoR0jJma7b3C8qdP2MYYtKHEjwR+jKxwljJtH2k3RLaF2lJ/8aS/ Brm2f5sBvBoSEjcfwpudo+vNPCx1CSAPolroQZxkFLKHjP3Q2ROvgWMIySxRB/tvOs m8nNnd7xZHYYZMasp17f9AUVFEiygpEChf6+R/aVV2Ke7lUjVQ9Ei3GjoDvpgeur0A SBI/SD073IBsQ== From: AngeloGioacchino Del Regno To: agross@kernel.org Cc: andersson@kernel.org, konrad.dybcio@somainline.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee@kernel.org, ulf.hansson@linaro.org, srinivas.kandagatla@linaro.org, jic23@kernel.org, lars@metafoo.de, keescook@chromium.org, tony.luck@intel.com, gpiccoli@igalia.com, bhupesh.sharma@linaro.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, linux-iio@vger.kernel.org, linux-hardening@vger.kernel.org, marijn.suijten@somainline.org, kernel@collabora.com, luca@z3ntu.xyz, a39.skl@gmail.com, AngeloGioacchino Del Regno Subject: [PATCH 7/9] arm64: dts: qcom: Add configuration for PM8950 peripheral Date: Fri, 4 Nov 2022 18:21:20 +0100 Message-Id: <20221104172122.252761-8-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20221104172122.252761-1-angelogioacchino.delregno@collabora.com> References: <20221104172122.252761-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-hardening@vger.kernel.org The PM8950 features integrated peripherals like ADC, GPIO controller, MPPs, PON keys and others. Add them to DT files that will be imported on boards having this PMIC combo (or one of them, anyways). Signed-off-by: Konrad Dybcio Co-Developed-by: Marijn Suijten Signed-off-by: Marijn Suijten Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/qcom/pm8950.dtsi | 165 +++++++++++++++++++++++++++ 1 file changed, 165 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/pm8950.dtsi diff --git a/arch/arm64/boot/dts/qcom/pm8950.dtsi b/arch/arm64/boot/dts/qcom/pm8950.dtsi new file mode 100644 index 000000000000..07c3896bd36f --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pm8950.dtsi @@ -0,0 +1,165 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022, AngeloGioacchino Del Regno + * + * Copyright (c) 2022, Marijn Suijten + */ + +#include +#include +#include +#include +#include + +&spmi_bus { + pmic@0 { + compatible = "qcom,pm8950", "qcom,spmi-pmic"; + reg = <0x0 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pon@800 { + compatible = "qcom,pm8916-pon"; + reg = <0x0800>; + mode-bootloader = <0x2>; + mode-recovery = <0x1>; + + pwrkey { + compatible = "qcom,pm8941-pwrkey"; + interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>; + debounce = <15625>; + bias-pull-up; + linux,code = ; + }; + }; + + pm8950_temp: temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400>; + interrupts = <0 0x24 0 IRQ_TYPE_EDGE_RISING>; + io-channels = <&pm8950_vadc VADC_DIE_TEMP>; + io-channel-names = "thermal"; + #thermal-sensor-cells = <0>; + }; + + pm8950_vadc: adc@3100 { + compatible = "qcom,spmi-vadc"; + reg = <0x3100>; + interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + + vcoin@5 { + reg = ; + qcom,pre-scaling = <1 1>; + }; + + vph-pwr@7 { + reg = ; + qcom,pre-scaling = <1 1>; + }; + + die-temp@8 { + reg = ; + qcom,pre-scaling = <1 1>; + }; + + ref-625mv@9 { + reg = ; + qcom,pre-scaling = <1 1>; + }; + + ref-1250mv@a { + reg = ; + qcom,pre-scaling = <1 1>; + }; + + ref-buf-625mv@c { + reg = ; + qcom,pre-scaling = <1 1>; + }; + + ref-gnd@e { + reg = ; + }; + + ref-vdd@f { + reg = ; + }; + + pa-therm1@11 { + reg = ; + qcom,pre-scaling = <1 1>; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + case-therm@13 { + reg = ; + qcom,pre-scaling = <1 1>; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + xo-therm@32 { + reg = ; + qcom,pre-scaling = <1 1>; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + pa-therm0@36 { + reg = ; + qcom,pre-scaling = <1 1>; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + xo-therm-buf@3c { + reg = ; + qcom,pre-scaling = <1 1>; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + }; + + rtc@6000 { + compatible = "qcom,pm8941-rtc"; + reg = <0x6000>; + reg-names = "rtc", "alarm"; + interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>; + }; + + pm8950_mpps: mpps@a000 { + compatible = "qcom,pm8950-mpp", "qcom,spmi-mpp"; + reg = <0xa000>; + gpio-controller; + gpio-ranges = <&pm8950_mpps 0 0 4>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + pm8950_gpio: gpio@c000 { + compatible = "qcom,pm8950-gpio", "qcom,spmi-gpio"; + reg = <0xc000>; + gpio-controller; + gpio-ranges = <&pm8950_gpio 0 0 8>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + pmic@1 { + compatible = "qcom,pm8950", "qcom,spmi-pmic"; + reg = <0x1 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8950_spmi_regulators: regulators { + compatible = "qcom,pm8950-regulators"; + }; + }; +}; From patchwork Fri Nov 4 17:21:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 13032413 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 361AFC4167D for ; Fri, 4 Nov 2022 17:22:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231923AbiKDRW0 (ORCPT ); Fri, 4 Nov 2022 13:22:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34808 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231814AbiKDRWT (ORCPT ); Fri, 4 Nov 2022 13:22:19 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B3ABA419A0; Fri, 4 Nov 2022 10:22:09 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 47DC566029BF; Fri, 4 Nov 2022 17:22:06 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1667582527; bh=9L1mfVQGnIjU2vBQIpRBmFl5JvPjKQm/Tn0A9zXl7Ug=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Q5vImTDCznUDBRBoTXwbj0exgf33oRitmreiMjgymRP/DAgFsMDcMckrbjWIvZlwT lCDFkGAc9cBu4Oxk2nUCNbRz1vUEpe9ZQ9nQ4Z9HBC7LO1cLqLpvZeEG3t5GvGh9io 42OSdkfDCyHpQlVSgqVazSD61N1GfSv+sGfnNyA7UDLAhN0dJNsidxtsGXi9KiC/az y2yc3udyktdV9L0QA3qKeTq20SQYBVlUy97XuU9z61vRttr4wW5D1q5kI/r5TiOxql 9V/8V2EPnxazvM/xZHb/J2O330sysskw/d/SiJVz3XVq24AMbvZBdWspUkX20wv/tJ 0DJUVi1RJx9Cw== From: AngeloGioacchino Del Regno To: agross@kernel.org Cc: andersson@kernel.org, konrad.dybcio@somainline.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee@kernel.org, ulf.hansson@linaro.org, srinivas.kandagatla@linaro.org, jic23@kernel.org, lars@metafoo.de, keescook@chromium.org, tony.luck@intel.com, gpiccoli@igalia.com, bhupesh.sharma@linaro.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, linux-iio@vger.kernel.org, linux-hardening@vger.kernel.org, marijn.suijten@somainline.org, kernel@collabora.com, luca@z3ntu.xyz, a39.skl@gmail.com, AngeloGioacchino Del Regno , AngeloGioacchino Del Regno Subject: [PATCH 8/9] arm64: dts: qcom: Add DTS for MSM8976 and MSM8956 SoCs Date: Fri, 4 Nov 2022 18:21:21 +0100 Message-Id: <20221104172122.252761-9-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20221104172122.252761-1-angelogioacchino.delregno@collabora.com> References: <20221104172122.252761-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-hardening@vger.kernel.org From: AngeloGioacchino Del Regno This commit adds device trees for MSM8956 and MSM8976 SoCs. They are *almost* identical, with minor differences, such as MSM8956 having two A72 cores less. However, there is a bug in Sony Loire bootloader that requires presence of all 8 cores in the cpu{} node, so these will not be deleted. Co-developed-by: Konrad Dybcio Signed-off-by: Konrad Dybcio Co-developed-by: Marijn Suijten Signed-off-by: Marijn Suijten Signed-off-by: AngeloGioacchino Del Regno Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/qcom/msm8956.dtsi | 18 + arch/arm64/boot/dts/qcom/msm8976.dtsi | 1208 +++++++++++++++++++++++++ 2 files changed, 1226 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/msm8956.dtsi create mode 100644 arch/arm64/boot/dts/qcom/msm8976.dtsi diff --git a/arch/arm64/boot/dts/qcom/msm8956.dtsi b/arch/arm64/boot/dts/qcom/msm8956.dtsi new file mode 100644 index 000000000000..eb2c1345172c --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8956.dtsi @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2016-2022, AngeloGioacchino Del Regno + * + * Copyright (c) 2022, Konrad Dybcio + * Copyright (c) 2022, Marijn Suijten + */ + +#include "msm8976.dtsi" + +&pmu { + interrupts = ; +}; + +/* + * You might be wondering.. why is it so empty out there? + * Well, the SoCs are almost identical. + */ diff --git a/arch/arm64/boot/dts/qcom/msm8976.dtsi b/arch/arm64/boot/dts/qcom/msm8976.dtsi new file mode 100644 index 000000000000..e084a3a78f18 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8976.dtsi @@ -0,0 +1,1208 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2016-2022, AngeloGioacchino Del Regno + * + * Copyright (c) 2022, Konrad Dybcio + * Copyright (c) 2022, Marijn Suijten + */ + +#include +#include +#include +#include +#include +#include + +/ { + interrupt-parent = <&intc>; + #address-cells = <2>; + #size-cells = <2>; + + chosen { }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0>; + enable-method = "psci"; + cpu-idle-states = <&little_cpu_sleep_0>; + capacity-dmips-mhz = <573>; + next-level-cache = <&l2_0>; + #cooling-cells = <2>; + }; + + CPU1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x1>; + enable-method = "psci"; + cpu-idle-states = <&little_cpu_sleep_0>; + capacity-dmips-mhz = <573>; + next-level-cache = <&l2_0>; + #cooling-cells = <2>; + }; + + CPU2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x2>; + enable-method = "psci"; + cpu-idle-states = <&little_cpu_sleep_0>; + capacity-dmips-mhz = <573>; + next-level-cache = <&l2_0>; + #cooling-cells = <2>; + }; + + CPU3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x3>; + enable-method = "psci"; + cpu-idle-states = <&little_cpu_sleep_0>; + capacity-dmips-mhz = <573>; + next-level-cache = <&l2_0>; + #cooling-cells = <2>; + }; + + CPU4: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x100>; + enable-method = "psci"; + cpu-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; + capacity-dmips-mhz = <1024>; + next-level-cache = <&l2_1>; + #cooling-cells = <2>; + }; + + CPU5: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x101>; + enable-method = "psci"; + cpu-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; + capacity-dmips-mhz = <1024>; + next-level-cache = <&l2_1>; + #cooling-cells = <2>; + }; + + CPU6: cpu@102 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x102>; + enable-method = "psci"; + cpu-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; + capacity-dmips-mhz = <1024>; + next-level-cache = <&l2_1>; + #cooling-cells = <2>; + }; + + CPU7: cpu@103 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x103>; + enable-method = "psci"; + cpu-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; + capacity-dmips-mhz = <1024>; + next-level-cache = <&l2_1>; + #cooling-cells = <2>; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + }; + + cluster1 { + core0 { + cpu = <&CPU4>; + }; + + core1 { + cpu = <&CPU5>; + }; + + core2 { + cpu = <&CPU6>; + }; + + core3 { + cpu = <&CPU7>; + }; + }; + }; + + idle-states { + entry-method = "psci"; + + little_cpu_sleep_0: cpu-sleep-0-0 { + compatible = "arm,idle-state"; + idle-state-name = "little-power-collapse"; + arm,psci-suspend-param = <0x40000003>; + entry-latency-us = <181>; + exit-latency-us = <149>; + min-residency-us = <703>; + local-timer-stop; + }; + + big_cpu_sleep_0: cpu-sleep-1-0 { + compatible = "arm,idle-state"; + idle-state-name = "big-retention"; + arm,psci-suspend-param = <0x00000002>; + entry-latency-us = <142>; + exit-latency-us = <99>; + min-residency-us = <242>; + }; + + big_cpu_sleep_1: cpu-sleep-1-1 { + compatible = "arm,idle-state"; + idle-state-name = "big-power-collapse"; + arm,psci-suspend-param = <0x40000003>; + entry-latency-us = <158>; + exit-latency-us = <144>; + min-residency-us = <863>; + local-timer-stop; + }; + }; + + l2_0: l2-cache0 { + compatible = "cache"; + cache-level = <2>; + }; + + l2_1: l2-cache1 { + compatible = "cache"; + cache-level = <2>; + }; + }; + + firmware { + scm: scm { + compatible = "qcom,scm-msm8976", "qcom,scm"; + clocks = <&gcc GCC_CRYPTO_CLK>, + <&gcc GCC_CRYPTO_AXI_CLK>, + <&gcc GCC_CRYPTO_AHB_CLK>; + clock-names = "core", "bus", "iface"; + #reset-cells = <1>; + + qcom,dload-mode = <&tcsr 0x6100>; + }; + }; + + memory@80000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the size */ + reg = <0x0 0x80000000 0x0 0x0>; + }; + + pmu: pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = ; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cont_splash_mem: memory@83000000 { + reg = <0x0 0x83000000 0x0 0x2800000>; + }; + + ext_region: memory@85b00000 { + reg = <0x0 0x85b00000 0x0 0x500000>; + no-map; + }; + + smem: memory@86300000 { + compatible = "qcom,smem"; + reg = <0x0 0x86300000 0x0 0x100000>; + no-map; + + hwlocks = <&tcsr_mutex 3>; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + }; + + removed_mem: memory@86400000 { + reg = <0x0 0x86400000 0x0 0x800000>; + no-map; + }; + + mpss_region: memory@86c00000 { + reg = <0x0 0x86c00000 0x0 0x5600000>; + no-map; + }; + + lpass_region: memory@8c200000 { + reg = <0x0 0x8c200000 0x0 0x1800000>; + no-map; + }; + + venus_region: memory@8da00000 { + reg = <0x0 0x8da00000 0x0 0x2600000>; + no-map; + }; + + tz_apps: memory@8dd00000 { + reg = <0x0 0x8dd00000 0x0 0x1400000>; + no-map; + }; + }; + + smp2p-hexagon { + compatible = "qcom,smp2p"; + interrupts = ; + qcom,ipc = <&apcs 8 10>; + + qcom,local-pid = <0>; + qcom,remote-pid = <2>; + qcom,smem = <443>, <429>; + + adsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + + #qcom,smem-state-cells = <1>; + }; + + adsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smp2p-modem { + compatible = "qcom,smp2p"; + interrupts = ; + qcom,ipc = <&apcs 8 13>; + + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + qcom,smem = <435>, <428>; + + modem_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + + #qcom,smem-state-cells = <1>; + }; + + modem_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smp2p-wcnss { + compatible = "qcom,smp2p"; + interrupts = ; + qcom,ipc = <&apcs 8 17>; + + qcom,local-pid = <0>; + qcom,remote-pid = <4>; + qcom,smem = <451>, <431>; + + wcnss_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + + #qcom,smem-state-cells = <1>; + }; + + wcnss_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smd { + compatible = "qcom,smd"; + + rpm { + interrupts = ; + qcom,ipc = <&apcs 8 0>; + qcom,smd-edge = <15>; + + rpm_requests: rpm-requests { + compatible = "qcom,rpm-msm8976"; + qcom,smd-channels = "rpm_requests"; + + rpmcc: clock-controller { + compatible = "qcom,rpmcc-msm8976", "qcom,rpmcc"; + #clock-cells = <1>; + }; + + rpmpd: power-controller { + compatible = "qcom,msm8976-rpmpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmpd_opp_table>; + + rpmpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmpd_opp_ret: opp1 { + opp-level = ; + }; + + rpmpd_opp_ret_plus: opp2 { + opp-level = ; + }; + + rpmpd_opp_min_svs: opp3 { + opp-level = ; + }; + + rpmpd_opp_low_svs: opp4 { + opp-level = ; + }; + + rpmpd_opp_svs: opp5 { + opp-level = ; + }; + + rpmpd_opp_svs_plus: opp6 { + opp-level = ; + }; + + rpmpd_opp_nom: opp7 { + opp-level = ; + }; + + rpmpd_opp_nom_plus: opp8 { + opp-level = ; + }; + + rpmpd_opp_turbo: opp9 { + opp-level = ; + }; + + rpmpd_opp_turbo_no_cpr: opp10 { + opp-level = ; + }; + + rpmpd_opp_turbo_high: opp111 { + opp-level = ; + }; + }; + }; + }; + }; + }; + + smsm { + compatible = "qcom,smsm"; + + #address-cells = <1>; + #size-cells = <0>; + + qcom,ipc-1 = <&apcs 8 12>; + qcom,ipc-2 = <&apcs 8 9>; + qcom,ipc-3 = <&apcs 8 18>; + + apps_smsm: apps@0 { + reg = <0>; + #qcom,smem-state-cells = <1>; + }; + + hexagon_smsm: hexagon@1 { + reg = <1>; + interrupts = <0 290 IRQ_TYPE_EDGE_RISING>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + wcnss_smsm: wcnss@6 { + reg = <6>; + interrupts = ; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + soc: soc@0 { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + compatible = "simple-bus"; + + rng@22000 { + compatible = "qcom,prng"; + reg = <0x00022000 0x140>; + clocks = <&gcc GCC_PRNG_AHB_CLK>; + clock-names = "core"; + }; + + rpm_msg_ram: sram@60000 { + compatible = "qcom,rpm-msg-ram"; + reg = <0x00060000 0x8000>; + }; + + usb_hs_phy: phy@6c000 { + compatible = "qcom,usb-hs-28nm-femtophy"; + reg = <0x0006c000 0x200>; + #phy-cells = <0>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, + <&gcc GCC_USB2A_PHY_SLEEP_CLK>; + clock-names = "ref", "ahb", "sleep"; + resets = <&gcc RST_QUSB2_PHY_BCR>, + <&gcc RST_USB2_HS_PHY_ONLY_BCR>; + reset-names = "phy", "por"; + status = "disabled"; + }; + + qfprom: qfprom@a4000 { + compatible = "qcom,msm8976-qfprom", "qcom,qfprom"; + reg = <0x000a4000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + tsens_caldata: caldata@218 { + reg = <0x218 0x18>; + }; + }; + + tsens: thermal-sensor@4a9000 { + compatible = "qcom,msm8976-tsens", "qcom,tsens-v1"; + reg = <0x004a9000 0x1000>, /* TM */ + <0x004a8000 0x1000>; /* SROT */ + interrupts = ; + interrupt-names = "uplow"; + nvmem-cells = <&tsens_caldata>; + nvmem-cell-names = "calib"; + #qcom,sensors = <11>; + #thermal-sensor-cells = <1>; + }; + + tlmm: pinctrl@1000000 { + compatible = "qcom,msm8976-pinctrl"; + reg = <0x01000000 0x300000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + + spi1_default: spi0-default-state { + spi-pins { + pins = "gpio0", "gpio1", "gpio3"; + function = "blsp_spi1"; + drive-strength = <12>; + bias-disable; + }; + + cs-pins { + pins = "gpio2"; + function = "blsp_spi1"; + drive-strength = <2>; + bias-disable; + }; + }; + + spi1_sleep: spi0-sleep-state { + spi-pins { + pins = "gpio0", "gpio1", "gpio3"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + cs-pins { + pins = "gpio2"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_i2c2_default: blsp1-i2c2-default-state { + pins = "gpio6", "gpio7"; + function = "blsp_i2c2"; + drive-strength = <2>; + bias-disable; + }; + + blsp1_i2c2_sleep: blsp1-i2c2-sleep-state { + pins = "gpio6", "gpio7"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + blsp1_i2c4_default: blsp1-i2c4-default-state { + pins = "gpio14", "gpio15"; + function = "blsp_i2c4"; + drive-strength = <2>; + bias-disable; + }; + + blsp1_i2c4_sleep: blsp1-i2c4-sleep-state { + pins = "gpio14", "gpio15"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + blsp2_uart2_active: blsp2-uart2-active-state { + pins = "gpio20", "gpio21"; + function = "blsp_uart6"; + drive-strength = <4>; + bias-disable; + }; + + blsp2_uart2_sleep: blsp2-uart2-sleep-state { + pins = "gpio20", "gpio21"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + /* 4 (not 6!) interfaces per QUP, BLSP2 indexes are numbered (n)+4 */ + blsp2_i2c2_default: blsp2-i2c2-default-state { + pins = "gpio22", "gpio23"; + function = "blsp_i2c6"; + drive-strength = <2>; + bias-disable; + }; + + blsp2_i2c2_sleep: blsp2-i2c2-sleep-state { + pins = "gpio22", "gpio23"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + blsp2_i2c4_default: blsp2-i2c4-default-state { + pins = "gpio18", "gpio19"; + function = "blsp_i2c8"; + drive-strength = <2>; + bias-disable; + }; + + blsp2_i2c4_sleep: blsp2-i2c4-sleep-state { + pins = "gpio18", "gpio19"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + }; + + gcc: clock-controller@1800000 { + compatible = "qcom,gcc-msm8976"; + reg = <0x01800000 0x80000>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + + assigned-clocks = <&gcc GPLL3>; + assigned-clock-rates = <1100000000>; + + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&rpmcc RPM_SMD_XO_A_CLK_SRC>, + <0>, + <0>, + <0>, + <0>; + clock-names = "xo", + "xo_a", + "dsi0pll", + "dsi0pllbyte", + "dsi1pll", + "dsi1pllbyte"; + }; + + tcsr_mutex: hwlock@1905000 { + compatible = "qcom,tcsr-mutex"; + reg = <0x01905000 0x20000>; + #hwlock-cells = <1>; + }; + + tcsr: syscon@1937000 { + compatible = "qcom,tcsr-msm8976", "syscon"; + reg = <0x01937000 0x30000>; + }; + + spmi_bus: spmi@200f000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0x0200f000 0x1000>, + <0x02400000 0x800000>, + <0x02c00000 0x800000>, + <0x03800000 0x200000>, + <0x0200a000 0x2100>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupts = ; + interrupt-names = "periph_irq"; + qcom,channel = <0>; + qcom,ee = <0>; + + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + cell-index = <0>; + }; + + sdhc_1: mmc@7824000 { + compatible = "qcom,msm8976-sdhci", "qcom,sdhci-msm-v4"; + reg = <0x07824900 0x500>, <0x07824000 0x800>; + reg-names = "hc", "core"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "iface", "core", "xo"; + + bus-width = <8>; + non-removable; + status = "disabled"; + }; + + sdhc_2: mmc@7864000 { + compatible = "qcom,msm8976-sdhci", "qcom,sdhci-msm-v4"; + reg = <0x07864900 0x11c>, <0x07864000 0x800>; + reg-names = "hc", "core"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "iface", "core", "xo"; + + bus-width = <4>; + status = "disabled"; + }; + + blsp1_dma: dma-controller@7884000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0x07884000 0x1f000>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + }; + + blsp1_uart1: serial@78af000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x078af000 0x200>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp1_dma 0>, <&blsp1_dma 1>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + blsp1_uart2: serial@78b0000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x078b0000 0x200>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp1_dma 2>, <&blsp1_dma 3>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + blsp1_spi1: spi@78b5000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x078b5000 0x500>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp1_dma 4>, <&blsp1_dma 5>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&spi1_default>; + pinctrl-1 = <&spi1_sleep>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp1_i2c2: i2c@78b6000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x078b6000 0x500>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + clock-frequency = <400000>; + dmas = <&blsp1_dma 6>, <&blsp1_dma 7>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp1_i2c2_default>; + pinctrl-1 = <&blsp1_i2c2_default>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp1_i2c4: i2c@78b8000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x078b8000 0x500>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + clock-frequency = <400000>; + dmas = <&blsp1_dma 10>, <&blsp1_dma 11>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp1_i2c4_default>; + pinctrl-1 = <&blsp1_i2c4_sleep>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + otg: usb@78db000 { + compatible = "qcom,ci-hdrc"; + reg = <0x078db000 0x200>, + <0x078db200 0x200>; + interrupts = , + ; + clocks = <&gcc GCC_USB_HS_AHB_CLK>, <&gcc GCC_USB_HS_SYSTEM_CLK>; + clock-names = "iface", "core"; + assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>; + assigned-clock-rates = <80000000>; + resets = <&gcc RST_USB_HS_BCR>; + reset-names = "core"; + ahb-burst-config = <0>; + dr_mode = "peripheral"; + phy_type = "ulpi"; + phy-names = "usb-phy"; + phys = <&usb_hs_phy>; + status = "disabled"; + #reset-cells = <1>; + }; + + sdhc_3: mmc@7a24000 { + compatible = "qcom,msm8976-sdhci", "qcom,sdhci-msm-v4"; + reg = <0x07a24900 0x11c>, <0x07a24000 0x800>; + reg-names = "hc", "core"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC3_AHB_CLK>, + <&gcc GCC_SDCC3_APPS_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "iface", "core", "xo"; + bus-width = <4>; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + blsp2_dma: dma-controller@7ac4000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0x07ac4000 0x1f000>; + interrupts = ; + clocks = <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + }; + + blsp2_uart2: serial@7af0000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x07af0000 0x200>; + interrupts = ; + clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp2_dma 0>, <&blsp2_dma 1>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + blsp2_i2c2: i2c@7af6000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x07af6000 0x600>; + interrupts = ; + clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; + clock-frequency = <400000>; + dmas = <&blsp2_dma 6>, <&blsp2_dma 7>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp2_i2c2_default>; + pinctrl-1 = <&blsp2_i2c2_sleep>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp2_i2c4: i2c@7af8000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x07af8000 0x600>; + interrupts = ; + clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; + clock-frequency = <400000>; + dmas = <&blsp2_dma 10>, <&blsp2_dma 11>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp2_i2c4_default>; + pinctrl-1 = <&blsp2_i2c4_sleep>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + intc: interrupt-controller@b000000 { + compatible = "qcom,msm-qgic2"; + reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>; + interrupt-controller; + #interrupt-cells = <3>; + }; + + apcs: syscon@b011000 { + compatible = "syscon"; + reg = <0x0b011000 0x1000>; + }; + + timer@b120000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x0b120000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clock-frequency = <19200000>; + + frame@b121000 { + reg = <0x0b121000 0x1000>, <0x0b122000 0x1000>; + interrupts = , + ; + frame-number = <0>; + }; + + frame@b123000 { + reg = <0x0b123000 0x1000>; + interrupts = ; + frame-number = <1>; + status = "disabled"; + }; + + frame@b124000 { + reg = <0x0b124000 0x1000>; + interrupts = ; + frame-number = <2>; + status = "disabled"; + }; + + frame@b125000 { + reg = <0x0b125000 0x1000>; + interrupts = ; + frame-number = <3>; + status = "disabled"; + }; + + frame@b126000 { + reg = <0x0b126000 0x1000>; + interrupts = ; + frame-number = <4>; + status = "disabled"; + }; + + frame@b127000 { + reg = <0x0b127000 0x1000>; + interrupts = ; + frame-number = <5>; + status = "disabled"; + }; + + frame@b128000 { + reg = <0x0b128000 0x1000>; + interrupts = ; + frame-number = <6>; + status = "disabled"; + }; + }; + + imem: imem@8600000 { + compatible = "simple-mfd"; + reg = <0x08600000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + ranges = <0 0x08600000 0x1000>; + + pil-reloc@94c { + compatible = "qcom,pil-reloc-info"; + reg = <0x94c 0xc8>; + }; + }; + }; + + thermal-zones { + aoss0-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 0>; + + trips { + aoss0_alert0: trip-point0 { + temperature = <75000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + modem-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 1>; + trips { + modem_alert0: trip-point0 { + temperature = <75000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + qdsp-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 2>; + trips { + qdsp_alert0: trip-point0 { + temperature = <75000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + cam-isp-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 3>; + trips { + cam_isp_alert0: trip-point0 { + temperature = <75000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + cpu4-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsens 4>; + + trips { + cpu4_alert0: trip-point0 { + temperature = <50000>; + hysteresis = <2000>; + type = "hot"; + }; + cpu4_alert1: trip-point1 { + temperature = <55000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu4_crit: cpu-crit { + temperature = <75000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpu5-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsens 5>; + + trips { + cpu5_alert0: trip-point0 { + temperature = <50000>; + hysteresis = <2000>; + type = "hot"; + }; + cpu5_alert1: trip-point1 { + temperature = <55000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu5_crit: cpu-crit { + temperature = <75000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpu6-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsens 6>; + + trips { + cpu6_alert0: trip-point0 { + temperature = <50000>; + hysteresis = <2000>; + type = "hot"; + }; + cpu6_alert1: trip-point1 { + temperature = <55000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu6_crit: cpu-crit { + temperature = <75000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpu7-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsens 7>; + + trips { + cpu7_alert0: trip-point0 { + temperature = <50000>; + hysteresis = <2000>; + type = "hot"; + }; + cpu7_alert1: trip-point1 { + temperature = <55000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu7_crit: cpu-crit { + temperature = <75000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + big-l2-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsens 8>; + + trips { + l2_alert0: trip-point0 { + temperature = <50000>; + hysteresis = <2000>; + type = "hot"; + }; + l2_alert1: trip-point1 { + temperature = <55000>; + hysteresis = <2000>; + type = "passive"; + }; + l2_crit: l2-crit { + temperature = <75000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpu0-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsens 9>; + + trips { + cpu0_alert0: trip-point0 { + temperature = <50000>; + hysteresis = <2000>; + type = "hot"; + }; + cpu0_alert1: trip-point1 { + temperature = <55000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu0_crit: cpu-crit { + temperature = <75000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + gpu-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsens 10>; + + trips { + gpu_alert0: trip-point0 { + temperature = <50000>; + hysteresis = <2000>; + type = "hot"; + }; + gpu_alert1: trip-point1 { + temperature = <55000>; + hysteresis = <2000>; + type = "passive"; + }; + gpu_crit: gpu-crit { + temperature = <75000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + clock-frequency = <19200000>; + }; +}; From patchwork Fri Nov 4 17:21:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 13032412 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C0CF3C4332F for ; Fri, 4 Nov 2022 17:22:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231873AbiKDRWZ (ORCPT ); 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b=Q1D65A7/7aSe7/+j6edpGLnIj0gexTW6+ufMRuli1IOAv1zVGxajwqzrwoF51F0C8 AnnDLUKXSBGU/lt8ToWj7kXaBlGV3eaTmNFdaVhyAnXDNgz98jU46fImy2ftobSpOT KzZKDangddif6TYWDXfR50C3OhokEiVjN8C9Jd1TF1sR3BSUfk16o3LhM3kMdDxud8 6w1r1ErKllNbszeOYJg5m04nJH6prN9j0al3tzhvjXiLvtei9cXDheCYd8c8s2D9CI JnYH3pZJIRHjT2GLOWcSPwbFxAk2W8iFkhAbDdwgCbbgwwzBmYp8O5xzXkMPr1h7P9 nTgmnrbWrGMpg== From: AngeloGioacchino Del Regno To: agross@kernel.org Cc: andersson@kernel.org, konrad.dybcio@somainline.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee@kernel.org, ulf.hansson@linaro.org, srinivas.kandagatla@linaro.org, jic23@kernel.org, lars@metafoo.de, keescook@chromium.org, tony.luck@intel.com, gpiccoli@igalia.com, bhupesh.sharma@linaro.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, linux-iio@vger.kernel.org, linux-hardening@vger.kernel.org, marijn.suijten@somainline.org, kernel@collabora.com, luca@z3ntu.xyz, a39.skl@gmail.com, AngeloGioacchino Del Regno , AngeloGioacchino Del Regno Subject: [PATCH 9/9] arm64: dts: qcom: Add support for SONY Xperia X/X Compact Date: Fri, 4 Nov 2022 18:21:22 +0100 Message-Id: <20221104172122.252761-10-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20221104172122.252761-1-angelogioacchino.delregno@collabora.com> References: <20221104172122.252761-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-hardening@vger.kernel.org From: AngeloGioacchino Del Regno This adds support for the Sony Xperia Loire/SmartLoire platform with a base configuration that is common across all of the devices that are based on this project. Also adds a base DT configuration for the Xperia X and Xperia X Compact (respectively, Suzu and Kugo) which is valid for both their RoW (single-sim), DSDS (dual-sim) and other regional variants of these two smartphones, that makes us able to boot to a UART console. Please note that, currently, the APC0/1 (cluster 0/1) vregs are set to a safe voltage in order to ensure boot stability until a proper solution for CPU DVFS scaling lands. Co-developed-by: Konrad Dybcio Signed-off-by: Konrad Dybcio Co-developed-by: Marijn Suijten Signed-off-by: Marijn Suijten Signed-off-by: AngeloGioacchino Del Regno Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/qcom/Makefile | 2 + .../qcom/msm8956-sony-xperia-loire-kugo.dts | 36 +++ .../qcom/msm8956-sony-xperia-loire-suzu.dts | 17 ++ .../dts/qcom/msm8956-sony-xperia-loire.dtsi | 269 ++++++++++++++++++ 4 files changed, 324 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/msm8956-sony-xperia-loire-kugo.dts create mode 100644 arch/arm64/boot/dts/qcom/msm8956-sony-xperia-loire-suzu.dts create mode 100644 arch/arm64/boot/dts/qcom/msm8956-sony-xperia-loire.dtsi diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index b0558d3389e5..55ba551963fc 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -21,6 +21,8 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-grandmax.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-j5.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-serranove.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-wingtech-wt88047.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8956-sony-xperia-loire-kugo.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8956-sony-xperia-loire-suzu.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8992-lg-bullhead-rev-10.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8992-lg-bullhead-rev-101.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8992-msft-lumia-octagon-talkman.dtb diff --git a/arch/arm64/boot/dts/qcom/msm8956-sony-xperia-loire-kugo.dts b/arch/arm64/boot/dts/qcom/msm8956-sony-xperia-loire-kugo.dts new file mode 100644 index 000000000000..0e34e15f2ae8 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8956-sony-xperia-loire-kugo.dts @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2016-2022, AngeloGioacchino Del Regno + * + * Copyright (c) 2022, Konrad Dybcio + * Copyright (c) 2022, Marijn Suijten + */ + +/dts-v1/; + +#include "msm8956-sony-xperia-loire.dtsi" + +/ { + model = "Sony Xperia X Compact"; + compatible = "sony,kugo-row", "qcom,msm8956"; + chassis-type = "handset"; +}; + +&blsp2_i2c2 { + status = "okay"; + + /* FUSB301 USB-C Controller */ +}; + +&blsp2_i2c4 { + status = "okay"; + + /* ST STMVL53L0 ToF @ 29 */ + /* AMS TCS349 RGBCIR @ 72 */ +}; + +&pm8950_l1 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + qcom,init-voltage = <1200000>; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8956-sony-xperia-loire-suzu.dts b/arch/arm64/boot/dts/qcom/msm8956-sony-xperia-loire-suzu.dts new file mode 100644 index 000000000000..87d657f6806b --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8956-sony-xperia-loire-suzu.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2016-2022, AngeloGioacchino Del Regno + * + * Copyright (c) 2022, Konrad Dybcio + * Copyright (c) 2022, Marijn Suijten + */ + +/dts-v1/; + +#include "msm8956-sony-xperia-loire.dtsi" + +/ { + model = "Sony Xperia X"; + compatible = "sony,suzu-row", "qcom,msm8956"; + chassis-type = "handset"; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8956-sony-xperia-loire.dtsi b/arch/arm64/boot/dts/qcom/msm8956-sony-xperia-loire.dtsi new file mode 100644 index 000000000000..2ac21b05cb68 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8956-sony-xperia-loire.dtsi @@ -0,0 +1,269 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2016-2022, AngeloGioacchino Del Regno + * + * Copyright (c) 2022, Konrad Dybcio + * Copyright (c) 2022, Marijn Suijten + */ + +#include "msm8956.dtsi" + +#include "pm8004.dtsi" +#include "pm8950.dtsi" +#include "pmi8950.dtsi" + +/ { + qcom,msm-id = <266 0x10001>; /* MSM8956 v1.1 */ + qcom,board-id = <8 0>; + + aliases { + mmc0 = &sdhc_1; /* SDC1 eMMC slot */ + mmc1 = &sdhc_2; /* SDC2 SD card slot */ + mmc2 = &sdhc_3; /* SDC3 SDIO card slot */ + serial0 = &blsp2_uart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + reserved-memory { + ramoops@57f00000 { + compatible = "ramoops"; + reg = <0 0x57f00000 0 0x100000>; + record-size = <0x20000>; + console-size = <0x40000>; + ftrace-size = <0x20000>; + pmsg-size = <0x20000>; + ecc-size = <16>; + }; + }; + + usbphy_1p2: regulator-usbphy-1p2 { + compatible = "regulator-fixed"; + regulator-name = "usbphy-1p2"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + vin-supply = <&vph_pwr>; + }; + + vph_pwr: regulator-vph-pwr { + compatible = "regulator-fixed"; + regulator-name = "vph-pwr"; + regulator-always-on; + regulator-boot-on; + }; +}; + +&blsp1_i2c4 { + status = "okay"; + + /* Synaptics RMI4 @ 2c */ +}; + +&blsp2_uart2 { + status = "okay"; +}; + +&gcc { + vdd_gfx-supply = <&pm8004_s5>; +}; + +&otg { + status = "okay"; +}; + +&pm8004_spmi_regulators { + vdd_s2-supply = <&vph_pwr>; + vdd_s5-supply = <&vph_pwr>; + + /* Cluster 1 supply */ + pm8004_s2: s2 { + /* regulator-min-microvolt = <500000>; */ + /* Set .95V to prevent unstabilities until CPR for this SoC is done */ + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1165000>; + regulator-name = "vdd_apc1"; + /* Set always on until the CPU PLL is done */ + regulator-always-on; + regulator-boot-on; + }; + + pm8004_s5: s5 { + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1165000>; + regulator-enable-ramp-delay = <500>; + regulator-name = "vdd_gfx"; + /* Hack this on until the gpu driver is ready for it */ + regulator-always-on; + }; +}; + +&pm8950_spmi_regulators { + vdd_s5-supply = <&vph_pwr>; + + /* Cluster 0 supply */ + pm8950_spmi_s5: s5 { + /* Set .95V to prevent unstabilities until CPR for this SoC is done */ + /* regulator-min-microvolt = <790000>; */ + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1165000>; + regulator-name = "vdd_apc0"; + /* Set always on until the CPU PLL is done */ + regulator-always-on; + regulator-boot-on; + }; +}; + +&rpm_requests { + pm8950_regulators: regulators { + compatible = "qcom,rpm-pm8950-regulators"; + + vdd_s1-supply = <&vph_pwr>; + vdd_s2-supply = <&vph_pwr>; + vdd_s3-supply = <&vph_pwr>; + vdd_s4-supply = <&vph_pwr>; + vdd_s6-supply = <&vph_pwr>; + vdd_l1_l19-supply = <&pm8950_s3>; + vdd_l2_l23-supply = <&pm8950_s3>; + vdd_l3-supply = <&pm8950_s3>; + vdd_l5_l6_l7_l16-supply = <&pm8950_s4>; + vdd_l8_l11_l12_l17_l22-supply = <&vph_pwr>; + + pm8950_s1: s1 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1162500>; + }; + + pm8950_s3: s3 { + regulator-min-microvolt = <1325000>; + regulator-max-microvolt = <1325000>; + regulator-always-on; + }; + + pm8950_s4: s4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + pm8950_l1: l1 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1100000>; + }; + + pm8950_l2: l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + pm8950_l3: l3 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1200000>; + }; + + pm8950_l5: l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8950_l6: l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8950_l7: l7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8950_l8: l8 { + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + }; + + pm8950_l9: l9 { + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2400000>; + }; + + pm8950_l10: l10 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2900000>; + }; + + pm8950_l11: l11 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + }; + + pm8950_l12: l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pm8950_l13: l13 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + }; + + pm8950_l14: l14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + pm8950_l15: l15 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + pm8950_l16: l16 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8950_l17: l17 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2900000>; + }; + + pm8950_l22: l22 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + pm8950_l23: l23 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + }; +}; + +&sdhc_1 { + status = "okay"; + + vmmc-supply = <&pm8950_l8>; + vqmmc-supply = <&pm8950_l5>; +}; + +&sdhc_2 { + status = "okay"; + + vmmc-supply = <&pm8950_l11>; + vqmmc-supply = <&pm8950_l12>; + cd-gpios = <&tlmm 100 GPIO_ACTIVE_HIGH>; +}; + +&tlmm { + gpio-reserved-ranges = <0 4>; +}; + +&usb_hs_phy { + status = "okay"; + + vdd-supply = <&usbphy_1p2>; + vdda1p8-supply = <&pm8950_l7>; + vdda3p3-supply = <&pm8950_l13>; +};