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At this stage, embed a member of type struct atmel_pwm_registers in it. Signed-off-by: Claudiu Beznea --- drivers/pwm/pwm-atmel.c | 64 +++++++++++++++++++++++++++---------------------- 1 file changed, 36 insertions(+), 28 deletions(-) diff --git a/drivers/pwm/pwm-atmel.c b/drivers/pwm/pwm-atmel.c index 530d7dc5f1b5..7e86a5266eb6 100644 --- a/drivers/pwm/pwm-atmel.c +++ b/drivers/pwm/pwm-atmel.c @@ -65,11 +65,15 @@ struct atmel_pwm_registers { u8 duty_upd; }; +struct atmel_pwm_data { + struct atmel_pwm_registers regs; +}; + struct atmel_pwm_chip { struct pwm_chip chip; struct clk *clk; void __iomem *base; - const struct atmel_pwm_registers *regs; + const struct atmel_pwm_data *data; unsigned int updated_pwms; /* ISR is cleared when read, ensure only one thread does that */ @@ -150,15 +154,15 @@ static void atmel_pwm_update_cdty(struct pwm_chip *chip, struct pwm_device *pwm, struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip); u32 val; - if (atmel_pwm->regs->duty_upd == - atmel_pwm->regs->period_upd) { + if (atmel_pwm->data->regs.duty_upd == + atmel_pwm->data->regs.period_upd) { val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR); val &= ~PWM_CMR_UPD_CDTY; atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val); } atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, - atmel_pwm->regs->duty_upd, cdty); + atmel_pwm->data->regs.duty_upd, cdty); } static void atmel_pwm_set_cprd_cdty(struct pwm_chip *chip, @@ -168,9 +172,9 @@ static void atmel_pwm_set_cprd_cdty(struct pwm_chip *chip, struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip); atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, - atmel_pwm->regs->duty, cdty); + atmel_pwm->data->regs.duty, cdty); atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, - atmel_pwm->regs->period, cprd); + atmel_pwm->data->regs.period, cprd); } static void atmel_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm, @@ -225,7 +229,7 @@ static int atmel_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, cstate.polarity == state->polarity && cstate.period == state->period) { cprd = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, - atmel_pwm->regs->period); + atmel_pwm->data->regs.period); atmel_pwm_calculate_cdty(state, cprd, &cdty); atmel_pwm_update_cdty(chip, pwm, cdty); return 0; @@ -277,27 +281,31 @@ static const struct pwm_ops atmel_pwm_ops = { .owner = THIS_MODULE, }; -static const struct atmel_pwm_registers atmel_pwm_regs_v1 = { - .period = PWMV1_CPRD, - .period_upd = PWMV1_CUPD, - .duty = PWMV1_CDTY, - .duty_upd = PWMV1_CUPD, +static const struct atmel_pwm_data atmel_pwm_data_v1 = { + .regs = { + .period = PWMV1_CPRD, + .period_upd = PWMV1_CUPD, + .duty = PWMV1_CDTY, + .duty_upd = PWMV1_CUPD, + }, }; -static const struct atmel_pwm_registers atmel_pwm_regs_v2 = { - .period = PWMV2_CPRD, - .period_upd = PWMV2_CPRDUPD, - .duty = PWMV2_CDTY, - .duty_upd = PWMV2_CDTYUPD, +static const struct atmel_pwm_data atmel_pwm_data_v2 = { + .regs = { + .period = PWMV2_CPRD, + .period_upd = PWMV2_CPRDUPD, + .duty = PWMV2_CDTY, + .duty_upd = PWMV2_CDTYUPD, + }, }; static const struct platform_device_id atmel_pwm_devtypes[] = { { .name = "at91sam9rl-pwm", - .driver_data = (kernel_ulong_t)&atmel_pwm_regs_v1, + .driver_data = (kernel_ulong_t)&atmel_pwm_data_v1, }, { .name = "sama5d3-pwm", - .driver_data = (kernel_ulong_t)&atmel_pwm_regs_v2, + .driver_data = (kernel_ulong_t)&atmel_pwm_data_v2, }, { /* sentinel */ }, @@ -307,20 +315,20 @@ MODULE_DEVICE_TABLE(platform, atmel_pwm_devtypes); static const struct of_device_id atmel_pwm_dt_ids[] = { { .compatible = "atmel,at91sam9rl-pwm", - .data = &atmel_pwm_regs_v1, + .data = &atmel_pwm_data_v1, }, { .compatible = "atmel,sama5d3-pwm", - .data = &atmel_pwm_regs_v2, + .data = &atmel_pwm_data_v2, }, { .compatible = "atmel,sama5d2-pwm", - .data = &atmel_pwm_regs_v2, + .data = &atmel_pwm_data_v2, }, { /* sentinel */ }, }; MODULE_DEVICE_TABLE(of, atmel_pwm_dt_ids); -static inline const struct atmel_pwm_registers * +static inline const struct atmel_pwm_data * atmel_pwm_get_driver_data(struct platform_device *pdev) { const struct platform_device_id *id; @@ -330,18 +338,18 @@ atmel_pwm_get_driver_data(struct platform_device *pdev) id = platform_get_device_id(pdev); - return (struct atmel_pwm_registers *)id->driver_data; + return (struct atmel_pwm_data *)id->driver_data; } static int atmel_pwm_probe(struct platform_device *pdev) { - const struct atmel_pwm_registers *regs; + const struct atmel_pwm_data *data; struct atmel_pwm_chip *atmel_pwm; struct resource *res; int ret; - regs = atmel_pwm_get_driver_data(pdev); - if (!regs) + data = atmel_pwm_get_driver_data(pdev); + if (!data) return -ENODEV; atmel_pwm = devm_kzalloc(&pdev->dev, sizeof(*atmel_pwm), GFP_KERNEL); @@ -373,7 +381,7 @@ static int atmel_pwm_probe(struct platform_device *pdev) atmel_pwm->chip.base = -1; atmel_pwm->chip.npwm = 4; - atmel_pwm->regs = regs; + atmel_pwm->data = data; atmel_pwm->updated_pwms = 0; mutex_init(&atmel_pwm->isr_lock); From patchwork Mon Jan 21 12:30:53 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 10773831 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0B16A1390 for ; Mon, 21 Jan 2019 12:31:33 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E8B0E29C2E for ; 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Mon, 21 Jan 2019 12:30:53 +0000 From: To: , , , , , Subject: [PATCH 2/4] pwm: atmel: add support for controllers with 32 bit counters Thread-Topic: [PATCH 2/4] pwm: atmel: add support for controllers with 32 bit counters Thread-Index: AQHUsYUm31frJ/4ukkWUPCYXEQw2XQ== Date: Mon, 21 Jan 2019 12:30:53 +0000 Message-ID: <1548073783-22640-3-git-send-email-claudiu.beznea@microchip.com> References: <1548073783-22640-1-git-send-email-claudiu.beznea@microchip.com> In-Reply-To: <1548073783-22640-1-git-send-email-claudiu.beznea@microchip.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: BYAPR07CA0038.namprd07.prod.outlook.com (2603:10b6:a03:60::15) To MWHPR11MB1920.namprd11.prod.outlook.com (2603:10b6:300:110::19) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Claudiu.Beznea@microchip.com; x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.7.4 x-originating-ip: [94.177.32.154] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; 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Update the current driver to work with old controller (that uses 16 bits counters) and with the new SAM9X60's controller. Signed-off-by: Claudiu Beznea --- drivers/pwm/pwm-atmel.c | 38 +++++++++++++++++++++++++++----------- 1 file changed, 27 insertions(+), 11 deletions(-) diff --git a/drivers/pwm/pwm-atmel.c b/drivers/pwm/pwm-atmel.c index 7e86a5266eb6..44f4a1c9f60b 100644 --- a/drivers/pwm/pwm-atmel.c +++ b/drivers/pwm/pwm-atmel.c @@ -48,15 +48,15 @@ #define PWMV2_CPRD 0x0C #define PWMV2_CPRDUPD 0x10 -/* - * Max value for duty and period - * - * Although the duty and period register is 32 bit, - * however only the LSB 16 bits are significant. - */ -#define PWM_MAX_DTY 0xFFFF -#define PWM_MAX_PRD 0xFFFF -#define PRD_MAX_PRES 10 +/* Max values for period and prescaler */ + +/* Only the LSB 16 bits are significant. */ +#define PWM_MAXV1_PRD 0xFFFF + +/* All 32 bits are significant. */ +#define PWM_MAXV2_PRD 0xFFFFFFFF + +#define PRD_MAXV1_PRES 10 struct atmel_pwm_registers { u8 period; @@ -65,8 +65,14 @@ struct atmel_pwm_registers { u8 duty_upd; }; +struct atmel_pwm_config { + u32 max_period; + u32 max_pres; +}; + struct atmel_pwm_data { struct atmel_pwm_registers regs; + struct atmel_pwm_config cfg; }; struct atmel_pwm_chip { @@ -125,10 +131,10 @@ static int atmel_pwm_calculate_cprd_and_pres(struct pwm_chip *chip, cycles *= clk_get_rate(atmel_pwm->clk); do_div(cycles, NSEC_PER_SEC); - for (*pres = 0; cycles > PWM_MAX_PRD; cycles >>= 1) + for (*pres = 0; cycles > atmel_pwm->data->cfg.max_period; cycles >>= 1) (*pres)++; - if (*pres > PRD_MAX_PRES) { + if (*pres > atmel_pwm->data->cfg.max_pres) { dev_err(chip->dev, "pres exceeds the maximum value\n"); return -EINVAL; } @@ -288,6 +294,11 @@ static const struct atmel_pwm_data atmel_pwm_data_v1 = { .duty = PWMV1_CDTY, .duty_upd = PWMV1_CUPD, }, + .cfg = { + /* 16 bits to keep period and duty. */ + .max_period = PWM_MAXV1_PRD, + .max_pres = PRD_MAXV1_PRES, + }, }; static const struct atmel_pwm_data atmel_pwm_data_v2 = { @@ -297,6 +308,11 @@ static const struct atmel_pwm_data atmel_pwm_data_v2 = { .duty = PWMV2_CDTY, .duty_upd = PWMV2_CDTYUPD, }, + .cfg = { + /* 16 bits to keep period and duty. */ + .max_period = PWM_MAXV1_PRD, + .max_pres = PRD_MAXV1_PRES, + }, }; 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Signed-off-by: Claudiu Beznea --- drivers/pwm/pwm-atmel.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/pwm/pwm-atmel.c b/drivers/pwm/pwm-atmel.c index 44f4a1c9f60b..44a99ba60e11 100644 --- a/drivers/pwm/pwm-atmel.c +++ b/drivers/pwm/pwm-atmel.c @@ -315,6 +315,20 @@ static const struct atmel_pwm_data atmel_pwm_data_v2 = { }, }; +static const struct atmel_pwm_data atmel_pwm_data_v3 = { + .regs = { + .period = PWMV1_CPRD, + .period_upd = PWMV1_CUPD, + .duty = PWMV1_CDTY, + .duty_upd = PWMV1_CUPD, + }, + .cfg = { + /* 32 bits to keep period and duty. */ + .max_period = PWM_MAXV2_PRD, + .max_pres = PRD_MAXV1_PRES, + }, +}; + static const struct platform_device_id atmel_pwm_devtypes[] = { { .name = "at91sam9rl-pwm", @@ -339,6 +353,9 @@ static const struct of_device_id atmel_pwm_dt_ids[] = { .compatible = "atmel,sama5d2-pwm", .data = &atmel_pwm_data_v2, }, { + .compatible = "microchip,sam9x60-pwm", + .data = &atmel_pwm_data_v3, + }, { /* sentinel */ }, }; From patchwork Mon Jan 21 12:31:01 2019 Content-Type: text/plain; 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Signed-off-by: Claudiu Beznea Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/pwm/atmel-pwm.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pwm/atmel-pwm.txt b/Documentation/devicetree/bindings/pwm/atmel-pwm.txt index c8c831d7b0d1..591ecdd39c7b 100644 --- a/Documentation/devicetree/bindings/pwm/atmel-pwm.txt +++ b/Documentation/devicetree/bindings/pwm/atmel-pwm.txt @@ -5,6 +5,7 @@ Required properties: - "atmel,at91sam9rl-pwm" - "atmel,sama5d3-pwm" - "atmel,sama5d2-pwm" + - "microchip,sam9x60-pwm" - reg: physical base address and length of the controller's registers - #pwm-cells: Should be 3. See pwm.txt in this directory for a description of the cells format.