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[108.26.185.122]) by smtp.gmail.com with ESMTPSA id br8-20020a05620a460800b006cf38fd659asm6318428qkb.103.2022.11.06.23.15.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 06 Nov 2022 23:15:13 -0800 (PST) From: Jesse Taube X-Google-Original-From: Jesse Taube To: linux-imx@nxp.com Cc: robh+dt@kernel.org, sboyd@kernel.org, shawnguo@kernel.org, kernel@pengutronix.de, festevam@gmail.com, aisheng.dong@nxp.com, stefan@agner.ch, linus.walleij@linaro.org, gregkh@linuxfoundation.org, arnd@arndb.de, linux@armlinux.org.uk, abel.vesa@nxp.com, dev@lynxeye.de, marcel.ziswiler@toradex.com, tharvey@gateworks.com, leoyang.li@nxp.com, fugang.duan@nxp.com, Mr.Bossman075@gmail.com, giulio.benetti@benettiengineering.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, Rob Herring Subject: [PATCH v1 1/7] dt-bindings: arm: imx: Add i.MXRT compatible Documentation Date: Mon, 7 Nov 2022 02:15:05 -0500 Message-Id: <20221107071511.2764628-2-Mr.Bossman075@gmail.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20221107071511.2764628-1-Mr.Bossman075@gmail.com> References: <20221107071511.2764628-1-Mr.Bossman075@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221106_231515_550463_35930A77 X-CRM114-Status: UNSURE ( 9.14 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Recently the imxrt1050 was added but the cpu compatible node wasn't added. Add both i.MXRT1170 and 1050 compatibles to fsl.yaml. Cc: Giulio Benetti Signed-off-by: Jesse Taube Acked-by: Rob Herring --- Documentation/devicetree/bindings/arm/fsl.yaml | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 59e6e8b4dab3..a95b774e5d67 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1046,6 +1046,18 @@ properties: - fsl,imx93-11x11-evk # i.MX93 11x11 EVK Board - const: fsl,imx93 + - description: i.MXRT1050 based Boards + items: + - enum: + - fsl,imxrt1050-evk # i.MXRT1050 EVK Board + - const: fsl,imxrt1050 + + - description: i.MXRT1170 based Boards + items: + - enum: + - fsl,imxrt1170-evk # i.MXRT1170 EVK Board + - const: fsl,imxrt1170 + - description: Freescale Vybrid Platform Device Tree Bindings From patchwork Mon Nov 7 07:15:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jesse Taube X-Patchwork-Id: 13033854 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 049E7C43219 for ; Mon, 7 Nov 2022 07:16:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=t+7uIwP9/QNY09HutuvySb8b32BMoA2PTcEP75s1uYM=; b=4Cwpd34d57WRDK b/9Qz9hUaDRvhi0W3Oin+cnz/FFtzz3ItDrQbT/uF20VgXrx43GFGmphphrO7HrR2B2V7UQIEPcfN DDm59/s/khSd3VGTI5tJwwcAXgHp3tKhQK0ZmANrtr9yFrUmsgEnxWbFaZptSTOHLJecRspZLmJEz Lo+liGKvtGfGt0CUx2LxAuCKOWQ3Lhi7wuELKP1hl+RCmUVzhoDPOasskVwBEudefqOeFvMhvIG1S 5WH2M/uL4hKhqW+rIErDCEfFvSb7lZnajzqSIeYxMqmi6CIik9LSKfCLkfzUGjiTXVQNeOf6OFntn GHucyv6Wa8+UXmmR8iew==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1orwM2-00CFqG-Fy; Mon, 07 Nov 2022 07:15:34 +0000 Received: from mail-qk1-x729.google.com ([2607:f8b0:4864:20::729]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1orwLk-00CFh2-In for linux-arm-kernel@lists.infradead.org; Mon, 07 Nov 2022 07:15:17 +0000 Received: by mail-qk1-x729.google.com with SMTP id p18so2133044qkg.2 for ; Sun, 06 Nov 2022 23:15:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=8XNx+rgJgduq7rCvuRhTlcngQGfS0jYPWbvWIVqx1qM=; b=fkfG9ot2ZJgYRbjgmfQajtUOKmevc7ckdcsndCM1TmZAPhW6j+EysoQPGDBwIJRxgq NE3yWYDf/T5yPZRzXdSOGT+vS4p83A0LAfW44V+LJFZgK9HfZBlMxEsYoYeWeMyXy4KR Qneape2Fqn0VRYB72SmDoFFfjTxZNdaDxjcD54Ie9/QNzwfLHy0GVt7fFqgpiWOfVIiO 2/ZnikDSmoABsfIoxJ0p34AQIgAg6jtB3imD0BYedVnBBB1qfS1wnApFT2H7f1Kd0Gti Xqzt60nux9KRPbQAhfoM1GMffCVsXXi2CEJKKCPjXbrYLSbVeV2PowzLNHs5MP37kAl2 UIMw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8XNx+rgJgduq7rCvuRhTlcngQGfS0jYPWbvWIVqx1qM=; b=I8NDI56LM1fpjNTEW91IqIvtFTlOs3D3uqVXdkPc0i/hCL9WvlZt/TgCAHJb3gAqaQ VcJAAyMV4/a2SoE4h7IdtMvvIpbOUfHLk0fLF5a8z2074yDg2g2YNsxAsc8gHFkr+fbH 0bQzniPnPKhoa+J9rlRr725QwFUcrlcVi3ujc9pAvawrhKVI2Ft8YYvCaFLV+V7j7WQK JSldlgjWxS3ZjErL+W8ZvT1ZNfJIkqFiIS4+HQwp0nSL267/Scb+8N//Sy4n/WrvZjjj ZYaVoUFreyeL1B9stAvnmHYXCdtGTIYlMpng38OwKvgkGvKlrmjzSFMhuGuhJT+iDsEv 9s/w== X-Gm-Message-State: ACrzQf36xLZjkA/q+SrmbjWZJp3TZqGe0geZ5ucPZBDmpl6BCkEGSsw/ V5w3dWhlzueQD208QxTXkys= X-Google-Smtp-Source: AMsMyM77e+VuZnZM7E7UgYqBiy6cpufDm9treTU+akYNQtE5dR3s7GTF4Q0lLO9teekpOEtECVAWow== X-Received: by 2002:a05:620a:2b45:b0:6fa:509f:d0c2 with SMTP id dp5-20020a05620a2b4500b006fa509fd0c2mr21882138qkb.302.1667805315213; Sun, 06 Nov 2022 23:15:15 -0800 (PST) Received: from jesse-desktop.jtp-bos.lab (pool-108-26-185-122.bstnma.fios.verizon.net. [108.26.185.122]) by smtp.gmail.com with ESMTPSA id br8-20020a05620a460800b006cf38fd659asm6318428qkb.103.2022.11.06.23.15.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 06 Nov 2022 23:15:14 -0800 (PST) From: Jesse Taube X-Google-Original-From: Jesse Taube To: linux-imx@nxp.com Cc: robh+dt@kernel.org, sboyd@kernel.org, shawnguo@kernel.org, kernel@pengutronix.de, festevam@gmail.com, aisheng.dong@nxp.com, stefan@agner.ch, linus.walleij@linaro.org, gregkh@linuxfoundation.org, arnd@arndb.de, linux@armlinux.org.uk, abel.vesa@nxp.com, dev@lynxeye.de, marcel.ziswiler@toradex.com, tharvey@gateworks.com, leoyang.li@nxp.com, fugang.duan@nxp.com, Mr.Bossman075@gmail.com, giulio.benetti@benettiengineering.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org Subject: [PATCH v1 2/7] dt-bindings: pinctrl: Fix file path for pinfunc include Date: Mon, 7 Nov 2022 02:15:06 -0500 Message-Id: <20221107071511.2764628-3-Mr.Bossman075@gmail.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20221107071511.2764628-1-Mr.Bossman075@gmail.com> References: <20221107071511.2764628-1-Mr.Bossman075@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221106_231516_635497_16DBB22F X-CRM114-Status: GOOD ( 12.42 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Reference to pinfunc.h was wrong. Fix it. Cc: Giulio Benetti Signed-off-by: Jesse Taube --- Documentation/devicetree/bindings/pinctrl/fsl,imxrt1050.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imxrt1050.yaml b/Documentation/devicetree/bindings/pinctrl/fsl,imxrt1050.yaml index 1278f7293560..db5fe66ad873 100644 --- a/Documentation/devicetree/bindings/pinctrl/fsl,imxrt1050.yaml +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imxrt1050.yaml @@ -35,7 +35,7 @@ patternProperties: each entry consists of 6 integers and represents the mux and config setting for one pin. The first 5 integers are specified using a PIN_FUNC_ID macro, which can - be found in . The last + be found in . The last integer CONFIG is the pad setting value like pull-up on this pin. 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[108.26.185.122]) by smtp.gmail.com with ESMTPSA id br8-20020a05620a460800b006cf38fd659asm6318428qkb.103.2022.11.06.23.15.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 06 Nov 2022 23:15:16 -0800 (PST) From: Jesse Taube X-Google-Original-From: Jesse Taube To: linux-imx@nxp.com Cc: robh+dt@kernel.org, sboyd@kernel.org, shawnguo@kernel.org, kernel@pengutronix.de, festevam@gmail.com, aisheng.dong@nxp.com, stefan@agner.ch, linus.walleij@linaro.org, gregkh@linuxfoundation.org, arnd@arndb.de, linux@armlinux.org.uk, abel.vesa@nxp.com, dev@lynxeye.de, marcel.ziswiler@toradex.com, tharvey@gateworks.com, leoyang.li@nxp.com, fugang.duan@nxp.com, Mr.Bossman075@gmail.com, giulio.benetti@benettiengineering.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, Krzysztof Kozlowski Subject: [PATCH v1 3/7] dt-bindings: timer: gpt: Add i.MXRT compatible Documentation Date: Mon, 7 Nov 2022 02:15:07 -0500 Message-Id: <20221107071511.2764628-4-Mr.Bossman075@gmail.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20221107071511.2764628-1-Mr.Bossman075@gmail.com> References: <20221107071511.2764628-1-Mr.Bossman075@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221106_231518_298339_90855C0B X-CRM114-Status: UNSURE ( 9.33 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Both the i.MXRT1170 and 1050 have the same GPT timer as "fsl,imx6dl-gpt" Add i.MXRT to the compatible list. Cc: Giulio Benetti Signed-off-by: Jesse Taube Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/timer/fsl,imxgpt.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/timer/fsl,imxgpt.yaml b/Documentation/devicetree/bindings/timer/fsl,imxgpt.yaml index a4f51f46b7a1..716c6afcca1f 100644 --- a/Documentation/devicetree/bindings/timer/fsl,imxgpt.yaml +++ b/Documentation/devicetree/bindings/timer/fsl,imxgpt.yaml @@ -31,6 +31,8 @@ properties: - enum: - fsl,imx6sl-gpt - fsl,imx6sx-gpt + - fsl,imxrt1050-gpt + - fsl,imxrt1170-gpt - const: fsl,imx6dl-gpt reg: From patchwork Mon Nov 7 07:15:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jesse Taube X-Patchwork-Id: 13033856 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5A162C4332F for ; Mon, 7 Nov 2022 07:17:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=qtoFLdKIwcWdy/qYPP5EJq4F7L4avNhd4EJSkZX+hlc=; b=MD/466thn5RbOf FP9nx7YTJJeFuSpmvDDWtha2AjjILVId520sQrIS5ukSypj06HXv7C0RJ/h9NIvKfbJGP2FlnzIkP JWEd5fyRqOfvXiTQcvbixNtNxuYRGYu/kgFL1PeygHsxOBHpPtW4LXCiIzB3BsJ3UdYNYt0T0seLX kf1qvGADzVMq+l92VNRnSQvBkH/ReRDiEhEDAucpz2e6zxSGba6I+qx+fCfhV1ywnHBL2/XxG+A6b NFV6a/psCGBwktYFMGdeKNFpFn7VaBnNpgRttar5zvbB2k+afRV6/Z0UJLOpX0gTaEUSXcitTSJZ1 qC8Qc7JiHIw9ciPJJ7Pg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1orwMJ-00CFvU-DC; Mon, 07 Nov 2022 07:15:51 +0000 Received: from mail-qt1-x82c.google.com ([2607:f8b0:4864:20::82c]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1orwLm-00CFhv-Va for linux-arm-kernel@lists.infradead.org; Mon, 07 Nov 2022 07:15:20 +0000 Received: by mail-qt1-x82c.google.com with SMTP id fz10so6447599qtb.3 for ; Sun, 06 Nov 2022 23:15:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=FevbBLdguXCFmnA0gYiJMt8h51HW7EHdkkwF3DmVtiM=; b=Oj0vqp+43Yq+/jWzQLRnuJhR+XUgWDl31H1CMGjjWKzn9r8KSbLXPNTvPdJEaZ5LZI q0MoSips3u+fpLOOMflvcjpjvyHYCYof38b3K4RFWeTtVCT7vOqgzTstARhu2SGwZ5eN RbfQACddReC7PUwmkvuMRr6z3s8M2BHVvamSCwAp+KQV6AKPJDYvBMPGskowB03uihae DCxz4EXPbPSz3mxqN8S7a+Egc602hA2cYKRn/cia5q81vyKYiIQ0CIzpEgbpQaAM3j7e nf6rKB1Rvpgv2X1vmH/u3iSF/JcwAOHP58jjUrs0TKhaG8DPnACLEyb9VSIJt2HrqZ04 5Atw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FevbBLdguXCFmnA0gYiJMt8h51HW7EHdkkwF3DmVtiM=; b=Wnj9J15h03ki1eAUSz18ZqEa68sZlMw77qrBxFf3o+Qu+NU8nbP8miwzH1vHZ8w7ai hA2KhGZMIrJf1W8u0FjXsbbL4D8fkhXeqbSeKvVLSZGErxXRgOvSJqQyP1Ox3ygsVjCh 0ra2TsrSupKtSfbACVP0tiJswlC4VZ6hKL2Xmz7nw3GHIcJxd9aHNgc5C2482nJeFbId oxRtbOUB3fUk66A+WvXyslFN1m+0wdj8B/lLtRfO1ZFzXGYc7LWGQ+pCoFTSfop5iViT yxRJeE9ntVKqqIAEqWFLOQ0wVuPfh/PEltGkXLYTxchERNYKa7PmEzjtfw0G0jKwUPq1 7Uow== X-Gm-Message-State: ANoB5pltfctjtw1lI016m9Wb5D9/T+/Prw5+MZ3fe2NhYbVXN2Akb2EV pSGTWDs1WjUx58hr5h6GXdA= X-Google-Smtp-Source: AA0mqf7SQASvWKnqHMl5xXSgn1OAMYbUQcQ7wyKnX1Z91mCBgs4y4/2sjwK3qPE81S9M9O3kpXEbRQ== X-Received: by 2002:a05:622a:11d0:b0:3a5:8ff2:8496 with SMTP id n16-20020a05622a11d000b003a58ff28496mr2679067qtk.302.1667805317449; Sun, 06 Nov 2022 23:15:17 -0800 (PST) Received: from jesse-desktop.jtp-bos.lab (pool-108-26-185-122.bstnma.fios.verizon.net. [108.26.185.122]) by smtp.gmail.com with ESMTPSA id br8-20020a05620a460800b006cf38fd659asm6318428qkb.103.2022.11.06.23.15.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 06 Nov 2022 23:15:17 -0800 (PST) From: Jesse Taube X-Google-Original-From: Jesse Taube To: linux-imx@nxp.com Cc: robh+dt@kernel.org, sboyd@kernel.org, shawnguo@kernel.org, kernel@pengutronix.de, festevam@gmail.com, aisheng.dong@nxp.com, stefan@agner.ch, linus.walleij@linaro.org, gregkh@linuxfoundation.org, arnd@arndb.de, linux@armlinux.org.uk, abel.vesa@nxp.com, dev@lynxeye.de, marcel.ziswiler@toradex.com, tharvey@gateworks.com, leoyang.li@nxp.com, fugang.duan@nxp.com, Mr.Bossman075@gmail.com, giulio.benetti@benettiengineering.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, Rob Herring Subject: [PATCH v1 4/7] dt-bindings: serial: fsl-lpuart: add i.MXRT1170 compatible Date: Mon, 7 Nov 2022 02:15:08 -0500 Message-Id: <20221107071511.2764628-5-Mr.Bossman075@gmail.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20221107071511.2764628-1-Mr.Bossman075@gmail.com> References: <20221107071511.2764628-1-Mr.Bossman075@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221106_231519_035498_5B710700 X-CRM114-Status: UNSURE ( 8.84 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add i.MXRT1170 compatible string to Documentation. Cc: Giulio Benetti Signed-off-by: Jesse Taube Acked-by: Rob Herring --- Documentation/devicetree/bindings/serial/fsl-lpuart.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/serial/fsl-lpuart.yaml b/Documentation/devicetree/bindings/serial/fsl-lpuart.yaml index 30eaa62e1aed..74f75f669e77 100644 --- a/Documentation/devicetree/bindings/serial/fsl-lpuart.yaml +++ b/Documentation/devicetree/bindings/serial/fsl-lpuart.yaml @@ -32,6 +32,9 @@ properties: - fsl,imx8qm-lpuart - fsl,imx8dxl-lpuart - const: fsl,imx8qxp-lpuart + - items: + - const: fsl,imxrt1050-lpuart + - const: fsl,imxrt1170-lpuart reg: maxItems: 1 From patchwork Mon Nov 7 07:15:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jesse Taube X-Patchwork-Id: 13033857 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8CCD8C433FE for ; Mon, 7 Nov 2022 07:17:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=hiqBRl78PCKgbEYfieroVqfcw8Vsigo0owIFEhBQ7KI=; b=4ZeggF8IfdP59Y 0RMnhK6iLnsATIrebfneq/NfFYMxOpSrc2/M2p4ykUQQWeTo4OWJHmvtlcE67OxZL5HbAN3mbSaPP j4LHpGP26Kh2h9TlsR4rHToqbFwqz+890P4lMMnNF2prGD9aPN7ib7AIOlLdZBw8ZLc2yqRFPyuce K54/YrBc3UPzkTdaum9dDynJYSAeFf9yTwxREdAP5Io+MwQU7TCK856SIFz8weM5ypIX9Kqf2V9f3 HbO69kbG1d6eGcYGNKlOaLyKT9UXfiY50Vi74aam9GbzK+86BH/wjlkjQN5eOBRhO1LmrJMdjX1xr RkYCt9FwnWynfO9IKNrA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1orwMR-00CFz5-SP; Mon, 07 Nov 2022 07:16:00 +0000 Received: from mail-qk1-x735.google.com ([2607:f8b0:4864:20::735]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1orwLp-00CFib-1n for linux-arm-kernel@lists.infradead.org; Mon, 07 Nov 2022 07:15:22 +0000 Received: by mail-qk1-x735.google.com with SMTP id 8so6698131qka.1 for ; Sun, 06 Nov 2022 23:15:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=h0r57Vvw4A7lJzIo/9EbiUI/3USItkedCC8EGqi95SU=; b=FmYBOZqYub8si8sSull+j9QRtiVf7LQKFWqcrUoqWpAz/CjcJmAbFmKbUQiUB2HMya WLVc8I+SP19VDoZZ5exD/CvkLgRcuX23bE5NRaTfJG7NVFjXGZJes0VeqCxZ4SICr+lQ Q9kG0U5bueB+d1T7hNWtWMtsvDin8p1Jn5Q0ubf8ClzFXepOumhs3uQ1qjDzZRWEt1V6 JVe4uyeZlx/NVfW3hQmRl+MkAdMQq21aqyAXbKbxcob1LcMUZ+8mVyfwM5ChBuCO+Dql ILziT+Pvc/mUADH/AcTg5Db7KY395ykiVuNRr7vvdFyBFx+5VjJd/YXBoT5wUx/E35eU qbqw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=h0r57Vvw4A7lJzIo/9EbiUI/3USItkedCC8EGqi95SU=; b=ZNPvQB57RRjL8zGwbjLPreGZGQkCYWy4Jo3CdU3h07DHjZIsov1UnXCC4V7KbCT0Zi x6XOkmT/NcLjL0fTsw/TRVWGWEw7fH0Ox/9KyzJdgLxO7ijKOi1ObXhhK5/uPywrbvYr EEUtZx1TqynqyH2wVIas1RAxNb8tsz4xJFA0MuJmOBmxJ6SW8E9Uz6EB7rPev6oXPJjg swRc88GnTEU7g7qVYiEg5TBuC1h4vsH2E5pPc+Yp3wP6/PoWf5Udo875YKIkDvwSmm6/ vc99vzr+vdSQy2MlGNlfSyPeaJqyLBuj5C59pHO/2a2zGFTsIBctrz1UqDu8uVRdnzMP aVMQ== X-Gm-Message-State: ACrzQf0VdzsMymnba6UYIWMblwxKIVselIY1APUsbduZowxLF1HdToOY sukKbqJD4iiWszqlK6jscx0= X-Google-Smtp-Source: AMsMyM4Cger4O1dNqIMvlSZOE1rmt3mv+pZVh6V5xEukOqvLnKxxpug2f51xjjbdOYp+fpY6Jbtzcw== X-Received: by 2002:a05:620a:9cb:b0:6fa:22bf:9fa with SMTP id y11-20020a05620a09cb00b006fa22bf09famr30741111qky.625.1667805319141; Sun, 06 Nov 2022 23:15:19 -0800 (PST) Received: from jesse-desktop.jtp-bos.lab (pool-108-26-185-122.bstnma.fios.verizon.net. [108.26.185.122]) by smtp.gmail.com with ESMTPSA id br8-20020a05620a460800b006cf38fd659asm6318428qkb.103.2022.11.06.23.15.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 06 Nov 2022 23:15:18 -0800 (PST) From: Jesse Taube X-Google-Original-From: Jesse Taube To: linux-imx@nxp.com Cc: robh+dt@kernel.org, sboyd@kernel.org, shawnguo@kernel.org, kernel@pengutronix.de, festevam@gmail.com, aisheng.dong@nxp.com, stefan@agner.ch, linus.walleij@linaro.org, gregkh@linuxfoundation.org, arnd@arndb.de, linux@armlinux.org.uk, abel.vesa@nxp.com, dev@lynxeye.de, marcel.ziswiler@toradex.com, tharvey@gateworks.com, leoyang.li@nxp.com, fugang.duan@nxp.com, Mr.Bossman075@gmail.com, giulio.benetti@benettiengineering.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, Rob Herring Subject: [PATCH v1 5/7] dt-bindings: mmc: fsl-imx-esdhc: add i.MXRT1170 compatible Date: Mon, 7 Nov 2022 02:15:09 -0500 Message-Id: <20221107071511.2764628-6-Mr.Bossman075@gmail.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20221107071511.2764628-1-Mr.Bossman075@gmail.com> References: <20221107071511.2764628-1-Mr.Bossman075@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221106_231521_111704_5B91FE3E X-CRM114-Status: UNSURE ( 8.52 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add i.MXRT1170 compatible string to Documentation. Cc: Giulio Benetti Signed-off-by: Jesse Taube Acked-by: Rob Herring --- Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml b/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml index 29339d0196ec..0e7833478869 100644 --- a/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml +++ b/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml @@ -75,6 +75,10 @@ properties: - const: fsl,imx8qxp-usdhc - const: fsl,imx7d-usdhc deprecated: true + - items: + - enum: + - fsl,imxrt1170-usdhc + - const: fsl,imxrt1050-usdhc reg: maxItems: 1 From patchwork Mon Nov 7 07:15:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jesse Taube X-Patchwork-Id: 13033859 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 985B5C4332F for ; Mon, 7 Nov 2022 07:17:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=e+GdBtuxpUuVWzhixUWEoxHoecvoArzyINnZ2E7SnhQ=; b=oeIlV6BDwBZFCM nxY6LDxfNtmVROl436daKU51k5zB2GWVpLY8MIkB0slWE0jiGOsq7PIezilyVVhj3YuZqckJyEklF gGlZ40G4L1LToRmoCMXroyslfJjILg+4u0PrPYt4QmqkmXCvyeR2VhoCfWDEa8uGACt+yZwDI8mrv 3mGb68xPNRQ/vhALvPJbdI6q7ajTho2k0Z1Y1pUAw0HeH2i+zVk/8HnTh/R3RPy1IFqJ7I11IjirS aFI9uVc+Mnt8RiHi8L7D4/J31iQK2vyFgAo5Tn6qg+EJokjrFJaT39EHURHx6fjOog4NxHfRWWZLv JbAoPNSc9EfLZjMtYGmw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1orwMv-00CGH7-V8; Mon, 07 Nov 2022 07:16:30 +0000 Received: from mail-qv1-xf31.google.com ([2607:f8b0:4864:20::f31]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1orwLp-00CFio-LG for linux-arm-kernel@lists.infradead.org; Mon, 07 Nov 2022 07:15:24 +0000 Received: by mail-qv1-xf31.google.com with SMTP id n18so7535485qvt.11 for ; Sun, 06 Nov 2022 23:15:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=rX9oq4gzaxqNQxYOSZWc5oRwei2M0k3tGKlh2M3xFwY=; b=nXubkkCNVy4EbvJWJwlGX52yAVpSvJfugoUK65TWlb9kHAah9rt/Czzhyy+xGyacY6 Nm5jjZ3o7WYsuNlg/NEJVn0Jt6RDvQbI4h9kE7QYwPpd3GdMSqAPbqnnj2ELOqIZfziv qmsrtZ5IzPItyA+BBfhITZbS9TNdKNbvl3OO47g7/nXujavFl7kq7z3MdMLliYT52T+h h4+7dsLzlFcKldjT10mX2NwxCQl/UmSwDIa9F5rAVReZBjVF6AbCyPQ7V63fKFGYGb7p R9i7/lWgs3NamZ4nh8rLhRjaDpblu+od2hc8QmKJBWBp5H4nHBh95HPAB2dmkSOwXkbK 2sZw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rX9oq4gzaxqNQxYOSZWc5oRwei2M0k3tGKlh2M3xFwY=; b=St350aCLc/D/wbt3fTBISlzOVSt0c4ZClM00DxXvYMgZnMOCWFnDCacuLGoHi+WJaZ QOnCnZ24Q2N5tWmIuBtCCnRpKhjxgjoiWJMiuLJI/OjwwcDYLvb40oT8CxYUh90QMPgw c7BGCJYXVoz/VtYpoypsBK801XvRyzEGzREdo3g96VHpFVGfhw0NVuafzHvrHP4Lun8I 0VSIPTk3poGGwmHs4u7yP0kbhSWabc3OnrEq88hlMx0Y9sniwEXMthI2UIf+LVJCp0UU Lx0q3C0PKitX4uuBWrf2MDgIU0HyugjpNPDKXPh0xk2qzCTfDjwJovhFt5q+I0wIz1kj OkJA== X-Gm-Message-State: ACrzQf1wsAhnoEBIeEwi9ftk5brr2gPVbf6cCO03wZnzQ28pQXGygx4V jB65y+rP9B+4KDHnmOXb1H0= X-Google-Smtp-Source: AMsMyM75UWsLtkNX29wLm6t+PvP+g8F6i0ThbS1ahxlr4tDFGa2Q84ZiHgouH3LyD3hwtnVsryBb4Q== X-Received: by 2002:a05:6214:29e9:b0:4bc:da6:d604 with SMTP id jv9-20020a05621429e900b004bc0da6d604mr32888792qvb.106.1667805320233; Sun, 06 Nov 2022 23:15:20 -0800 (PST) Received: from jesse-desktop.jtp-bos.lab (pool-108-26-185-122.bstnma.fios.verizon.net. [108.26.185.122]) by smtp.gmail.com with ESMTPSA id br8-20020a05620a460800b006cf38fd659asm6318428qkb.103.2022.11.06.23.15.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 06 Nov 2022 23:15:19 -0800 (PST) From: Jesse Taube X-Google-Original-From: Jesse Taube To: linux-imx@nxp.com Cc: robh+dt@kernel.org, sboyd@kernel.org, shawnguo@kernel.org, kernel@pengutronix.de, festevam@gmail.com, aisheng.dong@nxp.com, stefan@agner.ch, linus.walleij@linaro.org, gregkh@linuxfoundation.org, arnd@arndb.de, linux@armlinux.org.uk, abel.vesa@nxp.com, dev@lynxeye.de, marcel.ziswiler@toradex.com, tharvey@gateworks.com, leoyang.li@nxp.com, fugang.duan@nxp.com, Mr.Bossman075@gmail.com, giulio.benetti@benettiengineering.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org Subject: [PATCH v1 6/7] pinctrl: freescale: Fix i.MXRT1050 pad names Date: Mon, 7 Nov 2022 02:15:10 -0500 Message-Id: <20221107071511.2764628-7-Mr.Bossman075@gmail.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20221107071511.2764628-1-Mr.Bossman075@gmail.com> References: <20221107071511.2764628-1-Mr.Bossman075@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221106_231521_731393_0BE5C275 X-CRM114-Status: GOOD ( 10.71 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The pad names for the i.MXRT1050 were incorrect. Fix them. Cc: Giulio Benetti Signed-off-by: Jesse Taube --- drivers/pinctrl/freescale/pinctrl-imxrt1050.c | 546 ++++++++---------- 1 file changed, 253 insertions(+), 293 deletions(-) diff --git a/drivers/pinctrl/freescale/pinctrl-imxrt1050.c b/drivers/pinctrl/freescale/pinctrl-imxrt1050.c index 11f31c90ad30..def683839ebe 100644 --- a/drivers/pinctrl/freescale/pinctrl-imxrt1050.c +++ b/drivers/pinctrl/freescale/pinctrl-imxrt1050.c @@ -13,155 +13,135 @@ #include "pinctrl-imx.h" enum imxrt1050_pads { - IMXRT1050_PAD_RESERVE0 = 0, - IMXRT1050_PAD_RESERVE1 = 1, - IMXRT1050_PAD_RESERVE2 = 2, - IMXRT1050_PAD_RESERVE3 = 3, - IMXRT1050_PAD_RESERVE4 = 4, - IMXRT1050_PAD_RESERVE5 = 5, - IMXRT1050_PAD_RESERVE6 = 6, - IMXRT1050_PAD_RESERVE7 = 7, - IMXRT1050_PAD_RESERVE8 = 8, - IMXRT1050_PAD_RESERVE9 = 9, - IMXRT1050_IOMUXC_GPIO1_IO00 = 10, - IMXRT1050_IOMUXC_GPIO1_IO01 = 11, - IMXRT1050_IOMUXC_GPIO1_IO02 = 12, - IMXRT1050_IOMUXC_GPIO1_IO03 = 13, - IMXRT1050_IOMUXC_GPIO1_IO04 = 14, - IMXRT1050_IOMUXC_GPIO1_IO05 = 15, - IMXRT1050_IOMUXC_GPIO1_IO06 = 16, - IMXRT1050_IOMUXC_GPIO1_IO07 = 17, - IMXRT1050_IOMUXC_GPIO1_IO08 = 18, - IMXRT1050_IOMUXC_GPIO1_IO09 = 19, - IMXRT1050_IOMUXC_GPIO1_IO10 = 20, - IMXRT1050_IOMUXC_GPIO1_IO11 = 21, - IMXRT1050_IOMUXC_GPIO1_IO12 = 22, - IMXRT1050_IOMUXC_GPIO1_IO13 = 23, - IMXRT1050_IOMUXC_GPIO1_IO14 = 24, - IMXRT1050_IOMUXC_GPIO1_IO15 = 25, - IMXRT1050_IOMUXC_ENET_MDC = 26, - IMXRT1050_IOMUXC_ENET_MDIO = 27, - IMXRT1050_IOMUXC_ENET_TD3 = 28, - IMXRT1050_IOMUXC_ENET_TD2 = 29, - IMXRT1050_IOMUXC_ENET_TD1 = 30, - IMXRT1050_IOMUXC_ENET_TD0 = 31, - IMXRT1050_IOMUXC_ENET_TX_CTL = 32, - IMXRT1050_IOMUXC_ENET_TXC = 33, - IMXRT1050_IOMUXC_ENET_RX_CTL = 34, - IMXRT1050_IOMUXC_ENET_RXC = 35, - IMXRT1050_IOMUXC_ENET_RD0 = 36, - IMXRT1050_IOMUXC_ENET_RD1 = 37, - IMXRT1050_IOMUXC_ENET_RD2 = 38, - IMXRT1050_IOMUXC_ENET_RD3 = 39, - IMXRT1050_IOMUXC_SD1_CLK = 40, - IMXRT1050_IOMUXC_SD1_CMD = 41, - IMXRT1050_IOMUXC_SD1_DATA0 = 42, - IMXRT1050_IOMUXC_SD1_DATA1 = 43, - IMXRT1050_IOMUXC_SD1_DATA2 = 44, - IMXRT1050_IOMUXC_SD1_DATA3 = 45, - IMXRT1050_IOMUXC_SD1_DATA4 = 46, - IMXRT1050_IOMUXC_SD1_DATA5 = 47, - IMXRT1050_IOMUXC_SD1_DATA6 = 48, - IMXRT1050_IOMUXC_SD1_DATA7 = 49, - IMXRT1050_IOMUXC_SD1_RESET_B = 50, - IMXRT1050_IOMUXC_SD1_STROBE = 51, - IMXRT1050_IOMUXC_SD2_CD_B = 52, - IMXRT1050_IOMUXC_SD2_CLK = 53, - IMXRT1050_IOMUXC_SD2_CMD = 54, - IMXRT1050_IOMUXC_SD2_DATA0 = 55, - IMXRT1050_IOMUXC_SD2_DATA1 = 56, - IMXRT1050_IOMUXC_SD2_DATA2 = 57, - IMXRT1050_IOMUXC_SD2_DATA3 = 58, - IMXRT1050_IOMUXC_SD2_RESET_B = 59, - IMXRT1050_IOMUXC_SD2_WP = 60, - IMXRT1050_IOMUXC_NAND_ALE = 61, - IMXRT1050_IOMUXC_NAND_CE0 = 62, - IMXRT1050_IOMUXC_NAND_CE1 = 63, - IMXRT1050_IOMUXC_NAND_CE2 = 64, - IMXRT1050_IOMUXC_NAND_CE3 = 65, - IMXRT1050_IOMUXC_NAND_CLE = 66, - IMXRT1050_IOMUXC_NAND_DATA00 = 67, - IMXRT1050_IOMUXC_NAND_DATA01 = 68, - IMXRT1050_IOMUXC_NAND_DATA02 = 69, - IMXRT1050_IOMUXC_NAND_DATA03 = 70, - IMXRT1050_IOMUXC_NAND_DATA04 = 71, - IMXRT1050_IOMUXC_NAND_DATA05 = 72, - IMXRT1050_IOMUXC_NAND_DATA06 = 73, - IMXRT1050_IOMUXC_NAND_DATA07 = 74, - IMXRT1050_IOMUXC_NAND_DQS = 75, - IMXRT1050_IOMUXC_NAND_RE_B = 76, - IMXRT1050_IOMUXC_NAND_READY_B = 77, - IMXRT1050_IOMUXC_NAND_WE_B = 78, - IMXRT1050_IOMUXC_NAND_WP_B = 79, - IMXRT1050_IOMUXC_SAI5_RXFS = 80, - IMXRT1050_IOMUXC_SAI5_RXC = 81, - IMXRT1050_IOMUXC_SAI5_RXD0 = 82, - IMXRT1050_IOMUXC_SAI5_RXD1 = 83, - IMXRT1050_IOMUXC_SAI5_RXD2 = 84, - IMXRT1050_IOMUXC_SAI5_RXD3 = 85, - IMXRT1050_IOMUXC_SAI5_MCLK = 86, - IMXRT1050_IOMUXC_SAI1_RXFS = 87, - IMXRT1050_IOMUXC_SAI1_RXC = 88, - IMXRT1050_IOMUXC_SAI1_RXD0 = 89, - IMXRT1050_IOMUXC_SAI1_RXD1 = 90, - IMXRT1050_IOMUXC_SAI1_RXD2 = 91, - IMXRT1050_IOMUXC_SAI1_RXD3 = 92, - IMXRT1050_IOMUXC_SAI1_RXD4 = 93, - IMXRT1050_IOMUXC_SAI1_RXD5 = 94, - IMXRT1050_IOMUXC_SAI1_RXD6 = 95, - IMXRT1050_IOMUXC_SAI1_RXD7 = 96, - IMXRT1050_IOMUXC_SAI1_TXFS = 97, - IMXRT1050_IOMUXC_SAI1_TXC = 98, - IMXRT1050_IOMUXC_SAI1_TXD0 = 99, - IMXRT1050_IOMUXC_SAI1_TXD1 = 100, - IMXRT1050_IOMUXC_SAI1_TXD2 = 101, - IMXRT1050_IOMUXC_SAI1_TXD3 = 102, - IMXRT1050_IOMUXC_SAI1_TXD4 = 103, - IMXRT1050_IOMUXC_SAI1_TXD5 = 104, - IMXRT1050_IOMUXC_SAI1_TXD6 = 105, - IMXRT1050_IOMUXC_SAI1_TXD7 = 106, - IMXRT1050_IOMUXC_SAI1_MCLK = 107, - IMXRT1050_IOMUXC_SAI2_RXFS = 108, - IMXRT1050_IOMUXC_SAI2_RXC = 109, - IMXRT1050_IOMUXC_SAI2_RXD0 = 110, - IMXRT1050_IOMUXC_SAI2_TXFS = 111, - IMXRT1050_IOMUXC_SAI2_TXC = 112, - IMXRT1050_IOMUXC_SAI2_TXD0 = 113, - IMXRT1050_IOMUXC_SAI2_MCLK = 114, - IMXRT1050_IOMUXC_SAI3_RXFS = 115, - IMXRT1050_IOMUXC_SAI3_RXC = 116, - IMXRT1050_IOMUXC_SAI3_RXD = 117, - IMXRT1050_IOMUXC_SAI3_TXFS = 118, - IMXRT1050_IOMUXC_SAI3_TXC = 119, - IMXRT1050_IOMUXC_SAI3_TXD = 120, - IMXRT1050_IOMUXC_SAI3_MCLK = 121, - IMXRT1050_IOMUXC_SPDIF_TX = 122, - IMXRT1050_IOMUXC_SPDIF_RX = 123, - IMXRT1050_IOMUXC_SPDIF_EXT_CLK = 124, - IMXRT1050_IOMUXC_ECSPI1_SCLK = 125, - IMXRT1050_IOMUXC_ECSPI1_MOSI = 126, - IMXRT1050_IOMUXC_ECSPI1_MISO = 127, - IMXRT1050_IOMUXC_ECSPI1_SS0 = 128, - IMXRT1050_IOMUXC_ECSPI2_SCLK = 129, - IMXRT1050_IOMUXC_ECSPI2_MOSI = 130, - IMXRT1050_IOMUXC_ECSPI2_MISO = 131, - IMXRT1050_IOMUXC_ECSPI2_SS0 = 132, - IMXRT1050_IOMUXC_I2C1_SCL = 133, - IMXRT1050_IOMUXC_I2C1_SDA = 134, - IMXRT1050_IOMUXC_I2C2_SCL = 135, - IMXRT1050_IOMUXC_I2C2_SDA = 136, - IMXRT1050_IOMUXC_I2C3_SCL = 137, - IMXRT1050_IOMUXC_I2C3_SDA = 138, - IMXRT1050_IOMUXC_I2C4_SCL = 139, - IMXRT1050_IOMUXC_I2C4_SDA = 140, - IMXRT1050_IOMUXC_UART1_RXD = 141, - IMXRT1050_IOMUXC_UART1_TXD = 142, - IMXRT1050_IOMUXC_UART2_RXD = 143, - IMXRT1050_IOMUXC_UART2_TXD = 144, - IMXRT1050_IOMUXC_UART3_RXD = 145, - IMXRT1050_IOMUXC_UART3_TXD = 146, - IMXRT1050_IOMUXC_UART4_RXD = 147, - IMXRT1050_IOMUXC_UART4_TXD = 148, + IMXRT1050_PAD_RESERVE0, + IMXRT1050_PAD_RESERVE1, + IMXRT1050_PAD_RESERVE2, + IMXRT1050_PAD_RESERVE3, + IMXRT1050_PAD_RESERVE4, + IMXRT1050_PAD_EMC_00, + IMXRT1050_PAD_EMC_01, + IMXRT1050_PAD_EMC_02, + IMXRT1050_PAD_EMC_03, + IMXRT1050_PAD_EMC_04, + IMXRT1050_PAD_EMC_05, + IMXRT1050_PAD_EMC_06, + IMXRT1050_PAD_EMC_07, + IMXRT1050_PAD_EMC_08, + IMXRT1050_PAD_EMC_09, + IMXRT1050_PAD_EMC_10, + IMXRT1050_PAD_EMC_11, + IMXRT1050_PAD_EMC_12, + IMXRT1050_PAD_EMC_13, + IMXRT1050_PAD_EMC_14, + IMXRT1050_PAD_EMC_15, + IMXRT1050_PAD_EMC_16, + IMXRT1050_PAD_EMC_17, + IMXRT1050_PAD_EMC_18, + IMXRT1050_PAD_EMC_19, + IMXRT1050_PAD_EMC_20, + IMXRT1050_PAD_EMC_21, + IMXRT1050_PAD_EMC_22, + IMXRT1050_PAD_EMC_23, + IMXRT1050_PAD_EMC_24, + IMXRT1050_PAD_EMC_25, + IMXRT1050_PAD_EMC_26, + IMXRT1050_PAD_EMC_27, + IMXRT1050_PAD_EMC_28, + IMXRT1050_PAD_EMC_29, + IMXRT1050_PAD_EMC_30, + IMXRT1050_PAD_EMC_31, + IMXRT1050_PAD_EMC_32, + IMXRT1050_PAD_EMC_33, + IMXRT1050_PAD_EMC_34, + IMXRT1050_PAD_EMC_35, + IMXRT1050_PAD_EMC_36, + IMXRT1050_PAD_EMC_37, + IMXRT1050_PAD_EMC_38, + IMXRT1050_PAD_EMC_39, + IMXRT1050_PAD_EMC_40, + IMXRT1050_PAD_EMC_41, + IMXRT1050_PAD_AD_B0_00, + IMXRT1050_PAD_AD_B0_01, + IMXRT1050_PAD_AD_B0_02, + IMXRT1050_PAD_AD_B0_03, + IMXRT1050_PAD_AD_B0_04, + IMXRT1050_PAD_AD_B0_05, + IMXRT1050_PAD_AD_B0_06, + IMXRT1050_PAD_AD_B0_07, + IMXRT1050_PAD_AD_B0_08, + IMXRT1050_PAD_AD_B0_09, + IMXRT1050_PAD_AD_B0_10, + IMXRT1050_PAD_AD_B0_11, + IMXRT1050_PAD_AD_B0_12, + IMXRT1050_PAD_AD_B0_13, + IMXRT1050_PAD_AD_B0_14, + IMXRT1050_PAD_AD_B0_15, + IMXRT1050_PAD_AD_B1_00, + IMXRT1050_PAD_AD_B1_01, + IMXRT1050_PAD_AD_B1_02, + IMXRT1050_PAD_AD_B1_03, + IMXRT1050_PAD_AD_B1_04, + IMXRT1050_PAD_AD_B1_05, + IMXRT1050_PAD_AD_B1_06, + IMXRT1050_PAD_AD_B1_07, + IMXRT1050_PAD_AD_B1_08, + IMXRT1050_PAD_AD_B1_09, + IMXRT1050_PAD_AD_B1_10, + IMXRT1050_PAD_AD_B1_11, + IMXRT1050_PAD_AD_B1_12, + IMXRT1050_PAD_AD_B1_13, + IMXRT1050_PAD_AD_B1_14, + IMXRT1050_PAD_AD_B1_15, + IMXRT1050_PAD_B0_00, + IMXRT1050_PAD_B0_01, + IMXRT1050_PAD_B0_02, + IMXRT1050_PAD_B0_03, + IMXRT1050_PAD_B0_04, + IMXRT1050_PAD_B0_05, + IMXRT1050_PAD_B0_06, + IMXRT1050_PAD_B0_07, + IMXRT1050_PAD_B0_08, + IMXRT1050_PAD_B0_09, + IMXRT1050_PAD_B0_10, + IMXRT1050_PAD_B0_11, + IMXRT1050_PAD_B0_12, + IMXRT1050_PAD_B0_13, + IMXRT1050_PAD_B0_14, + IMXRT1050_PAD_B0_15, + IMXRT1050_PAD_B1_00, + IMXRT1050_PAD_B1_01, + IMXRT1050_PAD_B1_02, + IMXRT1050_PAD_B1_03, + IMXRT1050_PAD_B1_04, + IMXRT1050_PAD_B1_05, + IMXRT1050_PAD_B1_06, + IMXRT1050_PAD_B1_07, + IMXRT1050_PAD_B1_08, + IMXRT1050_PAD_B1_09, + IMXRT1050_PAD_B1_10, + IMXRT1050_PAD_B1_11, + IMXRT1050_PAD_B1_12, + IMXRT1050_PAD_B1_13, + IMXRT1050_PAD_B1_14, + IMXRT1050_PAD_B1_15, + IMXRT1050_PAD_SD_B0_00, + IMXRT1050_PAD_SD_B0_01, + IMXRT1050_PAD_SD_B0_02, + IMXRT1050_PAD_SD_B0_03, + IMXRT1050_PAD_SD_B0_04, + IMXRT1050_PAD_SD_B0_05, + IMXRT1050_PAD_SD_B1_00, + IMXRT1050_PAD_SD_B1_01, + IMXRT1050_PAD_SD_B1_02, + IMXRT1050_PAD_SD_B1_03, + IMXRT1050_PAD_SD_B1_04, + IMXRT1050_PAD_SD_B1_05, + IMXRT1050_PAD_SD_B1_06, + IMXRT1050_PAD_SD_B1_07, + IMXRT1050_PAD_SD_B1_08, + IMXRT1050_PAD_SD_B1_09, + IMXRT1050_PAD_SD_B1_10, + IMXRT1050_PAD_SD_B1_11, }; /* Pad names for the pinmux subsystem */ @@ -171,150 +151,130 @@ static const struct pinctrl_pin_desc imxrt1050_pinctrl_pads[] = { IMX_PINCTRL_PIN(IMXRT1050_PAD_RESERVE2), IMX_PINCTRL_PIN(IMXRT1050_PAD_RESERVE3), IMX_PINCTRL_PIN(IMXRT1050_PAD_RESERVE4), - IMX_PINCTRL_PIN(IMXRT1050_PAD_RESERVE5), - IMX_PINCTRL_PIN(IMXRT1050_PAD_RESERVE6), - IMX_PINCTRL_PIN(IMXRT1050_PAD_RESERVE7), - IMX_PINCTRL_PIN(IMXRT1050_PAD_RESERVE8), - IMX_PINCTRL_PIN(IMXRT1050_PAD_RESERVE9), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO00), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO01), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO02), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO03), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO04), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO05), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO06), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO07), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO08), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO09), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO10), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO11), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO12), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO13), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO14), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO15), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_MDC), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_MDIO), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_TD3), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_TD2), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_TD1), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_TD0), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_TX_CTL), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_TXC), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_RX_CTL), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_RXC), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_RD0), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_RD1), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_RD2), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_RD3), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD1_CLK), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD1_CMD), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD1_DATA0), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD1_DATA1), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD1_DATA2), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD1_DATA3), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD1_DATA4), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD1_DATA5), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD1_DATA6), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD1_DATA7), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD1_RESET_B), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD1_STROBE), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD2_CD_B), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD2_CLK), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD2_CMD), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD2_DATA0), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD2_DATA1), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD2_DATA2), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD2_DATA3), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD2_RESET_B), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD2_WP), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_ALE), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_CE0), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_CE1), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_CE2), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_CE3), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_CLE), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_DATA00), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_DATA01), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_DATA02), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_DATA03), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_DATA04), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_DATA05), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_DATA06), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_DATA07), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_DQS), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_RE_B), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_READY_B), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_WE_B), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_WP_B), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI5_RXFS), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI5_RXC), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI5_RXD0), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI5_RXD1), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI5_RXD2), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI5_RXD3), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI5_MCLK), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_RXFS), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_RXC), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_RXD0), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_RXD1), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_RXD2), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_RXD3), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_RXD4), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_RXD5), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_RXD6), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_RXD7), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_TXFS), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_TXC), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_TXD0), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_TXD1), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_TXD2), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_TXD3), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_TXD4), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_TXD5), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_TXD6), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_TXD7), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_MCLK), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI2_RXFS), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI2_RXC), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI2_RXD0), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI2_TXFS), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI2_TXC), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI2_TXD0), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI2_MCLK), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI3_RXFS), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI3_RXC), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI3_RXD), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI3_TXFS), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI3_TXC), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI3_TXD), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI3_MCLK), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SPDIF_TX), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SPDIF_RX), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SPDIF_EXT_CLK), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ECSPI1_SCLK), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ECSPI1_MOSI), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ECSPI1_MISO), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ECSPI1_SS0), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ECSPI2_SCLK), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ECSPI2_MOSI), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ECSPI2_MISO), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ECSPI2_SS0), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_I2C1_SCL), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_I2C1_SDA), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_I2C2_SCL), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_I2C2_SDA), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_I2C3_SCL), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_I2C3_SDA), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_I2C4_SCL), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_I2C4_SDA), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_UART1_RXD), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_UART1_TXD), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_UART2_RXD), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_UART2_TXD), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_UART3_RXD), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_UART3_TXD), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_UART4_RXD), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_UART4_TXD), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_00), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_01), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_02), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_03), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_04), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_05), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_06), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_07), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_08), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_09), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_10), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_11), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_12), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_13), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_14), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_15), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_16), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_17), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_18), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_19), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_20), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_21), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_22), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_23), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_24), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_25), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_26), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_27), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_28), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_29), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_30), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_31), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_32), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_33), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_34), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_35), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_36), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_37), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_38), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_39), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_40), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_41), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_00), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_01), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_02), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_03), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_04), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_05), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_06), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_07), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_08), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_09), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_10), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_11), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_12), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_13), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_14), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_15), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_00), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_01), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_02), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_03), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_04), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_05), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_06), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_07), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_08), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_09), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_10), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_11), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_12), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_13), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_14), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_15), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_00), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_01), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_02), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_03), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_04), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_05), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_06), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_07), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_08), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_09), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_10), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_11), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_12), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_13), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_14), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_15), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_00), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_01), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_02), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_03), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_04), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_05), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_06), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_07), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_08), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_09), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_10), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_11), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_12), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_13), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_14), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_15), + IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B0_00), + IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B0_01), + IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B0_02), + IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B0_03), + IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B0_04), + IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B0_05), + IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B1_00), + IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B1_01), + IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B1_02), + IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B1_03), + IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B1_04), + IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B1_05), + IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B1_06), + IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B1_07), + IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B1_08), + IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B1_09), + IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B1_10), + IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B1_11), }; static const struct imx_pinctrl_soc_info imxrt1050_pinctrl_info = { From patchwork Mon Nov 7 07:15:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jesse Taube X-Patchwork-Id: 13033858 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 66E0AC4332F for ; Mon, 7 Nov 2022 07:17:22 +0000 (UTC) DKIM-Signature: v=1; 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[108.26.185.122]) by smtp.gmail.com with ESMTPSA id br8-20020a05620a460800b006cf38fd659asm6318428qkb.103.2022.11.06.23.15.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 06 Nov 2022 23:15:21 -0800 (PST) From: Jesse Taube X-Google-Original-From: Jesse Taube To: linux-imx@nxp.com Cc: robh+dt@kernel.org, sboyd@kernel.org, shawnguo@kernel.org, kernel@pengutronix.de, festevam@gmail.com, aisheng.dong@nxp.com, stefan@agner.ch, linus.walleij@linaro.org, gregkh@linuxfoundation.org, arnd@arndb.de, linux@armlinux.org.uk, abel.vesa@nxp.com, dev@lynxeye.de, marcel.ziswiler@toradex.com, tharvey@gateworks.com, leoyang.li@nxp.com, fugang.duan@nxp.com, Mr.Bossman075@gmail.com, giulio.benetti@benettiengineering.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org Subject: [PATCH v1 7/7] ARM: dts: imx: Update i.MXRT1050.dtsi compatibles Date: Mon, 7 Nov 2022 02:15:11 -0500 Message-Id: <20221107071511.2764628-8-Mr.Bossman075@gmail.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20221107071511.2764628-1-Mr.Bossman075@gmail.com> References: <20221107071511.2764628-1-Mr.Bossman075@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221106_231522_798689_F818DADE X-CRM114-Status: GOOD ( 10.07 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Remove unused compatibles from i.MXRT1050.dtsi. Change GPT clock-names to match documentation. Cc: Giulio Benetti Signed-off-by: Jesse Taube --- arch/arm/boot/dts/imxrt1050.dtsi | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/imxrt1050.dtsi b/arch/arm/boot/dts/imxrt1050.dtsi index 03e6a858a7be..8d79de239046 100644 --- a/arch/arm/boot/dts/imxrt1050.dtsi +++ b/arch/arm/boot/dts/imxrt1050.dtsi @@ -29,7 +29,7 @@ osc3M: osc3M { soc { lpuart1: serial@40184000 { - compatible = "fsl,imxrt1050-lpuart", "fsl,imx7ulp-lpuart"; + compatible = "fsl,imxrt1050-lpuart"; reg = <0x40184000 0x4000>; interrupts = <20>; clocks = <&clks IMXRT1050_CLK_LPUART1>; @@ -40,7 +40,6 @@ lpuart1: serial@40184000 { iomuxc: pinctrl@401f8000 { compatible = "fsl,imxrt1050-iomuxc"; reg = <0x401f8000 0x4000>; - fsl,mux_mask = <0x7>; }; anatop: anatop@400d8000 { @@ -83,7 +82,7 @@ edma1: dma-controller@400e8000 { }; usdhc1: mmc@402c0000 { - compatible = "fsl,imxrt1050-usdhc", "fsl,imx6sl-usdhc"; + compatible = "fsl,imxrt1050-usdhc"; reg = <0x402c0000 0x4000>; interrupts = <110>; clocks = <&clks IMXRT1050_CLK_IPG_PDOF>, @@ -150,11 +149,11 @@ gpio5: gpio@400c0000 { }; gpt: timer@401ec000 { - compatible = "fsl,imxrt1050-gpt", "fsl,imx6dl-gpt", "fsl,imx6sl-gpt"; + compatible = "fsl,imxrt1050-gpt", "fsl,imx6dl-gpt"; reg = <0x401ec000 0x4000>; interrupts = <100>; - clocks = <&osc3M>; - clock-names = "per"; + clocks = <&osc3M>, <&osc3M>; + clock-names = "ipg", "per"; }; }; };