From patchwork Mon Nov 7 13:28:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 13034338 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F4166C4332F for ; Mon, 7 Nov 2022 13:29:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232011AbiKGN3T (ORCPT ); Mon, 7 Nov 2022 08:29:19 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60474 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231667AbiKGN3S (ORCPT ); Mon, 7 Nov 2022 08:29:18 -0500 Received: from mail-ej1-x630.google.com (mail-ej1-x630.google.com [IPv6:2a00:1450:4864:20::630]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9EF211CB0D; Mon, 7 Nov 2022 05:29:05 -0800 (PST) Received: by mail-ej1-x630.google.com with SMTP id d26so30036373eje.10; Mon, 07 Nov 2022 05:29:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=4s/Ptq8qmBpFC+qJpngwSoeByDBagm3Zx2Ag2l+arII=; b=L2PeUV/vUgUVmloujR/vHOf91PEBnyAq+3zmOkc/1hunmGtWrlLICfsUgd0JwBoOUT bBfomTM43fmiMli/d4SrMTUHLjvFhvkyF1DF+Bw66b+QdZoHOJwJ4pIeLR/jVT7tlnii jU1gZJL2rRk6pTzfGaEw1Dmx4kN+yaw88/ofOkt57hseoZ7yMjh4TNuAWbhwmQ8GCCAD HMlgfNfW790FXoM50zTC/NTBLGefApdwayg6+JAmL6phIFVMnuwk5AQlTbZ1k3kDanhm 5bHu9GL2FfO9hRr+XK9phvhMELcg9otEYnT0mTBj4kkBtsqN9rXK+wzYUYJpC5BP3LGs rBqw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=4s/Ptq8qmBpFC+qJpngwSoeByDBagm3Zx2Ag2l+arII=; b=LlCfFSGoE4BWaqBZ+DKn2oaQ4PNye78Gh4e3niJ7SKSd8UHuQqMB6D8erSVD/D0UbD HxCvlAfgDaX0nX8JxJN00BdO9YUuyf6RZhkhLda/CD2KjluK+skiDU/bucL8Cng7KOFK hmO9Ouy4QAMlpfDeY+Y5TG/ODOSHLlll1nOmqtrq8gh6ndS5A3eq0EIFyBf6S8JL4lcx 86CX5bOrtIh2Hos66Ob7fnPsgWofRuTcDIQ9+QdBxOh18nb33KrxsAKD59LHXCpSFlJi A8007s43AHYCQb8W8JhQmY4VRRzeVHDanyu7JuxvWpCJa1ikiGv3MllaT1ebVYXcQNjI nMYg== X-Gm-Message-State: ACrzQf2bCe75t8Fpl7jXXxqiwfmkg4APsAKqMaAVwzubFBHqz7IRXKVP /g77w1NXwwlf1LPg+fB4Bek= X-Google-Smtp-Source: AMsMyM4TLYEv7krxKJO9xwNS3FvCmLCYf5ofH5o7VJkH2pssMqj/zXD3EyEdd1qPST+FPuEXv2IuXg== X-Received: by 2002:a17:906:794a:b0:7a0:72b8:2368 with SMTP id l10-20020a170906794a00b007a072b82368mr47657792ejo.601.1667827744013; Mon, 07 Nov 2022 05:29:04 -0800 (PST) Received: from fedora.. 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[88.207.98.26]) by smtp.googlemail.com with ESMTPSA id ky14-20020a170907778e00b0073c8d4c9f38sm3446037ejc.177.2022.11.07.05.29.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Nov 2022 05:29:03 -0800 (PST) From: Robert Marko To: agross@kernel.org, andersson@kernel.org, konrad.dybcio@somainline.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Cc: Robert Marko Subject: [PATCH 1/3] clk: qcom: reset: support resetting multiple bits Date: Mon, 7 Nov 2022 14:28:59 +0100 Message-Id: <20221107132901.489240-1-robimarko@gmail.com> X-Mailer: git-send-email 2.38.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org This patch adds the support for giving the complete bitmask in reset structure and reset operation will use this bitmask for all reset operations. Currently, reset structure only takes a single bit for each reset and then calculates the bitmask by using the BIT() macro. However, this is not sufficient anymore for newer SoC-s like IPQ8074, IPQ6018 and more, since their networking resets require multiple bits to be asserted in order to properly reset the HW block completely. So, in order to allow asserting multiple bits add "bitmask" field to qcom_reset_map, and then use that bitmask value if its populated in the driver, if its not populated, then we just default to existing behaviour and calculate the bitmask on the fly. Signed-off-by: Robert Marko --- drivers/clk/qcom/reset.c | 4 ++-- drivers/clk/qcom/reset.h | 1 + 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/clk/qcom/reset.c b/drivers/clk/qcom/reset.c index 2a16adb572d2..0e914ec7aeae 100644 --- a/drivers/clk/qcom/reset.c +++ b/drivers/clk/qcom/reset.c @@ -30,7 +30,7 @@ qcom_reset_assert(struct reset_controller_dev *rcdev, unsigned long id) rst = to_qcom_reset_controller(rcdev); map = &rst->reset_map[id]; - mask = BIT(map->bit); + mask = map->bitmask ? map->bitmask : BIT(map->bit); return regmap_update_bits(rst->regmap, map->reg, mask, mask); } @@ -44,7 +44,7 @@ qcom_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id) rst = to_qcom_reset_controller(rcdev); map = &rst->reset_map[id]; - mask = BIT(map->bit); + mask = map->bitmask ? map->bitmask : BIT(map->bit); return regmap_update_bits(rst->regmap, map->reg, mask, 0); } diff --git a/drivers/clk/qcom/reset.h b/drivers/clk/qcom/reset.h index b8c113582072..9a47c838d9b1 100644 --- a/drivers/clk/qcom/reset.h +++ b/drivers/clk/qcom/reset.h @@ -12,6 +12,7 @@ struct qcom_reset_map { unsigned int reg; u8 bit; u8 udelay; + u32 bitmask; }; struct regmap; From patchwork Mon Nov 7 13:29:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 13034339 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 50846C4167D for ; Mon, 7 Nov 2022 13:29:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232094AbiKGN3V (ORCPT ); Mon, 7 Nov 2022 08:29:21 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60494 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231860AbiKGN3S (ORCPT ); Mon, 7 Nov 2022 08:29:18 -0500 Received: from mail-ej1-x634.google.com (mail-ej1-x634.google.com [IPv6:2a00:1450:4864:20::634]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B1C851CB28; Mon, 7 Nov 2022 05:29:06 -0800 (PST) Received: by mail-ej1-x634.google.com with SMTP id sc25so29998146ejc.12; Mon, 07 Nov 2022 05:29:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=xDq+dF/YTBWalc8Ldtbu93f8AMlelceS56nsDHxpWFY=; b=AN7WfcRNngvJVDPpT0OecabQU542LiG7ZfGJ3aRwjFuTIlK2vHkwGk84ZkAYjHJK5q DX+wo9NFVOtMc5YMUfz1m8AmjbFl6mfslo3w57e8nHieYGwLGgIT2N7iaOaQa2IyKVF7 GLsRQQb6Earm+QlBMfoRoo53azeVbNRR2/p1ntWnVDFbdFSRpvkkxHF/ngKPrdJYRtTa A1UutbAtAsWR9/Ro2eYmZ722gRT1rxa5zD5gHMFzDVeEme7idVKxXXiTskr9XQ1+SZxE 7XbORXZ1/PNFW08JnUNRLH5a3mqtwc8kMsmajR0fgUzODDlD79oLyU+v7efol0d5q2ie ihMg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xDq+dF/YTBWalc8Ldtbu93f8AMlelceS56nsDHxpWFY=; b=LhwICmhqW5MoKX272ytSGR5d+mG6m7L0xNvEa8aZZRz8oVjWISDtRn1TEAxgCW/0k3 uUv1nxbLUh9xnzUvRc9h49G8opkOIK5I1nFQCBJLJ5vJ1rH/C0dK1jxSxICixP0g6BG0 Fs4qUbzr54JDJji6psjTqp2afTRbAAQytbp+H0UoB7ZSkaTM4WV5Kle7InaxFsxQYk7y XmqZT/o4xyOQIXXOjj15+PMu/Z84fZwM7ibtBZqpnhVbpTz8kBL+8SNCKWol/jwyPgwN sFnIHBWeZ8o9WSbDXDwZzZC6xLiYRn0UgUc5GQTO0Zryj5LdHw+3DZyHI8AvsUzFbY+f oCEw== X-Gm-Message-State: ACrzQf0g1MV7uNhvSbgSzO8sxyamyVb+pwLLBt6ukZsbWX7EptKmajqJ 42/G4hJZXtJ16jkQG1dOeCo= X-Google-Smtp-Source: AMsMyM50xw5FgmSWx6+qGInHwOD7WrjtxwN78sUG7ovQeIJVMTjaYTUU2cS0rRbrUefXygE7Dds4JA== X-Received: by 2002:a17:907:6a09:b0:7ae:2793:aa23 with SMTP id rf9-20020a1709076a0900b007ae2793aa23mr19134094ejc.184.1667827745265; Mon, 07 Nov 2022 05:29:05 -0800 (PST) Received: from fedora.. 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[88.207.98.26]) by smtp.googlemail.com with ESMTPSA id ky14-20020a170907778e00b0073c8d4c9f38sm3446037ejc.177.2022.11.07.05.29.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Nov 2022 05:29:04 -0800 (PST) From: Robert Marko To: agross@kernel.org, andersson@kernel.org, konrad.dybcio@somainline.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Cc: Robert Marko Subject: [PATCH 2/3] dt-bindings: clock: qcom: ipq8074: add missing networking resets Date: Mon, 7 Nov 2022 14:29:00 +0100 Message-Id: <20221107132901.489240-2-robimarko@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221107132901.489240-1-robimarko@gmail.com> References: <20221107132901.489240-1-robimarko@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add bindings for the missing networking resets found in IPQ8074 GCC. Signed-off-by: Robert Marko Acked-by: Krzysztof Kozlowski --- include/dt-bindings/clock/qcom,gcc-ipq8074.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/include/dt-bindings/clock/qcom,gcc-ipq8074.h b/include/dt-bindings/clock/qcom,gcc-ipq8074.h index e4991d303708..f9ea55811104 100644 --- a/include/dt-bindings/clock/qcom,gcc-ipq8074.h +++ b/include/dt-bindings/clock/qcom,gcc-ipq8074.h @@ -367,6 +367,20 @@ #define GCC_PCIE1_AHB_ARES 129 #define GCC_PCIE1_AXI_MASTER_STICKY_ARES 130 #define GCC_PCIE0_AXI_SLAVE_STICKY_ARES 131 +#define GCC_PPE_FULL_RESET 132 +#define GCC_UNIPHY0_SOFT_RESET 133 +#define GCC_UNIPHY0_XPCS_RESET 134 +#define GCC_UNIPHY1_SOFT_RESET 135 +#define GCC_UNIPHY1_XPCS_RESET 136 +#define GCC_UNIPHY2_SOFT_RESET 137 +#define GCC_UNIPHY2_XPCS_RESET 138 +#define GCC_EDMA_HW_RESET 139 +#define GCC_NSSPORT1_RESET 140 +#define GCC_NSSPORT2_RESET 141 +#define GCC_NSSPORT3_RESET 142 +#define GCC_NSSPORT4_RESET 143 +#define GCC_NSSPORT5_RESET 144 +#define GCC_NSSPORT6_RESET 145 #define USB0_GDSC 0 #define USB1_GDSC 1 From patchwork Mon Nov 7 13:29:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 13034340 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1441DC433FE for ; Mon, 7 Nov 2022 13:29:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232128AbiKGN3V (ORCPT ); Mon, 7 Nov 2022 08:29:21 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60476 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231883AbiKGN3S (ORCPT ); Mon, 7 Nov 2022 08:29:18 -0500 Received: from mail-ej1-x631.google.com (mail-ej1-x631.google.com [IPv6:2a00:1450:4864:20::631]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D5D6E1CB17; Mon, 7 Nov 2022 05:29:07 -0800 (PST) Received: by mail-ej1-x631.google.com with SMTP id q9so30216325ejd.0; Mon, 07 Nov 2022 05:29:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=XDOdLV96aBPIAMlkNzE1ZyzcwED/u+zRiKOTdjgBJUU=; b=YgLNaVxs1RztJCcCieI8ERHtdHkFdvRBWXaoGj+AFLeV0EnQ6J9GsBnutFSoPtBsGf wqGEIUoUKqYNOPeCTfn1rUDGU9lSJJHHLAMyEkvxmsyoJ9eWysOIIAcot7QrHsOycz5S +q4LOxO5qs1upjjEHf4jIk1N12UBXbFxAZwTxHCwRSJIduSE0b0ZzJNltKmKYx1KkoUt XJ67MNa49mxB1PeKRLXDPhmykww37tN+1pOnpwTxZmVGCP7PD+HZlxp/DKqcBopnEb1V ylZmHLI/HZ8aYw8pU8iCpTAdKu75zLJV/mhhhXEMhmp5q2GkuQ0NwczZFxyfCRvo4mQz AOgw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=XDOdLV96aBPIAMlkNzE1ZyzcwED/u+zRiKOTdjgBJUU=; b=HPDnA8geCSuNImobfdCHM3QjfHemVxFNMA51rvatLbGeqXs7CECMrHkTGjef3qo1Uj /RVYurq6X9xcTIgoDB0zgWFANkW1kO4/aPwabmB509O0H2AjujbrlGC8BpM5CEm2fX9V TOiVzQAA8JilnNpRkRCFwwk9qt54x9qzaMBmB12QZpgz9vX7XDUWI6O4ggw83iWYj5Yb ad3pHHD+9CaeSNjYNhNFZNElK4NqIhuc4EiZobBIa2Fb63jzAGCZyyBOrYKbGgHT2KTG ZRzc2CWJSfnhvQ3tFaznCu+wCnPstk0WTSyn9F16FGb2WGXx7Wk/HyjK4HDvF1J8SGwk nZ0g== X-Gm-Message-State: ACrzQf1XyZ3V1GmH0n6DITaINeHWXd5isafndPNkzxXfznc5nGtCcG3x INVQdlwU81DQE7ihHX/+wNk= X-Google-Smtp-Source: AMsMyM6fliBlCshCjtfYk2Qg/pWwCrenj7y+n7lKdApNLB8h60d8aRsQrVG5i6G87s0IUlZDUF0Mgg== X-Received: by 2002:a17:907:c711:b0:7ae:35c9:f07b with SMTP id ty17-20020a170907c71100b007ae35c9f07bmr16421779ejc.423.1667827746465; Mon, 07 Nov 2022 05:29:06 -0800 (PST) Received: from fedora.. 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[88.207.98.26]) by smtp.googlemail.com with ESMTPSA id ky14-20020a170907778e00b0073c8d4c9f38sm3446037ejc.177.2022.11.07.05.29.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Nov 2022 05:29:06 -0800 (PST) From: Robert Marko To: agross@kernel.org, andersson@kernel.org, konrad.dybcio@somainline.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Cc: Robert Marko Subject: [PATCH 3/3] clk: qcom: ipq8074: add missing networking resets Date: Mon, 7 Nov 2022 14:29:01 +0100 Message-Id: <20221107132901.489240-3-robimarko@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221107132901.489240-1-robimarko@gmail.com> References: <20221107132901.489240-1-robimarko@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Downstream QCA 5.4 kernel defines networking resets which are not present in the mainline kernel but are required for the networking drivers. So, port the downstream resets and avoid using magic values for mask, construct mask for resets which require multiple bits to be set/cleared. Signed-off-by: Robert Marko --- drivers/clk/qcom/gcc-ipq8074.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c index 42d185fe19c8..37d8a9f4105e 100644 --- a/drivers/clk/qcom/gcc-ipq8074.c +++ b/drivers/clk/qcom/gcc-ipq8074.c @@ -4826,6 +4826,20 @@ static const struct qcom_reset_map gcc_ipq8074_resets[] = { [GCC_PCIE1_AXI_SLAVE_ARES] = { 0x76040, 4 }, [GCC_PCIE1_AHB_ARES] = { 0x76040, 5 }, [GCC_PCIE1_AXI_MASTER_STICKY_ARES] = { 0x76040, 6 }, + [GCC_PPE_FULL_RESET] = { .reg = 0x68014, .bitmask = GENMASK(19, 16) }, + [GCC_UNIPHY0_SOFT_RESET] = { .reg = 0x56004, .bitmask = GENMASK(13, 4) | BIT(1) }, + [GCC_UNIPHY0_XPCS_RESET] = { 0x56004, 2 }, + [GCC_UNIPHY1_SOFT_RESET] = { .reg = 0x56104, .bitmask = GENMASK(5, 4) | BIT(1) }, + [GCC_UNIPHY1_XPCS_RESET] = { 0x56104, 2 }, + [GCC_UNIPHY2_SOFT_RESET] = { .reg = 0x56204, .bitmask = GENMASK(5, 4) | BIT(1) }, + [GCC_UNIPHY2_XPCS_RESET] = { 0x56204, 2 }, + [GCC_EDMA_HW_RESET] = { .reg = 0x68014, .bitmask = GENMASK(21, 20) }, + [GCC_NSSPORT1_RESET] = { .reg = 0x68014, .bitmask = BIT(24) | GENMASK(1, 0) }, + [GCC_NSSPORT2_RESET] = { .reg = 0x68014, .bitmask = BIT(25) | GENMASK(3, 2) }, + [GCC_NSSPORT3_RESET] = { .reg = 0x68014, .bitmask = BIT(26) | GENMASK(5, 4) }, + [GCC_NSSPORT4_RESET] = { .reg = 0x68014, .bitmask = BIT(27) | GENMASK(9, 8) }, + [GCC_NSSPORT5_RESET] = { .reg = 0x68014, .bitmask = BIT(28) | GENMASK(11, 10) }, + [GCC_NSSPORT6_RESET] = { .reg = 0x68014, .bitmask = BIT(29) | GENMASK(13, 12) }, }; static struct gdsc *gcc_ipq8074_gdscs[] = {