From patchwork Tue Oct 25 15:33:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: ~axelheider X-Patchwork-Id: 13034866 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7E0B0C4332F for ; Mon, 7 Nov 2022 16:44:33 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1os5Cj-0002Dn-OC; Mon, 07 Nov 2022 11:42:33 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1os5CO-00025E-90; Mon, 07 Nov 2022 11:42:12 -0500 Received: from mail-b.sr.ht ([173.195.146.151]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1os5CI-0004nG-L4; Mon, 07 Nov 2022 11:42:10 -0500 Authentication-Results: mail-b.sr.ht; dkim=none Received: from git.sr.ht (unknown [173.195.146.142]) by mail-b.sr.ht (Postfix) with ESMTPSA id 5BDA211F0AA; Mon, 7 Nov 2022 16:42:04 +0000 (UTC) From: ~axelheider Date: Tue, 25 Oct 2022 17:33:43 +0200 Subject: [PATCH qemu.git v2 1/9] hw/timer/imx_epit: improve comments Message-ID: <166783932395.3279.1096141058484230644-1@git.sr.ht> X-Mailer: git.sr.ht In-Reply-To: <166783932395.3279.1096141058484230644-0@git.sr.ht> To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org MIME-Version: 1.0 Received-SPF: pass client-ip=173.195.146.151; envelope-from=outgoing@sr.ht; helo=mail-b.sr.ht X-Spam_score_int: 36 X-Spam_score: 3.6 X-Spam_bar: +++ X-Spam_report: (3.6 / 5.0 requ) BAYES_00=-1.9, DATE_IN_PAST_96_XX=3.405, FREEMAIL_FORGED_REPLYTO=2.095, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: ~axelheider Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Axel Heider Fix typos, add background information Signed-off-by: Axel Heider Reviewed-by: Peter Maydell --- hw/timer/imx_epit.c | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c index ec0fa440d7..4af730593f 100644 --- a/hw/timer/imx_epit.c +++ b/hw/timer/imx_epit.c @@ -100,9 +100,7 @@ static void imx_epit_reset(DeviceState *dev) { IMXEPITState *s = IMX_EPIT(dev); - /* - * Soft reset doesn't touch some bits; hard reset clears them - */ + /* Soft reset doesn't touch some bits; hard reset clears them */ s->cr &= (CR_EN|CR_ENMOD|CR_STOPEN|CR_DOZEN|CR_WAITEN|CR_DBGEN); s->sr = 0; s->lr = EPIT_TIMER_MAX; @@ -214,6 +212,7 @@ static void imx_epit_write(void *opaque, hwaddr offset, uint64_t value, ptimer_transaction_begin(s->timer_cmp); ptimer_transaction_begin(s->timer_reload); + /* Update the frequency. Has been done already in case of a reset. */ if (!(s->cr & CR_SWR)) { imx_epit_set_freq(s); } @@ -254,7 +253,7 @@ static void imx_epit_write(void *opaque, hwaddr offset, uint64_t value, break; case 1: /* SR - ACK*/ - /* writing 1 to OCIF clear the OCIF bit */ + /* writing 1 to OCIF clears the OCIF bit */ if (value & 0x01) { s->sr = 0; imx_epit_update_int(s); @@ -352,8 +351,18 @@ static void imx_epit_realize(DeviceState *dev, Error **errp) 0x00001000); sysbus_init_mmio(sbd, &s->iomem); + /* + * The reload timer keeps running when the peripheral is enabled. It is a + * kind of wall clock that does not generate any interrupts. The callback + * needs to be provided, but it does nothing as the ptimer already supports + * all necessary reloading functionality. + */ s->timer_reload = ptimer_init(imx_epit_reload, s, PTIMER_POLICY_LEGACY); + /* + * The compare timer is running only when the peripheral configuration is + * in a state that will generate compare interrupts. + */ s->timer_cmp = ptimer_init(imx_epit_cmp, s, PTIMER_POLICY_LEGACY); } From patchwork Sun Oct 30 23:59:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: ~axelheider X-Patchwork-Id: 13034867 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7F7AEC433FE for ; Mon, 7 Nov 2022 16:44:35 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1os5Ck-0002Em-8S; Mon, 07 Nov 2022 11:42:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1os5CO-00025F-8y; Mon, 07 Nov 2022 11:42:12 -0500 Received: from mail-b.sr.ht ([173.195.146.151]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1os5CI-0004oZ-Kt; Mon, 07 Nov 2022 11:42:10 -0500 Authentication-Results: mail-b.sr.ht; dkim=none Received: from git.sr.ht (unknown [173.195.146.142]) by mail-b.sr.ht (Postfix) with ESMTPSA id 80A3E11F30B; Mon, 7 Nov 2022 16:42:04 +0000 (UTC) From: ~axelheider Date: Mon, 31 Oct 2022 00:59:29 +0100 Subject: [PATCH qemu.git v2 2/9] hw/timer/imx_epit: cleanup CR defines Message-ID: <166783932395.3279.1096141058484230644-2@git.sr.ht> X-Mailer: git.sr.ht In-Reply-To: <166783932395.3279.1096141058484230644-0@git.sr.ht> To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org MIME-Version: 1.0 Received-SPF: pass client-ip=173.195.146.151; envelope-from=outgoing@sr.ht; helo=mail-b.sr.ht X-Spam_score_int: 36 X-Spam_score: 3.6 X-Spam_bar: +++ X-Spam_report: (3.6 / 5.0 requ) BAYES_00=-1.9, DATE_IN_PAST_96_XX=3.405, FREEMAIL_FORGED_REPLYTO=2.095, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: ~axelheider Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Axel Heider remove unused defines, add needed defines Signed-off-by: Axel Heider Reviewed-by: Peter Maydell --- hw/timer/imx_epit.c | 4 ++-- include/hw/timer/imx_epit.h | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c index 4af730593f..8ec770f674 100644 --- a/hw/timer/imx_epit.c +++ b/hw/timer/imx_epit.c @@ -82,8 +82,8 @@ static void imx_epit_set_freq(IMXEPITState *s) uint32_t clksrc; uint32_t prescaler; - clksrc = extract32(s->cr, CR_CLKSRC_SHIFT, 2); - prescaler = 1 + extract32(s->cr, CR_PRESCALE_SHIFT, 12); + clksrc = extract32(s->cr, CR_CLKSRC_SHIFT, CR_CLKSRC_BITS); + prescaler = 1 + extract32(s->cr, CR_PRESCALE_SHIFT, CR_PRESCALE_BITS); s->freq = imx_ccm_get_clock_frequency(s->ccm, imx_epit_clocks[clksrc]) / prescaler; diff --git a/include/hw/timer/imx_epit.h b/include/hw/timer/imx_epit.h index 2acc41e982..e2cb96229b 100644 --- a/include/hw/timer/imx_epit.h +++ b/include/hw/timer/imx_epit.h @@ -43,7 +43,7 @@ #define CR_OCIEN (1 << 2) #define CR_RLD (1 << 3) #define CR_PRESCALE_SHIFT (4) -#define CR_PRESCALE_MASK (0xfff) +#define CR_PRESCALE_BITS (12) #define CR_SWR (1 << 16) #define CR_IOVW (1 << 17) #define CR_DBGEN (1 << 18) @@ -51,7 +51,7 @@ #define CR_DOZEN (1 << 20) #define CR_STOPEN (1 << 21) #define CR_CLKSRC_SHIFT (24) -#define CR_CLKSRC_MASK (0x3 << CR_CLKSRC_SHIFT) +#define CR_CLKSRC_BITS (2) #define EPIT_TIMER_MAX 0XFFFFFFFFUL From patchwork Tue Oct 25 11:23:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: ~axelheider X-Patchwork-Id: 13034863 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0A7F1C433FE for ; Mon, 7 Nov 2022 16:43:51 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1os5CS-000266-Dh; Mon, 07 Nov 2022 11:42:16 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1os5CM-00024e-9g; Mon, 07 Nov 2022 11:42:10 -0500 Received: from mail-b.sr.ht ([173.195.146.151]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1os5CI-0004pV-L4; Mon, 07 Nov 2022 11:42:09 -0500 Authentication-Results: mail-b.sr.ht; dkim=none Received: from git.sr.ht (unknown [173.195.146.142]) by mail-b.sr.ht (Postfix) with ESMTPSA id B137C11F30C; Mon, 7 Nov 2022 16:42:04 +0000 (UTC) From: ~axelheider Date: Tue, 25 Oct 2022 13:23:07 +0200 Subject: [PATCH qemu.git v2 3/9] hw/timer/imx_epit: simplify interrupt logic Message-ID: <166783932395.3279.1096141058484230644-3@git.sr.ht> X-Mailer: git.sr.ht In-Reply-To: <166783932395.3279.1096141058484230644-0@git.sr.ht> To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org MIME-Version: 1.0 Received-SPF: pass client-ip=173.195.146.151; envelope-from=outgoing@sr.ht; helo=mail-b.sr.ht X-Spam_score_int: 36 X-Spam_score: 3.6 X-Spam_bar: +++ X-Spam_report: (3.6 / 5.0 requ) BAYES_00=-1.9, DATE_IN_PAST_96_XX=3.405, FREEMAIL_FORGED_REPLYTO=2.095, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: ~axelheider Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Axel Heider Signed-off-by: Axel Heider --- hw/timer/imx_epit.c | 27 +++++++++++---------------- 1 file changed, 11 insertions(+), 16 deletions(-) diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c index 8ec770f674..2e9dae0bc8 100644 --- a/hw/timer/imx_epit.c +++ b/hw/timer/imx_epit.c @@ -61,18 +61,6 @@ static const IMXClk imx_epit_clocks[] = { CLK_32k, /* 11 ipg_clk_32k -- ~32kHz */ }; -/* - * Update interrupt status - */ -static void imx_epit_update_int(IMXEPITState *s) -{ - if (s->sr && (s->cr & CR_OCIEN) && (s->cr & CR_EN)) { - qemu_irq_raise(s->irq); - } else { - qemu_irq_lower(s->irq); - } -} - /* * Must be called from within a ptimer_transaction_begin/commit block * for both s->timer_cmp and s->timer_reload. @@ -253,10 +241,10 @@ static void imx_epit_write(void *opaque, hwaddr offset, uint64_t value, break; case 1: /* SR - ACK*/ - /* writing 1 to OCIF clears the OCIF bit */ + /* writing 1 to OCIF clears the OCIF bit and the interrupt */ if (value & 0x01) { s->sr = 0; - imx_epit_update_int(s); + qemu_irq_lower(s->irq); } break; @@ -305,10 +293,17 @@ static void imx_epit_cmp(void *opaque) { IMXEPITState *s = IMX_EPIT(opaque); + /* Set the interrupt status flag to signaled. */ DPRINTF("sr was %d\n", s->sr); - s->sr = 1; - imx_epit_update_int(s); + + /* + * An actual interrupt is generated only if the peripheral is enabled + * and the interrupt generation is enabled. + */ + if ((s->cr & (CR_EN | CR_OCIEN)) == (CR_EN | CR_OCIEN)) { + qemu_irq_raise(s->irq); + } } static void imx_epit_reload(void *opaque) From patchwork Tue Oct 25 18:32:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: ~axelheider X-Patchwork-Id: 13034861 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2B5C8C433FE for ; Mon, 7 Nov 2022 16:43:24 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1os5Cd-0002AX-Mi; Mon, 07 Nov 2022 11:42:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1os5CM-00024c-9U; Mon, 07 Nov 2022 11:42:10 -0500 Received: from mail-b.sr.ht ([173.195.146.151]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1os5CI-0004qY-K0; Mon, 07 Nov 2022 11:42:08 -0500 Authentication-Results: mail-b.sr.ht; dkim=none Received: from git.sr.ht (unknown [173.195.146.142]) by mail-b.sr.ht (Postfix) with ESMTPSA id D61ED11F30F; Mon, 7 Nov 2022 16:42:04 +0000 (UTC) From: ~axelheider Date: Tue, 25 Oct 2022 20:32:30 +0200 Subject: [PATCH qemu.git v2 4/9] hw/timer/imx_epit: software reset clears the interrupt Message-ID: <166783932395.3279.1096141058484230644-4@git.sr.ht> X-Mailer: git.sr.ht In-Reply-To: <166783932395.3279.1096141058484230644-0@git.sr.ht> To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org MIME-Version: 1.0 Received-SPF: pass client-ip=173.195.146.151; envelope-from=outgoing@sr.ht; helo=mail-b.sr.ht X-Spam_score_int: 36 X-Spam_score: 3.6 X-Spam_bar: +++ X-Spam_report: (3.6 / 5.0 requ) BAYES_00=-1.9, DATE_IN_PAST_96_XX=3.405, FREEMAIL_FORGED_REPLYTO=2.095, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: ~axelheider Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Axel Heider Signed-off-by: Axel Heider --- hw/timer/imx_epit.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c index 2e9dae0bc8..5315d9633e 100644 --- a/hw/timer/imx_epit.c +++ b/hw/timer/imx_epit.c @@ -94,6 +94,10 @@ static void imx_epit_reset(DeviceState *dev) s->lr = EPIT_TIMER_MAX; s->cmp = 0; s->cnt = 0; + + /* clear the interrupt */ + qemu_irq_lower(s->irq); + ptimer_transaction_begin(s->timer_cmp); ptimer_transaction_begin(s->timer_reload); /* stop both timers */ From patchwork Wed Nov 2 15:36:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: ~axelheider X-Patchwork-Id: 13034864 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8B407C433FE for ; Mon, 7 Nov 2022 16:43:55 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1os5Ck-0002FH-QR; Mon, 07 Nov 2022 11:42:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1os5CQ-00025u-Bb; Mon, 07 Nov 2022 11:42:14 -0500 Received: from mail-b.sr.ht ([173.195.146.151]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1os5CN-0005Jo-6h; Mon, 07 Nov 2022 11:42:13 -0500 Authentication-Results: mail-b.sr.ht; dkim=none Received: from git.sr.ht (unknown [173.195.146.142]) by mail-b.sr.ht (Postfix) with ESMTPSA id 08F6611F847; Mon, 7 Nov 2022 16:42:05 +0000 (UTC) From: ~axelheider Date: Wed, 02 Nov 2022 16:36:43 +0100 Subject: [PATCH qemu.git v2 5/9] hw/timer/imx_epit: do not persist CR.SWR bit Message-ID: <166783932395.3279.1096141058484230644-5@git.sr.ht> X-Mailer: git.sr.ht In-Reply-To: <166783932395.3279.1096141058484230644-0@git.sr.ht> To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org MIME-Version: 1.0 Received-SPF: pass client-ip=173.195.146.151; envelope-from=outgoing@sr.ht; helo=mail-b.sr.ht X-Spam_score_int: 36 X-Spam_score: 3.6 X-Spam_bar: +++ X-Spam_report: (3.6 / 5.0 requ) BAYES_00=-1.9, DATE_IN_PAST_96_XX=3.405, FREEMAIL_FORGED_REPLYTO=2.095, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: ~axelheider Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Axel Heider Signed-off-by: Axel Heider --- hw/timer/imx_epit.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c index 5315d9633e..6af460946f 100644 --- a/hw/timer/imx_epit.c +++ b/hw/timer/imx_epit.c @@ -191,8 +191,9 @@ static void imx_epit_write(void *opaque, hwaddr offset, uint64_t value, case 0: /* CR */ oldcr = s->cr; - s->cr = value & 0x03ffffff; - if (s->cr & CR_SWR) { + /* SWR bit is never persisted, it clears itself once reset is done */ + s->cr = (value & ~CR_SWR) & 0x03ffffff; + if (value & CR_SWR) { /* handle the reset */ imx_epit_reset(DEVICE(s)); /* @@ -205,7 +206,7 @@ static void imx_epit_write(void *opaque, hwaddr offset, uint64_t value, ptimer_transaction_begin(s->timer_reload); /* Update the frequency. Has been done already in case of a reset. */ - if (!(s->cr & CR_SWR)) { + if (!(value & CR_SWR)) { imx_epit_set_freq(s); } From patchwork Tue Oct 25 10:33:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: ~axelheider X-Patchwork-Id: 13034869 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9B313C433FE for ; Mon, 7 Nov 2022 16:44:55 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1os5Co-0002Fx-GE; Mon, 07 Nov 2022 11:42:38 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1os5CW-000281-12; Mon, 07 Nov 2022 11:42:20 -0500 Received: from mail-b.sr.ht ([173.195.146.151]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1os5CO-0005Jl-D9; Mon, 07 Nov 2022 11:42:19 -0500 Authentication-Results: mail-b.sr.ht; dkim=none Received: from git.sr.ht (unknown [173.195.146.142]) by mail-b.sr.ht (Postfix) with ESMTPSA id 26D1B11F84A; Mon, 7 Nov 2022 16:42:05 +0000 (UTC) From: ~axelheider Date: Tue, 25 Oct 2022 12:33:42 +0200 Subject: [PATCH qemu.git v2 6/9] hw/timer/imx_epit: remove explicit fields cnt and freq Message-ID: <166783932395.3279.1096141058484230644-6@git.sr.ht> X-Mailer: git.sr.ht In-Reply-To: <166783932395.3279.1096141058484230644-0@git.sr.ht> To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org MIME-Version: 1.0 Received-SPF: pass client-ip=173.195.146.151; envelope-from=outgoing@sr.ht; helo=mail-b.sr.ht X-Spam_score_int: 36 X-Spam_score: 3.6 X-Spam_bar: +++ X-Spam_report: (3.6 / 5.0 requ) BAYES_00=-1.9, DATE_IN_PAST_96_XX=3.405, FREEMAIL_FORGED_REPLYTO=2.095, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: ~axelheider Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Axel Heider The CNT register is a read-only register. There is no need to store it's value, it can be calculated on demand. The calculated frequency is needed temporarily only. Signed-off-by: Axel Heider --- hw/timer/imx_epit.c | 76 +++++++++++++++---------------------- include/hw/timer/imx_epit.h | 2 - 2 files changed, 30 insertions(+), 48 deletions(-) diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c index 6af460946f..b0ef727efb 100644 --- a/hw/timer/imx_epit.c +++ b/hw/timer/imx_epit.c @@ -61,27 +61,16 @@ static const IMXClk imx_epit_clocks[] = { CLK_32k, /* 11 ipg_clk_32k -- ~32kHz */ }; -/* - * Must be called from within a ptimer_transaction_begin/commit block - * for both s->timer_cmp and s->timer_reload. - */ -static void imx_epit_set_freq(IMXEPITState *s) +static uint32_t imx_epit_get_freq(IMXEPITState *s) { - uint32_t clksrc; - uint32_t prescaler; - - clksrc = extract32(s->cr, CR_CLKSRC_SHIFT, CR_CLKSRC_BITS); - prescaler = 1 + extract32(s->cr, CR_PRESCALE_SHIFT, CR_PRESCALE_BITS); - - s->freq = imx_ccm_get_clock_frequency(s->ccm, - imx_epit_clocks[clksrc]) / prescaler; - - DPRINTF("Setting ptimer frequency to %u\n", s->freq); - - if (s->freq) { - ptimer_set_freq(s->timer_reload, s->freq); - ptimer_set_freq(s->timer_cmp, s->freq); - } + uint32_t clksrc = extract32(s->cr, CR_CLKSRC_SHIFT, CR_CLKSRC_BITS); + uint32_t prescaler = 1 + extract32(s->cr, CR_PRESCALE_SHIFT, + CR_PRESCALE_BITS); + uint32_t f_in = imx_ccm_get_clock_frequency(s->ccm, + imx_epit_clocks[clksrc]); + uint32_t freq = f_in / prescaler; + DPRINTF("ptimer frequency is %u\n", freq); + return freq; } static void imx_epit_reset(DeviceState *dev) @@ -93,36 +82,26 @@ static void imx_epit_reset(DeviceState *dev) s->sr = 0; s->lr = EPIT_TIMER_MAX; s->cmp = 0; - s->cnt = 0; - /* clear the interrupt */ qemu_irq_lower(s->irq); ptimer_transaction_begin(s->timer_cmp); ptimer_transaction_begin(s->timer_reload); - /* stop both timers */ + + /* + * The reset switches off the input clock, so even if the CR.EN is still + * set, the timers are no longer running. + */ + assert(0 == imx_epit_get_freq(s)); ptimer_stop(s->timer_cmp); ptimer_stop(s->timer_reload); - /* compute new frequency */ - imx_epit_set_freq(s); /* init both timers to EPIT_TIMER_MAX */ ptimer_set_limit(s->timer_cmp, EPIT_TIMER_MAX, 1); ptimer_set_limit(s->timer_reload, EPIT_TIMER_MAX, 1); - if (s->freq && (s->cr & CR_EN)) { - /* if the timer is still enabled, restart it */ - ptimer_run(s->timer_reload, 0); - } ptimer_transaction_commit(s->timer_cmp); ptimer_transaction_commit(s->timer_reload); } -static uint32_t imx_epit_update_count(IMXEPITState *s) -{ - s->cnt = ptimer_get_count(s->timer_reload); - - return s->cnt; -} - static uint64_t imx_epit_read(void *opaque, hwaddr offset, unsigned size) { IMXEPITState *s = IMX_EPIT(opaque); @@ -146,8 +125,7 @@ static uint64_t imx_epit_read(void *opaque, hwaddr offset, unsigned size) break; case 4: /* CNT */ - imx_epit_update_count(s); - reg_value = s->cnt; + reg_value = ptimer_get_count(s->timer_reload); break; default: @@ -166,7 +144,7 @@ static void imx_epit_reload_compare_timer(IMXEPITState *s) { if ((s->cr & (CR_EN | CR_OCIEN)) == (CR_EN | CR_OCIEN)) { /* if the compare feature is on and timers are running */ - uint32_t tmp = imx_epit_update_count(s); + uint32_t tmp = ptimer_get_count(s->timer_reload); uint64_t next; if (tmp > s->cmp) { /* It'll fire in this round of the timer */ @@ -182,6 +160,7 @@ static void imx_epit_write(void *opaque, hwaddr offset, uint64_t value, unsigned size) { IMXEPITState *s = IMX_EPIT(opaque); + uint64_t freq = 0; uint64_t oldcr; DPRINTF("(%s, value = 0x%08x)\n", imx_epit_reg_name(offset >> 2), @@ -205,12 +184,19 @@ static void imx_epit_write(void *opaque, hwaddr offset, uint64_t value, ptimer_transaction_begin(s->timer_cmp); ptimer_transaction_begin(s->timer_reload); - /* Update the frequency. Has been done already in case of a reset. */ + /* + * Update the frequency. In case of a reset the input clock was + * switched off, so this can be skipped. + */ if (!(value & CR_SWR)) { - imx_epit_set_freq(s); + freq = imx_epit_get_freq(s); + if (freq) { + ptimer_set_freq(s->timer_reload, freq); + ptimer_set_freq(s->timer_cmp, freq); + } } - if (s->freq && (s->cr & CR_EN) && !(oldcr & CR_EN)) { + if (freq && (s->cr & CR_EN) && !(oldcr & CR_EN)) { if (s->cr & CR_ENMOD) { if (s->cr & CR_RLD) { ptimer_set_limit(s->timer_reload, s->lr, 1); @@ -324,15 +310,13 @@ static const MemoryRegionOps imx_epit_ops = { static const VMStateDescription vmstate_imx_timer_epit = { .name = TYPE_IMX_EPIT, - .version_id = 2, - .minimum_version_id = 2, + .version_id = 3, + .minimum_version_id = 3, .fields = (VMStateField[]) { VMSTATE_UINT32(cr, IMXEPITState), VMSTATE_UINT32(sr, IMXEPITState), VMSTATE_UINT32(lr, IMXEPITState), VMSTATE_UINT32(cmp, IMXEPITState), - VMSTATE_UINT32(cnt, IMXEPITState), - VMSTATE_UINT32(freq, IMXEPITState), VMSTATE_PTIMER(timer_reload, IMXEPITState), VMSTATE_PTIMER(timer_cmp, IMXEPITState), VMSTATE_END_OF_LIST() diff --git a/include/hw/timer/imx_epit.h b/include/hw/timer/imx_epit.h index e2cb96229b..f6d41be7e1 100644 --- a/include/hw/timer/imx_epit.h +++ b/include/hw/timer/imx_epit.h @@ -72,9 +72,7 @@ struct IMXEPITState { uint32_t sr; uint32_t lr; uint32_t cmp; - uint32_t cnt; - uint32_t freq; qemu_irq irq; }; From patchwork Thu Oct 27 13:09:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: ~axelheider X-Patchwork-Id: 13034865 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 743F7C4332F for ; Mon, 7 Nov 2022 16:44:08 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1os5Cn-0002Fq-Tv; Mon, 07 Nov 2022 11:42:37 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1os5CS-00027E-SO; Mon, 07 Nov 2022 11:42:18 -0500 Received: from mail-b.sr.ht ([173.195.146.151]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1os5CO-0005Jv-CA; Mon, 07 Nov 2022 11:42:16 -0500 Authentication-Results: mail-b.sr.ht; dkim=none Received: from git.sr.ht (unknown [173.195.146.142]) by mail-b.sr.ht (Postfix) with ESMTPSA id 5098A11F852; Mon, 7 Nov 2022 16:42:05 +0000 (UTC) From: ~axelheider Date: Thu, 27 Oct 2022 15:09:58 +0200 Subject: [PATCH qemu.git v2 7/9] hw/timer/imx_epit: factor out register write handlers Message-ID: <166783932395.3279.1096141058484230644-7@git.sr.ht> X-Mailer: git.sr.ht In-Reply-To: <166783932395.3279.1096141058484230644-0@git.sr.ht> To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org MIME-Version: 1.0 Received-SPF: pass client-ip=173.195.146.151; envelope-from=outgoing@sr.ht; helo=mail-b.sr.ht X-Spam_score_int: 36 X-Spam_score: 3.6 X-Spam_bar: +++ X-Spam_report: (3.6 / 5.0 requ) BAYES_00=-1.9, DATE_IN_PAST_96_XX=3.405, FREEMAIL_FORGED_REPLYTO=2.095, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: ~axelheider Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Axel Heider Signed-off-by: Axel Heider --- hw/timer/imx_epit.c | 211 ++++++++++++++++++++++++-------------------- 1 file changed, 115 insertions(+), 96 deletions(-) diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c index b0ef727efb..30280a9ac1 100644 --- a/hw/timer/imx_epit.c +++ b/hw/timer/imx_epit.c @@ -156,130 +156,149 @@ static void imx_epit_reload_compare_timer(IMXEPITState *s) } } -static void imx_epit_write(void *opaque, hwaddr offset, uint64_t value, - unsigned size) +static void imx_epit_write_cr(IMXEPITState *s, uint32_t value) { - IMXEPITState *s = IMX_EPIT(opaque); - uint64_t freq = 0; - uint64_t oldcr; - - DPRINTF("(%s, value = 0x%08x)\n", imx_epit_reg_name(offset >> 2), - (uint32_t)value); + uint32_t freq = 0; + uint32_t oldcr = s->cr; - switch (offset >> 2) { - case 0: /* CR */ - - oldcr = s->cr; - /* SWR bit is never persisted, it clears itself once reset is done */ - s->cr = (value & ~CR_SWR) & 0x03ffffff; - if (value & CR_SWR) { - /* handle the reset */ - imx_epit_reset(DEVICE(s)); - /* - * TODO: could we 'break' here? following operations appear - * to duplicate the work imx_epit_reset() already did. - */ - } - - ptimer_transaction_begin(s->timer_cmp); - ptimer_transaction_begin(s->timer_reload); + /* SWR bit is never persisted, it clears itself once reset is done */ + s->cr = (value & ~CR_SWR) & 0x03ffffff; + if (value & CR_SWR) { + /* handle the reset */ + imx_epit_reset(DEVICE(s)); /* - * Update the frequency. In case of a reset the input clock was - * switched off, so this can be skipped. + * TODO: could we 'break' here? following operations appear + * to duplicate the work imx_epit_reset() already did. */ - if (!(value & CR_SWR)) { - freq = imx_epit_get_freq(s); - if (freq) { - ptimer_set_freq(s->timer_reload, freq); - ptimer_set_freq(s->timer_cmp, freq); - } - } + } - if (freq && (s->cr & CR_EN) && !(oldcr & CR_EN)) { - if (s->cr & CR_ENMOD) { - if (s->cr & CR_RLD) { - ptimer_set_limit(s->timer_reload, s->lr, 1); - ptimer_set_limit(s->timer_cmp, s->lr, 1); - } else { - ptimer_set_limit(s->timer_reload, EPIT_TIMER_MAX, 1); - ptimer_set_limit(s->timer_cmp, EPIT_TIMER_MAX, 1); - } - } + ptimer_transaction_begin(s->timer_cmp); + ptimer_transaction_begin(s->timer_reload); - imx_epit_reload_compare_timer(s); - ptimer_run(s->timer_reload, 0); - if (s->cr & CR_OCIEN) { - ptimer_run(s->timer_cmp, 0); + /* + * Update the frequency. In case of a reset the input clock was + * switched off, so this can be skipped. + */ + if (!(value & CR_SWR)) { + freq = imx_epit_get_freq(s); + if (freq) { + ptimer_set_freq(s->timer_reload, freq); + ptimer_set_freq(s->timer_cmp, freq); + } + } + + if (freq && (s->cr & CR_EN) && !(oldcr & CR_EN)) { + if (s->cr & CR_ENMOD) { + if (s->cr & CR_RLD) { + ptimer_set_limit(s->timer_reload, s->lr, 1); + ptimer_set_limit(s->timer_cmp, s->lr, 1); } else { - ptimer_stop(s->timer_cmp); - } - } else if (!(s->cr & CR_EN)) { - /* stop both timers */ - ptimer_stop(s->timer_reload); - ptimer_stop(s->timer_cmp); - } else if (s->cr & CR_OCIEN) { - if (!(oldcr & CR_OCIEN)) { - imx_epit_reload_compare_timer(s); - ptimer_run(s->timer_cmp, 0); + ptimer_set_limit(s->timer_reload, EPIT_TIMER_MAX, 1); + ptimer_set_limit(s->timer_cmp, EPIT_TIMER_MAX, 1); } + } + + imx_epit_reload_compare_timer(s); + ptimer_run(s->timer_reload, 0); + if (s->cr & CR_OCIEN) { + ptimer_run(s->timer_cmp, 0); } else { ptimer_stop(s->timer_cmp); } + } else if (!(s->cr & CR_EN)) { + /* stop both timers */ + ptimer_stop(s->timer_reload); + ptimer_stop(s->timer_cmp); + } else if (s->cr & CR_OCIEN) { + if (!(oldcr & CR_OCIEN)) { + imx_epit_reload_compare_timer(s); + ptimer_run(s->timer_cmp, 0); + } + } else { + ptimer_stop(s->timer_cmp); + } + + ptimer_transaction_commit(s->timer_cmp); + ptimer_transaction_commit(s->timer_reload); +} + +static void imx_epit_write_sr(IMXEPITState *s, uint32_t value) +{ + /* writing 1 to OCIF clears the OCIF bit and the interrupt */ + if (value & 0x01) { + s->sr = 0; + qemu_irq_lower(s->irq); + } +} + +static void imx_epit_write_lr(IMXEPITState *s, uint32_t value) +{ + s->lr = value; + + ptimer_transaction_begin(s->timer_cmp); + ptimer_transaction_begin(s->timer_reload); + if (s->cr & CR_RLD) { + /* Also set the limit if the LRD bit is set */ + /* If IOVW bit is set then set the timer value */ + ptimer_set_limit(s->timer_reload, s->lr, s->cr & CR_IOVW); + ptimer_set_limit(s->timer_cmp, s->lr, 0); + } else if (s->cr & CR_IOVW) { + /* If IOVW bit is set then set the timer value */ + ptimer_set_count(s->timer_reload, s->lr); + } + /* + * Commit the change to s->timer_reload, so it can propagate. Otherwise + * the timer interrupt may not fire properly. The commit must happen + * before calling imx_epit_reload_compare_timer(), which reads + * s->timer_reload internally again. + */ + ptimer_transaction_commit(s->timer_reload); + imx_epit_reload_compare_timer(s); + ptimer_transaction_commit(s->timer_cmp); +} + +static void imx_epit_write_cmp(IMXEPITState *s, uint32_t value) +{ + s->cmp = value; + + ptimer_transaction_begin(s->timer_cmp); + imx_epit_reload_compare_timer(s); + ptimer_transaction_commit(s->timer_cmp); +} + +static void imx_epit_write(void *opaque, hwaddr offset, uint64_t value, + unsigned size) +{ + IMXEPITState *s = IMX_EPIT(opaque); + + DPRINTF("(%s, value = 0x%08x)\n", imx_epit_reg_name(offset >> 2), + (uint32_t)value); - ptimer_transaction_commit(s->timer_cmp); - ptimer_transaction_commit(s->timer_reload); + switch (offset >> 2) { + case 0: /* CR */ + imx_epit_write_cr(s, (uint32_t)value); break; - case 1: /* SR - ACK*/ - /* writing 1 to OCIF clears the OCIF bit and the interrupt */ - if (value & 0x01) { - s->sr = 0; - qemu_irq_lower(s->irq); - } + case 1: /* SR */ + imx_epit_write_sr(s, (uint32_t)value); break; - case 2: /* LR - set ticks */ - s->lr = value; - - ptimer_transaction_begin(s->timer_cmp); - ptimer_transaction_begin(s->timer_reload); - if (s->cr & CR_RLD) { - /* Also set the limit if the LRD bit is set */ - /* If IOVW bit is set then set the timer value */ - ptimer_set_limit(s->timer_reload, s->lr, s->cr & CR_IOVW); - ptimer_set_limit(s->timer_cmp, s->lr, 0); - } else if (s->cr & CR_IOVW) { - /* If IOVW bit is set then set the timer value */ - ptimer_set_count(s->timer_reload, s->lr); - } - /* - * Commit the change to s->timer_reload, so it can propagate. Otherwise - * the timer interrupt may not fire properly. The commit must happen - * before calling imx_epit_reload_compare_timer(), which reads - * s->timer_reload internally again. - */ - ptimer_transaction_commit(s->timer_reload); - imx_epit_reload_compare_timer(s); - ptimer_transaction_commit(s->timer_cmp); + case 2: /* LR */ + imx_epit_write_lr(s, (uint32_t)value); break; case 3: /* CMP */ - s->cmp = value; - - ptimer_transaction_begin(s->timer_cmp); - imx_epit_reload_compare_timer(s); - ptimer_transaction_commit(s->timer_cmp); - + imx_epit_write_cmp(s, (uint32_t)value); break; default: qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%" HWADDR_PRIx "\n", TYPE_IMX_EPIT, __func__, offset); - break; } } + static void imx_epit_cmp(void *opaque) { IMXEPITState *s = IMX_EPIT(opaque); From patchwork Fri Nov 4 15:01:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: ~axelheider X-Patchwork-Id: 13034862 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E4925C43217 for ; Mon, 7 Nov 2022 16:43:24 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1os5Ch-0002Ck-Es; Mon, 07 Nov 2022 11:42:31 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1os5CS-00026w-Jr; Mon, 07 Nov 2022 11:42:18 -0500 Received: from mail-b.sr.ht ([173.195.146.151]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1os5CO-0005Jw-C1; Mon, 07 Nov 2022 11:42:15 -0500 Authentication-Results: mail-b.sr.ht; dkim=none Received: from git.sr.ht (unknown [173.195.146.142]) by mail-b.sr.ht (Postfix) with ESMTPSA id 8DBE511F853; Mon, 7 Nov 2022 16:42:05 +0000 (UTC) From: ~axelheider Date: Fri, 04 Nov 2022 16:01:28 +0100 Subject: [PATCH qemu.git v2 8/9] hw/timer/imx_epit: change reset handling Message-ID: <166783932395.3279.1096141058484230644-8@git.sr.ht> X-Mailer: git.sr.ht In-Reply-To: <166783932395.3279.1096141058484230644-0@git.sr.ht> To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org MIME-Version: 1.0 Received-SPF: pass client-ip=173.195.146.151; envelope-from=outgoing@sr.ht; helo=mail-b.sr.ht X-Spam_score_int: 2 X-Spam_score: 0.2 X-Spam_bar: / X-Spam_report: (0.2 / 5.0 requ) BAYES_00=-1.9, FREEMAIL_FORGED_REPLYTO=2.095, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: ~axelheider Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Axel Heider - inline software reset - make hardware reset invoke software reset - simplify code flow Signed-off-by: Axel Heider --- hw/timer/imx_epit.c | 66 ++++++++++++++++----------------------------- 1 file changed, 23 insertions(+), 43 deletions(-) diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c index 30280a9ac1..77bd2b0a2b 100644 --- a/hw/timer/imx_epit.c +++ b/hw/timer/imx_epit.c @@ -73,35 +73,6 @@ static uint32_t imx_epit_get_freq(IMXEPITState *s) return freq; } -static void imx_epit_reset(DeviceState *dev) -{ - IMXEPITState *s = IMX_EPIT(dev); - - /* Soft reset doesn't touch some bits; hard reset clears them */ - s->cr &= (CR_EN|CR_ENMOD|CR_STOPEN|CR_DOZEN|CR_WAITEN|CR_DBGEN); - s->sr = 0; - s->lr = EPIT_TIMER_MAX; - s->cmp = 0; - /* clear the interrupt */ - qemu_irq_lower(s->irq); - - ptimer_transaction_begin(s->timer_cmp); - ptimer_transaction_begin(s->timer_reload); - - /* - * The reset switches off the input clock, so even if the CR.EN is still - * set, the timers are no longer running. - */ - assert(0 == imx_epit_get_freq(s)); - ptimer_stop(s->timer_cmp); - ptimer_stop(s->timer_reload); - /* init both timers to EPIT_TIMER_MAX */ - ptimer_set_limit(s->timer_cmp, EPIT_TIMER_MAX, 1); - ptimer_set_limit(s->timer_reload, EPIT_TIMER_MAX, 1); - ptimer_transaction_commit(s->timer_cmp); - ptimer_transaction_commit(s->timer_reload); -} - static uint64_t imx_epit_read(void *opaque, hwaddr offset, unsigned size) { IMXEPITState *s = IMX_EPIT(opaque); @@ -164,23 +135,23 @@ static void imx_epit_write_cr(IMXEPITState *s, uint32_t value) /* SWR bit is never persisted, it clears itself once reset is done */ s->cr = (value & ~CR_SWR) & 0x03ffffff; - if (value & CR_SWR) { - /* handle the reset */ - imx_epit_reset(DEVICE(s)); - /* - * TODO: could we 'break' here? following operations appear - * to duplicate the work imx_epit_reset() already did. - */ - } - ptimer_transaction_begin(s->timer_cmp); ptimer_transaction_begin(s->timer_reload); - /* - * Update the frequency. In case of a reset the input clock was - * switched off, so this can be skipped. - */ - if (!(value & CR_SWR)) { + if (value & CR_SWR) { + /* Soft reset doesn't touch some bits; only a hard reset clears them */ + s->cr &= (CR_EN|CR_ENMOD|CR_STOPEN|CR_DOZEN|CR_WAITEN|CR_DBGEN); + s->sr = 0; + s->lr = EPIT_TIMER_MAX; + s->cmp = 0; + /* reset is supposed to disable the input clock */ + assert(0 == imx_epit_get_freq(s)); + /* turn interrupt off since SR and the OCIEN bit got cleared */ + qemu_irq_lower(s->irq); + /* reset timer limits, set timer values to these limits */ + ptimer_set_limit(s->timer_cmp, EPIT_TIMER_MAX, 1); + ptimer_set_limit(s->timer_reload, EPIT_TIMER_MAX, 1); + } else { freq = imx_epit_get_freq(s); if (freq) { ptimer_set_freq(s->timer_reload, freq); @@ -369,6 +340,15 @@ static void imx_epit_realize(DeviceState *dev, Error **errp) s->timer_cmp = ptimer_init(imx_epit_cmp, s, PTIMER_POLICY_LEGACY); } +static void imx_epit_reset(DeviceState *dev) +{ + IMXEPITState *s = IMX_EPIT(dev); + + /* initialize CR and perform a software reset */ + s->cr = 0; + imx_epit_write_cr(s, CR_SWR); +} + static void imx_epit_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); From patchwork Thu Nov 3 11:09:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: ~axelheider X-Patchwork-Id: 13034868 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BC872C433FE for ; Mon, 7 Nov 2022 16:44:48 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1os5Cm-0002Fb-C2; Mon, 07 Nov 2022 11:42:36 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1os5CT-00027G-Ao; Mon, 07 Nov 2022 11:42:18 -0500 Received: from mail-b.sr.ht ([173.195.146.151]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1os5CO-0005KB-EJ; Mon, 07 Nov 2022 11:42:17 -0500 Authentication-Results: mail-b.sr.ht; dkim=none Received: from git.sr.ht (unknown [173.195.146.142]) by mail-b.sr.ht (Postfix) with ESMTPSA id BA2AF11F854; Mon, 7 Nov 2022 16:42:05 +0000 (UTC) From: ~axelheider Date: Thu, 03 Nov 2022 12:09:28 +0100 Subject: [PATCH qemu.git v2 9/9] hw/timer/imx_epit: fix compare timer handling Message-ID: <166783932395.3279.1096141058484230644-9@git.sr.ht> X-Mailer: git.sr.ht In-Reply-To: <166783932395.3279.1096141058484230644-0@git.sr.ht> To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org MIME-Version: 1.0 Received-SPF: pass client-ip=173.195.146.151; envelope-from=outgoing@sr.ht; helo=mail-b.sr.ht X-Spam_score_int: 36 X-Spam_score: 3.6 X-Spam_bar: +++ X-Spam_report: (3.6 / 5.0 requ) BAYES_00=-1.9, DATE_IN_PAST_96_XX=3.405, FREEMAIL_FORGED_REPLYTO=2.095, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: ~axelheider Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Axel Heider - fix #1263 - rework compare time handling - The compare timer has to run even if CR.OCIEN is not set, as SR.OCIF must be updated. - The compare timer fires exactly once when the compare value is less than the current value, but the reload values is less than the compare value. - The compare timer will never fire if the reload value is less than the compare value. Disable it in this case. Signed-off-by: Axel Heider --- hw/timer/imx_epit.c | 188 +++++++++++++++++++++++++++++--------------- 1 file changed, 123 insertions(+), 65 deletions(-) diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c index 77bd2b0a2b..cb2880cabc 100644 --- a/hw/timer/imx_epit.c +++ b/hw/timer/imx_epit.c @@ -6,6 +6,7 @@ * Originally written by Hans Jiang * Updated by Peter Chubb * Updated by Jean-Christophe Dubois + * Updated by Axel Heider * * This code is licensed under GPL version 2 or later. See * the COPYING file in the top-level directory. @@ -110,33 +111,84 @@ static uint64_t imx_epit_read(void *opaque, hwaddr offset, unsigned size) return reg_value; } -/* Must be called from ptimer_transaction_begin/commit block for s->timer_cmp */ -static void imx_epit_reload_compare_timer(IMXEPITState *s) +/* + * Must be called from a ptimer_transaction_begin/commit block for + * s->timer_cmp, but outside of a transaction block of s->timer_reload, + * so the proper counter value is read. + */ +static void imx_epit_update_compare_timer(IMXEPITState *s) { - if ((s->cr & (CR_EN | CR_OCIEN)) == (CR_EN | CR_OCIEN)) { - /* if the compare feature is on and timers are running */ - uint32_t tmp = ptimer_get_count(s->timer_reload); - uint64_t next; - if (tmp > s->cmp) { - /* It'll fire in this round of the timer */ - next = tmp - s->cmp; - } else { /* catch it next time around */ - next = tmp - s->cmp + ((s->cr & CR_RLD) ? EPIT_TIMER_MAX : s->lr); + uint64_t counter = 0; + bool is_oneshot = false; + /* The compare timer only has to run if the timer peripheral is active + * and there is an input clock, Otherwise it can be switched off. + */ + bool is_active = (s->cr & CR_EN) && imx_epit_get_freq(s); + if (is_active) + { + /* + * Calculate next timeout for compare timer. Reading the reload + * counter returns proper results only if pending transactions + * on it are committed here. Otherwise stale values are be read. + */ + counter = ptimer_get_count(s->timer_reload); + uint64_t limit = ptimer_get_limit(s->timer_cmp); + /* The compare timer is a periodic timer if the limit is at least + * the compare value. Otherwise it may fire at most once in the + * current round. + */ + bool is_oneshot = (limit >= s->cmp); + if (counter >= s->cmp) { + /* The compare timer fires in the current round. */ + counter -= s->cmp; + } else if (!is_oneshot) { + /* + * The compare timer fires after a reload, as it below the + * compare value already in this round. Note that the counter + * value calculated below can be above the 32-bit limit, which + * is legal here because the compare timer is an internal + * helper ptimer only. + */ + counter += limit - s->cmp; + } else { + /* + * The compare timer wont fire in this round, and the limit is + * set to a value below the compare value. This practically means + * it will never fire, so it can be switched off. + */ + is_active = false; } - ptimer_set_count(s->timer_cmp, next); } + + /* + * Set the compare timer and let it run, or stop it. This is agnostic + * of CR.OCIEN bit, as this only matters for interrupt generation. The + * compare timer needs to run in any case, as the SR.OCIF bit must be + * updated even if no interrupt in generated. + * Note that the timer might already be stopped or be running with + * counter values. However, finding out when an update is needed and + * when not is not trivial. It's much easier applying the setting again, + * as this does not harm either and the overhead is negligible. + */ + if (is_active) { + ptimer_set_count(s->timer_cmp, counter); + ptimer_run(s->timer_cmp, is_oneshot ? 1 : 0); + } else { + ptimer_stop(s->timer_cmp); + } + } static void imx_epit_write_cr(IMXEPITState *s, uint32_t value) { uint32_t freq = 0; - uint32_t oldcr = s->cr; + bool set_limit = false; + bool set_counter = false; /* SWR bit is never persisted, it clears itself once reset is done */ + uint32_t old_cr = s->cr; s->cr = (value & ~CR_SWR) & 0x03ffffff; - - ptimer_transaction_begin(s->timer_cmp); - ptimer_transaction_begin(s->timer_reload); + uint32_t toggled_cr = old_cr ^ s->cr; if (value & CR_SWR) { /* Soft reset doesn't touch some bits; only a hard reset clears them */ @@ -149,49 +201,52 @@ static void imx_epit_write_cr(IMXEPITState *s, uint32_t value) /* turn interrupt off since SR and the OCIEN bit got cleared */ qemu_irq_lower(s->irq); /* reset timer limits, set timer values to these limits */ - ptimer_set_limit(s->timer_cmp, EPIT_TIMER_MAX, 1); - ptimer_set_limit(s->timer_reload, EPIT_TIMER_MAX, 1); + set_limit = true; + set_counter = true; } else { - freq = imx_epit_get_freq(s); - if (freq) { - ptimer_set_freq(s->timer_reload, freq); - ptimer_set_freq(s->timer_cmp, freq); - } + /* re-initialize the limits if CR.RLD has changed */ + set_limit = toggled_cr & CR_RLD; + /* set the counter if the timer got just enabled and CR.ENMOD is set */ + set_counter = ((toggled_cr & s->cr) & CR_EN) && (s->cr & CR_ENMOD); + } + + ptimer_transaction_begin(s->timer_cmp); + ptimer_transaction_begin(s->timer_reload); + + freq = imx_epit_get_freq(s); + if (freq) { + ptimer_set_freq(s->timer_reload, freq); + ptimer_set_freq(s->timer_cmp, freq); } - if (freq && (s->cr & CR_EN) && !(oldcr & CR_EN)) { - if (s->cr & CR_ENMOD) { - if (s->cr & CR_RLD) { - ptimer_set_limit(s->timer_reload, s->lr, 1); - ptimer_set_limit(s->timer_cmp, s->lr, 1); - } else { - ptimer_set_limit(s->timer_reload, EPIT_TIMER_MAX, 1); - ptimer_set_limit(s->timer_cmp, EPIT_TIMER_MAX, 1); - } + if (set_limit || set_counter) { + uint64_t limit = (s->cr & CR_RLD) ? s->lr : EPIT_TIMER_MAX; + if (set_limit) { + ptimer_set_limit(s->timer_cmp, limit, 0); } + ptimer_set_limit(s->timer_reload, limit, set_counter ? 1 : 0); + } - imx_epit_reload_compare_timer(s); + /* + * If there is an input clock and the peripheral is enabled, then ensure + * the wall clock timer is ticking. Otherwise stop the timers. The compare + * timer will be updated later. + */ + if (freq && (s->cr & CR_EN)) { ptimer_run(s->timer_reload, 0); - if (s->cr & CR_OCIEN) { - ptimer_run(s->timer_cmp, 0); - } else { - ptimer_stop(s->timer_cmp); - } - } else if (!(s->cr & CR_EN)) { - /* stop both timers */ - ptimer_stop(s->timer_reload); - ptimer_stop(s->timer_cmp); - } else if (s->cr & CR_OCIEN) { - if (!(oldcr & CR_OCIEN)) { - imx_epit_reload_compare_timer(s); - ptimer_run(s->timer_cmp, 0); - } } else { + ptimer_stop(s->timer_reload); + /* Stop the compare timer also. This just plays safe, the call to + * imx_epit_update_compare_timer() below should also so this. */ ptimer_stop(s->timer_cmp); } - ptimer_transaction_commit(s->timer_cmp); + /* Commit the changes to s->timer_reload, so they can propagate. */ ptimer_transaction_commit(s->timer_reload); + + /* Update the compare timer based on the committed reload timer value. */ + imx_epit_update_compare_timer(s); + ptimer_transaction_commit(s->timer_cmp); } static void imx_epit_write_sr(IMXEPITState *s, uint32_t value) @@ -218,14 +273,10 @@ static void imx_epit_write_lr(IMXEPITState *s, uint32_t value) /* If IOVW bit is set then set the timer value */ ptimer_set_count(s->timer_reload, s->lr); } - /* - * Commit the change to s->timer_reload, so it can propagate. Otherwise - * the timer interrupt may not fire properly. The commit must happen - * before calling imx_epit_reload_compare_timer(), which reads - * s->timer_reload internally again. - */ + /* Commit the changes to s->timer_reload, so they can propagate. */ ptimer_transaction_commit(s->timer_reload); - imx_epit_reload_compare_timer(s); + /* Update the compare timer based on the committed reload timer value. */ + imx_epit_update_compare_timer(s); ptimer_transaction_commit(s->timer_cmp); } @@ -233,8 +284,9 @@ static void imx_epit_write_cmp(IMXEPITState *s, uint32_t value) { s->cmp = value; + /* Update the compare timer based on the committed reload timer value. */ ptimer_transaction_begin(s->timer_cmp); - imx_epit_reload_compare_timer(s); + imx_epit_update_compare_timer(s); ptimer_transaction_commit(s->timer_cmp); } @@ -274,16 +326,22 @@ static void imx_epit_cmp(void *opaque) { IMXEPITState *s = IMX_EPIT(opaque); - /* Set the interrupt status flag to signaled. */ - DPRINTF("sr was %d\n", s->sr); - s->sr = 1; + if (s->cr & CR_EN) { + /* Set the interrupt status flag to signaled. */ + DPRINTF("sr was %d\n", s->sr); + s->sr = 1; - /* - * An actual interrupt is generated only if the peripheral is enabled - * and the interrupt generation is enabled. - */ - if ((s->cr & (CR_EN | CR_OCIEN)) == (CR_EN | CR_OCIEN)) { - qemu_irq_raise(s->irq); + /* If CR,OCIEN is set, an actual interrupt is generated */ + if (s->cr & CR_OCIEN) { + qemu_irq_raise(s->irq); + } + } else { + /* + * The cmp ptimer is not supposed to be running when the + * peripheral is not enabled. Ignore this. However, it's + * worth investigating why this happened. + */ + DPRINTF("compare trigger when timer not enabled\n"); } }