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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id o16sm128900134wrn.11.2019.01.21.07.22.21 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 21 Jan 2019 07:22:22 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Mon, 21 Jan 2019 15:22:15 +0000 Message-Id: <20190121152218.9592-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190121152218.9592-1-peter.maydell@linaro.org> References: <20190121152218.9592-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 Subject: [Qemu-devel] [PATCH v3 1/4] hw/arm/xlx-zynqmp: Realize cluster after putting RPUs in it X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eduardo Habkost , Peter Crosthwaite , Alistair Francis , Richard Henderson , "Emilio G . Cota" , "Edgar E. Iglesias" , Paolo Bonzini , Aleksandar Markovic Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Currently the cluster implementation doesn't have any constraints on the ordering of realizing the TYPE_CPU_CLUSTER and populating it with child objects. We want to impose a constraint that realize must happen only after all the child objects are added, so move the realize of rpu_cluster. (The apu_cluster is already realized after child population.) Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Luc Michel Reviewed-by: Alistair Francis Reviewed-by: Edgar E. Iglesias --- hw/arm/xlnx-zynqmp.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c index c67ac2e64ac..370b0e44a38 100644 --- a/hw/arm/xlnx-zynqmp.c +++ b/hw/arm/xlnx-zynqmp.c @@ -183,8 +183,6 @@ static void xlnx_zynqmp_create_rpu(XlnxZynqMPState *s, const char *boot_cpu, &error_abort, NULL); qdev_prop_set_uint32(DEVICE(&s->rpu_cluster), "cluster-id", 1); - qdev_init_nofail(DEVICE(&s->rpu_cluster)); - for (i = 0; i < num_rpus; i++) { char *name; @@ -212,6 +210,8 @@ static void xlnx_zynqmp_create_rpu(XlnxZynqMPState *s, const char *boot_cpu, return; } } + + qdev_init_nofail(DEVICE(&s->rpu_cluster)); } static void xlnx_zynqmp_init(Object *obj) From patchwork Mon Jan 21 15:22:16 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 10773981 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 77BE91390 for ; Mon, 21 Jan 2019 15:23:55 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 65DDC2835B for ; Mon, 21 Jan 2019 15:23:55 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 596B529904; Mon, 21 Jan 2019 15:23:55 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id A35602835B for ; Mon, 21 Jan 2019 15:23:54 +0000 (UTC) Received: from localhost ([127.0.0.1]:55176 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1glbQX-0000fH-OO for patchwork-qemu-devel@patchwork.kernel.org; Mon, 21 Jan 2019 10:23:53 -0500 Received: from eggs.gnu.org ([209.51.188.92]:44558) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1glbPL-000811-Pi for qemu-devel@nongnu.org; Mon, 21 Jan 2019 10:22:41 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1glbPJ-0003wB-DR for qemu-devel@nongnu.org; Mon, 21 Jan 2019 10:22:39 -0500 Received: from mail-wm1-x342.google.com ([2a00:1450:4864:20::342]:36837) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1glbPH-0003rB-6H for qemu-devel@nongnu.org; Mon, 21 Jan 2019 10:22:35 -0500 Received: by mail-wm1-x342.google.com with SMTP id p6so11162599wmc.1 for ; Mon, 21 Jan 2019 07:22:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=dW3XYUmi+127c7xazctmwe4gw2x2VuqOsI6Nkm1CZQ4=; b=JaiSTkMuDG9yYdoVn9j8PHj//y1/3F+NUCp2oVY9uQ2/4l+rylAWmciwtoJymDGQ6e wwShQuxrOcdHRUlGapFVnEh3cDQ7sykiVfuLdgtISDCeLY9x/Jcv57qvtRQPt/6/8xsv stGTpvbhGrw+R5XeOIJO27BBg99GPoJgni040= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=dW3XYUmi+127c7xazctmwe4gw2x2VuqOsI6Nkm1CZQ4=; b=GA9ovWR6EpFj+ATze7NWVGEikkEeACuwccDcwlofgic+dejC209JLsPRCm/BakPGSE O4o6VPOUSDtujBicUx40j0YNRGj1WV55hVfXHgru5BNfeQEONRSzQu6D2B1+RV8UCzmc J4X4p8ccfWl/RwJxEMTbnr2QR+JqYzTCTYpF84sZ1O6kF6ohIj18UnZdePbqIDlCoHUC 8NDA73G+aqiy28WHKyX2zu1NgcrIy8JHAdNmkjy/dNQ71KQYnVnY1eObSx/ByU9oSa/Q 8nXpM7LUK8o0y40ypJSVeJh8PTCC6Z+EpQ907AZUgEOxE4owYHttI6WpcINWtY3nERoM 1jWw== X-Gm-Message-State: AJcUukdVrH7yANZj4jjs/RMxihcxrIXsb+J6O0zAPgwyxksBtB8Volsw NlZUrq0GnYkIC512cD1qcEQhpQ== X-Google-Smtp-Source: ALg8bN5MhRHXjJ2jqdyb21LLnhFkst+uJJbHUsK5gLXQlaqExEwJkCh781dsfCAJZvgnhpI9xZM9lg== X-Received: by 2002:a1c:e044:: with SMTP id x65mr10063934wmg.86.1548084144516; Mon, 21 Jan 2019 07:22:24 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id o16sm128900134wrn.11.2019.01.21.07.22.23 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 21 Jan 2019 07:22:23 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Mon, 21 Jan 2019 15:22:16 +0000 Message-Id: <20190121152218.9592-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190121152218.9592-1-peter.maydell@linaro.org> References: <20190121152218.9592-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::342 Subject: [Qemu-devel] [PATCH v3 2/4] qom/cpu: Add cluster_index to CPUState X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eduardo Habkost , Peter Crosthwaite , Alistair Francis , Richard Henderson , "Emilio G . Cota" , "Edgar E. Iglesias" , Paolo Bonzini , Aleksandar Markovic Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP For TCG we want to distinguish which cluster a CPU is in, and we need to do it quickly. Cache the cluster index in the CPUState struct, by having the cluster object set cpu->cluster_index for each CPU child when it is realized. This means that board/SoC code must add all CPUs to the cluster before realizing the cluster object. Regrettably QOM provides no way to prevent adding children to a realized object and no way for the parent to be notified when a new child is added to it, so we don't have any way to enforce/assert this constraint; all we can do is document it in a comment. We can at least put in a check that the cluster contains at least one CPU, which should catch the typical cases of "realized cluster too early" or "forgot to parent the CPUs into it". The restriction on how many clusters can exist in the system is imposed by TCG code which will be added in a subsequent commit, but the check to enforce it in cluster.c fits better in this one. Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias Reviewed-by: Alistair Francis --- Changes v2->v3: * allow CPU objects to be indirect children of the cluster; this is useful for ARMv7M, where the CPU object is a child of the armv7m container and the board code that sets up the cluster object only has the armv7m container object: this is done by using object_child_foreach_recursive() rather than an open-coded child iteration * add an assertion that the cluster has at least one CPU, which catches the easiest-to-make errors when creating and populating the cluster --- include/hw/cpu/cluster.h | 24 +++++++++++++++++++++ include/qom/cpu.h | 7 ++++++ hw/cpu/cluster.c | 46 ++++++++++++++++++++++++++++++++++++++++ qom/cpu.c | 1 + 4 files changed, 78 insertions(+) diff --git a/include/hw/cpu/cluster.h b/include/hw/cpu/cluster.h index 73818232437..549c2d31d43 100644 --- a/include/hw/cpu/cluster.h +++ b/include/hw/cpu/cluster.h @@ -34,12 +34,36 @@ * Arm big.LITTLE system) they should be in different clusters. If the CPUs do * not have the same view of memory (for example the main CPU and a management * controller processor) they should be in different clusters. + * + * A cluster is created by creating an object of TYPE_CPU_CLUSTER, and then + * adding the CPUs to it as QOM child objects (e.g. using the + * object_initialize_child() or object_property_add_child() functions). + * The CPUs may be either direct children of the cluster object, or indirect + * children (e.g. children of children of the cluster object). + * + * All CPUs must be added as children before the cluster is realized. + * (Regrettably QOM provides no way to prevent adding children to a realized + * object and no way for the parent to be notified when a new child is added + * to it, so this restriction is not checked for, but the system will not + * behave correctly if it is not adhered to. The cluster will assert that + * it contains at least one CPU, which should catch most inadvertent + * violations of this constraint.) + * + * A CPU which is not put into any cluster will be considered implicitly + * to be in a cluster with all the other "loose" CPUs, so all CPUs that are + * not assigned to clusters must be identical. */ #define TYPE_CPU_CLUSTER "cpu-cluster" #define CPU_CLUSTER(obj) \ OBJECT_CHECK(CPUClusterState, (obj), TYPE_CPU_CLUSTER) +/* + * This limit is imposed by TCG, which puts the cluster ID into an + * 8 bit field (and uses all-1s for the default "not in any cluster"). + */ +#define MAX_CLUSTERS 255 + /** * CPUClusterState: * @cluster_id: The cluster ID. This value is for internal use only and should diff --git a/include/qom/cpu.h b/include/qom/cpu.h index 16bbed1ae09..4c2feb9c17b 100644 --- a/include/qom/cpu.h +++ b/include/qom/cpu.h @@ -280,6 +280,11 @@ struct qemu_work_item; /** * CPUState: * @cpu_index: CPU index (informative). + * @cluster_index: Identifies which cluster this CPU is in. + * For boards which don't define clusters or for "loose" CPUs not assigned + * to a cluster this will be UNASSIGNED_CLUSTER_INDEX; otherwise it will + * be the same as the cluster-id property of the CPU object's TYPE_CPU_CLUSTER + * QOM parent. * @nr_cores: Number of cores within this CPU package. * @nr_threads: Number of threads within this CPU. * @running: #true if CPU is currently running (lockless). @@ -405,6 +410,7 @@ struct CPUState { /* TODO Move common fields from CPUArchState here. */ int cpu_index; + int cluster_index; uint32_t halted; uint32_t can_do_io; int32_t exception_index; @@ -1111,5 +1117,6 @@ extern const struct VMStateDescription vmstate_cpu_common; #endif /* NEED_CPU_H */ #define UNASSIGNED_CPU_INDEX -1 +#define UNASSIGNED_CLUSTER_INDEX -1 #endif diff --git a/hw/cpu/cluster.c b/hw/cpu/cluster.c index 9d50a235d5c..25f90702b16 100644 --- a/hw/cpu/cluster.c +++ b/hw/cpu/cluster.c @@ -20,19 +20,65 @@ #include "qemu/osdep.h" #include "hw/cpu/cluster.h" +#include "qom/cpu.h" #include "qapi/error.h" #include "qemu/module.h" +#include "qemu/cutils.h" static Property cpu_cluster_properties[] = { DEFINE_PROP_UINT32("cluster-id", CPUClusterState, cluster_id, 0), DEFINE_PROP_END_OF_LIST() }; +typedef struct CallbackData { + CPUClusterState *cluster; + int cpu_count; +} CallbackData; + +static int add_cpu_to_cluster(Object *obj, void *opaque) +{ + CallbackData *cbdata = opaque; + CPUState *cpu = (CPUState *)object_dynamic_cast(obj, TYPE_CPU); + + if (cpu) { + cpu->cluster_index = cbdata->cluster->cluster_id; + cbdata->cpu_count++; + } + return 0; +} + +static void cpu_cluster_realize(DeviceState *dev, Error **errp) +{ + /* Iterate through all our CPU children and set their cluster_index */ + CPUClusterState *cluster = CPU_CLUSTER(dev); + Object *cluster_obj = OBJECT(dev); + CallbackData cbdata = { + .cluster = cluster, + .cpu_count = 0, + }; + + if (cluster->cluster_id >= MAX_CLUSTERS) { + error_setg(errp, "cluster-id must be less than %d", MAX_CLUSTERS); + return; + } + + object_child_foreach_recursive(cluster_obj, add_cpu_to_cluster, &cbdata); + + /* + * A cluster with no CPUs is a bug in the board/SoC code that created it; + * if you hit this during development of new code, check that you have + * created the CPUs and parented them into the cluster object before + * realizing the cluster object. + */ + assert(cbdata.cpu_count > 0); +} + static void cpu_cluster_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); dc->props = cpu_cluster_properties; + dc->realize = cpu_cluster_realize; } static const TypeInfo cpu_cluster_type_info = { diff --git a/qom/cpu.c b/qom/cpu.c index 5442a7323be..f5579b1cd50 100644 --- a/qom/cpu.c +++ b/qom/cpu.c @@ -364,6 +364,7 @@ static void cpu_common_initfn(Object *obj) CPUClass *cc = CPU_GET_CLASS(obj); cpu->cpu_index = UNASSIGNED_CPU_INDEX; + cpu->cluster_index = UNASSIGNED_CLUSTER_INDEX; cpu->gdb_num_regs = cpu->gdb_num_g_regs = cc->gdb_num_core_regs; /* *-user doesn't have configurable SMP topology */ /* the default value is changed by qemu_init_vcpu() for softmmu */ From patchwork Mon Jan 21 15:22:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 10773979 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 250F31390 for ; Mon, 21 Jan 2019 15:23:54 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 140ED2835B for ; Mon, 21 Jan 2019 15:23:54 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 06CE629904; Mon, 21 Jan 2019 15:23:54 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 8C7912835B for ; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id o16sm128900134wrn.11.2019.01.21.07.22.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 21 Jan 2019 07:22:25 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Mon, 21 Jan 2019 15:22:17 +0000 Message-Id: <20190121152218.9592-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190121152218.9592-1-peter.maydell@linaro.org> References: <20190121152218.9592-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 Subject: [Qemu-devel] [PATCH v3 3/4] accel/tcg: Add cluster number to TCG TB hash X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eduardo Habkost , Peter Crosthwaite , Alistair Francis , Richard Henderson , "Emilio G . Cota" , "Edgar E. Iglesias" , Paolo Bonzini , Aleksandar Markovic Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Include the cluster number in the hash we use to look up TBs. This is important because a TB that is valid for one cluster at a given physical address and set of CPU flags is not necessarily valid for another: the two clusters may have different views of physical memory, or may have different CPU features (eg FPU present or absent). We put the cluster number in the high 8 bits of the TB cflags. This gives us up to 256 clusters, which should be enough for anybody. If we ever need more, or need more bits in cflags for other purposes, we could make tb_hash_func() take more data (and expand qemu_xxhash7() to qemu_xxhash8()). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Edgar E. Iglesias Reviewed-by: Alistair Francis --- v1->v2: move the setting of the cluster index in cf_mask in tb_htable_lookup() up to before we set desc.cf_mask from it... --- include/exec/exec-all.h | 4 +++- accel/tcg/cpu-exec.c | 3 +++ accel/tcg/translate-all.c | 3 +++ 3 files changed, 9 insertions(+), 1 deletion(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 815e5b1e838..aa7b81aaf01 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -351,9 +351,11 @@ struct TranslationBlock { #define CF_USE_ICOUNT 0x00020000 #define CF_INVALID 0x00040000 /* TB is stale. Set with @jmp_lock held */ #define CF_PARALLEL 0x00080000 /* Generate code for a parallel context */ +#define CF_CLUSTER_MASK 0xff000000 /* Top 8 bits are cluster ID */ +#define CF_CLUSTER_SHIFT 24 /* cflags' mask for hashing/comparison */ #define CF_HASH_MASK \ - (CF_COUNT_MASK | CF_LAST_IO | CF_USE_ICOUNT | CF_PARALLEL) + (CF_COUNT_MASK | CF_LAST_IO | CF_USE_ICOUNT | CF_PARALLEL | CF_CLUSTER_MASK) /* Per-vCPU dynamic tracing state used to generate this TB */ uint32_t trace_vcpu_dstate; diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 870027d4359..6c4a33262f5 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -325,6 +325,9 @@ TranslationBlock *tb_htable_lookup(CPUState *cpu, target_ulong pc, struct tb_desc desc; uint32_t h; + cf_mask &= ~CF_CLUSTER_MASK; + cf_mask |= cpu->cluster_index << CF_CLUSTER_SHIFT; + desc.env = (CPUArchState *)cpu->env_ptr; desc.cs_base = cs_base; desc.flags = flags; diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 8cb8c8870e6..7364e8a071f 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -1688,6 +1688,9 @@ TranslationBlock *tb_gen_code(CPUState *cpu, cflags |= CF_NOCACHE | 1; } + cflags &= ~CF_CLUSTER_MASK; + cflags |= cpu->cluster_index << CF_CLUSTER_SHIFT; + buffer_overflow: tb = tb_alloc(pc); if (unlikely(!tb)) { From patchwork Mon Jan 21 15:22:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 10773985 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 93708746 for ; Mon, 21 Jan 2019 15:26:09 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8329F29C7A for ; Mon, 21 Jan 2019 15:26:09 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 76C7F2A123; Mon, 21 Jan 2019 15:26:09 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id CEA4729C7A for ; Mon, 21 Jan 2019 15:26:08 +0000 (UTC) Received: from localhost ([127.0.0.1]:55228 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1glbSi-0002fN-6M for patchwork-qemu-devel@patchwork.kernel.org; Mon, 21 Jan 2019 10:26:08 -0500 Received: from eggs.gnu.org ([209.51.188.92]:44529) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1glbPL-00080b-AD for qemu-devel@nongnu.org; Mon, 21 Jan 2019 10:22:40 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1glbPJ-0003w3-Cs for qemu-devel@nongnu.org; Mon, 21 Jan 2019 10:22:38 -0500 Received: from mail-wm1-x343.google.com ([2a00:1450:4864:20::343]:38948) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1glbPH-0003s6-5a for qemu-devel@nongnu.org; Mon, 21 Jan 2019 10:22:35 -0500 Received: by mail-wm1-x343.google.com with SMTP id y8so11136847wmi.4 for ; Mon, 21 Jan 2019 07:22:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=z6np4aEV6kepum56jAKTLhBF7tWQywONgDj9IEtWngY=; b=EgXS8CKCfBSjXbi0wQozZG6omguld7mMH7t3HaXqQ9K7h8aZACJMounSwi5WfGf63K 8sgtuF47yd6NvgPjn0USJZFHtb+cwDuZBDj4rMtOJqyuZwagJde1bQ7F97hUDSQKHBZj +UvoGRD/+iO2KxkDsCr+Atrd/KwS/N8N7GXNY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=z6np4aEV6kepum56jAKTLhBF7tWQywONgDj9IEtWngY=; b=OMtQSo03HZs9Y+Ed0oThYulGAEVwcs5pD/w3LEVDls6Wreb2Y8wvfgRdz8tsN1+6jN CfZYB038pRs4K024oO2qMYVwfChQKP2LYULmhvBZSqyNhX0dKH8LHkxTjl28JiWTgxhQ Fsp3ycFISKUGQbQmmSz5BP56ErRYKIHqz5j8/njYA6J8WBarw8JzXX6hWUByl8863CV/ A74rgmWTG/aQCAAI7rcm+4KQxCw87fEwCGYaCbEv9IemckKb59oRTW7z4kakplEE7FVq S/KOL7V/Htz3LHQ14bzOphtXeD0Mzq1IWxZ5t1j02w97fW3PkdU55fyUvrNZUpstoIzc Glow== X-Gm-Message-State: AJcUukc1kISR7v5lchNc+izfpzY/Y4Qm0f0jv3W7ivAS9aBiFlfR0v7m EygPkl8kwXGjWhFZZKR/HfBz+A== X-Google-Smtp-Source: ALg8bN7ZSsbK+d25xG3D3geoEqFgRFMM7PAw34qapn/0uei7llwGokS4LO0D4V2ATfUjjBvketcYrA== X-Received: by 2002:a1c:a00f:: with SMTP id j15mr24001656wme.84.1548084147814; Mon, 21 Jan 2019 07:22:27 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id o16sm128900134wrn.11.2019.01.21.07.22.26 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 21 Jan 2019 07:22:26 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Mon, 21 Jan 2019 15:22:18 +0000 Message-Id: <20190121152218.9592-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190121152218.9592-1-peter.maydell@linaro.org> References: <20190121152218.9592-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 Subject: [Qemu-devel] [PATCH v3 4/4] gdbstub: Simplify gdb_get_cpu_pid() to use cpu->cluster_index X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eduardo Habkost , Peter Crosthwaite , Alistair Francis , Richard Henderson , "Emilio G . Cota" , "Edgar E. Iglesias" , Paolo Bonzini , Aleksandar Markovic Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Now we're keeping the cluster index in the CPUState, we don't need to jump through hoops in gdb_get_cpu_pid() to find the associated cluster object. Signed-off-by: Peter Maydell Reviewed-by: Luc Michel Reviewed-by: Edgar E. Iglesias --- gdbstub.c | 48 +++++------------------------------------------- 1 file changed, 5 insertions(+), 43 deletions(-) diff --git a/gdbstub.c b/gdbstub.c index bfc7afb5096..5d6cbea9d35 100644 --- a/gdbstub.c +++ b/gdbstub.c @@ -644,50 +644,12 @@ static int memtox(char *buf, const char *mem, int len) static uint32_t gdb_get_cpu_pid(const GDBState *s, CPUState *cpu) { -#ifndef CONFIG_USER_ONLY - gchar *path, *name = NULL; - Object *obj; - CPUClusterState *cluster; - uint32_t ret; - - path = object_get_canonical_path(OBJECT(cpu)); - - if (path == NULL) { - /* Return the default process' PID */ - ret = s->processes[s->process_num - 1].pid; - goto out; - } - - name = object_get_canonical_path_component(OBJECT(cpu)); - assert(name != NULL); - - /* - * Retrieve the CPU parent path by removing the last '/' and the CPU name - * from the CPU canonical path. - */ - path[strlen(path) - strlen(name) - 1] = '\0'; - - obj = object_resolve_path_type(path, TYPE_CPU_CLUSTER, NULL); - - if (obj == NULL) { - /* Return the default process' PID */ - ret = s->processes[s->process_num - 1].pid; - goto out; - } - - cluster = CPU_CLUSTER(obj); - ret = cluster->cluster_id + 1; - -out: - g_free(name); - g_free(path); - - return ret; - -#else /* TODO: In user mode, we should use the task state PID */ - return s->processes[s->process_num - 1].pid; -#endif + if (cpu->cluster_index == UNASSIGNED_CLUSTER_INDEX) { + /* Return the default process' PID */ + return s->processes[s->process_num - 1].pid; + } + return cpu->cluster_index + 1; } static GDBProcess *gdb_get_process(const GDBState *s, uint32_t pid)