From patchwork Mon Nov 7 23:58:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13035544 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DF2AAC4332F for ; Tue, 8 Nov 2022 00:02:04 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1osC0r-0004BK-9Q; Mon, 07 Nov 2022 18:58:45 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1osC0p-0004B4-Sg for qemu-devel@nongnu.org; Mon, 07 Nov 2022 18:58:43 -0500 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1osC0d-00005u-C4 for qemu-devel@nongnu.org; Mon, 07 Nov 2022 18:58:43 -0500 Received: by mail-wr1-x42a.google.com with SMTP id bk15so18471251wrb.13 for ; Mon, 07 Nov 2022 15:58:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=NSxc66Fm/34b2nxJZ5QbpZSZKGj6yqN6NZyd5TCHUxQ=; b=dsC1oSDlOD15/529xDLe1V0yCa25ADRM3otJbXCKDueymzLfm/UhETNInmmmtGowk9 +YJi7T75vLxsZJR6nKmYCZgFWYbtL9utL6W9eJcB+xhdVlAjvfUdWxS9/Z79GeGDlA/F aJINZWyDbh6HoeoJ2Aegw69UWaZ+8PhB0DHTRni34/osGj8Dbp+C/GFnJSy/XjOI+2Ln nx5nh84wZxJhOsEi19i4bnAjbqE4rY4+3TQ7s8Ppartggbp0+VAe0359YP0BycCuRgbj 9fl5HQW3cHN5OjCzQXRcy7SxnOuPDLW+G4lAnHEQGPGgDZkJRP6Y0nrycvCaTTBg/+9G 1y7w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NSxc66Fm/34b2nxJZ5QbpZSZKGj6yqN6NZyd5TCHUxQ=; b=isaLw5wurrBTV0Dqvs3Cxm10JxElgntEAOXBI52ytwxnVov+xm6dCY4UaoV7ck3ttN 4YiH1zi8xe+EIWUbkEzPpkYDZbaau5DyY4SuPPRz3KQE8le3TFThCndEmSYc3SH5YgN1 fkLUs16YNn6D9HnP8nyo3gVh5MLXMNCn7cLQ5nHchK5fV+6fwoto/b3GS+fW5HxUHUHB sg0Qu0g2rU0w0UxbwQrxzS/Vorhcon+uuGgTk+uPYYhxLi1nrduYBG/GIifzU+zRpU5x pjwvzhniQuICrs+P5A89HRRAQw6o4FqfXrGaYn4AsexP3GgaYYLSooovr1lEN9cwM0n5 ttzQ== X-Gm-Message-State: ACrzQf0kLDOt2YHTErmFSx4GPGArO4ZaVKwjrnv7hkQRc+FJ4F5ux7iP ftb+R5idU1TsKi/pgMquBMAtO6wy+V0SRg== X-Google-Smtp-Source: AMsMyM679MsX2Ddk79Mmv57AYEyft46IMz5ly/hKtfCa1AXNo8TrdWBhQNd674Zxo+wZxXFCH4olXw== X-Received: by 2002:adf:d4d2:0:b0:236:594f:4a2c with SMTP id w18-20020adfd4d2000000b00236594f4a2cmr32728960wrk.705.1667865508886; Mon, 07 Nov 2022 15:58:28 -0800 (PST) Received: from localhost.localdomain ([185.126.107.38]) by smtp.gmail.com with ESMTPSA id l27-20020a05600c1d1b00b003b95ed78275sm10101767wms.20.2022.11.07.15.58.28 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 07 Nov 2022 15:58:28 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Aurelien Jarno , Aleksandar Rikalo , Jiaxun Yang , Richard Henderson Subject: [PULL 01/14] target/mips: Set CP0St_{KX, SX, UX} for Loongson-2F Date: Tue, 8 Nov 2022 00:58:09 +0100 Message-Id: <20221107235822.71458-2-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221107235822.71458-1-philmd@linaro.org> References: <20221107235822.71458-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=philmd@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Jiaxun Yang As per an unpublished document, in later reversion of chips CP0St_{KX, SX, UX} is not writeable and hardcoded to 1. Without those bits set, kernel is unable to access XKPHYS address segment. So just set them up on CPU reset. Signed-off-by: Jiaxun Yang Acked-by: Richard Henderson Message-Id: <20221031132531.18122-2-jiaxun.yang@flygoat.com> Signed-off-by: Philippe Mathieu-Daudé --- target/mips/cpu.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/mips/cpu.c b/target/mips/cpu.c index e997c1b9cb..7a565466cb 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -302,6 +302,12 @@ static void mips_cpu_reset(DeviceState *dev) env->CP0_EntryHi_ASID_mask = (env->CP0_Config5 & (1 << CP0C5_MI)) ? 0x0 : (env->CP0_Config4 & (1 << CP0C4_AE)) ? 0x3ff : 0xff; env->CP0_Status = (1 << CP0St_BEV) | (1 << CP0St_ERL); + if (env->insn_flags & INSN_LOONGSON2F) { + /* Loongson-2F has those bits hardcoded to 1 */ + env->CP0_Status |= (1 << CP0St_KX) | (1 << CP0St_SX) | + (1 << CP0St_UX); + } + /* * Vectored interrupts not implemented, timer on int 7, * no performance counters. From patchwork Mon Nov 7 23:58:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13035508 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B8BCEC4332F for ; Mon, 7 Nov 2022 23:59:23 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1osC0k-00047J-MC; Mon, 07 Nov 2022 18:58:38 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1osC0j-000476-Dd for qemu-devel@nongnu.org; Mon, 07 Nov 2022 18:58:37 -0500 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1osC0h-0000TM-R9 for qemu-devel@nongnu.org; Mon, 07 Nov 2022 18:58:37 -0500 Received: by mail-wm1-x32b.google.com with SMTP id i5-20020a1c3b05000000b003cfa97c05cdso23329wma.4 for ; Mon, 07 Nov 2022 15:58:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=wqdXWOgF+QqRi3UtOQa5YNqdO+ylycMo+xdPULOGfzw=; b=aoeAt2eMTMja+2VjIMLDVi7a5CKWaAATS7ECeWBJ850iYPMFXzP+eVK0oGQisRblmz 0B392hght6sXes1Zz5NshVBlDUTSQ5QHHiAQVyOR/JrfaYJyguilQ6fyvWIc1gLCZ9wA x/WBisxPCIi0nWtlRsdt4RDpH7S/Zho9wDjWdwuegr7YrxNC0CFlaTFZCRFkMbvBMjgt PDt2jr2fL9gvHCbeN+Viwvqo0d2bszQkoCjUlAEjRaFyXwsL+XqQ/TdhpEn53kIn8n7q lskDxguLs/veqhIv+W9y2YbeRT6jl9H8H9JUn8518oaYC5A8oQy5IhTJ0t00NMehPpxy f17Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wqdXWOgF+QqRi3UtOQa5YNqdO+ylycMo+xdPULOGfzw=; b=gEVh6SVLQkOKwg90uMVIP0DoDY46n0+AgEYqDVJeBdSlp+3LXq64MAloVsOmRD6g3N RCh24IDE4sBSCElDCUhz6ExPdUS+Cwf5YwsdKSW8EgPZ1k8TXK1fDp/yuXwvGxmjMqQp jpP4A2mW0L6qhLIMgR1EDzPGLSqqHywSrlhGfOAeDXDURmqIylOAJHZXHZ2WNnfmQmWl ogK7ZRjbHqgjvI/C3YeCWBCNva8/V2ndyfH9ULEylQEQl81TIGGTv9aSuttIFlIwpS1y kfB9nC1o9d7qbhpHpzpqfo7sOcgWeXDn6MbcedIz9AmLCoA/q2q9/pfcWFAC4Y3Pwd71 iRbA== X-Gm-Message-State: ACrzQf1wQ49LvAJSufbIh8iN9j9+rqBnsTFQTRrkojHDfPuDgNdS53yf 2NDB26E+a+0yyjwuYM3SZf+YH2AyrjZNpw== X-Google-Smtp-Source: AMsMyM7/T7kRcPkLlbwXKD4jbzB51WaZq95ub4t/C3hyGVQ0bxJCcZk8iFp98lZpvqzC2FdXe9r2fg== X-Received: by 2002:a05:600c:1994:b0:3cf:7c1e:8227 with SMTP id t20-20020a05600c199400b003cf7c1e8227mr25441066wmq.103.1667865513965; Mon, 07 Nov 2022 15:58:33 -0800 (PST) Received: from localhost.localdomain ([185.126.107.38]) by smtp.gmail.com with ESMTPSA id m21-20020a7bca55000000b003c6c182bef9sm15153410wml.36.2022.11.07.15.58.33 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 07 Nov 2022 15:58:33 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Aurelien Jarno , Aleksandar Rikalo , Jiaxun Yang , Richard Henderson , Pavel Dovgalyuk Subject: [PULL 02/14] target/mips: Cast offset field of Octeon BBIT to int16_t Date: Tue, 8 Nov 2022 00:58:10 +0100 Message-Id: <20221107235822.71458-3-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221107235822.71458-1-philmd@linaro.org> References: <20221107235822.71458-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=philmd@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Jiaxun Yang As per "Cavium Networks OCTEON Plus CN50XX Hardware Reference Manual" offset field is signed 16 bit value. However arg_BBIT.offset is unsigned. We need to cast it as signed to do address calculation. Signed-off-by: Jiaxun Yang Acked-by: Richard Henderson Acked-by: Pavel Dovgalyuk Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20221031132531.18122-3-jiaxun.yang@flygoat.com> Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/octeon.decode | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/mips/tcg/octeon.decode b/target/mips/tcg/octeon.decode index 8929ad088e..0c787cb498 100644 --- a/target/mips/tcg/octeon.decode +++ b/target/mips/tcg/octeon.decode @@ -12,7 +12,7 @@ # BBIT132 111110 ..... ..... ................ %bbit_p 28:1 16:5 -BBIT 11 set:1 . 10 rs:5 ..... offset:16 p=%bbit_p +BBIT 11 set:1 . 10 rs:5 ..... offset:s16 p=%bbit_p # Arithmetic # BADDU rd, rs, rt From patchwork Mon Nov 7 23:58:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13035513 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9B66AC433FE for ; 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Mon, 07 Nov 2022 15:58:38 -0800 (PST) Received: from localhost.localdomain ([185.126.107.38]) by smtp.gmail.com with ESMTPSA id g12-20020adffc8c000000b0022cd96b3ba6sm9826641wrr.90.2022.11.07.15.58.37 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 07 Nov 2022 15:58:38 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Aurelien Jarno , Aleksandar Rikalo , Jiaxun Yang , Pavel Dovgalyuk , Pavel Dovgalyuk Subject: [PULL 03/14] target/mips: Enable LBX/LWX/* instructions for Octeon Date: Tue, 8 Nov 2022 00:58:11 +0100 Message-Id: <20221107235822.71458-4-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221107235822.71458-1-philmd@linaro.org> References: <20221107235822.71458-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=philmd@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Pavel Dovgalyuk This patch changes condition and function name for enabling indexed load instructions for Octeon vCPUs. Octeons do not have DSP extension, but implement LBX-and-others. Signed-off-by: Pavel Dovgalyuk Reviewed-by: Philippe Mathieu-Daudé Message-Id: <166728058455.229236.13834649461181619195.stgit@pasha-ThinkPad-X280> Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/translate.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 2f2d707a12..4c4bd0823d 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -12173,12 +12173,16 @@ enum { #include "nanomips_translate.c.inc" /* MIPSDSP functions. */ -static void gen_mipsdsp_ld(DisasContext *ctx, uint32_t opc, - int rd, int base, int offset) + +/* Indexed load is not for DSP only */ +static void gen_mips_lx(DisasContext *ctx, uint32_t opc, + int rd, int base, int offset) { TCGv t0; - check_dsp(ctx); + if (!(ctx->insn_flags & INSN_OCTEON)) { + check_dsp(ctx); + } t0 = tcg_temp_new(); if (base == 0) { @@ -14523,7 +14527,7 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx) case OPC_LBUX: case OPC_LHX: case OPC_LWX: - gen_mipsdsp_ld(ctx, op2, rd, rs, rt); + gen_mips_lx(ctx, op2, rd, rs, rt); break; default: /* Invalid */ MIPS_INVAL("MASK LX"); From patchwork Mon Nov 7 23:58:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13035549 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2E508C4332F for ; Tue, 8 Nov 2022 00:03:20 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1osC0v-0004EK-EW; Mon, 07 Nov 2022 18:58:49 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1osC0u-0004EC-Qs for qemu-devel@nongnu.org; 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Mon, 07 Nov 2022 15:58:43 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Aurelien Jarno , Aleksandar Rikalo , Jiaxun Yang , Richard Henderson , Pavel Dovgalyuk Subject: [PULL 04/14] target/mips: Disable DSP ASE for Octeon68XX Date: Tue, 8 Nov 2022 00:58:12 +0100 Message-Id: <20221107235822.71458-5-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221107235822.71458-1-philmd@linaro.org> References: <20221107235822.71458-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=philmd@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Jiaxun Yang I don't have access to Octeon68XX hardware but according to my investigation Octeon never had DSP ASE support. As per "Cavium Networks OCTEON Plus CN50XX Hardware Reference Manual" CP0C3_DSPP is reserved bit and read as 0. Also I do have access to a Ubiquiti Edgerouter 4 which has Octeon CN7130 processor and I can confirm CP0C3_DSPP is read as 0 on that processor. Further more, in linux kernel: arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h cpu_has_dsp is overridden as 0. So I believe we shouldn't emulate DSP in QEMU as well. Signed-off-by: Jiaxun Yang Acked-by: Richard Henderson Reviewed-by: Pavel Dovgalyuk Message-Id: <20221031132531.18122-4-jiaxun.yang@flygoat.com> Signed-off-by: Philippe Mathieu-Daudé --- target/mips/cpu-defs.c.inc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc index 7f53c94ec8..480e60aeec 100644 --- a/target/mips/cpu-defs.c.inc +++ b/target/mips/cpu-defs.c.inc @@ -934,7 +934,7 @@ const mips_def_t mips_defs[] = (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) | (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), .CP0_Config2 = MIPS_CONFIG2, - .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA) | (1 << CP0C3_DSPP) , + .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA), .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (0x3c << CP0C4_KScrExist) | (1U << CP0C4_MMUExtDef) | (3U << CP0C4_MMUSizeExt), @@ -946,7 +946,7 @@ const mips_def_t mips_defs[] = .CP0_Status_rw_bitmask = 0x12F8FFFF, .SEGBITS = 42, .PABITS = 49, - .insn_flags = CPU_MIPS64R2 | INSN_OCTEON | ASE_DSP, + .insn_flags = CPU_MIPS64R2 | INSN_OCTEON, .mmu_type = MMU_TYPE_R4000, }, From patchwork Mon Nov 7 23:58:13 2022 Content-Type: text/plain; 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Mon, 07 Nov 2022 15:58:48 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Aurelien Jarno , Aleksandar Rikalo , Jiaxun Yang Subject: [PULL 05/14] target/mips: Don't check COP1X for 64 bit FP mode Date: Tue, 8 Nov 2022 00:58:13 +0100 Message-Id: <20221107235822.71458-6-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221107235822.71458-1-philmd@linaro.org> References: <20221107235822.71458-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=philmd@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Jiaxun Yang Some implementations (i.e. Loongson-2F) may decide to implement a 64 bit FPU without implementing COP1X instructions. As the eligibility of 64 bit FP instructions is already determined by CP0St_FR, there is no need to check for COP1X again. Signed-off-by: Jiaxun Yang Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20221102165719.190378-1-jiaxun.yang@flygoat.com> [PMD: Add missing trailing parenthesis (buildfix)] Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 4c4bd0823d..624e6b7786 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -1545,7 +1545,7 @@ void check_cop1x(DisasContext *ctx) */ void check_cp1_64bitmode(DisasContext *ctx) { - if (unlikely(~ctx->hflags & (MIPS_HFLAG_F64 | MIPS_HFLAG_COP1X))) { + if (unlikely(~ctx->hflags & MIPS_HFLAG_F64)) { gen_reserved_instruction(ctx); } } From patchwork Mon Nov 7 23:58:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13035512 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4A7D0C433FE for ; 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Mon, 07 Nov 2022 15:58:53 -0800 (PST) Received: from localhost.localdomain ([185.126.107.38]) by smtp.gmail.com with ESMTPSA id iv9-20020a05600c548900b003cf87623c16sm14389624wmb.4.2022.11.07.15.58.52 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 07 Nov 2022 15:58:53 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Aurelien Jarno , Aleksandar Rikalo , Jiaxun Yang , Stefan Weil Subject: [PULL 06/14] disas/nanomips: Fix invalid PRId64 format calling img_format() Date: Tue, 8 Nov 2022 00:58:14 +0100 Message-Id: <20221107235822.71458-7-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221107235822.71458-1-philmd@linaro.org> References: <20221107235822.71458-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=philmd@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Fix warnings such: disas/nanomips.c:3251:64: warning: format specifies type 'char *' but the argument has type 'int64' (aka 'long long') [-Wformat] return img_format("CACHE 0x%" PRIx64 ", %s(%s)", op_value, s_value, rs); ~~ ^~~~~~~ %lld To avoid crashes such (kernel from commit f375ad6a0d): $ qemu-system-mipsel -cpu I7200 -d in_asm -kernel generic_nano32r6el_page4k ... ---------------- IN: __bzero 0x805c6084: 20c4 6950 ADDU r13, a0, a2 0x805c6088: 9089 ADDIU a0, 1 Process 70261 stopped * thread #6, stop reason = EXC_BAD_ACCESS (code=1, address=0xfffffffffffffff0) frame #0: 0x00000001bfe38864 libsystem_platform.dylib`_platform_strlen + 4 libsystem_platform.dylib`: -> 0x1bfe38864 <+4>: ldr q0, [x1] 0x1bfe38868 <+8>: adr x3, #-0xc8 ; ___lldb_unnamed_symbol314 0x1bfe3886c <+12>: ldr q2, [x3], #0x10 0x1bfe38870 <+16>: and x2, x0, #0xf Target 0: (qemu-system-mipsel) stopped. (lldb) bt * thread #6, stop reason = EXC_BAD_ACCESS (code=1, address=0xfffffffffffffff0) * frame #0: 0x00000001bfe38864 libsystem_platform.dylib`_platform_strlen + 4 frame #1: 0x00000001bfce76a0 libsystem_c.dylib`__vfprintf + 4544 frame #2: 0x00000001bfd158b4 libsystem_c.dylib`_vasprintf + 280 frame #3: 0x0000000101c22fb0 libglib-2.0.0.dylib`g_vasprintf + 28 frame #4: 0x0000000101bfb7d8 libglib-2.0.0.dylib`g_strdup_vprintf + 32 frame #5: 0x000000010000fb70 qemu-system-mipsel`img_format(format=) at nanomips.c:103:14 [opt] frame #6: 0x0000000100018868 qemu-system-mipsel`SB_S9_(instruction=, info=) at nanomips.c:12616:12 [opt] frame #7: 0x000000010000f90c qemu-system-mipsel`print_insn_nanomips at nanomips.c:589:28 [opt] Fixes: 4066c152b3 ("disas/nanomips: Remove IMMEDIATE functions") Reported-by: Stefan Weil Reviewed-by: Stefan Weil Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20221101114458.25756-2-philmd@linaro.org> --- disas/nanomips.c | 35 ++++++++++++++++++++--------------- 1 file changed, 20 insertions(+), 15 deletions(-) diff --git a/disas/nanomips.c b/disas/nanomips.c index 9647f1a8e3..6466c80dc5 100644 --- a/disas/nanomips.c +++ b/disas/nanomips.c @@ -3252,7 +3252,8 @@ static char *CACHE(uint64 instruction, Dis_info *info) const char *rs = GPR(rs_value, info); - return img_format("CACHE 0x%" PRIx64 ", %s(%s)", op_value, s_value, rs); + return img_format("CACHE 0x%" PRIx64 ", %" PRId64 "(%s)", + op_value, s_value, rs); } @@ -3274,7 +3275,8 @@ static char *CACHEE(uint64 instruction, Dis_info *info) const char *rs = GPR(rs_value, info); - return img_format("CACHEE 0x%" PRIx64 ", %s(%s)", op_value, s_value, rs); + return img_format("CACHEE 0x%" PRIx64 ", %" PRId64 "(%s)", + op_value, s_value, rs); } @@ -5173,7 +5175,7 @@ static char *DADDIU_48_(uint64 instruction, Dis_info *info) const char *rt = GPR(rt_value, info); - return img_format("DADDIU %s, %s", rt, s_value); + return img_format("DADDIU %s, %" PRId64, rt, s_value); } @@ -11859,7 +11861,7 @@ static char *PREF_S9_(uint64 instruction, Dis_info *info) const char *rs = GPR(rs_value, info); - return img_format("PREF 0x%" PRIx64 ", %s(%s)", + return img_format("PREF 0x%" PRIx64 ", %" PRId64 "(%s)", hint_value, s_value, rs); } @@ -11905,7 +11907,8 @@ static char *PREFE(uint64 instruction, Dis_info *info) const char *rs = GPR(rs_value, info); - return img_format("PREFE 0x%" PRIx64 ", %s(%s)", hint_value, s_value, rs); + return img_format("PREFE 0x%" PRIx64 ", %" PRId64 "(%s)", + hint_value, s_value, rs); } @@ -12079,7 +12082,7 @@ static char *REPL_PH(uint64 instruction, Dis_info *info) const char *rt = GPR(rt_value, info); - return img_format("REPL.PH %s, %s", rt, s_value); + return img_format("REPL.PH %s, %" PRId64, rt, s_value); } @@ -12613,7 +12616,7 @@ static char *SB_S9_(uint64 instruction, Dis_info *info) const char *rt = GPR(rt_value, info); const char *rs = GPR(rs_value, info); - return img_format("SB %s, %s(%s)", rt, s_value, rs); + return img_format("SB %s, %" PRId64 "(%s)", rt, s_value, rs); } @@ -12659,7 +12662,7 @@ static char *SBE(uint64 instruction, Dis_info *info) const char *rt = GPR(rt_value, info); const char *rs = GPR(rs_value, info); - return img_format("SBE %s, %s(%s)", rt, s_value, rs); + return img_format("SBE %s, %" PRId64 "(%s)", rt, s_value, rs); } @@ -12706,7 +12709,7 @@ static char *SC(uint64 instruction, Dis_info *info) const char *rt = GPR(rt_value, info); const char *rs = GPR(rs_value, info); - return img_format("SC %s, %s(%s)", rt, s_value, rs); + return img_format("SC %s, %" PRId64 "(%s)", rt, s_value, rs); } @@ -12729,7 +12732,7 @@ static char *SCD(uint64 instruction, Dis_info *info) const char *rt = GPR(rt_value, info); const char *rs = GPR(rs_value, info); - return img_format("SCD %s, %s(%s)", rt, s_value, rs); + return img_format("SCD %s, %" PRId64 "(%s)", rt, s_value, rs); } @@ -12776,7 +12779,7 @@ static char *SCE(uint64 instruction, Dis_info *info) const char *rt = GPR(rt_value, info); const char *rs = GPR(rs_value, info); - return img_format("SCE %s, %s(%s)", rt, s_value, rs); + return img_format("SCE %s, %" PRId64 "(%s)", rt, s_value, rs); } @@ -12868,7 +12871,7 @@ static char *SD_S9_(uint64 instruction, Dis_info *info) const char *rt = GPR(rt_value, info); const char *rs = GPR(rs_value, info); - return img_format("SD %s, %s(%s)", rt, s_value, rs); + return img_format("SD %s, %" PRId64 "(%s)", rt, s_value, rs); } @@ -12973,7 +12976,7 @@ static char *SDC1_S9_(uint64 instruction, Dis_info *info) const char *ft = FPR(ft_value, info); const char *rs = GPR(rs_value, info); - return img_format("SDC1 %s, %s(%s)", ft, s_value, rs); + return img_format("SDC1 %s, %" PRId64 "(%s)", ft, s_value, rs); } @@ -13066,7 +13069,8 @@ static char *SDC2(uint64 instruction, Dis_info *info) const char *rs = GPR(rs_value, info); - return img_format("SDC2 CP%" PRIu64 ", %s(%s)", cs_value, s_value, rs); + return img_format("SDC2 CP%" PRIu64 ", %" PRId64 "(%s)", + cs_value, s_value, rs); } @@ -13091,7 +13095,8 @@ static char *SDM(uint64 instruction, Dis_info *info) const char *rs = GPR(rs_value, info); uint64 count3 = encode_count3_from_count(count3_value); - return img_format("SDM %s, %s(%s), 0x%" PRIx64, rt, s_value, rs, count3); + return img_format("SDM %s, %" PRId64 "(%s), 0x%" PRIx64, + rt, s_value, rs, count3); } From patchwork Mon Nov 7 23:58:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13035509 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1B534C433FE for ; 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Mon, 07 Nov 2022 15:58:58 -0800 (PST) Received: from localhost.localdomain ([185.126.107.38]) by smtp.gmail.com with ESMTPSA id bk8-20020a0560001d8800b002366e3f1497sm8731873wrb.6.2022.11.07.15.58.57 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 07 Nov 2022 15:58:58 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Aurelien Jarno , Aleksandar Rikalo , Jiaxun Yang , Stefan Weil Subject: [PULL 07/14] disas/nanomips: Fix invalid PRIx64 format calling img_format() Date: Tue, 8 Nov 2022 00:58:15 +0100 Message-Id: <20221107235822.71458-8-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221107235822.71458-1-philmd@linaro.org> References: <20221107235822.71458-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=philmd@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Fix: disas/nanomips.c:12231:62: warning: format specifies type 'char *' but the argument has type 'uint64' (aka 'unsigned long long') [-Wformat] return img_format("RESTOREF 0x%" PRIx64 ", %s", u_value, count_value); ~~ ^~~~~~~~~~~ %llu Fixes: 4066c152b3 ("disas/nanomips: Remove IMMEDIATE functions") Reported-by: Stefan Weil Reviewed-by: Stefan Weil Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20221101114458.25756-3-philmd@linaro.org> --- disas/nanomips.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/disas/nanomips.c b/disas/nanomips.c index 6466c80dc5..e4b21e7c45 100644 --- a/disas/nanomips.c +++ b/disas/nanomips.c @@ -12235,7 +12235,8 @@ static char *RESTOREF(uint64 instruction, Dis_info *info) uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3__s3(instruction); - return img_format("RESTOREF 0x%" PRIx64 ", %s", u_value, count_value); + return img_format("RESTOREF 0x%" PRIx64 ", 0x%" PRIx64, + u_value, count_value); } From patchwork Mon Nov 7 23:58:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13035514 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C4341C4332F for ; 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Mon, 07 Nov 2022 15:59:03 -0800 (PST) Received: from localhost.localdomain ([185.126.107.38]) by smtp.gmail.com with ESMTPSA id j5-20020adfe505000000b0023c8026841csm8730142wrm.23.2022.11.07.15.59.02 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 07 Nov 2022 15:59:03 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Aurelien Jarno , Aleksandar Rikalo , Jiaxun Yang , Stefan Weil Subject: [PULL 08/14] disas/nanomips: Use G_GNUC_PRINTF to avoid invalid string formats Date: Tue, 8 Nov 2022 00:58:16 +0100 Message-Id: <20221107235822.71458-9-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221107235822.71458-1-philmd@linaro.org> References: <20221107235822.71458-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=philmd@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Suggested-by: Stefan Weil Reviewed-by: Stefan Weil Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20221101114458.25756-4-philmd@linaro.org> --- disas/nanomips.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/disas/nanomips.c b/disas/nanomips.c index e4b21e7c45..3f45447292 100644 --- a/disas/nanomips.c +++ b/disas/nanomips.c @@ -95,7 +95,7 @@ typedef struct Pool { #define IMGASSERTONCE(test) -static char *img_format(const char *format, ...) +static char * G_GNUC_PRINTF(1, 2) img_format(const char *format, ...) { char *buffer; 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Mon, 07 Nov 2022 15:59:08 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Aurelien Jarno , Aleksandar Rikalo , Jiaxun Yang , Stefan Weil Subject: [PULL 09/14] disas/nanomips: Remove headers already included by "qemu/osdep.h" Date: Tue, 8 Nov 2022 00:58:17 +0100 Message-Id: <20221107235822.71458-10-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221107235822.71458-1-philmd@linaro.org> References: <20221107235822.71458-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=philmd@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Reviewed-by: Stefan Weil Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20221101114458.25756-5-philmd@linaro.org> --- disas/nanomips.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/disas/nanomips.c b/disas/nanomips.c index 3f45447292..821d4f8832 100644 --- a/disas/nanomips.c +++ b/disas/nanomips.c @@ -30,10 +30,6 @@ #include "qemu/osdep.h" #include "disas/dis-asm.h" -#include -#include -#include - typedef int64_t int64; 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Mon, 07 Nov 2022 15:59:12 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Aurelien Jarno , Aleksandar Rikalo , Jiaxun Yang , Richard Henderson Subject: [PULL 10/14] disas/nanomips: Move setjmp into nanomips_dis Date: Tue, 8 Nov 2022 00:58:18 +0100 Message-Id: <20221107235822.71458-11-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221107235822.71458-1-philmd@linaro.org> References: <20221107235822.71458-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=philmd@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Richard Henderson Reduce the number of local variables within the scope of the setjmp by moving it to the existing helper. The actual length returned from Disassemble is not used, because we have already determined the length while reading bytes. Fixes: nanomips.c: In function ‘print_insn_nanomips’: nanomips.c:21925:14: error: variable ‘insn1’ might be clobbered by ‘longjmp’ or ‘vfork’ [-Werror=clobbered] nanomips.c:21925:25: error: variable ‘insn2’ might be clobbered by ‘longjmp’ or ‘vfork’ [-Werror=clobbered] nanomips.c:21925:36: error: variable ‘insn3’ might be clobbered by ‘longjmp’ or ‘vfork’ [-Werror=clobbered] nanomips.c:21926:22: error: variable ‘buf’ might be clobbered by ‘longjmp’ or ‘vfork’ [-Werror=clobbered] Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson Message-Id: <20221106212852.152384-2-richard.henderson@linaro.org> --- disas/nanomips.c | 42 +++++++++++++++++------------------------- 1 file changed, 17 insertions(+), 25 deletions(-) diff --git a/disas/nanomips.c b/disas/nanomips.c index 821d4f8832..83a39a878c 100644 --- a/disas/nanomips.c +++ b/disas/nanomips.c @@ -21907,22 +21907,24 @@ static const Pool MAJOR[2] = { 0x0 }, /* P16 */ }; -static int nanomips_dis(char **buf, - Dis_info *info, - unsigned short one, - unsigned short two, - unsigned short three) +static bool nanomips_dis(char **buf, Dis_info *info, + unsigned short one, + unsigned short two, + unsigned short three) { uint16 bits[3] = {one, two, three}; - TABLE_ENTRY_TYPE type; - int size = Disassemble(bits, buf, &type, MAJOR, 2, info); - return size; + + /* Handle runtime errors. */ + if (unlikely(sigsetjmp(info->buf, 0) != 0)) { + return false; + } + return Disassemble(bits, buf, &type, MAJOR, ARRAY_SIZE(MAJOR), info) >= 0; } int print_insn_nanomips(bfd_vma memaddr, struct disassemble_info *info) { - int status; + int status, length; bfd_byte buffer[2]; uint16_t insn1 = 0, insn2 = 0, insn3 = 0; g_autofree char *buf = NULL; @@ -21952,6 +21954,7 @@ int print_insn_nanomips(bfd_vma memaddr, struct disassemble_info *info) } else { insn1 = bfd_getl16(buffer); } + length = 2; (*info->fprintf_func)(info->stream, "%04x ", insn1); /* Handle 32-bit opcodes. */ @@ -21967,6 +21970,7 @@ int print_insn_nanomips(bfd_vma memaddr, struct disassemble_info *info) } else { insn2 = bfd_getl16(buffer); } + length = 4; (*info->fprintf_func)(info->stream, "%04x ", insn2); } else { (*info->fprintf_func)(info->stream, " "); @@ -21984,27 +21988,15 @@ int print_insn_nanomips(bfd_vma memaddr, struct disassemble_info *info) } else { insn3 = bfd_getl16(buffer); } + length = 6; (*info->fprintf_func)(info->stream, "%04x ", insn3); } else { (*info->fprintf_func)(info->stream, " "); } - /* Handle runtime errors. */ - if (sigsetjmp(disassm_info.buf, 0) != 0) { - info->insn_type = dis_noninsn; - return insn3 ? 6 : insn2 ? 4 : 2; + if (nanomips_dis(&buf, &disassm_info, insn1, insn2, insn3)) { + (*info->fprintf_func) (info->stream, "%s", buf); } - int length = nanomips_dis(&buf, &disassm_info, insn1, insn2, insn3); - - /* FIXME: Should probably use a hash table on the major opcode here. */ - - (*info->fprintf_func) (info->stream, "%s", buf); - if (length > 0) { - return length / 8; - } - - info->insn_type = dis_noninsn; - - return insn3 ? 6 : insn2 ? 4 : 2; + return length; } From patchwork Mon Nov 7 23:58:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13035511 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 08111C4332F for ; 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Mon, 07 Nov 2022 15:59:18 -0800 (PST) Received: from localhost.localdomain ([185.126.107.38]) by smtp.gmail.com with ESMTPSA id r8-20020a05600c320800b003b4935f04a4sm10990386wmp.5.2022.11.07.15.59.17 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 07 Nov 2022 15:59:17 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Aurelien Jarno , Aleksandar Rikalo , Jiaxun Yang , Richard Henderson Subject: [PULL 11/14] disas/nanomips: Merge insn{1,2,3} into words[3] Date: Tue, 8 Nov 2022 00:58:19 +0100 Message-Id: <20221107235822.71458-12-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221107235822.71458-1-philmd@linaro.org> References: <20221107235822.71458-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=philmd@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Richard Henderson Since Disassemble wants the data in this format, collect it that way. This allows using a loop to print the bytes. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson Message-Id: <20221106212852.152384-3-richard.henderson@linaro.org> --- disas/nanomips.c | 44 +++++++++++++++++++++----------------------- 1 file changed, 21 insertions(+), 23 deletions(-) diff --git a/disas/nanomips.c b/disas/nanomips.c index 83a39a878c..e462256760 100644 --- a/disas/nanomips.c +++ b/disas/nanomips.c @@ -21907,26 +21907,22 @@ static const Pool MAJOR[2] = { 0x0 }, /* P16 */ }; -static bool nanomips_dis(char **buf, Dis_info *info, - unsigned short one, - unsigned short two, - unsigned short three) +static bool nanomips_dis(const uint16_t *data, char **buf, Dis_info *info) { - uint16 bits[3] = {one, two, three}; TABLE_ENTRY_TYPE type; /* Handle runtime errors. */ if (unlikely(sigsetjmp(info->buf, 0) != 0)) { return false; } - return Disassemble(bits, buf, &type, MAJOR, ARRAY_SIZE(MAJOR), info) >= 0; + return Disassemble(data, buf, &type, MAJOR, ARRAY_SIZE(MAJOR), info) >= 0; } int print_insn_nanomips(bfd_vma memaddr, struct disassemble_info *info) { int status, length; bfd_byte buffer[2]; - uint16_t insn1 = 0, insn2 = 0, insn3 = 0; + uint16_t words[3] = { }; g_autofree char *buf = NULL; info->bytes_per_chunk = 2; @@ -21950,15 +21946,14 @@ int print_insn_nanomips(bfd_vma memaddr, struct disassemble_info *info) } if (info->endian == BFD_ENDIAN_BIG) { - insn1 = bfd_getb16(buffer); + words[0] = bfd_getb16(buffer); } else { - insn1 = bfd_getl16(buffer); + words[0] = bfd_getl16(buffer); } length = 2; - (*info->fprintf_func)(info->stream, "%04x ", insn1); /* Handle 32-bit opcodes. */ - if ((insn1 & 0x1000) == 0) { + if ((words[0] & 0x1000) == 0) { status = (*info->read_memory_func)(memaddr + 2, buffer, 2, info); if (status != 0) { (*info->memory_error_func)(status, memaddr + 2, info); @@ -21966,17 +21961,15 @@ int print_insn_nanomips(bfd_vma memaddr, struct disassemble_info *info) } if (info->endian == BFD_ENDIAN_BIG) { - insn2 = bfd_getb16(buffer); + words[1] = bfd_getb16(buffer); } else { - insn2 = bfd_getl16(buffer); + words[1] = bfd_getl16(buffer); } length = 4; - (*info->fprintf_func)(info->stream, "%04x ", insn2); - } else { - (*info->fprintf_func)(info->stream, " "); } + /* Handle 48-bit opcodes. */ - if ((insn1 >> 10) == 0x18) { + if ((words[0] >> 10) == 0x18) { status = (*info->read_memory_func)(memaddr + 4, buffer, 2, info); if (status != 0) { (*info->memory_error_func)(status, memaddr + 4, info); @@ -21984,17 +21977,22 @@ int print_insn_nanomips(bfd_vma memaddr, struct disassemble_info *info) } if (info->endian == BFD_ENDIAN_BIG) { - insn3 = bfd_getb16(buffer); + words[2] = bfd_getb16(buffer); } else { - insn3 = bfd_getl16(buffer); + words[2] = bfd_getl16(buffer); } length = 6; - (*info->fprintf_func)(info->stream, "%04x ", insn3); - } else { - (*info->fprintf_func)(info->stream, " "); } - if (nanomips_dis(&buf, &disassm_info, insn1, insn2, insn3)) { + for (int i = 0; i < ARRAY_SIZE(words); i++) { + if (i * 2 < length) { + (*info->fprintf_func)(info->stream, "%04x ", words[i]); + } else { + (*info->fprintf_func)(info->stream, " "); + } + } + + if (nanomips_dis(words, &buf, &disassm_info)) { (*info->fprintf_func) (info->stream, "%s", buf); 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Mon, 07 Nov 2022 15:59:22 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Aurelien Jarno , Aleksandar Rikalo , Jiaxun Yang , Richard Henderson Subject: [PULL 12/14] disas/nanomips: Split out read_u16 Date: Tue, 8 Nov 2022 00:58:20 +0100 Message-Id: <20221107235822.71458-13-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221107235822.71458-1-philmd@linaro.org> References: <20221107235822.71458-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=philmd@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Richard Henderson Split out a helper function for reading a uint16_t with the correct endianness. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20221106023735.5277-4-richard.henderson@linaro.org> --- disas/nanomips.c | 48 +++++++++++++++++++----------------------------- 1 file changed, 19 insertions(+), 29 deletions(-) diff --git a/disas/nanomips.c b/disas/nanomips.c index e462256760..3b998118e3 100644 --- a/disas/nanomips.c +++ b/disas/nanomips.c @@ -21918,10 +21918,24 @@ static bool nanomips_dis(const uint16_t *data, char **buf, Dis_info *info) return Disassemble(data, buf, &type, MAJOR, ARRAY_SIZE(MAJOR), info) >= 0; } +static bool read_u16(uint16_t *ret, bfd_vma memaddr, + struct disassemble_info *info) +{ + int status = (*info->read_memory_func)(memaddr, (bfd_byte *)ret, 2, info); + if (status != 0) { + (*info->memory_error_func)(status, memaddr, info); + return false; + } + + if ((info->endian == BFD_ENDIAN_BIG) != HOST_BIG_ENDIAN) { + bswap16s(ret); + } + return true; +} + int print_insn_nanomips(bfd_vma memaddr, struct disassemble_info *info) { - int status, length; - bfd_byte buffer[2]; + int length; uint16_t words[3] = { }; g_autofree char *buf = NULL; @@ -21939,48 +21953,24 @@ int print_insn_nanomips(bfd_vma memaddr, struct disassemble_info *info) disassm_info.fprintf_func = info->fprintf_func; disassm_info.stream = info->stream; - status = (*info->read_memory_func)(memaddr, buffer, 2, info); - if (status != 0) { - (*info->memory_error_func)(status, memaddr, info); + if (!read_u16(&words[0], memaddr, info)) { return -1; } - - if (info->endian == BFD_ENDIAN_BIG) { - words[0] = bfd_getb16(buffer); - } else { - words[0] = bfd_getl16(buffer); - } length = 2; /* Handle 32-bit opcodes. */ if ((words[0] & 0x1000) == 0) { - status = (*info->read_memory_func)(memaddr + 2, buffer, 2, info); - if (status != 0) { - (*info->memory_error_func)(status, memaddr + 2, info); + if (!read_u16(&words[1], memaddr + 2, info)) { return -1; } - - if (info->endian == BFD_ENDIAN_BIG) { - words[1] = bfd_getb16(buffer); - } else { - words[1] = bfd_getl16(buffer); - } length = 4; } /* Handle 48-bit opcodes. */ if ((words[0] >> 10) == 0x18) { - status = (*info->read_memory_func)(memaddr + 4, buffer, 2, info); - if (status != 0) { - (*info->memory_error_func)(status, memaddr + 4, info); + if (!read_u16(&words[1], memaddr + 4, info)) { return -1; } - - if (info->endian == BFD_ENDIAN_BIG) { - words[2] = bfd_getb16(buffer); - } else { - words[2] = bfd_getl16(buffer); - } length = 6; } From patchwork Mon Nov 7 23:58:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13035546 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1D0CEC43217 for ; Tue, 8 Nov 2022 00:02:25 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1osC1d-0005LO-5Z; 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Mon, 07 Nov 2022 15:59:27 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Aurelien Jarno , Aleksandar Rikalo , Jiaxun Yang , Richard Henderson Subject: [PULL 13/14] disas/nanomips: Tidy read for 48-bit opcodes Date: Tue, 8 Nov 2022 00:58:21 +0100 Message-Id: <20221107235822.71458-14-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221107235822.71458-1-philmd@linaro.org> References: <20221107235822.71458-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=philmd@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Richard Henderson There is no point in looking for a 48-bit opcode if we've not read the second word for a 32-bit opcode. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20221106023735.5277-5-richard.henderson@linaro.org> --- disas/nanomips.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/disas/nanomips.c b/disas/nanomips.c index 3b998118e3..a0253598dd 100644 --- a/disas/nanomips.c +++ b/disas/nanomips.c @@ -21964,14 +21964,14 @@ int print_insn_nanomips(bfd_vma memaddr, struct disassemble_info *info) return -1; } length = 4; - } - /* Handle 48-bit opcodes. */ - if ((words[0] >> 10) == 0x18) { - if (!read_u16(&words[1], memaddr + 4, info)) { - return -1; + /* Handle 48-bit opcodes. */ + if ((words[0] >> 10) == 0x18) { + if (!read_u16(&words[1], memaddr + 4, info)) { + return -1; + } + length = 6; } - length = 6; } for (int i = 0; i < ARRAY_SIZE(words); i++) { From patchwork Mon Nov 7 23:58:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13035545 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 73A20C4332F for ; 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Mon, 07 Nov 2022 15:59:33 -0800 (PST) Received: from localhost.localdomain ([185.126.107.38]) by smtp.gmail.com with ESMTPSA id u8-20020a05600c19c800b003c6f8d30e40sm13859437wmq.31.2022.11.07.15.59.32 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 07 Nov 2022 15:59:33 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Aurelien Jarno , Aleksandar Rikalo , Jiaxun Yang , Vince Del Vecchio , Richard Henderson , Thomas Huth Subject: [PULL 14/14] MAINTAINERS: Inherit from nanoMIPS Date: Tue, 8 Nov 2022 00:58:22 +0100 Message-Id: <20221107235822.71458-15-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221107235822.71458-1-philmd@linaro.org> References: <20221107235822.71458-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=philmd@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org 6 months ago Stefan Pejic stepped in as nanoMIPS maintainer (see commit a 8e0e23445a "target/mips: Undeprecate nanoMIPS ISA support in QEMU"), however today his email is bouncing: ** Message blocked ** Your message to stefan.pejic@syrmia.com has been blocked. See technical details below for more information. The response from the remote server was: 550 5.4.1 Recipient address rejected: Access denied. AS(201806281) [DBAEUR03FT030.eop-EUR03.prod.protection.outlook.com] To avoid unmaintained code, I feel forced to merge this code back with the generic MIPS section. Historical references: - https://lore.kernel.org/qemu-devel/TY0PR03MB679726901BD6C6BE40114A2FE2A79@TY0PR03MB6797.apcprd03.prod.outlook.com/ - https://lore.kernel.org/qemu-devel/b858a20e97b74e7b90a94948314d0008@MTKMBS62N2.mediatek.inc/ Cc: Vince Del Vecchio Reviewed-by: Richard Henderson Message-Id: <49f41916-687f-b9e5-2de7-9c658fe0d4c7@linaro.org> Tested-by: Thomas Huth Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20221101114458.25756-6-philmd@linaro.org> --- MAINTAINERS | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 4adf8c65db..86bcd07a31 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -237,16 +237,10 @@ R: Jiaxun Yang R: Aleksandar Rikalo S: Odd Fixes F: target/mips/ -F: disas/mips.c +F: disas/*mips.c F: docs/system/cpu-models-mips.rst.inc F: tests/tcg/mips/ -MIPS TCG CPUs (nanoMIPS ISA) -M: Stefan Pejic -S: Maintained -F: disas/nanomips.* -F: target/mips/tcg/*nanomips* - NiosII TCG CPUs M: Chris Wulff M: Marek Vasut