From patchwork Tue Nov 8 03:33:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zhang, Rui" X-Patchwork-Id: 13035766 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 861E4C43217 for ; Tue, 8 Nov 2022 03:31:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232414AbiKHDbX (ORCPT ); Mon, 7 Nov 2022 22:31:23 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51714 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231659AbiKHDbW (ORCPT ); Mon, 7 Nov 2022 22:31:22 -0500 Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 49BC92F38A for ; Mon, 7 Nov 2022 19:31:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1667878281; x=1699414281; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=m1mveA+UN7i4ZII/zbafiFNqxU35dkL4cX1iih/BCSA=; b=Q8oAEfaU64bOUxX6ysjZPEea+hnWTVrrndN7vgEZu8tB+0eplG4vFNbM VSqomC4YbTWgXkZA6S3IkrTGGYeIUd7fRmKrFr/dFAN/mwkjbFgkpMbXt TqEAuP9Bnx2/LwieVnsaP0uYMHiUoUuXXdYNQuVIOI/Y+u/pZRbhpWDtZ D/MK3lu+rvAwHneRLX1vMy2WVeh069dDRHhrLR/DrU927nCmloH2lvjNG zzj5jgK4qUQOfa3SgodOA4dVF6vlawkA8BzlvQIIU4EzS4lA2+3o5boa9 JJT6KzknkWextlqhiR+NStTtTHarKPAeBsa1fz7c4839zCd0VpIlcLHfM w==; X-IronPort-AV: E=McAfee;i="6500,9779,10524"; a="372732523" X-IronPort-AV: E=Sophos;i="5.96,145,1665471600"; d="scan'208";a="372732523" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Nov 2022 19:31:21 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10524"; a="614120227" X-IronPort-AV: E=Sophos;i="5.96,145,1665471600"; d="scan'208";a="614120227" Received: from power-sh.sh.intel.com ([10.239.183.122]) by orsmga006.jf.intel.com with ESMTP; 07 Nov 2022 19:31:19 -0800 From: Zhang Rui To: rjw@rjwysocki.net, daniel.lezcano@linaro.org Cc: linux-pm@vger.kernel.org, srinivas.pandruvada@linux.intel.com Subject: [PATCH 1/6] thermal/intel: Introduce Intel TCC library Date: Tue, 8 Nov 2022 11:33:27 +0800 Message-Id: <20221108033332.27760-2-rui.zhang@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221108033332.27760-1-rui.zhang@intel.com> References: <20221108033332.27760-1-rui.zhang@intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org There are several different drivers that accesses the Intel TCC (thermal control circuitry) MSRs, and each of them has its own implementation for the same functionalities, e.g. getting the current temperature, getting the tj_max, and getting/setting the tj_max offset. Introduce a library to unify the code for Intel CPU TCC MSR access. At the same time, ensure the temperature is got based on the updated tjmax value because tjmax can be changed at runtime for cases like the Intel SST-PP (Intel Speed Select Technology - Performance Profile) level change. Signed-off-by: Zhang Rui --- drivers/thermal/intel/Kconfig | 4 + drivers/thermal/intel/Makefile | 1 + drivers/thermal/intel/intel_tcc.c | 131 ++++++++++++++++++++++++++++++ include/linux/intel_tcc.h | 18 ++++ 4 files changed, 154 insertions(+) create mode 100644 drivers/thermal/intel/intel_tcc.c create mode 100644 include/linux/intel_tcc.h diff --git a/drivers/thermal/intel/Kconfig b/drivers/thermal/intel/Kconfig index f0c845679250..6b938c040d6e 100644 --- a/drivers/thermal/intel/Kconfig +++ b/drivers/thermal/intel/Kconfig @@ -12,6 +12,10 @@ config X86_THERMAL_VECTOR def_bool y depends on X86 && CPU_SUP_INTEL && X86_LOCAL_APIC +config INTEL_TCC + bool + depends on X86 + config X86_PKG_TEMP_THERMAL tristate "X86 package temperature thermal driver" depends on X86_THERMAL_VECTOR diff --git a/drivers/thermal/intel/Makefile b/drivers/thermal/intel/Makefile index 9a8d8054f316..5d8833c82ab6 100644 --- a/drivers/thermal/intel/Makefile +++ b/drivers/thermal/intel/Makefile @@ -2,6 +2,7 @@ # # Makefile for various Intel thermal drivers. +obj-$(CONFIG_INTEL_TCC) += intel_tcc.o obj-$(CONFIG_INTEL_POWERCLAMP) += intel_powerclamp.o obj-$(CONFIG_X86_PKG_TEMP_THERMAL) += x86_pkg_temp_thermal.o obj-$(CONFIG_INTEL_SOC_DTS_IOSF_CORE) += intel_soc_dts_iosf.o diff --git a/drivers/thermal/intel/intel_tcc.c b/drivers/thermal/intel/intel_tcc.c new file mode 100644 index 000000000000..74b434914975 --- /dev/null +++ b/drivers/thermal/intel/intel_tcc.c @@ -0,0 +1,131 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * intel_tcc.c - Library for Intel TCC (thermal control circuitry) MSR access + * Copyright (c) 2022, Intel Corporation. + */ + +#include +#include +#include + +/** + * intel_tcc_get_tjmax() - returns the default TCC activation Temperature + * @cpu: cpu that the MSR should be run on. + * @tjmax: a valid pointer to where to store the Tjmax value + * + * Get the TjMax value, which is the default thermal throttling or TCC + * activation temperature in degrees C. + * + * Return: On success returns 0, an error code otherwise + */ + +int intel_tcc_get_tjmax(int cpu, int *tjmax) +{ + u32 eax, edx; + int err; + + err = rdmsr_safe_on_cpu(cpu, MSR_IA32_TEMPERATURE_TARGET, + &eax, &edx); + if (err) + return err; + + *tjmax = (eax >> 16) & 0xff; + + return *tjmax ? 0 : -EINVAL; +} +EXPORT_SYMBOL_NS_GPL(intel_tcc_get_tjmax, INTEL_TCC); + +/** + * intel_tcc_get_offset() - returns the TCC Offset value to Tjmax + * @cpu: cpu that the MSR should be run on. + * @offset: a valid pointer to where to store the offset value + * + * Get the TCC offset value to Tjmax. The effective thermal throttling or TCC + * activation temperature equals "Tjmax" - "TCC Offset", in degrees C. + * + * Return: On success returns 0, an error code otherwise + */ + +int intel_tcc_get_offset(int cpu, int *offset) +{ + u32 eax, edx; + int err; + + err = rdmsr_safe_on_cpu(cpu, MSR_IA32_TEMPERATURE_TARGET, + &eax, &edx); + if (err) + return err; + + *offset = (eax >> 24) & 0x3f; + + return 0; +} +EXPORT_SYMBOL_NS_GPL(intel_tcc_get_offset, INTEL_TCC); + +/** + * intel_tcc_set_offset() - set the TCC offset value to Tjmax + * @cpu: cpu that the MSR should be run on. + * @offset: TCC offset value in degree C + * + * Set the TCC Offset value to Tjmax. The effective thermal throttling or TCC + * activation temperature equals "Tjmax" - "TCC Offset", in degree C. + * + * Return: On success returns 0, an error code otherwise + */ + +int intel_tcc_set_offset(int cpu, int offset) +{ + u32 eax, edx; + int err; + + if (offset > 0x3f) + return -EINVAL; + + err = rdmsr_safe_on_cpu(cpu, MSR_IA32_TEMPERATURE_TARGET, + &eax, &edx); + if (err) + return err; + + if (eax & BIT(31)) + return -EPERM; + + eax &= ~(0x3f << 24); + eax |= (offset << 24); + + return wrmsr_safe_on_cpu(cpu, MSR_IA32_TEMPERATURE_TARGET, eax, edx); +} +EXPORT_SYMBOL_NS_GPL(intel_tcc_set_offset, INTEL_TCC); + +/** + * intel_tcc_get_temp() - returns the current temperature + * @cpu: cpu that the MSR should be run on. + * @pkg: true: Package Thermal Sensor. false: Core Thermal Sensor. + * @temp: a valid pointer to where to store the resulting temperature + * + * Get the current temperature returned by the CPU core/package level + * thermal sensor, in degrees C. + * + * Return: On success returns 0, an error code otherwise + */ +int intel_tcc_get_temp(int cpu, bool pkg, int *temp) +{ + u32 eax, edx; + u32 msr = pkg ? MSR_IA32_PACKAGE_THERM_STATUS : MSR_IA32_THERM_STATUS; + int tjmax, err; + + err = intel_tcc_get_tjmax(cpu, &tjmax); + if (err) + return err; + + err = rdmsr_safe_on_cpu(cpu, msr, &eax, &edx); + if (err) + return err; + + if (eax & 0x80000000) { + *temp = tjmax - ((eax >> 16) & 0x7f); + return 0; + } + return -EINVAL; +} +EXPORT_SYMBOL_NS_GPL(intel_tcc_get_temp, INTEL_TCC); + diff --git a/include/linux/intel_tcc.h b/include/linux/intel_tcc.h new file mode 100644 index 000000000000..94f8ceab5dd0 --- /dev/null +++ b/include/linux/intel_tcc.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * header for Intel TCC (thermal control circuitry) library + * + * Copyright (C) 2022 Intel Corporation. + */ + +#ifndef __INTEL_TCC_H__ +#define __INTEL_TCC_H__ + +#include + +int intel_tcc_get_tjmax(int cpu, int *tjmax); +int intel_tcc_get_offset(int cpu, int *offset); +int intel_tcc_set_offset(int cpu, int offset); +int intel_tcc_get_temp(int cpu, bool pkg, int *temp); + +#endif /* __INTEL_TCC_H__ */ From patchwork Tue Nov 8 03:33:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zhang, Rui" X-Patchwork-Id: 13035767 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ADA56C4332F for ; Tue, 8 Nov 2022 03:31:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232270AbiKHDb1 (ORCPT ); Mon, 7 Nov 2022 22:31:27 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51742 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232420AbiKHDbY (ORCPT ); Mon, 7 Nov 2022 22:31:24 -0500 Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E65212F3B1 for ; Mon, 7 Nov 2022 19:31:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1667878282; x=1699414282; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=vQHiKPUEUo9yZZX7kHYkQ3rjbJK7zqh1vCi42BPQ5Mc=; b=RQzhwFLNE5UL2Byw1NoRLLXCxCiN+jXTMYNJJXkf9912nRefV8Z66Ojq DsechE67wYj0fDOQPodQUtA500/9QlVXe/hLD+Rmn7tX/7nNoBDZet9t+ qY2Tf1EaJptsxDuXBuXitxgI27ugkOnHrI2f917RMvc0PWkmC+i4pSLdw GndL6odR9wGAqLpBm9LFbYOF+drMlo0H/ORO2ue7ZKrFStzDEuvBfVnIL i6Zjt7k8CvdsCfSi4PnqPnrVUnPWQqpw0ULQwAeUPk67zSmJIyR1tQ7c+ JqTwY55KNpR/4rzU0Yunqcnza4x4IQtgZ0KFPURnKaJbFH3g5xGJ7xUiS A==; X-IronPort-AV: E=McAfee;i="6500,9779,10524"; a="372732526" X-IronPort-AV: E=Sophos;i="5.96,145,1665471600"; d="scan'208";a="372732526" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Nov 2022 19:31:22 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10524"; a="614120234" X-IronPort-AV: E=Sophos;i="5.96,145,1665471600"; d="scan'208";a="614120234" Received: from power-sh.sh.intel.com ([10.239.183.122]) by orsmga006.jf.intel.com with ESMTP; 07 Nov 2022 19:31:21 -0800 From: Zhang Rui To: rjw@rjwysocki.net, daniel.lezcano@linaro.org Cc: linux-pm@vger.kernel.org, srinivas.pandruvada@linux.intel.com Subject: [PATCH 2/6] thermal/int340x/processor_thermal: Use Intel TCC library Date: Tue, 8 Nov 2022 11:33:28 +0800 Message-Id: <20221108033332.27760-3-rui.zhang@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221108033332.27760-1-rui.zhang@intel.com> References: <20221108033332.27760-1-rui.zhang@intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Cleanup the code by using Intel TCC library for TCC (Thermal Control Circuitry) MSR access. Signed-off-by: Zhang Rui --- drivers/thermal/intel/int340x_thermal/Kconfig | 1 + .../processor_thermal_device.c | 123 ++++-------------- 2 files changed, 25 insertions(+), 99 deletions(-) diff --git a/drivers/thermal/intel/int340x_thermal/Kconfig b/drivers/thermal/intel/int340x_thermal/Kconfig index 5d046de96a5d..0f511917e0e1 100644 --- a/drivers/thermal/intel/int340x_thermal/Kconfig +++ b/drivers/thermal/intel/int340x_thermal/Kconfig @@ -10,6 +10,7 @@ config INT340X_THERMAL select ACPI_THERMAL_REL select ACPI_FAN select INTEL_SOC_DTS_IOSF_CORE + select INTEL_TCC select PROC_THERMAL_MMIO_RAPL if POWERCAP help Newer laptops and tablets that use ACPI may have thermal sensors and diff --git a/drivers/thermal/intel/int340x_thermal/processor_thermal_device.c b/drivers/thermal/intel/int340x_thermal/processor_thermal_device.c index a8d98f1bd6c6..a9e08dddb773 100644 --- a/drivers/thermal/intel/int340x_thermal/processor_thermal_device.c +++ b/drivers/thermal/intel/int340x_thermal/processor_thermal_device.c @@ -4,6 +4,7 @@ * Copyright (c) 2014, Intel Corporation. */ #include +#include #include #include #include @@ -68,54 +69,17 @@ static const struct attribute_group power_limit_attribute_group = { .name = "power_limits" }; -static int tcc_get_offset(void) -{ - u64 val; - int err; - - err = rdmsrl_safe(MSR_IA32_TEMPERATURE_TARGET, &val); - if (err) - return err; - - return (val >> 24) & 0x3f; -} - static ssize_t tcc_offset_degree_celsius_show(struct device *dev, struct device_attribute *attr, char *buf) { - int tcc; - - tcc = tcc_get_offset(); - if (tcc < 0) - return tcc; - - return sprintf(buf, "%d\n", tcc); -} - -static int tcc_offset_update(unsigned int tcc) -{ - u64 val; - int err; + int offset, ret; - if (tcc > 63) - return -EINVAL; - - err = rdmsrl_safe(MSR_IA32_TEMPERATURE_TARGET, &val); - if (err) - return err; - - if (val & BIT(31)) - return -EPERM; - - val &= ~GENMASK_ULL(29, 24); - val |= (tcc & 0x3f) << 24; - - err = wrmsrl_safe(MSR_IA32_TEMPERATURE_TARGET, val); - if (err) - return err; + ret = intel_tcc_get_offset(cpumask_any(cpu_online_mask), &offset); + if (ret < 0) + return ret; - return 0; + return sprintf(buf, "%d\n", offset); } static ssize_t tcc_offset_degree_celsius_store(struct device *dev, @@ -136,7 +100,7 @@ static ssize_t tcc_offset_degree_celsius_store(struct device *dev, if (kstrtouint(buf, 0, &tcc)) return -EINVAL; - err = tcc_offset_update(tcc); + err = intel_tcc_set_offset(cpumask_any(cpu_online_mask), tcc); if (err) return err; @@ -145,66 +109,26 @@ static ssize_t tcc_offset_degree_celsius_store(struct device *dev, static DEVICE_ATTR_RW(tcc_offset_degree_celsius); -static int stored_tjmax; /* since it is fixed, we can have local storage */ - -static int get_tjmax(void) -{ - u32 eax, edx; - u32 val; - int err; - - err = rdmsr_safe(MSR_IA32_TEMPERATURE_TARGET, &eax, &edx); - if (err) - return err; - - val = (eax >> 16) & 0xff; - if (val) - return val; - - return -EINVAL; -} - -static int read_temp_msr(int *temp) +static int proc_thermal_get_zone_temp(struct thermal_zone_device *zone, + int *temp) { int cpu; - u32 eax, edx; int err; - unsigned long curr_temp_off = 0; + int curr_temp_off; *temp = 0; for_each_online_cpu(cpu) { - err = rdmsr_safe_on_cpu(cpu, MSR_IA32_THERM_STATUS, &eax, - &edx); + err = intel_tcc_get_temp(cpu, false, &curr_temp_off); if (err) - goto err_ret; - else { - if (eax & 0x80000000) { - curr_temp_off = (eax >> 16) & 0x7f; - if (!*temp || curr_temp_off < *temp) - *temp = curr_temp_off; - } else { - err = -EINVAL; - goto err_ret; - } - } + return err; + if (!*temp || curr_temp_off > *temp) + *temp = curr_temp_off; } - return 0; -err_ret: - return err; -} + *temp *= 1000; -static int proc_thermal_get_zone_temp(struct thermal_zone_device *zone, - int *temp) -{ - int ret; - - ret = read_temp_msr(temp); - if (!ret) - *temp = (stored_tjmax - *temp) * 1000; - - return ret; + return 0; } static struct thermal_zone_device_ops proc_thermal_local_ops = { @@ -286,7 +210,7 @@ int proc_thermal_add(struct device *dev, struct proc_thermal_device *proc_priv) acpi_status status; unsigned long long tmp; struct thermal_zone_device_ops *ops = NULL; - int ret; + int tjmax, ret; adev = ACPI_COMPANION(dev); if (!adev) @@ -302,8 +226,7 @@ int proc_thermal_add(struct device *dev, struct proc_thermal_device *proc_priv) status = acpi_evaluate_integer(adev->handle, "_TMP", NULL, &tmp); if (ACPI_FAILURE(status)) { /* there is no _TMP method, add local method */ - stored_tjmax = get_tjmax(); - if (stored_tjmax > 0) + if (!intel_tcc_get_tjmax(cpumask_any(cpu_online_mask), &tjmax)) ops = &proc_thermal_local_ops; } @@ -356,9 +279,10 @@ static int tcc_offset_save = -1; int proc_thermal_suspend(struct device *dev) { - tcc_offset_save = tcc_get_offset(); - if (tcc_offset_save < 0) - dev_warn(dev, "failed to save offset (%d)\n", tcc_offset_save); + if (intel_tcc_get_offset(cpumask_any(cpu_online_mask), &tcc_offset_save)) { + dev_warn(dev, "failed to save offset\n"); + tcc_offset_save = -1; + } return 0; } @@ -373,7 +297,7 @@ int proc_thermal_resume(struct device *dev) /* Do not update if saving failed */ if (tcc_offset_save >= 0) - tcc_offset_update(tcc_offset_save); + intel_tcc_set_offset(cpumask_any(cpu_online_mask), tcc_offset_save); return 0; } @@ -460,6 +384,7 @@ void proc_thermal_mmio_remove(struct pci_dev *pdev, struct proc_thermal_device * } EXPORT_SYMBOL_GPL(proc_thermal_mmio_remove); +MODULE_IMPORT_NS(INTEL_TCC); MODULE_AUTHOR("Srinivas Pandruvada "); MODULE_DESCRIPTION("Processor Thermal Reporting Device Driver"); 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07 Nov 2022 19:31:23 -0800 From: Zhang Rui To: rjw@rjwysocki.net, daniel.lezcano@linaro.org Cc: linux-pm@vger.kernel.org, srinivas.pandruvada@linux.intel.com Subject: [PATCH 3/6] thermal/intel/intel_soc_dts_iosf: Use Intel TCC library Date: Tue, 8 Nov 2022 11:33:29 +0800 Message-Id: <20221108033332.27760-4-rui.zhang@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221108033332.27760-1-rui.zhang@intel.com> References: <20221108033332.27760-1-rui.zhang@intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Cleanup the code by using Intel TCC library for TCC (Thermal Control Circuitry) MSR access. Signed-off-by: Zhang Rui --- drivers/thermal/intel/Kconfig | 1 + drivers/thermal/intel/intel_soc_dts_iosf.c | 33 ++++------------------ 2 files changed, 6 insertions(+), 28 deletions(-) diff --git a/drivers/thermal/intel/Kconfig b/drivers/thermal/intel/Kconfig index 6b938c040d6e..329c0ee934c4 100644 --- a/drivers/thermal/intel/Kconfig +++ b/drivers/thermal/intel/Kconfig @@ -32,6 +32,7 @@ config INTEL_SOC_DTS_IOSF_CORE tristate depends on X86 && PCI select IOSF_MBI + select INTEL_TCC help This is becoming a common feature for Intel SoCs to expose the additional digital temperature sensors (DTSs) using side band interface (IOSF). This diff --git a/drivers/thermal/intel/intel_soc_dts_iosf.c b/drivers/thermal/intel/intel_soc_dts_iosf.c index 342b0bb5a56d..87fc45b8f8c6 100644 --- a/drivers/thermal/intel/intel_soc_dts_iosf.c +++ b/drivers/thermal/intel/intel_soc_dts_iosf.c @@ -7,6 +7,7 @@ #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt #include +#include #include #include #include @@ -45,32 +46,6 @@ /* DTS0 and DTS 1 */ #define SOC_MAX_DTS_SENSORS 2 -static int get_tj_max(u32 *tj_max) -{ - u32 eax, edx; - u32 val; - int err; - - err = rdmsr_safe(MSR_IA32_TEMPERATURE_TARGET, &eax, &edx); - if (err) - goto err_ret; - else { - val = (eax >> 16) & 0xff; - if (val) - *tj_max = val * 1000; - else { - err = -EINVAL; - goto err_ret; - } - } - - return 0; -err_ret: - *tj_max = 0; - - return err; -} - static int sys_get_trip_temp(struct thermal_zone_device *tzd, int trip, int *temp) { @@ -415,8 +390,9 @@ struct intel_soc_dts_sensors *intel_soc_dts_iosf_init( if (!trip_count || read_only_trip_count > trip_count) return ERR_PTR(-EINVAL); - if (get_tj_max(&tj_max)) - return ERR_PTR(-EINVAL); + ret = intel_tcc_get_tjmax(cpumask_any(cpu_online_mask), &tj_max); + if (ret) + return ERR_PTR(ret); sensors = kzalloc(sizeof(*sensors), GFP_KERNEL); if (!sensors) @@ -475,4 +451,5 @@ void intel_soc_dts_iosf_exit(struct intel_soc_dts_sensors *sensors) } EXPORT_SYMBOL_GPL(intel_soc_dts_iosf_exit); +MODULE_IMPORT_NS(INTEL_TCC); MODULE_LICENSE("GPL v2"); From patchwork Tue Nov 8 03:33:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zhang, Rui" X-Patchwork-Id: 13035769 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 058ADC433FE for ; Tue, 8 Nov 2022 03:31:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232366AbiKHDbb (ORCPT ); Mon, 7 Nov 2022 22:31:31 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51742 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231659AbiKHDb1 (ORCPT ); Mon, 7 Nov 2022 22:31:27 -0500 Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 40C0B2F39E for ; Mon, 7 Nov 2022 19:31:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1667878286; x=1699414286; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=Eczi2fmvA4uOiYb+3UFSugNRt+4J2cDiLmkt92MiNt4=; b=bget73ANP8gYTTuVRIJTuVyYyAsOUppIJ6j4k34Owtx91MU+iUwydah/ ll3NTe0okBXt6XU75ZBKNG8WjFZoppvClPjGZibMRl/B0bMFgUgytIXZa VTyQX6iF/GGSHlBFdtFF4GPOx6N/mrZatqJVW+QTh6dEzaxXrCmKKxqgK tenZkskzV3Py2iPKreTWFVqsq8Ff6T6nKNx7sYXD0yqseKYYXQeCQuoCw KnJO3GIC5M5IuFCVLnvanEIahz2J3nQKKKgpbg0QDliieHRXNv+gP85aG tgwaThoD8wme8thPItmQ5e8Nf9aycA/Bt+DapjZ4TNz+tCtTLcEUZloGP A==; X-IronPort-AV: E=McAfee;i="6500,9779,10524"; a="372732539" X-IronPort-AV: E=Sophos;i="5.96,145,1665471600"; d="scan'208";a="372732539" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Nov 2022 19:31:25 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10524"; a="614120243" X-IronPort-AV: E=Sophos;i="5.96,145,1665471600"; d="scan'208";a="614120243" Received: from power-sh.sh.intel.com ([10.239.183.122]) by orsmga006.jf.intel.com with ESMTP; 07 Nov 2022 19:31:24 -0800 From: Zhang Rui To: rjw@rjwysocki.net, daniel.lezcano@linaro.org Cc: linux-pm@vger.kernel.org, srinivas.pandruvada@linux.intel.com Subject: [PATCH 4/6] thermal/intel/intel_tcc_cooling: Use Intel TCC library Date: Tue, 8 Nov 2022 11:33:30 +0800 Message-Id: <20221108033332.27760-5-rui.zhang@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221108033332.27760-1-rui.zhang@intel.com> References: <20221108033332.27760-1-rui.zhang@intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Cleanup the code by using Intel TCC library for TCC (Thermal Control Circuitry) MSR access. Signed-off-by: Zhang Rui --- drivers/thermal/intel/Kconfig | 1 + drivers/thermal/intel/intel_tcc_cooling.c | 37 +++-------------------- 2 files changed, 6 insertions(+), 32 deletions(-) diff --git a/drivers/thermal/intel/Kconfig b/drivers/thermal/intel/Kconfig index 329c0ee934c4..dafdb3dd3fc7 100644 --- a/drivers/thermal/intel/Kconfig +++ b/drivers/thermal/intel/Kconfig @@ -88,6 +88,7 @@ config INTEL_PCH_THERMAL config INTEL_TCC_COOLING tristate "Intel TCC offset cooling Driver" depends on X86 + select INTEL_TCC help Enable this to support system cooling by adjusting the effective TCC activation temperature via the TCC Offset register, which is widely diff --git a/drivers/thermal/intel/intel_tcc_cooling.c b/drivers/thermal/intel/intel_tcc_cooling.c index 95adac427b6f..8819afb7f23c 100644 --- a/drivers/thermal/intel/intel_tcc_cooling.c +++ b/drivers/thermal/intel/intel_tcc_cooling.c @@ -7,12 +7,11 @@ #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt #include +#include #include #include #include -#define TCC_SHIFT 24 -#define TCC_MASK (0x3fULL<<24) #define TCC_PROGRAMMABLE BIT(30) static struct thermal_cooling_device *tcc_cdev; @@ -20,47 +19,20 @@ static struct thermal_cooling_device *tcc_cdev; static int tcc_get_max_state(struct thermal_cooling_device *cdev, unsigned long *state) { - *state = TCC_MASK >> TCC_SHIFT; - return 0; -} - -static int tcc_offset_update(int tcc) -{ - u64 val; - int err; - - err = rdmsrl_safe(MSR_IA32_TEMPERATURE_TARGET, &val); - if (err) - return err; - - val &= ~TCC_MASK; - val |= tcc << TCC_SHIFT; - - err = wrmsrl_safe(MSR_IA32_TEMPERATURE_TARGET, val); - if (err) - return err; - + *state = 0x3f; return 0; } static int tcc_get_cur_state(struct thermal_cooling_device *cdev, unsigned long *state) { - u64 val; - int err; - - err = rdmsrl_safe(MSR_IA32_TEMPERATURE_TARGET, &val); - if (err) - return err; - - *state = (val & TCC_MASK) >> TCC_SHIFT; - return 0; + return intel_tcc_get_offset(cpumask_any(cpu_online_mask), (int *)state); } static int tcc_set_cur_state(struct thermal_cooling_device *cdev, unsigned long state) { - return tcc_offset_update(state); + return intel_tcc_set_offset(cpumask_any(cpu_online_mask), (int)state); } static const struct thermal_cooling_device_ops tcc_cooling_ops = { @@ -129,6 +101,7 @@ static void __exit tcc_cooling_exit(void) module_exit(tcc_cooling_exit) +MODULE_IMPORT_NS(INTEL_TCC); MODULE_DESCRIPTION("TCC offset cooling device Driver"); MODULE_AUTHOR("Zhang Rui "); MODULE_LICENSE("GPL v2"); From patchwork Tue Nov 8 03:33:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zhang, Rui" X-Patchwork-Id: 13035770 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B5305C4332F for ; Tue, 8 Nov 2022 03:31:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231659AbiKHDbc (ORCPT ); Mon, 7 Nov 2022 22:31:32 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51798 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232505AbiKHDb2 (ORCPT ); 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07 Nov 2022 19:31:27 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10524"; a="614120251" X-IronPort-AV: E=Sophos;i="5.96,145,1665471600"; d="scan'208";a="614120251" Received: from power-sh.sh.intel.com ([10.239.183.122]) by orsmga006.jf.intel.com with ESMTP; 07 Nov 2022 19:31:26 -0800 From: Zhang Rui To: rjw@rjwysocki.net, daniel.lezcano@linaro.org Cc: linux-pm@vger.kernel.org, srinivas.pandruvada@linux.intel.com Subject: [PATCH 5/6] thermal/x86_pkg_temp_thermal: Use Intel TCC library Date: Tue, 8 Nov 2022 11:33:31 +0800 Message-Id: <20221108033332.27760-6-rui.zhang@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221108033332.27760-1-rui.zhang@intel.com> References: <20221108033332.27760-1-rui.zhang@intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Cleanup the code by using Intel TCC library for TCC (Thermal Control Circuitry) MSR access. Signed-off-by: Zhang Rui --- drivers/thermal/intel/Kconfig | 1 + drivers/thermal/intel/x86_pkg_temp_thermal.c | 40 ++++++-------------- 2 files changed, 12 insertions(+), 29 deletions(-) diff --git a/drivers/thermal/intel/Kconfig b/drivers/thermal/intel/Kconfig index dafdb3dd3fc7..fd41c810629b 100644 --- a/drivers/thermal/intel/Kconfig +++ b/drivers/thermal/intel/Kconfig @@ -21,6 +21,7 @@ config X86_PKG_TEMP_THERMAL depends on X86_THERMAL_VECTOR select THERMAL_GOV_USER_SPACE select THERMAL_WRITABLE_TRIPS + select INTEL_TCC default m help Enable this to register CPU digital sensor for package temperature as diff --git a/drivers/thermal/intel/x86_pkg_temp_thermal.c b/drivers/thermal/intel/x86_pkg_temp_thermal.c index a0e234fce71a..cfe905735c62 100644 --- a/drivers/thermal/intel/x86_pkg_temp_thermal.c +++ b/drivers/thermal/intel/x86_pkg_temp_thermal.c @@ -7,6 +7,7 @@ #include #include +#include #include #include #include @@ -104,38 +105,18 @@ static struct zone_device *pkg_temp_thermal_get_dev(unsigned int cpu) return NULL; } -/* -* tj-max is interesting because threshold is set relative to this -* temperature. -*/ -static int get_tj_max(int cpu, u32 *tj_max) -{ - u32 eax, edx, val; - int err; - - err = rdmsr_safe_on_cpu(cpu, MSR_IA32_TEMPERATURE_TARGET, &eax, &edx); - if (err) - return err; - - val = (eax >> 16) & 0xff; - *tj_max = val * 1000; - - return val ? 0 : -EINVAL; -} - static int sys_get_curr_temp(struct thermal_zone_device *tzd, int *temp) { struct zone_device *zonedev = tzd->devdata; - u32 eax, edx; + int ret; - rdmsr_on_cpu(zonedev->cpu, MSR_IA32_PACKAGE_THERM_STATUS, - &eax, &edx); - if (eax & 0x80000000) { - *temp = zonedev->tj_max - ((eax >> 16) & 0x7f) * 1000; - pr_debug("sys_get_curr_temp %d\n", *temp); - return 0; - } - return -EINVAL; + ret = intel_tcc_get_temp(zonedev->cpu, true, temp); + if (ret) + return ret; + + *temp *= 1000; + pr_debug("sys_get_curr_temp %d\n", *temp); + return 0; } static int sys_get_trip_temp(struct thermal_zone_device *tzd, @@ -345,7 +326,7 @@ static int pkg_temp_thermal_device_add(unsigned int cpu) thres_count = clamp_val(thres_count, 0, MAX_NUMBER_OF_TRIPS); - err = get_tj_max(cpu, &tj_max); + err = intel_tcc_get_tjmax(cpu, &tj_max); if (err) return err; @@ -536,6 +517,7 @@ static void __exit pkg_temp_thermal_exit(void) } module_exit(pkg_temp_thermal_exit) +MODULE_IMPORT_NS(INTEL_TCC); MODULE_DESCRIPTION("X86 PKG TEMP Thermal Driver"); MODULE_AUTHOR("Srinivas Pandruvada "); MODULE_LICENSE("GPL v2"); From patchwork Tue Nov 8 03:33:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zhang, Rui" X-Patchwork-Id: 13035771 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2AA7DC43219 for ; Tue, 8 Nov 2022 03:31:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232060AbiKHDbd (ORCPT ); Mon, 7 Nov 2022 22:31:33 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51750 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232644AbiKHDba (ORCPT ); Mon, 7 Nov 2022 22:31:30 -0500 Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 54A7F2F672 for ; Mon, 7 Nov 2022 19:31:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1667878289; x=1699414289; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=ea1poUBCd4hPy458r9ilS29cRNF0FN/s2Pc7/4v/umw=; b=aYCzQ2jsLlKInTDebNZLwP8q749yDJE/8RKAO5LwWIa+u5mshYiEbcQe Pln+2LqGeMpedjnG2JWWRwywLndFlQ4roxt2LB243jRaygH5mnKGbp6ye xGzMxZZCJlooHK4TGIuKvw21nFQQYhYSvVh0Vakt30u6M7B+6qviMf8hL +1BF0gYSDV5zSqMQNWyWWQTAXGJ7rqM5Y5Pzn+HcDaoO/rJF+sn/II8Ns HtKsGqw9zdAwXffoC/MWd44hH4wqybR77GsbgPGU8XwruXTgaIbBwqh2d x9PceNyGxGS89pCVZd6M+I7xpW0sRDhDK0ycrVMTN8LkwXt0czco2SnFY Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10524"; a="372732572" X-IronPort-AV: E=Sophos;i="5.96,145,1665471600"; d="scan'208";a="372732572" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Nov 2022 19:31:29 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10524"; a="614120257" X-IronPort-AV: E=Sophos;i="5.96,145,1665471600"; d="scan'208";a="614120257" Received: from power-sh.sh.intel.com ([10.239.183.122]) by orsmga006.jf.intel.com with ESMTP; 07 Nov 2022 19:31:27 -0800 From: Zhang Rui To: rjw@rjwysocki.net, daniel.lezcano@linaro.org Cc: linux-pm@vger.kernel.org, srinivas.pandruvada@linux.intel.com Subject: [PATCH 6/6] thermal/x86_pkg_temp_thermal: Add support for handling dynamic tjmax Date: Tue, 8 Nov 2022 11:33:32 +0800 Message-Id: <20221108033332.27760-7-rui.zhang@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221108033332.27760-1-rui.zhang@intel.com> References: <20221108033332.27760-1-rui.zhang@intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Tjmax value retrieved from MSR_IA32_TEMPERATURE_TARGET can be changed at runtime when the Intel SST-PP (Intel Speed Select Technology - Performance Profile) level is changed. Enhance the code to use updated tjmax when programming the thermal interrupt thresholds. Signed-off-by: Zhang Rui --- drivers/thermal/intel/x86_pkg_temp_thermal.c | 22 +++++++++++++------- 1 file changed, 15 insertions(+), 7 deletions(-) diff --git a/drivers/thermal/intel/x86_pkg_temp_thermal.c b/drivers/thermal/intel/x86_pkg_temp_thermal.c index cfe905735c62..9a9866a602ec 100644 --- a/drivers/thermal/intel/x86_pkg_temp_thermal.c +++ b/drivers/thermal/intel/x86_pkg_temp_thermal.c @@ -49,7 +49,6 @@ MODULE_PARM_DESC(notify_delay_ms, struct zone_device { int cpu; bool work_scheduled; - u32 tj_max; u32 msr_pkg_therm_low; u32 msr_pkg_therm_high; struct delayed_work work; @@ -125,7 +124,7 @@ static int sys_get_trip_temp(struct thermal_zone_device *tzd, struct zone_device *zonedev = tzd->devdata; unsigned long thres_reg_value; u32 mask, shift, eax, edx; - int ret; + int tj_max, ret; if (trip >= MAX_NUMBER_OF_TRIPS) return -EINVAL; @@ -138,6 +137,11 @@ static int sys_get_trip_temp(struct thermal_zone_device *tzd, shift = THERM_SHIFT_THRESHOLD0; } + ret = intel_tcc_get_tjmax(zonedev->cpu, &tj_max); + if (ret) + return ret; + tj_max *= 1000; + ret = rdmsr_on_cpu(zonedev->cpu, MSR_IA32_PACKAGE_THERM_INTERRUPT, &eax, &edx); if (ret < 0) @@ -145,7 +149,7 @@ static int sys_get_trip_temp(struct thermal_zone_device *tzd, thres_reg_value = (eax & mask) >> shift; if (thres_reg_value) - *temp = zonedev->tj_max - thres_reg_value * 1000; + *temp = tj_max - thres_reg_value * 1000; else *temp = THERMAL_TEMP_INVALID; pr_debug("sys_get_trip_temp %d\n", *temp); @@ -158,9 +162,14 @@ sys_set_trip_temp(struct thermal_zone_device *tzd, int trip, int temp) { struct zone_device *zonedev = tzd->devdata; u32 l, h, mask, shift, intr; - int ret; + int tj_max, ret; + + ret = intel_tcc_get_tjmax(zonedev->cpu, &tj_max); + if (ret) + return ret; + tj_max *= 1000; - if (trip >= MAX_NUMBER_OF_TRIPS || temp >= zonedev->tj_max) + if (trip >= MAX_NUMBER_OF_TRIPS || temp >= tj_max) return -EINVAL; ret = rdmsr_on_cpu(zonedev->cpu, MSR_IA32_PACKAGE_THERM_INTERRUPT, @@ -185,7 +194,7 @@ sys_set_trip_temp(struct thermal_zone_device *tzd, int trip, int temp) if (!temp) { l &= ~intr; } else { - l |= (zonedev->tj_max - temp)/1000 << shift; + l |= (tj_max - temp)/1000 << shift; l |= intr; } @@ -336,7 +345,6 @@ static int pkg_temp_thermal_device_add(unsigned int cpu) INIT_DELAYED_WORK(&zonedev->work, pkg_temp_thermal_threshold_work_fn); zonedev->cpu = cpu; - zonedev->tj_max = tj_max; zonedev->tzone = thermal_zone_device_register("x86_pkg_temp", thres_count, (thres_count == MAX_NUMBER_OF_TRIPS) ? 0x03 : 0x01,