From patchwork Tue Nov 8 12:56:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 13036256 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6D823C433FE for ; Tue, 8 Nov 2022 12:59:14 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1osOB2-0006Rw-8I; Tue, 08 Nov 2022 07:58:04 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1osOB1-0006RE-1d for qemu-devel@nongnu.org; Tue, 08 Nov 2022 07:58:03 -0500 Received: from mail-ot1-x32a.google.com ([2607:f8b0:4864:20::32a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1osOAz-0005oW-Iy for qemu-devel@nongnu.org; Tue, 08 Nov 2022 07:58:02 -0500 Received: by mail-ot1-x32a.google.com with SMTP id 46-20020a9d0631000000b00666823da25fso8328911otn.0 for ; Tue, 08 Nov 2022 04:58:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=f/jrbFGYzUy50fye2d5xQf2USygLwFAgYaKpovyOzEw=; b=D0owSHw1CJzL2OBLtlniNmAjQqHX/H2HQkoZi1hkwvjYdG7d95FcErp7vbLlTEaNZS LR0o6mtv2b7YhNnN22V7T39BaKHIhnGvpYQFO9IpfZTfMUhG7jdVtZBG8sWKCwTn7L1F MrOcmLEVyURue7SmtkP0C48awloiwsV1x+eaEbTrNmLniXHEvSRmrp3ISdTkCLc9kBEG iq6ae3jFhciECZcXAAlAFd4bnVqm3Lq6jx9eeod1MgWLEM9+l8901txLAc7XEOuOOoA/ ZM9GU2AyKJudSlUlYeHRv14vejlqddrb83J2K96t4+kaQVNuCKe/GP+5wtLaTP0Earlw t8tQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=f/jrbFGYzUy50fye2d5xQf2USygLwFAgYaKpovyOzEw=; b=SPA91KTe5OpwMIh7RpZsI3F6Ee8IxlcFsmNn8SWfCaHdZaHXJ7XbgIbc4aVQYFIqED hL0tXcJtFFm10p3f0dp+DLvZDkfIJT5kG0sKFLI4pifh/2DzGYPHBg/aJDJ0gAYRHOvS lzu5SiEJEw7X1OezVq6xHqjARPe79Xizl5o36Zxcvq3QEazHZ5rMXq6Wh2KX1N68R8OW X6o1PLToPYClkTbMkDjBcbTLg0I92DTJT8vXEI0zO3cvef9AVi3tjtDy/3kBjYE5iSxg avHJDA39cdOmkE0ZhyGLQy/1kGOc1nyrWZ18EJdUd3k6dSwa8B6Y+vFSGXAE2/koHKeb TKQg== X-Gm-Message-State: ANoB5pmt/mp2T/Xhy9IxkQImvGD1J4gat9wrdpFRbf/kWF49Uhnxt6Cb zNOJtv8ODItucTQuOHja2Mwxzw== X-Google-Smtp-Source: AA0mqf5nP6xCiMFaTuJv8cxfUUdRkyvlSVDxznONoEf1HGYnWoqDkaAb13ze56uzlwjTy8tgEINIiw== X-Received: by 2002:a05:6830:134b:b0:66c:da9f:732a with SMTP id r11-20020a056830134b00b0066cda9f732amr5708603otq.76.1667912280070; Tue, 08 Nov 2022 04:58:00 -0800 (PST) Received: from anup-ubuntu64-vm.. ([103.97.165.210]) by smtp.gmail.com with ESMTPSA id w15-20020a0568080d4f00b0035a81480ffcsm2342501oik.38.2022.11.08.04.57.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Nov 2022 04:57:59 -0800 (PST) From: Anup Patel To: Peter Maydell , Palmer Dabbelt , Alistair Francis , Sagar Karandikar Cc: Atish Patra , Richard Henderson , Anup Patel , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Anup Patel , Alistair Francis Subject: [PATCH v2 1/5] target/riscv: Typo fix in sstc() predicate Date: Tue, 8 Nov 2022 18:26:59 +0530 Message-Id: <20221108125703.1463577-2-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221108125703.1463577-1-apatel@ventanamicro.com> References: <20221108125703.1463577-1-apatel@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::32a; envelope-from=apatel@ventanamicro.com; helo=mail-ot1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org We should use "&&" instead of "&" when checking hcounteren.TM and henvcfg.STCE bits. Fixes: 3ec0fe18a31f ("target/riscv: Add vstimecmp suppor") Signed-off-by: Anup Patel Reviewed-by: Alistair Francis --- target/riscv/csr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 5c9a7ee287..716f9d960e 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -838,7 +838,7 @@ static RISCVException sstc(CPURISCVState *env, int csrno) } if (riscv_cpu_virt_enabled(env)) { - if (!(get_field(env->hcounteren, COUNTEREN_TM) & + if (!(get_field(env->hcounteren, COUNTEREN_TM) && get_field(env->henvcfg, HENVCFG_STCE))) { return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; } From patchwork Tue Nov 8 12:57:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 13036252 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1ADD0C43217 for ; Tue, 8 Nov 2022 12:58:39 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1osOBM-0006Um-Fy; Tue, 08 Nov 2022 07:58:26 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1osOB9-0006TF-16 for qemu-devel@nongnu.org; Tue, 08 Nov 2022 07:58:11 -0500 Received: from mail-oa1-x2c.google.com ([2001:4860:4864:20::2c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1osOB5-0005pP-Tb for qemu-devel@nongnu.org; Tue, 08 Nov 2022 07:58:10 -0500 Received: by mail-oa1-x2c.google.com with SMTP id 586e51a60fabf-13b6c1c89bdso16091334fac.13 for ; Tue, 08 Nov 2022 04:58:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=7R8KmvJQzLthd8ndwN21jYsULXSllZr6f02cqF8O5YI=; b=JD13XmS9A8mVis2fTVUYrzeVnupO7cYUs9DIJMUrZTWAttQZoz19ycr6987aR+j81d Tf8ksJdpAdwGtnecfwXTpHYWbHOJMs2gFHRbxmOfBzAhvPWsk3ZWhS7NbpS/bmeD8gsg c6yDbREwuXvZ+hEP4NFEiEXNqUchFR1fC//Y1RSl8quVDih/Z6z7dLmYjIKDLw5NCf79 qg1pcQBBGiCLGrEuq3eYilIGWrlsKNJWa4ZBOICBhL//OKq/lYVi6b7Vs2OU0GWlC8XO lOZY6ce0WR72U35SmrYoiswvTA0IAil3jpseeXMk8LoqfYW6DemAakMN1Y2VE9/3aPc3 B/vg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7R8KmvJQzLthd8ndwN21jYsULXSllZr6f02cqF8O5YI=; b=0lJulEWR55mO9JvUN6Szh66ocsz2fCoKM1XOeokcX1NzEzrpF8jesZY1c0XKAalrDy h2O1ng4Xzum4R0/JG5E/le8tttIlx4iGl8dHzc5bg71ulx06WSTEZHeHCvSvb8d3dsxQ ExjDnuEdQThdnQlGSBDGekN1uPITYb8ALGyirKGCdszWfJ1zxwjg/P/k8x5m3NurRyw/ 9c2+invnWSiVHhCDlGh1EQhAnYHu2ymENAvyV4AWJz36jITahaYiOzGVRNRolQPb/cL7 z5tWu4EhzBcWXWSHJhpjiTkxA/DRdHBQ53ESzmZhEPw7SrplOfbh9RnIoRxhxRRkY/nY NgCw== X-Gm-Message-State: ACrzQf3XreVrEYlnYYwEvD2iXe8k2rvFSkKPnjrKbEevBiKxpnJD23+X EqgJe7Hh5J4nxGFQTuUwqCZOQA== X-Google-Smtp-Source: AMsMyM7BDaqmX4Gwda4zHPGCnGB+BwTb+Flrm2TD9nQNClUP9ZiDvcd0I6ihX2DcCh+tS5dHG88l9A== X-Received: by 2002:a05:6870:5b84:b0:131:e064:747c with SMTP id em4-20020a0568705b8400b00131e064747cmr43913730oab.273.1667912284953; Tue, 08 Nov 2022 04:58:04 -0800 (PST) Received: from anup-ubuntu64-vm.. ([103.97.165.210]) by smtp.gmail.com with ESMTPSA id w15-20020a0568080d4f00b0035a81480ffcsm2342501oik.38.2022.11.08.04.58.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Nov 2022 04:58:04 -0800 (PST) From: Anup Patel To: Peter Maydell , Palmer Dabbelt , Alistair Francis , Sagar Karandikar Cc: Atish Patra , Richard Henderson , Anup Patel , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Anup Patel , Alistair Francis Subject: [PATCH v2 2/5] target/riscv: Update VS timer whenever htimedelta changes Date: Tue, 8 Nov 2022 18:27:00 +0530 Message-Id: <20221108125703.1463577-3-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221108125703.1463577-1-apatel@ventanamicro.com> References: <20221108125703.1463577-1-apatel@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2001:4860:4864:20::2c; envelope-from=apatel@ventanamicro.com; helo=mail-oa1-x2c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The htimedelta[h] CSR has impact on the VS timer comparison so we should call riscv_timer_write_timecmp() whenever htimedelta changes. Fixes: 3ec0fe18a31f ("target/riscv: Add vstimecmp suppor") Signed-off-by: Anup Patel Reviewed-by: Alistair Francis --- target/riscv/csr.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 716f9d960e..4b1a608260 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -2722,6 +2722,8 @@ static RISCVException read_htimedelta(CPURISCVState *env, int csrno, static RISCVException write_htimedelta(CPURISCVState *env, int csrno, target_ulong val) { + RISCVCPU *cpu = env_archcpu(env); + if (!env->rdtime_fn) { return RISCV_EXCP_ILLEGAL_INST; } @@ -2731,6 +2733,12 @@ static RISCVException write_htimedelta(CPURISCVState *env, int csrno, } else { env->htimedelta = val; } + + if (cpu->cfg.ext_sstc && env->rdtime_fn) { + riscv_timer_write_timecmp(cpu, env->vstimer, env->vstimecmp, + env->htimedelta, MIP_VSTIP); + } + return RISCV_EXCP_NONE; } @@ -2748,11 +2756,19 @@ static RISCVException read_htimedeltah(CPURISCVState *env, int csrno, static RISCVException write_htimedeltah(CPURISCVState *env, int csrno, target_ulong val) { + RISCVCPU *cpu = env_archcpu(env); + if (!env->rdtime_fn) { return RISCV_EXCP_ILLEGAL_INST; } env->htimedelta = deposit64(env->htimedelta, 32, 32, (uint64_t)val); + + if (cpu->cfg.ext_sstc && env->rdtime_fn) { + riscv_timer_write_timecmp(cpu, env->vstimer, env->vstimecmp, + env->htimedelta, MIP_VSTIP); + } + return RISCV_EXCP_NONE; } From patchwork Tue Nov 8 12:57:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 13036253 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 27936C4332F for ; Tue, 8 Nov 2022 12:58:43 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1osOBT-0006Zl-Pw; Tue, 08 Nov 2022 07:58:31 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1osOBA-0006Tf-Py for qemu-devel@nongnu.org; Tue, 08 Nov 2022 07:58:13 -0500 Received: from mail-oi1-x22c.google.com ([2607:f8b0:4864:20::22c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1osOB9-0005qJ-4n for qemu-devel@nongnu.org; Tue, 08 Nov 2022 07:58:12 -0500 Received: by mail-oi1-x22c.google.com with SMTP id h132so7531752oif.2 for ; Tue, 08 Nov 2022 04:58:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=0xhD3CLA0c9U1Rhojr/MSgAAnAVHwGEX5bLXtLBauhM=; b=BOMPjZuqBFjGVBuYPMXHhA7T/hGudF6OcV5kmwAh/0DGD/+tWHJtmWP6t68hywwcRU scYdslrq4RHt4ZbTqsgyzOBG35iGEJp04pUguDn4mNyFz+B3UXIzxqPEPZXrn2FY1GuP FoaLJYSb+B44ppwDRvV2LN7KkGymI9ZzS4n67bKU85Yrao1J4Vsb78fOLh8jacKgw6j3 T1ie+RGPkvzF1jiDtts1Hr6uFCz29uwFkYNWO3n/sLfljUdRDfHTkzHwF/qPRmytwdCD Bv19CrwfQeULx+YAcRS40Jemg4J4ziV79yKnDVEgJuQEnomahdcQ5Na1VK3URjD8/Gbm Vd6g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0xhD3CLA0c9U1Rhojr/MSgAAnAVHwGEX5bLXtLBauhM=; b=ht5GGtlOB8CkUMeBXASXtUt8VLc5HK+bKqxWoNl9kyhDHdwhf6G+C2zH0qzNoKQPJH QsjS6EnC3gXoSuDpbRevw3FLlsOBeM/FeoS7mZcXhbM94vH0HUmIi1Btrf7BkCQGEkAZ elJfsv3zMActZfoCA3qpNlGig5oMS9AAin7ov231m+LBCV7yriuvLgVZCfvZZftILgmX AYAm6YnIm9ls04EzzgHAvfjpsdvcTlI1sUuGO50gm4lOT4W3nnExo/D3+MuqoDxOKXiK 7DMRomPPve9bUYl9JA7iwRMe4BacNX6SRw3CRALvGeigPmKYvsPzVFFGaTO/CflSrJIX ZarA== X-Gm-Message-State: ACrzQf055izi1rN6732zbqtekHTlSGKWy6PDOEfFVKt4fL847EQFHe1K /Z+4V5ZCgNTpR4rHpxpWuOqk3Q== X-Google-Smtp-Source: AMsMyM4a51uuQtNg7QF4wF7iGLbqKHA5uNdd2ySMb+1G96oSCn/c5K3ZHh59QBXdRy7QXsMjNtDC+g== X-Received: by 2002:a05:6808:11c8:b0:353:f092:f11b with SMTP id p8-20020a05680811c800b00353f092f11bmr28968853oiv.239.1667912289960; Tue, 08 Nov 2022 04:58:09 -0800 (PST) Received: from anup-ubuntu64-vm.. ([103.97.165.210]) by smtp.gmail.com with ESMTPSA id w15-20020a0568080d4f00b0035a81480ffcsm2342501oik.38.2022.11.08.04.58.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Nov 2022 04:58:09 -0800 (PST) From: Anup Patel To: Peter Maydell , Palmer Dabbelt , Alistair Francis , Sagar Karandikar Cc: Atish Patra , Richard Henderson , Anup Patel , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Anup Patel , Alistair Francis Subject: [PATCH v2 3/5] target/riscv: Don't clear mask in riscv_cpu_update_mip() for VSTIP Date: Tue, 8 Nov 2022 18:27:01 +0530 Message-Id: <20221108125703.1463577-4-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221108125703.1463577-1-apatel@ventanamicro.com> References: <20221108125703.1463577-1-apatel@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::22c; envelope-from=apatel@ventanamicro.com; helo=mail-oi1-x22c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Instead of clearing mask in riscv_cpu_update_mip() for VSTIP, we should call riscv_cpu_update_mip() with mask == 0 from timer_helper.c for VSTIP. Fixes: 3ec0fe18a31f ("target/riscv: Add vstimecmp suppor") Signed-off-by: Anup Patel Reviewed-by: Alistair Francis --- target/riscv/cpu_helper.c | 2 -- target/riscv/time_helper.c | 12 ++++++++---- 2 files changed, 8 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 5d66246c2c..a403825e49 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -617,8 +617,6 @@ uint64_t riscv_cpu_update_mip(RISCVCPU *cpu, uint64_t mask, uint64_t value) vsgein = (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0; } - /* No need to update mip for VSTIP */ - mask = ((mask == MIP_VSTIP) && env->vstime_irq) ? 0 : mask; vstip = env->vstime_irq ? MIP_VSTIP : 0; if (!qemu_mutex_iothread_locked()) { diff --git a/target/riscv/time_helper.c b/target/riscv/time_helper.c index 8cce667dfd..4fb2a471a9 100644 --- a/target/riscv/time_helper.c +++ b/target/riscv/time_helper.c @@ -27,7 +27,7 @@ static void riscv_vstimer_cb(void *opaque) RISCVCPU *cpu = opaque; CPURISCVState *env = &cpu->env; env->vstime_irq = 1; - riscv_cpu_update_mip(cpu, MIP_VSTIP, BOOL_TO_MASK(1)); + riscv_cpu_update_mip(cpu, 0, BOOL_TO_MASK(1)); } static void riscv_stimer_cb(void *opaque) @@ -57,16 +57,20 @@ void riscv_timer_write_timecmp(RISCVCPU *cpu, QEMUTimer *timer, */ if (timer_irq == MIP_VSTIP) { env->vstime_irq = 1; + riscv_cpu_update_mip(cpu, 0, BOOL_TO_MASK(1)); + } else { + riscv_cpu_update_mip(cpu, MIP_STIP, BOOL_TO_MASK(1)); } - riscv_cpu_update_mip(cpu, timer_irq, BOOL_TO_MASK(1)); return; } + /* Clear the [VS|S]TIP bit in mip */ if (timer_irq == MIP_VSTIP) { env->vstime_irq = 0; + riscv_cpu_update_mip(cpu, 0, BOOL_TO_MASK(0)); + } else { + riscv_cpu_update_mip(cpu, timer_irq, BOOL_TO_MASK(0)); } - /* Clear the [V]STIP bit in mip */ - riscv_cpu_update_mip(cpu, timer_irq, BOOL_TO_MASK(0)); /* otherwise, set up the future timer interrupt */ diff = timecmp - rtc_r; From patchwork Tue Nov 8 12:57:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 13036255 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 78A6EC43217 for ; Tue, 8 Nov 2022 12:59:12 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1osOBY-0006dB-5Z; Tue, 08 Nov 2022 07:58:36 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1osOBI-0006Uh-8L for qemu-devel@nongnu.org; Tue, 08 Nov 2022 07:58:20 -0500 Received: from mail-oa1-x2b.google.com ([2001:4860:4864:20::2b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1osOBF-0005rE-Df for qemu-devel@nongnu.org; Tue, 08 Nov 2022 07:58:19 -0500 Received: by mail-oa1-x2b.google.com with SMTP id 586e51a60fabf-1322d768ba7so16131725fac.5 for ; Tue, 08 Nov 2022 04:58:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=w6GWMr4kgqdcL841ipfLZDMDmhXesxTjEaat87znEVA=; b=I0fQvR35NsBac/lA5tB9dg7ivIGVXG/70tNbsPHc459HqX4D6Uz1+gjUX7JM5wvbuz SorCh1LHylLoRNjgHtCVYasAEaZkGBfv/rEaBqZU2IWXR/tHCoGbxD9Z70pMXEa5rrna /NLEOLbXrgQRaq5BciETJf59KE6PwbYDvJHDOSg0EMRLXS20IVNHHVai0So/CbObWqxu FFTCWNPgMgf2yehyUZbm8zECIRR1lVlLxpmdhLVPcASIQJwINAoh3K3S/ArWSMiuBqXs o0usyWyVfrZm23TfvYhFPSPndtGm5Jhjpb+na4XLp0HIRvDL16C2ug/0X+zgpOaD84xT Fg1g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=w6GWMr4kgqdcL841ipfLZDMDmhXesxTjEaat87znEVA=; b=mPkf/tMMC4FGUsqo6kkpUvvNc79lGsPu3gwS3RpkqzcaGOuSKh3S81YjDrLnZWlUfe zOskmw6JeB4jNf376e4qxsKWCGTJUJi6sHOvdwifIHeHeHCI60eOWKJuTNDrCKYlflzl IAX3c/YnKkvC9JtCMzOjkLdJ8bmIDa02zz+aeZn4ywbH0DGpbSt3ioUrBKwNiAJwArum qS4KTFqUpPI4pAftXsf+9ksVe4rAPncorQvtKLAuJ+LZA38X57sTBAihwJrA7zyk0OtF xZTj3iDOjZBkXasvcP2VE4fnE+e6xmNBOBLc0DXOyEMCvvlHz4ApBgtsfy08btHPYzTs a7SA== X-Gm-Message-State: ACrzQf1NqeuL/kBfOYnLfKIk83FeYcv2kRc5MWhTQNpPY+ZLM8FU082K o5MthdTm6T0xekmMprtNI+FPcw== X-Google-Smtp-Source: AMsMyM41Rg1WOvW6s84W2IAblnX816c2VOs+Ps4mc0GoFwlkddZeOH0A8M26q/eqH1iH/4LCNoJcfg== X-Received: by 2002:a05:6870:b526:b0:13a:e945:dad4 with SMTP id v38-20020a056870b52600b0013ae945dad4mr33517421oap.12.1667912295000; Tue, 08 Nov 2022 04:58:15 -0800 (PST) Received: from anup-ubuntu64-vm.. ([103.97.165.210]) by smtp.gmail.com with ESMTPSA id w15-20020a0568080d4f00b0035a81480ffcsm2342501oik.38.2022.11.08.04.58.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Nov 2022 04:58:14 -0800 (PST) From: Anup Patel To: Peter Maydell , Palmer Dabbelt , Alistair Francis , Sagar Karandikar Cc: Atish Patra , Richard Henderson , Anup Patel , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Anup Patel , Alistair Francis Subject: [PATCH v2 4/5] target/riscv: No need to re-start QEMU timer when timecmp == UINT64_MAX Date: Tue, 8 Nov 2022 18:27:02 +0530 Message-Id: <20221108125703.1463577-5-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221108125703.1463577-1-apatel@ventanamicro.com> References: <20221108125703.1463577-1-apatel@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2001:4860:4864:20::2b; envelope-from=apatel@ventanamicro.com; helo=mail-oa1-x2b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The time CSR will wrap-around immediately after reaching UINT64_MAX so we don't need to re-start QEMU timer when timecmp == UINT64_MAX in riscv_timer_write_timecmp(). Signed-off-by: Anup Patel Reviewed-by: Alistair Francis --- target/riscv/time_helper.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/target/riscv/time_helper.c b/target/riscv/time_helper.c index 4fb2a471a9..b654f91af9 100644 --- a/target/riscv/time_helper.c +++ b/target/riscv/time_helper.c @@ -72,6 +72,30 @@ void riscv_timer_write_timecmp(RISCVCPU *cpu, QEMUTimer *timer, riscv_cpu_update_mip(cpu, timer_irq, BOOL_TO_MASK(0)); } + /* + * Sstc specification says the following about timer interrupt: + * "A supervisor timer interrupt becomes pending - as reflected in + * the STIP bit in the mip and sip registers - whenever time contains + * a value greater than or equal to stimecmp, treating the values + * as unsigned integers. Writes to stimecmp are guaranteed to be + * reflected in STIP eventually, but not necessarily immediately. + * The interrupt remains posted until stimecmp becomes greater + * than time - typically as a result of writing stimecmp." + * + * When timecmp = UINT64_MAX, the time CSR will eventually reach + * timecmp value but on next timer tick the time CSR will wrap-around + * and become zero which is less than UINT64_MAX. Now, the timer + * interrupt behaves like a level triggered interrupt so it will + * become 1 when time = timecmp = UINT64_MAX and next timer tick + * it will become 0 again because time = 0 < timecmp = UINT64_MAX. + * + * Based on above, we don't re-start the QEMU timer when timecmp + * equals UINT64_MAX. + */ + if (timecmp == UINT64_MAX) { + return; + } + /* otherwise, set up the future timer interrupt */ diff = timecmp - rtc_r; /* back to ns (note args switched in muldiv64) */ From patchwork Tue Nov 8 12:57:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 13036254 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 04A2FC433FE for ; Tue, 8 Nov 2022 12:59:04 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1osOBY-0006eD-UM; Tue, 08 Nov 2022 07:58:36 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1osOBN-0006Wz-Mr for qemu-devel@nongnu.org; Tue, 08 Nov 2022 07:58:26 -0500 Received: from mail-oa1-x2c.google.com ([2001:4860:4864:20::2c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1osOBI-0005pP-MK for qemu-devel@nongnu.org; Tue, 08 Nov 2022 07:58:25 -0500 Received: by mail-oa1-x2c.google.com with SMTP id 586e51a60fabf-13b6c1c89bdso16092071fac.13 for ; Tue, 08 Nov 2022 04:58:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=SFXOtEFct7aZBn9qsLOf6vADmM9nDSRAlMOl6gM3bOU=; b=d9DIGKlp3/H3zKXQjsgXloo+q9f6M+lFAYH+7FQN+AAHGVbyyviR2Rf+tRo9JEMwh4 Cp0Ql/c5VxxOW4fMY0lRlQgnBRireVBnVocGhgJiloSGvZWLKhjBeDgmttUlh2wI54bb nXM7iHM+68YYbg95cC3rRUSrPItQpWBEoZT6ggqyXyHbSlTFWvZadjMInHfywRvHbYAc 7e2bB/OcdFq3FJ8oD8u3KmgcWy4uueZSU4T04oePv5BSAql2aPnl371jmpyjWwaEA189 +QkrGyfDxTFzAJckFLSzQoyMsWnHwOWn+r0wmoJ2g6wRngNEjwgIn4/W9VCGxBpkiscu LIuw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=SFXOtEFct7aZBn9qsLOf6vADmM9nDSRAlMOl6gM3bOU=; b=5UPm0OZdpwRQVDPWGwIZlJ+v3CTxWXBDaZe/sWL9lYo6a1Kn4e+wxSipA4Z/FqTk3W 5Eqb7+Bj86+Q/NQKY2LCPhBNUR6nlq6A0GAMNkiCW8NO9ArZ/ohgTlncMsMTiqNXnLlA Rv9hfFXgic481OAGJVkjfKbHxg4fYEw49toL1E6Q7SsxmlZQW+oJo1uf80d3dOoJMajq /A/7cbdEksOiD7qMEms1X5d+ntBR5dwF40+0Sc9bms44dLa6bY16F/xRkGpjUvMjqeZ+ qO8+AxW45AUjht4Homz3hx668P2l4YR60mDvwS48nFcgEFI3HRwQn0CynRkR/v9BbEzR 6Hvw== X-Gm-Message-State: ACrzQf2aUbNd/W3ruS4iM3kZLnYuRBOEdEbZSzlTcmPuAfgRG4F4DOmP kd60FlbHDU8gtRxz8SPyr+4BuA== X-Google-Smtp-Source: AMsMyM4sV8tpDE3Tk4lbBxlkATd8acT+EwA4p9ddYCQJD2AAyutnyT2oqH9wJTLhNGrTvl/twgfETA== X-Received: by 2002:a05:6870:d28c:b0:130:efc6:9790 with SMTP id d12-20020a056870d28c00b00130efc69790mr43807656oae.2.1667912299882; Tue, 08 Nov 2022 04:58:19 -0800 (PST) Received: from anup-ubuntu64-vm.. ([103.97.165.210]) by smtp.gmail.com with ESMTPSA id w15-20020a0568080d4f00b0035a81480ffcsm2342501oik.38.2022.11.08.04.58.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Nov 2022 04:58:19 -0800 (PST) From: Anup Patel To: Peter Maydell , Palmer Dabbelt , Alistair Francis , Sagar Karandikar Cc: Atish Patra , Richard Henderson , Anup Patel , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Anup Patel Subject: [PATCH v2 5/5] target/riscv: Ensure opcode is saved for all relevant instructions Date: Tue, 8 Nov 2022 18:27:03 +0530 Message-Id: <20221108125703.1463577-6-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221108125703.1463577-1-apatel@ventanamicro.com> References: <20221108125703.1463577-1-apatel@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2001:4860:4864:20::2c; envelope-from=apatel@ventanamicro.com; helo=mail-oa1-x2c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org We should call decode_save_opc() for all relevant instructions which can potentially generate a virtual instruction fault or a guest page fault because generating transformed instruction upon guest page fault expects opcode to be available. Without this, hypervisor will see transformed instruction as zero in htinst CSR for guest MMIO emulation which makes MMIO emulation in hypervisor slow and also breaks nested virtualization. Fixes: a9814e3e08d2 ("target/riscv: Minimize the calls to decode_save_opc") Signed-off-by: Anup Patel Reviewed-by: Alistair Francis --- target/riscv/insn_trans/trans_rva.c.inc | 10 +++++++--- target/riscv/insn_trans/trans_rvd.c.inc | 2 ++ target/riscv/insn_trans/trans_rvf.c.inc | 2 ++ target/riscv/insn_trans/trans_rvh.c.inc | 3 +++ target/riscv/insn_trans/trans_rvi.c.inc | 2 ++ target/riscv/insn_trans/trans_rvzfh.c.inc | 2 ++ target/riscv/insn_trans/trans_svinval.c.inc | 3 +++ 7 files changed, 21 insertions(+), 3 deletions(-) diff --git a/target/riscv/insn_trans/trans_rva.c.inc b/target/riscv/insn_trans/trans_rva.c.inc index 45db82c9be..5f194a447b 100644 --- a/target/riscv/insn_trans/trans_rva.c.inc +++ b/target/riscv/insn_trans/trans_rva.c.inc @@ -20,8 +20,10 @@ static bool gen_lr(DisasContext *ctx, arg_atomic *a, MemOp mop) { - TCGv src1 = get_address(ctx, a->rs1, 0); + TCGv src1; + decode_save_opc(ctx); + src1 = get_address(ctx, a->rs1, 0); if (a->rl) { tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); } @@ -43,6 +45,7 @@ static bool gen_sc(DisasContext *ctx, arg_atomic *a, MemOp mop) TCGLabel *l1 = gen_new_label(); TCGLabel *l2 = gen_new_label(); + decode_save_opc(ctx); src1 = get_address(ctx, a->rs1, 0); tcg_gen_brcond_tl(TCG_COND_NE, load_res, src1, l1); @@ -81,9 +84,10 @@ static bool gen_amo(DisasContext *ctx, arg_atomic *a, MemOp mop) { TCGv dest = dest_gpr(ctx, a->rd); - TCGv src1 = get_address(ctx, a->rs1, 0); - TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); + TCGv src1, src2 = get_gpr(ctx, a->rs2, EXT_NONE); + decode_save_opc(ctx); + src1 = get_address(ctx, a->rs1, 0); func(dest, src1, src2, ctx->mem_idx, mop); gen_set_gpr(ctx, a->rd, dest); diff --git a/target/riscv/insn_trans/trans_rvd.c.inc b/target/riscv/insn_trans/trans_rvd.c.inc index 1397c1ce1c..6e3159b797 100644 --- a/target/riscv/insn_trans/trans_rvd.c.inc +++ b/target/riscv/insn_trans/trans_rvd.c.inc @@ -38,6 +38,7 @@ static bool trans_fld(DisasContext *ctx, arg_fld *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVD); + decode_save_opc(ctx); addr = get_address(ctx, a->rs1, a->imm); tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], addr, ctx->mem_idx, MO_TEUQ); @@ -52,6 +53,7 @@ static bool trans_fsd(DisasContext *ctx, arg_fsd *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVD); + decode_save_opc(ctx); addr = get_address(ctx, a->rs1, a->imm); tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], addr, ctx->mem_idx, MO_TEUQ); return true; diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_trans/trans_rvf.c.inc index a1d3eb52ad..965e1f8d11 100644 --- a/target/riscv/insn_trans/trans_rvf.c.inc +++ b/target/riscv/insn_trans/trans_rvf.c.inc @@ -38,6 +38,7 @@ static bool trans_flw(DisasContext *ctx, arg_flw *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); + decode_save_opc(ctx); addr = get_address(ctx, a->rs1, a->imm); dest = cpu_fpr[a->rd]; tcg_gen_qemu_ld_i64(dest, addr, ctx->mem_idx, MO_TEUL); @@ -54,6 +55,7 @@ static bool trans_fsw(DisasContext *ctx, arg_fsw *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); + decode_save_opc(ctx); addr = get_address(ctx, a->rs1, a->imm); tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], addr, ctx->mem_idx, MO_TEUL); return true; diff --git a/target/riscv/insn_trans/trans_rvh.c.inc b/target/riscv/insn_trans/trans_rvh.c.inc index 4f8aecddc7..9248b48c36 100644 --- a/target/riscv/insn_trans/trans_rvh.c.inc +++ b/target/riscv/insn_trans/trans_rvh.c.inc @@ -36,6 +36,7 @@ static bool do_hlv(DisasContext *ctx, arg_r2 *a, MemOp mop) #ifdef CONFIG_USER_ONLY return false; #else + decode_save_opc(ctx); if (check_access(ctx)) { TCGv dest = dest_gpr(ctx, a->rd); TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE); @@ -82,6 +83,7 @@ static bool do_hsv(DisasContext *ctx, arg_r2_s *a, MemOp mop) #ifdef CONFIG_USER_ONLY return false; #else + decode_save_opc(ctx); if (check_access(ctx)) { TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE); TCGv data = get_gpr(ctx, a->rs2, EXT_NONE); @@ -135,6 +137,7 @@ static bool trans_hsv_d(DisasContext *ctx, arg_hsv_d *a) static bool do_hlvx(DisasContext *ctx, arg_r2 *a, void (*func)(TCGv, TCGv_env, TCGv)) { + decode_save_opc(ctx); if (check_access(ctx)) { TCGv dest = dest_gpr(ctx, a->rd); TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE); diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc index c49dbec0eb..1665efb639 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -261,6 +261,7 @@ static bool gen_load_i128(DisasContext *ctx, arg_lb *a, MemOp memop) static bool gen_load(DisasContext *ctx, arg_lb *a, MemOp memop) { + decode_save_opc(ctx); if (get_xl(ctx) == MXL_RV128) { return gen_load_i128(ctx, a, memop); } else { @@ -350,6 +351,7 @@ static bool gen_store_i128(DisasContext *ctx, arg_sb *a, MemOp memop) static bool gen_store(DisasContext *ctx, arg_sb *a, MemOp memop) { + decode_save_opc(ctx); if (get_xl(ctx) == MXL_RV128) { return gen_store_i128(ctx, a, memop); } else { diff --git a/target/riscv/insn_trans/trans_rvzfh.c.inc b/target/riscv/insn_trans/trans_rvzfh.c.inc index 5d07150cd0..2ad5716312 100644 --- a/target/riscv/insn_trans/trans_rvzfh.c.inc +++ b/target/riscv/insn_trans/trans_rvzfh.c.inc @@ -49,6 +49,7 @@ static bool trans_flh(DisasContext *ctx, arg_flh *a) REQUIRE_FPU; REQUIRE_ZFH_OR_ZFHMIN(ctx); + decode_save_opc(ctx); t0 = get_gpr(ctx, a->rs1, EXT_NONE); if (a->imm) { TCGv temp = temp_new(ctx); @@ -71,6 +72,7 @@ static bool trans_fsh(DisasContext *ctx, arg_fsh *a) REQUIRE_FPU; REQUIRE_ZFH_OR_ZFHMIN(ctx); + decode_save_opc(ctx); t0 = get_gpr(ctx, a->rs1, EXT_NONE); if (a->imm) { TCGv temp = tcg_temp_new(); diff --git a/target/riscv/insn_trans/trans_svinval.c.inc b/target/riscv/insn_trans/trans_svinval.c.inc index 2682bd969f..f3cd7d5c0b 100644 --- a/target/riscv/insn_trans/trans_svinval.c.inc +++ b/target/riscv/insn_trans/trans_svinval.c.inc @@ -28,6 +28,7 @@ static bool trans_sinval_vma(DisasContext *ctx, arg_sinval_vma *a) /* Do the same as sfence.vma currently */ REQUIRE_EXT(ctx, RVS); #ifndef CONFIG_USER_ONLY + decode_save_opc(ctx); gen_helper_tlb_flush(cpu_env); return true; #endif @@ -56,6 +57,7 @@ static bool trans_hinval_vvma(DisasContext *ctx, arg_hinval_vvma *a) /* Do the same as hfence.vvma currently */ REQUIRE_EXT(ctx, RVH); #ifndef CONFIG_USER_ONLY + decode_save_opc(ctx); gen_helper_hyp_tlb_flush(cpu_env); return true; #endif @@ -68,6 +70,7 @@ static bool trans_hinval_gvma(DisasContext *ctx, arg_hinval_gvma *a) /* Do the same as hfence.gvma currently */ REQUIRE_EXT(ctx, RVH); #ifndef CONFIG_USER_ONLY + decode_save_opc(ctx); gen_helper_hyp_gvma_tlb_flush(cpu_env); return true; #endif