From patchwork Wed Nov 9 08:25:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matt Ranostay X-Patchwork-Id: 13037246 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5BF2CC4332F for ; Wed, 9 Nov 2022 08:26:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229669AbiKII02 (ORCPT ); Wed, 9 Nov 2022 03:26:28 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39434 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229816AbiKII01 (ORCPT ); Wed, 9 Nov 2022 03:26:27 -0500 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9CC8D13F99 for ; Wed, 9 Nov 2022 00:26:25 -0800 (PST) Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 2A98Q5H3114264; Wed, 9 Nov 2022 02:26:05 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1667982366; bh=e2s8VocYp+n5PltoJno7/n82zHqJ2YvwboQOcALX6Cw=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=AKI4BH5oJ6SpUVGVEg+E4r4WfJJOGTYXtF1tFmYQ6yoPxVaYUXE3pu9hnjRi2MROJ sb8X1gCMOvCdftchwXpxPIgd3S1y9g5RbajnN+LzP+qz5aKCHf4GhoFpvpC87RZm0C EMkynHVJxNiGS7LBWYH9cMtjSWCnXr3raozQkIxQ= Received: from DFLE113.ent.ti.com (dfle113.ent.ti.com [10.64.6.34]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 2A98Q5Kp034564 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 9 Nov 2022 02:26:05 -0600 Received: from DFLE112.ent.ti.com (10.64.6.33) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6; Wed, 9 Nov 2022 02:26:05 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6 via Frontend Transport; Wed, 9 Nov 2022 02:26:05 -0600 Received: from localhost (ileaxei01-snat.itg.ti.com [10.180.69.5]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 2A98Q2Ls067988; Wed, 9 Nov 2022 02:26:04 -0600 From: Matt Ranostay To: , , , , CC: , , Matt Ranostay Subject: [PATCH v5 1/4] PCI: j721e: Add per platform maximum lane settings Date: Wed, 9 Nov 2022 00:25:53 -0800 Message-ID: <20221109082556.29265-2-mranostay@ti.com> X-Mailer: git-send-email 2.38.GIT In-Reply-To: <20221109082556.29265-1-mranostay@ti.com> References: <20221109082556.29265-1-mranostay@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Various platforms have different maximum amount of lanes that can be selected. Add max_lanes to struct j721e_pcie to allow for error checking on num-lanes selection from device tree. Signed-off-by: Matt Ranostay Signed-off-by: Vignesh Raghavendra --- drivers/pci/controller/cadence/pci-j721e.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c index a82f845cc4b5..875224d34958 100644 --- a/drivers/pci/controller/cadence/pci-j721e.c +++ b/drivers/pci/controller/cadence/pci-j721e.c @@ -48,8 +48,6 @@ enum link_status { #define GENERATION_SEL_MASK GENMASK(1, 0) -#define MAX_LANES 2 - struct j721e_pcie { struct cdns_pcie *cdns_pcie; struct clk *refclk; @@ -72,6 +70,7 @@ struct j721e_pcie_data { unsigned int quirk_disable_flr:1; u32 linkdown_irq_regfield; unsigned int byte_access_allowed:1; + unsigned int max_lanes; }; static inline u32 j721e_pcie_user_readl(struct j721e_pcie *pcie, u32 offset) @@ -291,11 +290,13 @@ static const struct j721e_pcie_data j721e_pcie_rc_data = { .quirk_retrain_flag = true, .byte_access_allowed = false, .linkdown_irq_regfield = LINK_DOWN, + .max_lanes = 2, }; static const struct j721e_pcie_data j721e_pcie_ep_data = { .mode = PCI_MODE_EP, .linkdown_irq_regfield = LINK_DOWN, + .max_lanes = 2, }; static const struct j721e_pcie_data j7200_pcie_rc_data = { @@ -303,23 +304,27 @@ static const struct j721e_pcie_data j7200_pcie_rc_data = { .quirk_detect_quiet_flag = true, .linkdown_irq_regfield = J7200_LINK_DOWN, .byte_access_allowed = true, + .max_lanes = 2, }; static const struct j721e_pcie_data j7200_pcie_ep_data = { .mode = PCI_MODE_EP, .quirk_detect_quiet_flag = true, .quirk_disable_flr = true, + .max_lanes = 2, }; static const struct j721e_pcie_data am64_pcie_rc_data = { .mode = PCI_MODE_RC, .linkdown_irq_regfield = J7200_LINK_DOWN, .byte_access_allowed = true, + .max_lanes = 1, }; static const struct j721e_pcie_data am64_pcie_ep_data = { .mode = PCI_MODE_EP, .linkdown_irq_regfield = J7200_LINK_DOWN, + .max_lanes = 1, }; static const struct of_device_id of_j721e_pcie_match[] = { @@ -433,7 +438,7 @@ static int j721e_pcie_probe(struct platform_device *pdev) pcie->user_cfg_base = base; ret = of_property_read_u32(node, "num-lanes", &num_lanes); - if (ret || num_lanes > MAX_LANES) + if (ret || num_lanes > data->max_lanes) num_lanes = 1; pcie->num_lanes = num_lanes; From patchwork Wed Nov 9 08:25:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matt Ranostay X-Patchwork-Id: 13037243 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2C0EAC4332F for ; Wed, 9 Nov 2022 08:26:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229687AbiKII0T (ORCPT ); Wed, 9 Nov 2022 03:26:19 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39292 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229526AbiKII0S (ORCPT ); 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Wed, 9 Nov 2022 02:26:10 -0600 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6 via Frontend Transport; Wed, 9 Nov 2022 02:26:10 -0600 Received: from localhost (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 2A98Q78m014421; Wed, 9 Nov 2022 02:26:09 -0600 From: Matt Ranostay To: , , , , CC: , , Matt Ranostay Subject: [PATCH v5 2/4] PCI: j721e: Add PCIe 4x lane selection support Date: Wed, 9 Nov 2022 00:25:54 -0800 Message-ID: <20221109082556.29265-3-mranostay@ti.com> X-Mailer: git-send-email 2.38.GIT In-Reply-To: <20221109082556.29265-1-mranostay@ti.com> References: <20221109082556.29265-1-mranostay@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add support for setting of two-bit field that allows selection of 4x lane PCIe which was previously limited to only 2x lanes. Signed-off-by: Matt Ranostay Reviewed-by: Vignesh Raghavendra --- drivers/pci/controller/cadence/pci-j721e.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c index 875224d34958..efd065bc0104 100644 --- a/drivers/pci/controller/cadence/pci-j721e.c +++ b/drivers/pci/controller/cadence/pci-j721e.c @@ -43,7 +43,6 @@ enum link_status { }; #define J721E_MODE_RC BIT(7) -#define LANE_COUNT_MASK BIT(8) #define LANE_COUNT(n) ((n) << 8) #define GENERATION_SEL_MASK GENMASK(1, 0) @@ -53,6 +52,7 @@ struct j721e_pcie { struct clk *refclk; u32 mode; u32 num_lanes; + u32 max_lanes; void __iomem *user_cfg_base; void __iomem *intd_cfg_base; u32 linkdown_irq_regfield; @@ -206,11 +206,15 @@ static int j721e_pcie_set_lane_count(struct j721e_pcie *pcie, { struct device *dev = pcie->cdns_pcie->dev; u32 lanes = pcie->num_lanes; + u32 mask = GENMASK(8, 8); u32 val = 0; int ret; + if (pcie->max_lanes == 4) + mask = GENMASK(9, 8); + val = LANE_COUNT(lanes - 1); - ret = regmap_update_bits(syscon, offset, LANE_COUNT_MASK, val); + ret = regmap_update_bits(syscon, offset, mask, val); if (ret) dev_err(dev, "failed to set link count\n"); @@ -440,6 +444,8 @@ static int j721e_pcie_probe(struct platform_device *pdev) ret = of_property_read_u32(node, "num-lanes", &num_lanes); if (ret || num_lanes > data->max_lanes) num_lanes = 1; + + pcie->max_lanes = data->max_lanes; pcie->num_lanes = num_lanes; if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48))) From patchwork Wed Nov 9 08:25:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matt Ranostay X-Patchwork-Id: 13037245 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9B1ABC433FE for ; Wed, 9 Nov 2022 08:26:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229781AbiKII01 (ORCPT ); Wed, 9 Nov 2022 03:26:27 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39402 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229784AbiKII0Z (ORCPT ); Wed, 9 Nov 2022 03:26:25 -0500 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CBC271C90D for ; Wed, 9 Nov 2022 00:26:23 -0800 (PST) Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 2A98QFnK114737; Wed, 9 Nov 2022 02:26:15 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1667982375; bh=5ZlAY8ts28/UA0TeHdRhIaPWxIjinl+puEaqQc+L5Ho=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=OsDPme+dL4gPId7v6YNyNU4k+z03LmV8ugvsXqGobA+USVKWIU7p05mlJY/3F3gA4 Kah/xcoOuBxTO5OOkEn9F1Qzw8YULRu6WtMO3wyEbj2lWvFLExzkuUrrAy1L/c+YPc qiX9MBXZsXY0LEc+1mmB3nNmQPm7+V9qSTJrJEes= Received: from DFLE103.ent.ti.com (dfle103.ent.ti.com [10.64.6.24]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 2A98QF0U039216 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 9 Nov 2022 02:26:15 -0600 Received: from DFLE112.ent.ti.com (10.64.6.33) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6; Wed, 9 Nov 2022 02:26:15 -0600 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6 via Frontend Transport; Wed, 9 Nov 2022 02:26:15 -0600 Received: from localhost (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 2A98QCO7039374; Wed, 9 Nov 2022 02:26:14 -0600 From: Matt Ranostay To: , , , , CC: , , Matt Ranostay , Achal Verma Subject: [PATCH v5 3/4] PCI: j721e: add j784s4 PCIe configuration Date: Wed, 9 Nov 2022 00:25:55 -0800 Message-ID: <20221109082556.29265-4-mranostay@ti.com> X-Mailer: git-send-email 2.38.GIT In-Reply-To: <20221109082556.29265-1-mranostay@ti.com> References: <20221109082556.29265-1-mranostay@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add PCIe configuration for j784s4 platform which has 4x lane support. Tested-by: Achal Verma Signed-off-by: Matt Ranostay --- drivers/pci/controller/cadence/pci-j721e.c | 23 ++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c index efd065bc0104..83b8100afaff 100644 --- a/drivers/pci/controller/cadence/pci-j721e.c +++ b/drivers/pci/controller/cadence/pci-j721e.c @@ -331,6 +331,21 @@ static const struct j721e_pcie_data am64_pcie_ep_data = { .max_lanes = 1, }; +static const struct j721e_pcie_data j784s4_pcie_rc_data = { + .mode = PCI_MODE_RC, + .quirk_retrain_flag = true, + .is_intc_v1 = true, + .byte_access_allowed = false, + .linkdown_irq_regfield = LINK_DOWN, + .max_lanes = 4, +}; + +static const struct j721e_pcie_data j784s4_pcie_ep_data = { + .mode = PCI_MODE_EP, + .linkdown_irq_regfield = LINK_DOWN, + .max_lanes = 4, +}; + static const struct of_device_id of_j721e_pcie_match[] = { { .compatible = "ti,j721e-pcie-host", @@ -356,6 +371,14 @@ static const struct of_device_id of_j721e_pcie_match[] = { .compatible = "ti,am64-pcie-ep", .data = &am64_pcie_ep_data, }, + { + .compatible = "ti,j784s4-pcie-host", + .data = &j784s4_pcie_rc_data, + }, + { + .compatible = "ti,j784s4-pcie-ep", + .data = &j784s4_pcie_ep_data, + }, {}, }; From patchwork Wed Nov 9 08:25:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matt Ranostay X-Patchwork-Id: 13037247 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3C0C0C4332F for ; Wed, 9 Nov 2022 08:26:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229797AbiKII0e (ORCPT ); Wed, 9 Nov 2022 03:26:34 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39512 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229814AbiKII0d (ORCPT ); Wed, 9 Nov 2022 03:26:33 -0500 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B3A1E13D52 for ; Wed, 9 Nov 2022 00:26:32 -0800 (PST) Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 2A98QK11114296; Wed, 9 Nov 2022 02:26:20 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1667982380; bh=hlEm72WqMoZKFSWrfJiaow4wqktKLw+YOG3Ivwy4ACE=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=uLI6is7rKQq7CjSfxfXpLNQRvjiAgDQZmBOqbOVak7iiZbeWQmvXjgzc4WAR/B8MS tlSlYWWotXPAH+n55FqmMFQFGbmbuDpYV+D8213y62QbR4RyEoc1f1UrO9N8eTKJBd 72z85knjLGz/qtBKcqyIVdAuhA4yNsqvG53sIfsk= Received: from DFLE107.ent.ti.com (dfle107.ent.ti.com [10.64.6.28]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 2A98QK82039242 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 9 Nov 2022 02:26:20 -0600 Received: from DFLE113.ent.ti.com (10.64.6.34) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6; Wed, 9 Nov 2022 02:26:20 -0600 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6 via Frontend Transport; Wed, 9 Nov 2022 02:26:20 -0600 Received: from localhost (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 2A98QHlX039434; Wed, 9 Nov 2022 02:26:18 -0600 From: Matt Ranostay To: , , , , CC: , , Matt Ranostay Subject: [PATCH v5 4/4] PCI: j721e: Add warnings on num-lanes misconfiguration Date: Wed, 9 Nov 2022 00:25:56 -0800 Message-ID: <20221109082556.29265-5-mranostay@ti.com> X-Mailer: git-send-email 2.38.GIT In-Reply-To: <20221109082556.29265-1-mranostay@ti.com> References: <20221109082556.29265-1-mranostay@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Added dev_warn messages to alert of misconfigurations for incorrect number of lanes setting, or the lack of one being defined. Signed-off-by: Matt Ranostay Reviewed-by: Vignesh Raghavendra --- drivers/pci/controller/cadence/pci-j721e.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c index 83b8100afaff..f6320ad75587 100644 --- a/drivers/pci/controller/cadence/pci-j721e.c +++ b/drivers/pci/controller/cadence/pci-j721e.c @@ -465,9 +465,16 @@ static int j721e_pcie_probe(struct platform_device *pdev) pcie->user_cfg_base = base; ret = of_property_read_u32(node, "num-lanes", &num_lanes); - if (ret || num_lanes > data->max_lanes) + if (ret) { + dev_warn(dev, "no num-lanes defined, defaulting to 1\n"); num_lanes = 1; + } + if (num_lanes > data->max_lanes) { + dev_warn(dev, "defined num-lanes %u is greater than the allowed maximum of %u, defaulting to 1\n", + num_lanes, data->max_lanes); + num_lanes = 1; + } pcie->max_lanes = data->max_lanes; pcie->num_lanes = num_lanes;