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Wysocki" , Len Brown , Jonathan Cameron , "Davidlohr Bueso" , Dave Jiang , Robert Richter Subject: [PATCH v3 1/9] cxl/acpi: Register CXL host ports by bridge device Date: Wed, 9 Nov 2022 11:40:51 +0100 Message-ID: <20221109104059.766720-2-rrichter@amd.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20221109104059.766720-1-rrichter@amd.com> References: <20221109104059.766720-1-rrichter@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT036:EE_|PH8PR12MB6700:EE_ X-MS-Office365-Filtering-Correlation-Id: b57c4e48-c5ec-47cf-ecf8-08dac23ef1d9 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Jaqi4CV/5UMVEI0BVvEJ0t+u/FolCQ6P1FRuc/uqeTpLTP06T3e+aVUct4Kbp1uIenye3eByx3sgUant5j7RFTjEJSyEMDB350HU1vd90EVwTuXrvVHKgHdLBzD9OsCUAIpJL/Dq6CfaAD77z4pSHTPveyWylrwao/a4g0mM+78tKFwQE12VKb5VSxtH5IFHs1EgOPsu8ZduLXaKbBIkR37jKTIdsvUKbr0mvsjVzjM/l5g4z+/OOY4RfpL0N+cUAIz9a12MYgRaLb1kMNAdZj22GBzGMRpV81ZxdDLg0yvPXwAIzb2hjO+14oaORk9x13OE4zA+1lwMSGu/P7jw6kjtciRC88iN5G8lL9e9ORSQxsPoaMUegxcAP05i0no1A/1MrA7ruYtMipu+fLJ7gF2Dm+NQUSgAQvHfyClfn6pLG5L7lNAtFUHpqbv/+K83JSv0iXqMA07K5LteYoEnO8NAlS3grGfsg+YBb6sbh0gNbF44b5jurR+CnZ8KuBj6+kVtQ02/15/UYKMYnEpv2KzopVai94K5xBfqElfvYHoKNk++KmtD8nNOIuNtmKzHrWSAACAmxrfqWFr0dfjroOWLSK4X02+sNOM/7jEAqRovHUUvnnMSh6WI4DX2lQY0nM46R8cFXil0eegOaomrimmLbVlIqdnJO/q06SPyV4lOs01kIe+wJ9bBfHOradqk8M5Kkvp44ZEbxk5IKtE9q813a3yJs0BQ2/Va4iE8dr5YPIl2hEjUa2WsCzKkxquj7VzHKWFQnUnW175D3+QqDr4LKu9rhBWcgvLqppyNnSCP1O9cYwd0ykcfOS6jK9aC X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(376002)(136003)(396003)(39860400002)(346002)(451199015)(36840700001)(40470700004)(46966006)(186003)(36756003)(8676002)(4326008)(26005)(41300700001)(81166007)(70206006)(7416002)(6666004)(40460700003)(356005)(2616005)(70586007)(16526019)(1076003)(8936002)(5660300002)(316002)(110136005)(54906003)(83380400001)(82740400003)(2906002)(426003)(36860700001)(82310400005)(336012)(47076005)(40480700001)(478600001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Nov 2022 10:41:22.6604 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b57c4e48-c5ec-47cf-ecf8-08dac23ef1d9 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT036.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB6700 Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org A port of a CXL host bridge links to the bridge's acpi device (&adev->dev) with its corresponding uport/dport device (uport_dev and dport_dev respectively). The device is not a direct parent device in the PCI topology as pdev->dev.parent points to a PCI bridge's (struct pci_host_bridge) device. The following CXL memory device hierarchy would be valid for an endpoint once an RCD EP would be enabled (note this will be done in a later patch): VH mode: cxlmd->dev.parent->parent ^^^\^^^^^^\ ^^^^^^\ \ \ pci_dev (Type 1, Downstream Port) \ pci_dev (Type 0, PCI Express Endpoint) cxl mem device RCD mode: cxlmd->dev.parent->parent ^^^\^^^^^^\ ^^^^^^\ \ \ pci_host_bridge \ pci_dev (Type 0, RCiEP) cxl mem device In VH mode a downstream port is created by port enumeration and thus always exists. Now, in RCD mode the host bridge also already exists but it references to an ACPI device. A port lookup by the PCI device's parent device will fail as a direct link to the registered port is missing. The ACPI device of the bridge must be determined first. To prevent this, change port registration of a CXL host to use the bridge device instead. Do this also for the VH case as port topology will better reflect the PCI topology then. If a mock device is registered by a test driver, the bridge pointer can be NULL. Keep using the matching ACPI device (&adev->dev) as a fallback in this case. Signed-off-by: Robert Richter Signed-off-by: Robert Richter Signed-off-by: Dan Williams --- drivers/cxl/acpi.c | 48 ++++++++++++++++++++++++++++++---------------- 1 file changed, 31 insertions(+), 17 deletions(-) diff --git a/drivers/cxl/acpi.c b/drivers/cxl/acpi.c index fb9f72813067..06150c953f58 100644 --- a/drivers/cxl/acpi.c +++ b/drivers/cxl/acpi.c @@ -185,6 +185,17 @@ __mock struct acpi_device *to_cxl_host_bridge(struct device *host, return NULL; } +static inline struct acpi_pci_root *to_cxl_pci_root(struct device *host, + struct device *match) +{ + struct acpi_device *adev = to_cxl_host_bridge(host, match); + + if (!adev) + return NULL; + + return acpi_pci_find_root(adev->handle); +} + /* * A host bridge is a dport to a CFMWS decode and it is a uport to the * dport (PCIe Root Ports) in the host bridge. @@ -193,35 +204,35 @@ static int add_host_bridge_uport(struct device *match, void *arg) { struct cxl_port *root_port = arg; struct device *host = root_port->dev.parent; - struct acpi_device *bridge = to_cxl_host_bridge(host, match); - struct acpi_pci_root *pci_root; + struct acpi_pci_root *pci_root = to_cxl_pci_root(host, match); struct cxl_dport *dport; struct cxl_port *port; + struct device *bridge; int rc; - if (!bridge) + if (!pci_root) return 0; - dport = cxl_find_dport_by_dev(root_port, match); + /* + * If it is a mock dev, the bridge can be NULL, use matching + * device (&adev->dev) as a fallback then then. + */ + bridge = pci_root->bus->bridge ?: match; + dport = cxl_find_dport_by_dev(root_port, bridge); if (!dport) { dev_dbg(host, "host bridge expected and not found\n"); return 0; } - /* - * Note that this lookup already succeeded in - * to_cxl_host_bridge(), so no need to check for failure here - */ - pci_root = acpi_pci_find_root(bridge->handle); - rc = devm_cxl_register_pci_bus(host, match, pci_root->bus); + rc = devm_cxl_register_pci_bus(host, bridge, pci_root->bus); if (rc) return rc; - port = devm_cxl_add_port(host, match, dport->component_reg_phys, dport); + port = devm_cxl_add_port(host, bridge, dport->component_reg_phys, dport); if (IS_ERR(port)) return PTR_ERR(port); - dev_info(pci_root->bus->bridge, "host supports CXL\n"); + dev_info(bridge, "host supports CXL\n"); return 0; } @@ -258,13 +269,16 @@ static int add_host_bridge_dport(struct device *match, void *arg) struct cxl_chbs_context ctx; struct cxl_port *root_port = arg; struct device *host = root_port->dev.parent; - struct acpi_device *bridge = to_cxl_host_bridge(host, match); + struct acpi_pci_root *pci_root = to_cxl_pci_root(host, match); + struct device *bridge; + acpi_handle handle; - if (!bridge) + if (!pci_root) return 0; - status = acpi_evaluate_integer(bridge->handle, METHOD_NAME__UID, NULL, - &uid); + bridge = pci_root->bus->bridge ?: match; + handle = pci_root->device->handle; + status = acpi_evaluate_integer(handle, METHOD_NAME__UID, NULL, &uid); if (status != AE_OK) { dev_err(match, "unable to retrieve _UID\n"); return -ENODEV; @@ -285,7 +299,7 @@ static int add_host_bridge_dport(struct device *match, void *arg) dev_dbg(match, "CHBCR found: 0x%08llx\n", (u64)ctx.chbcr); - dport = devm_cxl_add_dport(root_port, match, uid, ctx.chbcr); + dport = devm_cxl_add_dport(root_port, bridge, uid, ctx.chbcr); if (IS_ERR(dport)) return PTR_ERR(dport); From patchwork Wed Nov 9 10:40:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Richter X-Patchwork-Id: 13037347 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 87F8CC4321E for ; Wed, 9 Nov 2022 10:41:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231126AbiKIKlj (ORCPT ); Wed, 9 Nov 2022 05:41:39 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55658 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230526AbiKIKlg (ORCPT ); Wed, 9 Nov 2022 05:41:36 -0500 Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2048.outbound.protection.outlook.com [40.107.243.48]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9392F20F53; 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Wysocki" , Len Brown , Jonathan Cameron , "Davidlohr Bueso" , Dave Jiang , Robert Richter , Terry Bowman Subject: [PATCH v3 2/9] cxl/acpi: Extract component registers of restricted hosts from RCRB Date: Wed, 9 Nov 2022 11:40:52 +0100 Message-ID: <20221109104059.766720-3-rrichter@amd.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20221109104059.766720-1-rrichter@amd.com> References: <20221109104059.766720-1-rrichter@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT036:EE_|CH2PR12MB4923:EE_ X-MS-Office365-Filtering-Correlation-Id: 8a6d1dab-4814-41d7-8e06-08dac23ef5d1 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: wmkdADamZuswThwb1jWVgc7+BuSEywsgFc6v7y+YZWi5YUdKp8h24+50ai2O7FyxePqlCSKjIV4ykOIltHfcFfIQE0KsM1BX2d6G5giWOuQFEl5LpKkYkLeSjK7BPST1L0bTse2RCN8ru33j+K0ZvLoMa7n8EvUzYb5U1uH1tpmVGLE22+SRD11b4PiDMRKB67/LKlO0AgGtgUynJRVyp9oZIIwPBm+DNkj4w8nEd42nK1ef7zaVwRREIzuIJwpT+kM4gLf5qCIxiJ2ejq5e6XhVgvnVqr4wwhOZuNqxi2EaI/MkSqGvoY0lNqfyY8k5rwFCxVXFExhLpH9dsTvkxDgDUgMsklGf0L9gRhZE/v1NPCx6JwOZxIvRP+d0VI7PhWGAYPu63zYUsTUy05RfAj4fLFLHuGo+h9HTteWLZJoi/A983xFvxGAckKF/vTovu2nGYeHCzKP1BiOWZTjsArh/TtWCCc1YprQJd34FKRZL853Xo5Tgl5l8k9du/v0orRzX6FDRdRH48BYSiSIHvkBwnUWMiU4XDGsvs+4hTGfFS/Y43LVvhBUHpsS3wV9n21QOXClwQ0ap44BqofCMIO66XoLYKZiDFd0wdaqwSavnOfnSYDBzvK9ebHN2nlokR3QCSBX1PkZZcDIqJ6H80wx8yO3JMFf5ClvMFTe6H3N0cX4v5cCkvDxF2fZhZAbHQ0QfIs1CVLbENRrWCNbrjnvs/r0GvWlN7dv8fflr8eZ5MG+l4FhLVr8PnQF8JL2F4Rv1dvc4bfZff8F+dfeZBWwc2njCwcGGt5yZmTZJmt0= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(346002)(376002)(136003)(396003)(39860400002)(451199015)(40470700004)(36840700001)(46966006)(82310400005)(478600001)(356005)(110136005)(81166007)(6666004)(54906003)(316002)(336012)(36860700001)(82740400003)(70206006)(70586007)(4326008)(26005)(41300700001)(8676002)(8936002)(36756003)(2616005)(186003)(1076003)(16526019)(5660300002)(7416002)(2906002)(40480700001)(47076005)(426003)(83380400001)(40460700003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Nov 2022 10:41:29.3789 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8a6d1dab-4814-41d7-8e06-08dac23ef5d1 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT036.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4923 Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org A downstream port must be connected to a component register block. For restricted hosts the base address is determined from the RCRB. The RCRB is provided by the host's CEDT CHBS entry. Rework CEDT parser to get the RCRB and add code to extract the component register block from it. RCRB's BAR[0..1] point to the component block containing CXL subsystem component registers. MEMBAR extraction follows the PCI base spec here, esp. 64 bit extraction and memory range alignment (6.0, 7.5.1.2.1). Note: Right now the component register block is used for HDM decoder capability only which is optional for RCDs. If unsupported by the RCD, the HDM init will fail. It is future work to bypass it in this case. Co-developed-by: Terry Bowman Signed-off-by: Terry Bowman Signed-off-by: Robert Richter --- drivers/cxl/acpi.c | 43 +++++++++++++++++++++++++++++--------- drivers/cxl/core/regs.c | 46 +++++++++++++++++++++++++++++++++++++++++ drivers/cxl/cxl.h | 8 +++++++ 3 files changed, 87 insertions(+), 10 deletions(-) diff --git a/drivers/cxl/acpi.c b/drivers/cxl/acpi.c index 06150c953f58..caea42cf9522 100644 --- a/drivers/cxl/acpi.c +++ b/drivers/cxl/acpi.c @@ -9,6 +9,8 @@ #include "cxlpci.h" #include "cxl.h" +#define CXL_RCRB_SIZE SZ_8K + static unsigned long cfmws_to_decoder_flags(int restrictions) { unsigned long flags = CXL_DECODER_F_ENABLE; @@ -240,27 +242,46 @@ static int add_host_bridge_uport(struct device *match, void *arg) struct cxl_chbs_context { struct device *dev; unsigned long long uid; - resource_size_t chbcr; + struct acpi_cedt_chbs chbs; }; -static int cxl_get_chbcr(union acpi_subtable_headers *header, void *arg, - const unsigned long end) +static int cxl_get_chbs(union acpi_subtable_headers *header, void *arg, + const unsigned long end) { struct cxl_chbs_context *ctx = arg; struct acpi_cedt_chbs *chbs; - if (ctx->chbcr) + if (ctx->chbs.base) return 0; chbs = (struct acpi_cedt_chbs *) header; if (ctx->uid != chbs->uid) return 0; - ctx->chbcr = chbs->base; + ctx->chbs = *chbs; return 0; } +static resource_size_t cxl_get_chbcr(struct cxl_chbs_context *ctx) +{ + struct acpi_cedt_chbs *chbs = &ctx->chbs; + + if (!chbs->base) + return CXL_RESOURCE_NONE; + + if (chbs->cxl_version != ACPI_CEDT_CHBS_VERSION_CXL11) + return chbs->base; + + if (chbs->length != CXL_RCRB_SIZE) + return CXL_RESOURCE_NONE; + + dev_dbg(ctx->dev, "RCRB found for UID %lld: 0x%08llx\n", + ctx->uid, (u64)chbs->base); + + return cxl_rcrb_to_component(ctx->dev, chbs->base, CXL_RCRB_DOWNSTREAM); +} + static int add_host_bridge_dport(struct device *match, void *arg) { acpi_status status; @@ -272,6 +293,7 @@ static int add_host_bridge_dport(struct device *match, void *arg) struct acpi_pci_root *pci_root = to_cxl_pci_root(host, match); struct device *bridge; acpi_handle handle; + resource_size_t component_reg_phys; if (!pci_root) return 0; @@ -287,19 +309,20 @@ static int add_host_bridge_dport(struct device *match, void *arg) dev_dbg(match, "UID found: %lld\n", uid); ctx = (struct cxl_chbs_context) { - .dev = host, + .dev = match, .uid = uid, }; - acpi_table_parse_cedt(ACPI_CEDT_TYPE_CHBS, cxl_get_chbcr, &ctx); + acpi_table_parse_cedt(ACPI_CEDT_TYPE_CHBS, cxl_get_chbs, &ctx); - if (ctx.chbcr == 0) { + component_reg_phys = cxl_get_chbcr(&ctx); + if (component_reg_phys == CXL_RESOURCE_NONE) { dev_warn(match, "No CHBS found for Host Bridge (UID %lld)\n", uid); return 0; } - dev_dbg(match, "CHBCR found: 0x%08llx\n", (u64)ctx.chbcr); + dev_dbg(match, "CHBCR found: 0x%08llx\n", (u64)component_reg_phys); - dport = devm_cxl_add_dport(root_port, bridge, uid, ctx.chbcr); + dport = devm_cxl_add_dport(root_port, bridge, uid, component_reg_phys); if (IS_ERR(dport)) return PTR_ERR(dport); diff --git a/drivers/cxl/core/regs.c b/drivers/cxl/core/regs.c index ec178e69b18f..7a5bde81e949 100644 --- a/drivers/cxl/core/regs.c +++ b/drivers/cxl/core/regs.c @@ -307,3 +307,49 @@ int cxl_find_regblock(struct pci_dev *pdev, enum cxl_regloc_type type, return -ENODEV; } EXPORT_SYMBOL_NS_GPL(cxl_find_regblock, CXL); + +resource_size_t cxl_rcrb_to_component(struct device *dev, + resource_size_t rcrb, + enum cxl_rcrb which) +{ + resource_size_t component_reg_phys; + u32 bar0, bar1; + void *addr; + + if (which == CXL_RCRB_UPSTREAM) + rcrb += SZ_4K; + + /* + * RCRB's BAR[0..1] point to component block containing CXL + * subsystem component registers. MEMBAR extraction follows + * the PCI Base spec here, esp. 64 bit extraction and memory + * ranges alignment (6.0, 7.5.1.2.1). + */ + addr = ioremap(rcrb, PCI_BASE_ADDRESS_0 + SZ_8); + if (!addr) { + dev_err(dev, "Failed to map region %pr\n", addr); + return CXL_RESOURCE_NONE; + } + + bar0 = readl(addr + PCI_BASE_ADDRESS_0); + bar1 = readl(addr + PCI_BASE_ADDRESS_1); + iounmap(addr); + + /* sanity check */ + if (bar0 & (PCI_BASE_ADDRESS_MEM_TYPE_1M | PCI_BASE_ADDRESS_SPACE_IO)) + return CXL_RESOURCE_NONE; + + component_reg_phys = bar0 & PCI_BASE_ADDRESS_MEM_MASK; + if (bar0 & PCI_BASE_ADDRESS_MEM_TYPE_64) + component_reg_phys |= ((u64)bar1) << 32; + + if (!component_reg_phys) + return CXL_RESOURCE_NONE; + + /* MEMBAR is block size (64k) aligned. */ + if (!IS_ALIGNED(component_reg_phys, CXL_COMPONENT_REG_BLOCK_SIZE)) + return CXL_RESOURCE_NONE; + + return component_reg_phys; +} +EXPORT_SYMBOL_NS_GPL(cxl_rcrb_to_component, CXL); diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index ac8998b627b5..d6b4fe68a821 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -219,6 +219,14 @@ enum cxl_regloc_type; int cxl_find_regblock(struct pci_dev *pdev, enum cxl_regloc_type type, struct cxl_register_map *map); +enum cxl_rcrb { + CXL_RCRB_DOWNSTREAM, + CXL_RCRB_UPSTREAM, +}; +resource_size_t cxl_rcrb_to_component(struct device *dev, + resource_size_t rcrb, + enum cxl_rcrb which); + #define CXL_RESOURCE_NONE ((resource_size_t) -1) #define CXL_TARGET_STRLEN 20 From patchwork Wed Nov 9 10:40:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Robert Richter X-Patchwork-Id: 13037344 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1F748C433FE for ; Wed, 9 Nov 2022 10:41:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231133AbiKIKli (ORCPT ); Wed, 9 Nov 2022 05:41:38 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55596 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230520AbiKIKlc (ORCPT ); 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Wed, 9 Nov 2022 04:41:26 -0600 From: Robert Richter To: Alison Schofield , Vishal Verma , Ira Weiny , Ben Widawsky , Dan Williams CC: , , Bjorn Helgaas , "Rafael J. Wysocki" , Len Brown , Jonathan Cameron , "Davidlohr Bueso" , Dave Jiang , Robert Richter Subject: [PATCH v3 3/9] cxl/mem: Adjust cxl_mem_find_port() to find an RCH's port Date: Wed, 9 Nov 2022 11:40:53 +0100 Message-ID: <20221109104059.766720-4-rrichter@amd.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20221109104059.766720-1-rrichter@amd.com> References: <20221109104059.766720-1-rrichter@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT036:EE_|BN9PR12MB5275:EE_ X-MS-Office365-Filtering-Correlation-Id: f8ed6df7-a314-4116-779b-08dac23ef5fc X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: REEzWynFfBy8dikKxSV+hXuZAuNdeB94+/WFPs6o7b0bLcDOxbTYJwDN6PCpst381Wm1CvkJVlvICJI4pb1jj2Iz9YC4QmnfxG4TxcebwNltjzr8u/ZouuXGnQVlHgUbVc9D3eKXhXC7WC7Gd5YCnVRd4EUrms4JIxzyx+NTzYn8s23ngye64x42oUbwrDsUhQZsjWniU3anIp2/pb0lW3a1WWzLAUV/PhjljaPD8zSJfRjyvzYMUX77VSy8gAaMHFhtTT1r0WpNko+pC3gdlnLZRqEpwrXwVwC9SQI/1L87m3Jjn/obqxIPzQ8ZC4sZ3y2E7s/PIdhJGugN/FZ5E+WNqUw7PXUlTt2HoOp6S4rWW1zJSfQHC92XgbWC0OB4FN9z9Lr8FH9JFWI/cn0Da5EZ/Q+tCCly+Tm0eiZii1bmH6wZeITk5QsL2Iy8Q/V+LnMIexI+B6GkYSoJX8/iMTqofcELru1MW+85JJ8v9qrOySln8NqJLM3sXKvfX3fFgdhgljTJhLMqnMJZ+7n4HShdRSXpkPY4ceoaivXZO5HhiWe892rH5Fx3DGmA/bQ+ZFWpF3iZLcmtDqcuNtMGbxgHtBgflDo2XS5E03U8hK4c43anhORO7e4rJ3S2wQ2swxQf6bruoW0DQCQssNzUE0WnHVDGJAQvAQYvdoyjqCRmSeKWGZxbEodyoy2ZwmPCT8nQDExpGVN8uHACIjFd0i8fc/1tVDlS+m/yiRCDD5PCXn4mzuOB2Z0Fpg8l5NuAETkVEYd/YkU8JwKePhpG9tAqkjzb/8P4v7cUayzfJp0xqmv7RVCMa3uxDY/M5v00QSBzW0G1qBArFwgJRzEcjg== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(39860400002)(346002)(136003)(396003)(376002)(451199015)(36840700001)(40470700004)(46966006)(47076005)(186003)(426003)(336012)(16526019)(1076003)(70586007)(36860700001)(26005)(2906002)(7416002)(40460700003)(40480700001)(2616005)(110136005)(316002)(4326008)(478600001)(82310400005)(6666004)(5660300002)(8936002)(41300700001)(70206006)(54906003)(8676002)(36756003)(81166007)(82740400003)(356005)(37363002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Nov 2022 10:41:29.6602 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f8ed6df7-a314-4116-779b-08dac23ef5fc X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT036.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN9PR12MB5275 Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org The PCIe software view of an RCH and RCD is different to VH mode. An RCD is paired with an RCH and shows up as RCiEP with a parent already pointing to a PCI bridge (struct pci_host_bridge). In contrast, in VH mode an PCI Express Endpoint is a PCI type 0 device with a PCI type 1 device as parent (struct pci_dev, most of the time a downstream switch port, but could also be a root port). The following hierarchy applies in VH mode: CXL memory device, cxl_memdev endpoint └──PCIe Endpoint (type 0), pci_dev | └──Downstream Port (type 1), pci_dev (Nth switch) portN └──Upstream Port (type 1), pci_dev (Nth switch) | : : └──Downstream Port (type 1), pci_dev (1st switch) port1 └──Upstream Port (type 1), pci_dev (1st switch) | └──Root Port (type 1), pci_dev | └──PCI host bridge, pci_host_bridge port0 : | :..ACPI0017, acpi_dev root (There can be zero or any other number of switches in between.) An iterator through the grandparents takes us to the root port which is registered as dport to the bridge. The next port an endpoint is connected to can be determined by using the grandparent of the memory device as a dport_dev in cxl_mem_find_port(). The same does not work in RCD mode where only an RCiEP is connected to the host bridge: CXL memory device, cxl_memdev endpoint └──PCIe Endpoint (type 0), pci_dev | └──PCI host bridge, pci_host_bridge port0 : | :..ACPI0017, acpi_dev root Here, an endpoint is directly connected to the host bridge without a type 1 PCI device (root or downstream port) in between. To link the endpoint to the correct port, the endpoint's PCI device (parent of the memory device) must be taken as dport_dev arg in cxl_mem_find_port(). Change cxl_mem_find_port() to find an RCH's port. Signed-off-by: Robert Richter --- drivers/cxl/core/port.c | 38 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c index 0431ed860d8e..d10c3580719b 100644 --- a/drivers/cxl/core/port.c +++ b/drivers/cxl/core/port.c @@ -1354,6 +1354,14 @@ static int add_port_attach_ep(struct cxl_memdev *cxlmd, return rc; } +static inline bool is_cxl_restricted(struct cxl_memdev *cxlmd) +{ + struct device *parent = cxlmd->dev.parent; + if (!dev_is_pci(parent)) + return false; + return pci_pcie_type(to_pci_dev(parent)) == PCI_EXP_TYPE_RC_END; +} + int devm_cxl_enumerate_ports(struct cxl_memdev *cxlmd) { struct device *dev = &cxlmd->dev; @@ -1433,9 +1441,39 @@ int devm_cxl_enumerate_ports(struct cxl_memdev *cxlmd) } EXPORT_SYMBOL_NS_GPL(devm_cxl_enumerate_ports, CXL); +/* + * CXL memory device and port hierarchy: + * + * VH mode: + * + * CXL memory device, cxl_memdev endpoint + * └──PCIe Endpoint (type 0), pci_dev | + * └──Downstream Port (type 1), pci_dev (Nth switch) portN + * └──Upstream Port (type 1), pci_dev (Nth switch) | + * : : + * └──Downstream Port (type 1), pci_dev (1st switch) port1 + * └──Upstream Port (type 1), pci_dev (1st switch) | + * └──Root Port (type 1), pci_dev | + * └──PCI host bridge, pci_host_bridge port0 + * : | + * :..ACPI0017, acpi_dev root + * + * (There can be zero or any other number of switches in between.) + * + * RCD mode: + * + * CXL memory device, cxl_memdev endpoint + * └──PCIe Endpoint (type 0), pci_dev | + * └──PCI host bridge, pci_host_bridge port0 + * : | + * :..ACPI0017, acpi_dev root + */ struct cxl_port *cxl_mem_find_port(struct cxl_memdev *cxlmd, struct cxl_dport **dport) { + if (is_cxl_restricted(cxlmd)) + return find_cxl_port(cxlmd->dev.parent, dport); + return find_cxl_port(grandparent(&cxlmd->dev), dport); } EXPORT_SYMBOL_NS_GPL(cxl_mem_find_port, CXL); From patchwork Wed Nov 9 10:40:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Richter X-Patchwork-Id: 13037346 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 26F1CC433FE for ; Wed, 9 Nov 2022 10:41:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231135AbiKIKll (ORCPT ); Wed, 9 Nov 2022 05:41:41 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55700 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231132AbiKIKlh (ORCPT ); Wed, 9 Nov 2022 05:41:37 -0500 Received: from NAM11-CO1-obe.outbound.protection.outlook.com (mail-co1nam11on2086.outbound.protection.outlook.com [40.107.220.86]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EE40822BD8; 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Wysocki" , Len Brown , Jonathan Cameron , "Davidlohr Bueso" , Dave Jiang , Robert Richter Subject: [PATCH v3 4/9] cxl/mem: Skip intermediate port enumeration of restricted endpoints (RCDs) Date: Wed, 9 Nov 2022 11:40:54 +0100 Message-ID: <20221109104059.766720-5-rrichter@amd.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20221109104059.766720-1-rrichter@amd.com> References: <20221109104059.766720-1-rrichter@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT031:EE_|DM6PR12MB4217:EE_ X-MS-Office365-Filtering-Correlation-Id: f02be110-c5fe-4432-c41d-08dac23ef78e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: FfGGGblVlpaC5xC8B9kIIV8/QMzZl+3QX7kfyHCVzq2jfPK/1Box8j9P5o8fWKVp2j8AOjHt6Hncug/CvrStzfO8LbX2jk4Y26/neDhFO+AEkfqMioWAL5XGBIPU059vh/Mwfr0bKRmcD1sox/VNXv8AJfFxet8DJbXfhGKJSvDmML1NIC7iw25QLbnmuKdAYz6I2nHuCa2g/oSdeqBmz8K/Xt7n/5aAemorkz/tt6MFoC5AFfr64EvzM+CDUUJLkb3Zbk/b/CBOVBwKhoneMZKhoPNgZf4Wz49xFGs1tXgJ5zODV/dC2Ajx+rhC5c9aX8Jk7o6oV6yzjYIbXmsYzhTmcrn2BI1X1BtCuJN1xnW4G7LweQbCc53GvhQdEX9lX+UNlm0uiraQAgwPSkrcnqjPPm2nxwcmEC7CRFnU62y6lNH1LSUKBHudgz3g+L6HLMWEbbovciq6PGPVRefKHjNTcrpIJ3xSv0SfBaWJ2OFdwDhO7UhlRMmmP9Wq8WWIluRAv1LZk+ldDUjguMGpwTQSTRhSVcWxYDJWvOFWBGkvdCG87AG4jSFjUxawIKDsOAN/aHkiocwb5+Z6uV8dP/lbE/qCyT8cQfCPVPXPl/u6mKb0fgdghpVNXgpJgNTdq6BDza+kJNC0MLOaYC25Kkl4VTZ5lLx6VkZwgbTqhlQrMoG2PQmAEq1yHfL+AQ9YgHoo7tNfNk3Vnex2BfOUy9OcqTi8sT8iVQCEv3xhqCORpUY/ARupMPo1VH+12c4WklNv2yh1vXN0RKsKRQIdaaABgmMJW3EgMIGr6+2fKiS5D+SyEQeJ/vLnAFkhTs9U X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(346002)(136003)(376002)(39860400002)(396003)(451199015)(46966006)(40470700004)(36840700001)(82310400005)(478600001)(356005)(6666004)(81166007)(54906003)(110136005)(316002)(26005)(426003)(47076005)(40480700001)(70206006)(70586007)(4326008)(82740400003)(8676002)(7416002)(41300700001)(5660300002)(8936002)(36756003)(2616005)(186003)(1076003)(16526019)(40460700003)(83380400001)(2906002)(36860700001)(336012)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Nov 2022 10:41:32.2967 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f02be110-c5fe-4432-c41d-08dac23ef78e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT031.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4217 Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org When an endpoint is found, all ports in beetween the endpoint and the CXL host bridge need to be created. In the RCH case there are no ports in between a host bridge and the endpoint. Skip the enumeration of intermediate ports. The port enumeration does not only create all ports, it also initializes the endpoint chain by adding the endpoint to every downstream port up to the root bridge. This must be done also in RCD mode, but is much more simple as the endpoint only needs to be added to the host bridge's dport. Note: For endpoint removal the cxl_detach_ep() is not needed as it is released in cxl_port_release(). Signed-off-by: Robert Richter --- drivers/cxl/core/port.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c index d10c3580719b..e21a9c3fe4da 100644 --- a/drivers/cxl/core/port.c +++ b/drivers/cxl/core/port.c @@ -1366,8 +1366,24 @@ int devm_cxl_enumerate_ports(struct cxl_memdev *cxlmd) { struct device *dev = &cxlmd->dev; struct device *iter; + struct cxl_dport *dport; + struct cxl_port *port; int rc; + /* + * Skip intermediate port enumeration in the RCH case, there + * are no ports in between a host bridge and an endpoint. Only + * initialize the EP chain. + */ + if (is_cxl_restricted(cxlmd)) { + port = cxl_mem_find_port(cxlmd, &dport); + if (!port) + return -ENXIO; + rc = cxl_add_ep(dport, &cxlmd->dev); + put_device(&port->dev); + return rc; + } + rc = devm_add_action_or_reset(&cxlmd->dev, cxl_detach_ep, cxlmd); if (rc) return rc; @@ -1381,8 +1397,6 @@ int devm_cxl_enumerate_ports(struct cxl_memdev *cxlmd) for (iter = dev; iter; iter = grandparent(iter)) { struct device *dport_dev = grandparent(iter); struct device *uport_dev; - struct cxl_dport *dport; - struct cxl_port *port; if (!dport_dev) return 0; From patchwork Wed Nov 9 10:40:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Richter X-Patchwork-Id: 13037349 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DCFC7C4332F for ; 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Wysocki" , Len Brown , Jonathan Cameron , "Davidlohr Bueso" , Dave Jiang , Robert Richter Subject: [PATCH v3 5/9] cxl/pci: Only register RCDs with device 0, function 0 as CXL memory device Date: Wed, 9 Nov 2022 11:40:55 +0100 Message-ID: <20221109104059.766720-6-rrichter@amd.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20221109104059.766720-1-rrichter@amd.com> References: <20221109104059.766720-1-rrichter@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT031:EE_|MW4PR12MB7239:EE_ X-MS-Office365-Filtering-Correlation-Id: ddd8ab70-2fa1-40b1-f37c-08dac23efccc X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: y6/d7+PK4NJVWpH1W0AwtNNJLHO1LEtagbmHg2WGeJsfb0cmXvpPqSDWMUhkKt7yiszXCCNZAoTZrCVbaMR9N5COoMz2MkrkokyyHSEge4Ik0PpdKjDbiniGkrhLoCHAh5aBS4yqndaTRSzKIU8W32pv10mq/b/gvX8wmOv1Am6VpGLPkjtaPzw2OGDLyfeZPRABE2PxspIruvKHFT3O1vCSaMDc08GU0jB8sQfGKqHDd13NLJaWFSBJoAdra83UW6UU9SdUUSCVD3muDAL2bdDlDZ6wQhvlEirt1WhsSpEkZpi/atFyaOY91liHWid158PmC9QaGzsoOma1Z/fYVzltPfNgYsW8vRBPAbwt7aoKAZ5g9uDk4XFDG/Q88yb8MSZgW3T+ZC0/Su9kezd0JoXKKtZhS1o6ZS9MxQDTw0Nw7Lrg8PHxWaoN3GXFfAXEsQiYE1m1Fdy/yQWvHRgWo/jLfaKckt7YwwojVmgLWMdi041I4J/dREQWKsLYOGrgDB2T2nko1CTMFQoP3dWOOR6t2HPx4MqbTv8veepGua0m0FPq40Qpb2q75V8btEOalq8eu1Nv+UnV4uanQyigI8nLyaL3bYjuP7DQmb/9W7WHgXW2nB6lgvZfZPKnalt0uNslvzbTVur3f16MhIEJkuu7wevzumX/HMzLFSBVpo0YmepMcZhS0NUwqOCT32xakXnocvE2QuBdhUZuQyzxdJS5ior21GMd6iajssBb8wNKvCs0qgZa6cGnljkcPpsevTHpjLj7pBFANsT+JD72I3xwnMyVmTH/m/23oTanktUf0sk9fxaVyQjpPrVA0c/+ X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(346002)(39860400002)(396003)(376002)(136003)(451199015)(40470700004)(46966006)(36840700001)(356005)(81166007)(36756003)(26005)(2616005)(40460700003)(82740400003)(82310400005)(7416002)(8936002)(83380400001)(2906002)(5660300002)(8676002)(70206006)(4326008)(41300700001)(54906003)(70586007)(40480700001)(316002)(186003)(1076003)(478600001)(16526019)(47076005)(426003)(336012)(6666004)(36860700001)(110136005)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Nov 2022 10:41:41.0928 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ddd8ab70-2fa1-40b1-f37c-08dac23efccc X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT031.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB7239 Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org The Device 0, Function 0 DVSEC controls the CXL functionality of the entire device. Add a check to prevent registration of any other PCI device on the bus as a CXL memory device. Signed-off-by: Robert Richter --- drivers/cxl/pci.c | 25 +++++++++++++++++++++++-- 1 file changed, 23 insertions(+), 2 deletions(-) diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c index faeb5d9d7a7a..cc4f206f24b3 100644 --- a/drivers/cxl/pci.c +++ b/drivers/cxl/pci.c @@ -428,11 +428,26 @@ static void devm_cxl_pci_create_doe(struct cxl_dev_state *cxlds) } } +static int check_restricted_device(struct pci_dev *pdev, u16 pcie_dvsec) +{ + if (pci_pcie_type(pdev) != PCI_EXP_TYPE_RC_END) + return 0; /* no RCD */ + + if (pdev->devfn == PCI_DEVFN(0, 0) && pcie_dvsec) + return 0; /* ok */ + + dev_warn(&pdev->dev, "Skipping RCD: devfn=0x%02x dvsec=%u\n", + pdev->devfn, pcie_dvsec); + + return -ENODEV; +} + static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) { struct cxl_register_map map; struct cxl_memdev *cxlmd; struct cxl_dev_state *cxlds; + u16 pcie_dvsec; int rc; /* @@ -442,6 +457,13 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) BUILD_BUG_ON(offsetof(struct cxl_regs, memdev) != offsetof(struct cxl_regs, device_regs.memdev)); + pcie_dvsec = pci_find_dvsec_capability( + pdev, PCI_DVSEC_VENDOR_ID_CXL, CXL_DVSEC_PCIE_DEVICE); + + rc = check_restricted_device(pdev, pcie_dvsec); + if (rc) + return rc; + rc = pcim_enable_device(pdev); if (rc) return rc; @@ -451,8 +473,7 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) return PTR_ERR(cxlds); cxlds->serial = pci_get_dsn(pdev); - cxlds->cxl_dvsec = pci_find_dvsec_capability( - pdev, PCI_DVSEC_VENDOR_ID_CXL, CXL_DVSEC_PCIE_DEVICE); + cxlds->cxl_dvsec = pcie_dvsec; if (!cxlds->cxl_dvsec) dev_warn(&pdev->dev, "Device DVSEC not present, skip CXL.mem init\n"); From patchwork Wed Nov 9 10:40:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Richter X-Patchwork-Id: 13037348 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 30D19C433FE for ; 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Wysocki" , Len Brown , Jonathan Cameron , "Davidlohr Bueso" , Dave Jiang , Robert Richter Subject: [PATCH v3 6/9] cxl/pci: Do not ignore PCI config read errors in match_add_dports() Date: Wed, 9 Nov 2022 11:40:56 +0100 Message-ID: <20221109104059.766720-7-rrichter@amd.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20221109104059.766720-1-rrichter@amd.com> References: <20221109104059.766720-1-rrichter@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT031:EE_|PH7PR12MB6717:EE_ X-MS-Office365-Filtering-Correlation-Id: 41817502-b894-4b91-6bfd-08dac23efdce X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: jSBKg9rAB7T2XDBxfRmsslVdR47pvkd9pKrQL3qCRyUF/1LVyVlPiv822U9V+L3Vy6SqyhZaG0C6Fe/PalewkI+/Uu04irRHLyQHPjOFhqmGptYldBkRpSCZNkvt9SATlxzO0tcAVNh2Z7WfsMN1DJRz5aVndRW5pqamJgMl2x5urWhkDtCrb8142zNWtjsy+FbZ/AWjrK9qOl2upRDOaXtYbYDpOQ14IhTFXoe1WLNuCmMiFHZ7RWikpYNFEJPhWmXpXLfOcFZY4mEWD+IIbxHKbDZ/tECr2MAB687WIJZkmZx+7nO/uqR5PRmCcwhxLkcf/5FfIxINUx0MFZmapRJMVYTpMgLitCCfUyc+ycUZlbD9PWIhHvNa8JLQwcWu65sz/cOKsqbmRmTUgAvbmPz3Z5FjdO75m3bdUw9qCK+3G/HP6S1c1ZRQjeWDfKXGR2UpYUroqgYZvUBsD6Wub4ZRBdJcCwK0ZRdyPJj9qbztd3dz4lGnIUHxhd7o/YODujqcL5qHphOrY5FSCAAb43lrYHuY61LJEL47C/Hqj3VtBHF6OtSDrgLoO9VZ2dBvpLJgZQDSeRCYGFbke4SoeC22/gKcKqdLXnQfggxrZFpRF3tVOUxII5C+LcbAQ20NZMHa2CH9TSqJ41pDEYOSHdEkV89aZecZZUHQGrLDOTbdqRMmZfPO2NXX8ykw9f013H83yGuiKAJdZtGJygak69xEM4LMTJxP9TXXOOWH/Oo58Wa+DKT9qJAsmICOUciaXX7NQ6UF1U12kG7rShcd6sVNRUR4pCl/f950bcJJRK8= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(396003)(376002)(136003)(39860400002)(346002)(451199015)(40470700004)(46966006)(36840700001)(316002)(82740400003)(110136005)(36756003)(4744005)(6666004)(8936002)(356005)(40460700003)(1076003)(81166007)(54906003)(186003)(83380400001)(16526019)(336012)(70206006)(4326008)(8676002)(41300700001)(70586007)(2616005)(82310400005)(2906002)(7416002)(478600001)(36860700001)(26005)(5660300002)(40480700001)(47076005)(426003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Nov 2022 10:41:42.7802 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 41817502-b894-4b91-6bfd-08dac23efdce X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT031.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6717 Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org The link capabilities of a PCI device are read when enumerating its dports. This is done by reading the PCI config space. If that fails port enumeration ignores that error. However, reading the PCI config space should reliably work. To reduce some complexity to the code flow when factoring out parts of the code in match_add_dports() for later reuse, change this to throw an error. Signed-off-by: Robert Richter --- drivers/cxl/core/pci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index 0dbbe8d39b07..8271b8abde7a 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -47,7 +47,7 @@ static int match_add_dports(struct pci_dev *pdev, void *data) return 0; if (pci_read_config_dword(pdev, pci_pcie_cap(pdev) + PCI_EXP_LNKCAP, &lnkcap)) - return 0; + return -ENXIO; rc = cxl_find_regblock(pdev, CXL_REGLOC_RBI_COMPONENT, &map); if (rc) From patchwork Wed Nov 9 10:40:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Richter X-Patchwork-Id: 13037350 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B9920C43219 for ; Wed, 9 Nov 2022 10:42:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231129AbiKIKmA (ORCPT ); Wed, 9 Nov 2022 05:42:00 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55892 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231185AbiKIKl4 (ORCPT ); Wed, 9 Nov 2022 05:41:56 -0500 Received: from NAM02-DM3-obe.outbound.protection.outlook.com (mail-dm3nam02on2042.outbound.protection.outlook.com [40.107.95.42]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 023AD24BF5; Wed, 9 Nov 2022 02:41:45 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=USCOF7w3xwcxEoLfGpqF42/Xu41D/oAu5CVlQ+K3lcweACqHSF/mAGdmHAsL66BmA7vpDjrb5twzQGUZme4I7/YVaqR10XdhTyY956IHBb/qwdl+6LOlDzd4olG0Ph0XJ8YUTT3X8Gltmq+/X63xe5HRgKxRTtQjRJVyeM+OCIQypzBISj23DzLXL1ThIwC9TFYYPWrmJjN2Lp2giz5PX0WuDLl6kqLTP7OBwqQfLzCozZR/aXkdYGeCMLMdzWb0LKhzxxXujIvylInqOwjKvufQId2nYKSoAaBSljUd6xsI1buw/I6nNsEqgC/0ZN2szTi2D7P6QoAVfqtMfOD1Og== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=fKDHc51d7FEG0Lu5nY4eByWXC99jgX1kSwZm+TRGAHw=; b=Y9cOTi6WVx0pxiHSOcgYLTyJ9YENtpcJmMnSpVEUbFWKTfYZh81Ochtu8OvKa5ULxwRYzyK8cPr6LtwQZoETK5algqV6Gz8CNYt7YnH+rLs4N5BIO4Lifm4IixVIyBA9PvW9w6NwldLgz9Z89MkeE3pWSUAPgYKgk5+wJ09PXZkO75EHgK7IRNZJcb7J9byczSFk3/PsX+4dcTn09eD9MxVF3hPLVbXSbtvNrURPP/JAA1IdmQYPlFExTfSknQIenXIO6MlWW5RNMAvzY+XnUX/HyHXKRY7B/nOnxaOeMVkUN7EEPVudQwsEhfztmhKX/2YqsPTxOgIOzXtoTtya2Q== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=intel.com smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=fKDHc51d7FEG0Lu5nY4eByWXC99jgX1kSwZm+TRGAHw=; b=vHd+1d43xMCPm00zPhiVwRtid5K5I6WXpwUB3e+kjRrGq14/17R3HBby8zzuQX4VqBV6EkjCZgI9udmU1GLtb9TbWYlCncsmS3mAD3yhWVWLhAOBO6u9g5MdpABloQs2Bm54CiYzQDGOukaA7IRvBF4nOXZqeAFT7f8ccFa/xjw= Received: from BN0PR04CA0063.namprd04.prod.outlook.com (2603:10b6:408:ea::8) by DM4PR12MB5216.namprd12.prod.outlook.com (2603:10b6:5:398::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5791.27; Wed, 9 Nov 2022 10:41:43 +0000 Received: from BN8NAM11FT031.eop-nam11.prod.protection.outlook.com (2603:10b6:408:ea:cafe::88) by BN0PR04CA0063.outlook.office365.com (2603:10b6:408:ea::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5791.27 via Frontend Transport; Wed, 9 Nov 2022 10:41:43 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT031.mail.protection.outlook.com (10.13.177.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5813.12 via Frontend Transport; Wed, 9 Nov 2022 10:41:43 +0000 Received: from rric.localdomain (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.31; Wed, 9 Nov 2022 04:41:38 -0600 From: Robert Richter To: Alison Schofield , Vishal Verma , Ira Weiny , Ben Widawsky , Dan Williams CC: , , Bjorn Helgaas , "Rafael J. Wysocki" , Len Brown , Jonathan Cameron , "Davidlohr Bueso" , Dave Jiang , Robert Richter Subject: [PATCH v3 7/9] cxl/pci: Factor out code in match_add_dports() to pci_dev_add_dport() Date: Wed, 9 Nov 2022 11:40:57 +0100 Message-ID: <20221109104059.766720-8-rrichter@amd.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20221109104059.766720-1-rrichter@amd.com> References: <20221109104059.766720-1-rrichter@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT031:EE_|DM4PR12MB5216:EE_ X-MS-Office365-Filtering-Correlation-Id: e76397c1-a1ee-485a-0157-08dac23efe48 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 7zqoFqo/jzW42iUUSv6lS1sllGBlfaJDATCNc9zvjjUZfcTG408m4+JKnlVpOlkmBc6qMfPL6wMO+qx07ZssHQCJT4uVQ4bb4d3ekqJNnvgIakJcCXo5gxdksSa3MrImo2V/Q6O50QZffQbGaG1YPwIWSHdmkVnUtfpJrINmS2AvkmUEf8UpXx9XfZljLvReuycWcf4fXZ7ncLWc2vhMeIOt/f+D+csduUiz/dsoVTSwRiqVbC3oGmkI/fYWVybySJaCx8cbZLI/tPIxHf4SNMCFoCnzqhOCo+rRhbbCmW/TXqTAA1bxYDKGfYBvNw2y/+6Ik4tZqyK2b1tph6o3Drw0U4uPtczaflI4NK/RP5cTUosiz1T3Tl1UOyFyKPOTWONHHc0jZOlsXiCWllDsVxqKwwVETvB6TLbmBeAp0/iM45ZaDAGLPp5bQ92DAHqaxU2/+foqjT5T+NPlDdEJ2eQCi7lwn6CtB4H1GKMgulcNN+Gyd+AE4PPIeaE3z37viwGcrvOq5ak1gncZMMY4BfAwHSeKyPmK0tSVk2tofjVRe2hASReDLhf90ceJ6aQ9CTkb8YN8sKb47jOi+YRdBTdhHMAz297FMKPAoOYgMegYDpOnfiUlx3EHkmArY4VAgLP4iLhy3leCqc0cT1+9GbQM3WBCHSRSsAHyEB2bsm2ENivP6zYTjMy7fLFM/taejoDpBrI1NX8+URmgxMk9CPqfTNZCKalzE+bX3OH5l9wj4PfCpiooAPG7WyzZql5yx5uAjXdvkcq4PAmWqB9aj8WKUCjzz9fS/d0DonR0RP0= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(376002)(39860400002)(346002)(396003)(136003)(451199015)(36840700001)(46966006)(40470700004)(26005)(82740400003)(356005)(36860700001)(81166007)(82310400005)(8936002)(70586007)(41300700001)(8676002)(70206006)(4326008)(7416002)(5660300002)(110136005)(316002)(478600001)(40480700001)(54906003)(6666004)(40460700003)(426003)(47076005)(83380400001)(336012)(16526019)(1076003)(2906002)(186003)(36756003)(2616005)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Nov 2022 10:41:43.5770 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e76397c1-a1ee-485a-0157-08dac23efe48 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT031.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5216 Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org Factor out the code to register a PCI device's dport to a port. It will be reused to implement RCD mode. Signed-off-by: Robert Richter --- drivers/cxl/core/pci.c | 37 ++++++++++++++++++++++++++----------- 1 file changed, 26 insertions(+), 11 deletions(-) diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index 8271b8abde7a..667de4f125f6 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -29,14 +29,32 @@ struct cxl_walk_context { int count; }; +static int pci_dev_add_dport(struct pci_dev *pdev, struct cxl_port *port, + resource_size_t component_reg_phys) +{ + struct cxl_dport *dport; + u32 lnkcap, port_num; + + if (pci_read_config_dword(pdev, pci_pcie_cap(pdev) + PCI_EXP_LNKCAP, + &lnkcap)) + return -ENXIO; + + port_num = FIELD_GET(PCI_EXP_LNKCAP_PN, lnkcap); + dport = devm_cxl_add_dport(port, &pdev->dev, port_num, + component_reg_phys); + if (IS_ERR(dport)) + return PTR_ERR(dport); + + return 0; +} + static int match_add_dports(struct pci_dev *pdev, void *data) { struct cxl_walk_context *ctx = data; struct cxl_port *port = ctx->port; int type = pci_pcie_type(pdev); struct cxl_register_map map; - struct cxl_dport *dport; - u32 lnkcap, port_num; + resource_size_t component_reg_phys; int rc; if (pdev->bus != ctx->bus) @@ -45,21 +63,18 @@ static int match_add_dports(struct pci_dev *pdev, void *data) return 0; if (type != ctx->type) return 0; - if (pci_read_config_dword(pdev, pci_pcie_cap(pdev) + PCI_EXP_LNKCAP, - &lnkcap)) - return -ENXIO; rc = cxl_find_regblock(pdev, CXL_REGLOC_RBI_COMPONENT, &map); if (rc) dev_dbg(&port->dev, "failed to find component registers\n"); - port_num = FIELD_GET(PCI_EXP_LNKCAP_PN, lnkcap); - dport = devm_cxl_add_dport(port, &pdev->dev, port_num, - cxl_regmap_to_base(pdev, &map)); - if (IS_ERR(dport)) { - ctx->error = PTR_ERR(dport); - return PTR_ERR(dport); + component_reg_phys = cxl_regmap_to_base(pdev, &map); + rc = pci_dev_add_dport(pdev, port, component_reg_phys); + if (rc) { + ctx->error = rc; + return rc; } + ctx->count++; return 0; From patchwork Wed Nov 9 10:40:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Richter X-Patchwork-Id: 13037352 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 84DA0C43217 for ; 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Wysocki" , Len Brown , Jonathan Cameron , "Davidlohr Bueso" , Dave Jiang , Robert Richter Subject: [PATCH v3 8/9] cxl/pci: Extend devm_cxl_port_enumerate_dports() to support restricted hosts (RCH) Date: Wed, 9 Nov 2022 11:40:58 +0100 Message-ID: <20221109104059.766720-9-rrichter@amd.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20221109104059.766720-1-rrichter@amd.com> References: <20221109104059.766720-1-rrichter@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT031:EE_|DM6PR12MB4481:EE_ X-MS-Office365-Filtering-Correlation-Id: 0287038a-b35f-4394-b974-08dac23eff06 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: lEsqxFwAYunNQNz5kz9lhhq6GukyPJ3BoB8+i+cC4Cj6HdX9JooaRTJzpNM68r71lXzVK5knrM7mHI5gvK9fAEY6jTYu5EaEvBbxLirPm/kDmIkFywkhcAkX6pmgahWPdvKcW3XFlY5YGk3pvN+pJZibRe2KycBFOwJM0+Osi9hrPxafkZ7V34fMMbTJVLRS15vdy3e8yS3n3gb0nAvrExpycrkS/zOm8NYtY86goCj2LDO5yIyM3HX/sMqj1N71xGhSYgJtA3tYvXvPNiVNaF4HSvcbCSDlWlsTwxvJco7WwcGL6vdvLRAAKP5Ki5pPWz81TPHHiQKn0XKHb2Vg8QRVstfxXmVVzNRW4Mdhuusog/JYdRlzI7Z/3zGZ+3jUWIL24j2muQ5oPZj5C+nOlgvxCWpvC4lcgs48sfBlMhB7ZEI2/hxCKVundMtrH3x/JyoBC4+hM/wm1VjfRdmM5V7U7zRx0uYCTAOjLTcM0MhUrRLQ6XXsIiG4nGzveATg/PSb403XhVXRrEP0VGvpbpFUTTq/KN0uHpLKxvAs7yU7ur2Z1cJs5z0mWfPl45Y+5gAeTJZma9eNLyzIJWl5LSSDyFQOxal1sL6Wmed4c/PdsrnyNcHwywuCQx9V/S2oVWd7DtCuQ0pDwH1LcKmIsVyYCGnIH7+hIZeESh3JI6Z67xjvYESUvGn1snDcPwRL6gvfR/VxOZTHBoQzHt1XXycnDNOVHcQ+ebrVr2Y3DuVTbjnM0HWfvSe9o8Pi++xjrIJovv3zwpB4Y6KiqQ/U2c5siCTuwAVnosZKMCQdWAa/vhDblSFFg0JsQYir+WdG X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(376002)(346002)(39860400002)(136003)(396003)(451199015)(40470700004)(36840700001)(46966006)(83380400001)(47076005)(426003)(40480700001)(2906002)(478600001)(81166007)(356005)(40460700003)(36756003)(82740400003)(336012)(82310400005)(36860700001)(26005)(1076003)(186003)(2616005)(16526019)(4326008)(70586007)(316002)(8676002)(70206006)(41300700001)(54906003)(6666004)(8936002)(7416002)(110136005)(5660300002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Nov 2022 10:41:44.8269 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0287038a-b35f-4394-b974-08dac23eff06 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT031.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4481 Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org The PCIe Software View of an RCH and RCD is different to VH mode. An RCD is paired with an RCH and shows up as RCiEP. Its downstream and upstream ports are hidden to the PCI hierarchy. This different PCI topology requires a different handling of RCHs. Extend devm_cxl_port_enumerate_dports() to support restricted hosts (RCH). If an RCH is detected, register its port as dport to the device. An RCH is found if the host's dev 0 func 0 devices is an RCiEP with an existing PCIe DVSEC for CXL Devices (ID 0000h). Signed-off-by: Robert Richter --- drivers/cxl/core/pci.c | 37 ++++++++++++++++++++++++++++++++++++- 1 file changed, 36 insertions(+), 1 deletion(-) diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index 667de4f125f6..a6b1a1501db3 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -48,6 +48,37 @@ static int pci_dev_add_dport(struct pci_dev *pdev, struct cxl_port *port, return 0; } +static int restricted_host_enumerate_dport(struct cxl_port *port, + struct pci_bus *bus) +{ + struct pci_dev *pdev; + bool is_restricted_host; + int rc; + + /* Check CXL DVSEC of dev 0 func 0 */ + pdev = pci_get_slot(bus, PCI_DEVFN(0, 0)); + + is_restricted_host = pdev + && (pci_pcie_type(pdev) == PCI_EXP_TYPE_RC_END) + && pci_find_dvsec_capability(pdev, + PCI_DVSEC_VENDOR_ID_CXL, + CXL_DVSEC_PCIE_DEVICE); + if (is_restricted_host) + rc = pci_dev_add_dport(pdev, port, CXL_RESOURCE_NONE); + + pci_dev_put(pdev); + + if (!is_restricted_host) + return 0; + + dev_dbg(bus->bridge, "CXL restricted host found\n"); + + if (rc) + return rc; + + return 1; +} + static int match_add_dports(struct pci_dev *pdev, void *data) { struct cxl_walk_context *ctx = data; @@ -91,11 +122,15 @@ int devm_cxl_port_enumerate_dports(struct cxl_port *port) { struct pci_bus *bus = cxl_port_to_pci_bus(port); struct cxl_walk_context ctx; - int type; + int type, count; if (!bus) return -ENXIO; + count = restricted_host_enumerate_dport(port, bus); + if (count) + return count; + if (pci_is_root_bus(bus)) type = PCI_EXP_TYPE_ROOT_PORT; else From patchwork Wed Nov 9 10:40:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Richter X-Patchwork-Id: 13037351 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0C92CC4167D for ; Wed, 9 Nov 2022 10:42:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231147AbiKIKmC (ORCPT ); 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Wed, 9 Nov 2022 04:41:44 -0600 From: Robert Richter To: Alison Schofield , Vishal Verma , Ira Weiny , Ben Widawsky , Dan Williams , Bjorn Helgaas , "Rafael J. Wysocki" CC: , , Len Brown , Jonathan Cameron , "Davidlohr Bueso" , Dave Jiang , Robert Richter , Terry Bowman , , Subject: [PATCH v3 9/9] cxl/acpi: Set ACPI's CXL _OSC to indicate CXL1.1 support Date: Wed, 9 Nov 2022 11:40:59 +0100 Message-ID: <20221109104059.766720-10-rrichter@amd.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20221109104059.766720-1-rrichter@amd.com> References: <20221109104059.766720-1-rrichter@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT105:EE_|PH7PR12MB5687:EE_ X-MS-Office365-Filtering-Correlation-Id: 323ab923-8b23-4f2a-e6da-08dac23f0151 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: fax13Wjkm/oqgVNzJHzV5ilUftsAMVBjzQzFccCVDSIBzUK8KXCGEXouyz0bhZTiO6k1UIAr34pRS81P3/8Z+Gwqw8FKI2umx6DDI/ALw7r8xSvPa6zK8+mbtk6X0KKDRCwHuAjggwwnVcNsvsVoOsIcZYUN7Djd7/SBg3RTi7TIsJo2Q+EThhj/cVwwrZX9U5g41nJc1H28JLCQxnmoIeSEIhhn32mHEu0Hi2KYaQdFaF2SWEkMalgeiLx6UFf694/RlQJm8VwMTdZoWaiMheYJ+0vH0AHDnXMT/r8l0dGfjOeJdlfB1+YNOi7W3g3w7uphQcfMWXz0Fg12QHlyRJ5mtIlxuEiQx+68asL9vOgTjLeq1UV9j7dCtbGzgNnWVnhfUGTvcFJavfg2SDito226JWc7etMKkR4etxMtw85NHAazfnvLm8BzTDleEQsbuPYj9lgc1CgkKS20ujBzxX64nip7TO6qFo5gkmoF8TRa/QDd/7QWmx7JtT2wtSTUwSIw1GeOPRS2+CPTQX3SpMZCDumDIgXd99JOGBb/gxD+4chFtK+38aVdXys6udutUc8WW4bRwV8eb4e7mibKmddgi4p2WshACw4oT7eaz+m1M+My9Z2o3dKxR1kcdgZfS0yI9l5RFM7llnsO0Cfp1J4pqoAkGnxmPTv4LiYWSnWBAwJ9TQ0sqw2McV35cK0olLcdfha/1c37iVDUWcYhJtO6mmhF8jd4tAL8BtE6FqUrQUg+Zn6k7Nhzc8ZpcFOhOjD+IeoeYHEy4n9lX3AlKg/2AGrI1IJmwgaWNo9hfwyOZcoy9fJrUEcROalNfbNf X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(39860400002)(376002)(136003)(396003)(346002)(451199015)(36840700001)(46966006)(40470700004)(82310400005)(478600001)(54906003)(81166007)(110136005)(6666004)(356005)(316002)(47076005)(2906002)(40480700001)(26005)(4326008)(8676002)(70586007)(70206006)(82740400003)(7416002)(2616005)(36756003)(8936002)(41300700001)(5660300002)(16526019)(186003)(1076003)(83380400001)(40460700003)(426003)(336012)(36860700001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Nov 2022 10:41:48.6750 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 323ab923-8b23-4f2a-e6da-08dac23f0151 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT105.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB5687 Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org From: Terry Bowman ACPI includes a CXL _OSC support procedure to communicate the available CXL support to FW. The CXL support _OSC includes a field to indicate CXL1.1 RCH RCD support. The OS sets this bit to 1 if it supports access to RCD and RCH Port registers.[1] FW can potentially change it's operation depending on the _OSC support setting reported by the OS. The ACPI driver does not currently set the ACPI _OSC support to indicate CXL1.1 RCD RCH support. Change the capability reported to include CXL1.1. [1] CXL3.0 Table 9-26 'Interpretation of CXL _OSC Support Field' Signed-off-by: Terry Bowman Signed-off-by: Robert Richter Acked-by: Rafael J. Wysocki --- drivers/acpi/pci_root.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/acpi/pci_root.c b/drivers/acpi/pci_root.c index c8385ef54c37..094a59b216ae 100644 --- a/drivers/acpi/pci_root.c +++ b/drivers/acpi/pci_root.c @@ -492,6 +492,7 @@ static u32 calculate_cxl_support(void) u32 support; support = OSC_CXL_2_0_PORT_DEV_REG_ACCESS_SUPPORT; + support |= OSC_CXL_1_1_PORT_REG_ACCESS_SUPPORT; if (pci_aer_available()) support |= OSC_CXL_PROTOCOL_ERR_REPORTING_SUPPORT; if (IS_ENABLED(CONFIG_HOTPLUG_PCI_PCIE))