From patchwork Thu Nov 10 00:55:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 13038185 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 28C20C433FE for ; Thu, 10 Nov 2022 00:57:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=luDV01SsFEVO3pv57+xxqxensxN+wrE4aoaeXNLUNqs=; b=CkxMsWMlfVy71m tDx4ZppT45suMvNUqYfRBLxrfivCKCCjXZPYXwNmeLjPlProsAOQGP/NEiTQ+9rLXjfBbPNA2LEFd pC7LFFkC1vLinQJ+LLd5M59nBPhGzte/N9LebReQVk+pN51JNI4k11TMgkwvb00ICE2yNiYy3Keww bEpYNFznRiiQg5vN16eKWxwsr0JxQKqzcoB5gtze/60NSTRVwTQWGaVfkgjmwZLpb9NaXajQGOfqB awhpiHDC3oh0GpnitTorDjCDAqBSUmkGgSCjaczhoNQqqqXEFkK9aCJOVm7st1vUf5HICcu9+DpD8 xUNV2Zxp9RLb5jPoyd0w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1osvs4-001dcX-7u; Thu, 10 Nov 2022 00:56:44 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1osvs0-001dbv-S2 for linux-arm-kernel@lists.infradead.org; Thu, 10 Nov 2022 00:56:43 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3BE901FB; Wed, 9 Nov 2022 16:56:40 -0800 (PST) Received: from slackpad.fritz.box (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 85C833F703; Wed, 9 Nov 2022 16:56:32 -0800 (PST) From: Andre Przywara To: Rob Herring , Krzysztof Kozlowski , Chen-Yu Tsai , Samuel Holland , Jernej Skrabec Cc: Icenowy Zheng , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev Subject: [PATCH] ARM: dts: sunxi: H3/H5: Add phys property to USB HCI0 Date: Thu, 10 Nov 2022 00:55:07 +0000 Message-Id: <20221110005507.19464-1-andre.przywara@arm.com> X-Mailer: git-send-email 2.35.5 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221109_165640_990348_2C23306C X-CRM114-Status: GOOD ( 12.76 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org As many other Allwinner SoCs from the last years, the first USB host controller pair in the Allwinner H3 and H5 chips share a USB PHY with the MUSB OTG controller. This is probably the reason why we didn't have a "phys" property in those host controller nodes. This works fine as long as the MUSB controller driver is loaded, as this takes care of the proper PHY setup, including the muxing between MUSB and the HCI. However this requires the MUSB driver to be enabled and loaded, and also upsets U-Boot, which cannot use a HCI port without a "phys" property. Similar to what we did in commit cc72570747e4 ("arm64: dts: allwinner: A64: properly connect USB PHY to port 0"), add the "phys" property to the OHCI0 and EHCI0 DT nodes in the shared H3/H5 .dtsi file. This is not only the proper description of the hardware, but also avoids a nasty error message in U-Boot triggered by a recent patch. (The port never worked in host mode, but the error was suppressed due to a bug.) When using the MUSB port in OTG mode, this also fixes host mode switching, so people can use OTG adapters to connect a USB device to port 0. Signed-off-by: Andre Przywara Acked-by: Jernej Skrabec Reviewed-by: Samuel Holland Tested-by: Samuel Holland --- arch/arm/boot/dts/sunxi-h3-h5.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi index 09aefb4e90f8..686193bd6bd9 100644 --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi @@ -302,6 +302,8 @@ ehci0: usb@1c1a000 { interrupts = ; clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>; resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>; + phys = <&usbphy 0>; + phy-names = "usb"; status = "disabled"; }; @@ -312,6 +314,8 @@ ohci0: usb@1c1a400 { clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>, <&ccu CLK_USB_OHCI0>; resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>; + phys = <&usbphy 0>; + phy-names = "usb"; status = "disabled"; };