From patchwork Thu Nov 10 13:28:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Hoo X-Patchwork-Id: 13038784 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CA67BC4332F for ; Thu, 10 Nov 2022 13:29:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230000AbiKJN3G (ORCPT ); Thu, 10 Nov 2022 08:29:06 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48562 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230430AbiKJN3E (ORCPT ); Thu, 10 Nov 2022 08:29:04 -0500 Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 85622B37 for ; Thu, 10 Nov 2022 05:29:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1668086943; x=1699622943; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=enj4tN9io3koc4YxJUdQESrY3PZRj8EaFGLOmQnT/Ik=; b=FQp20qCBcv5Wf89Q5qp7gav5ygc21/iZnaZk/GgN8wy4oU8xjG0NlI4s 07o/jRte5f94MxO9ZrbvU0ZT2Mp0pku7AJ7Uwwl4ql+mdhw0bkpXY3AGa dXajgjNSP/Zh9V2/xOCfG9LSglvgqQv4fQ4VWffgcIA97djquJ5UYaxJU BJqqd0xe0eJIOESXyqD6ay1frnDG34AQoYJFEikdH2I4lM2cBEtRhab9y 11tXRn3Q6Z7OiqoyshU5PfIZW8FP2v/vspFmcz2DwpWb/bOCT/vYHQQhA a1D1ULqWrESDhGKEuJDLLNomWFlYAkw1BsTj5ksJ/YEqDVfkaqlf7jbID g==; X-IronPort-AV: E=McAfee;i="6500,9779,10526"; a="311306314" X-IronPort-AV: E=Sophos;i="5.96,153,1665471600"; d="scan'208";a="311306314" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Nov 2022 05:29:03 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10526"; a="812038305" X-IronPort-AV: E=Sophos;i="5.96,153,1665471600"; d="scan'208";a="812038305" Received: from sqa-gate.sh.intel.com (HELO robert-clx2.tsp.org) ([10.239.48.212]) by orsmga005.jf.intel.com with ESMTP; 10 Nov 2022 05:29:01 -0800 From: Robert Hoo To: pbonzini@redhat.com, seanjc@google.com, kirill.shutemov@linux.intel.com Cc: kvm@vger.kernel.org, Robert Hoo Subject: [PATCH v2 1/9] KVM: x86: Rename cr4_reserved/rsvd_* variables to be more readable Date: Thu, 10 Nov 2022 21:28:40 +0800 Message-Id: <20221110132848.330793-2-robert.hu@linux.intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20221110132848.330793-1-robert.hu@linux.intel.com> References: <20221110132848.330793-1-robert.hu@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org kvm_vcpu_arch::cr4_guest_owned_bits and kvm_vcpu_arch::cr4_guest_rsvd_bits looks confusing. Rename latter to cr4_host_rsvd_bits, because it in fact decribes the effective host reserved cr4 bits from the vcpu's perspective. Meanwhile, rename other related variables/macros to be better descriptive: * CR4_RESERVED_BITS --> CR4_HOST_RESERVED_BITS, which describes host bare metal CR4 reserved bits. * cr4_reserved_bits --> cr4_kvm_reserved_bits, which describes CR4_HOST_RESERVED_BITS + !kvm_cap_has() = kvm level cr4 reserved bits. * __cr4_reserved_bits() --> __cr4_calc_reserved_bits(), which to calc effective cr4 reserved bits for kvm or vm level, by corresponding x_cpu_has() input. Thus, by these renames, the hierarchical relations of those reserved CR4 bits is more clear. Just renames, no functional changes intended. Signed-off-by: Robert Hoo --- arch/x86/include/asm/kvm_host.h | 4 ++-- arch/x86/kvm/cpuid.c | 4 ++-- arch/x86/kvm/vmx/vmx.c | 2 +- arch/x86/kvm/x86.c | 12 ++++++------ arch/x86/kvm/x86.h | 4 ++-- 5 files changed, 13 insertions(+), 13 deletions(-) diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h index 7551b6f9c31c..ebb318433171 100644 --- a/arch/x86/include/asm/kvm_host.h +++ b/arch/x86/include/asm/kvm_host.h @@ -114,7 +114,7 @@ | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \ | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG)) -#define CR4_RESERVED_BITS \ +#define CR4_HOST_RESERVED_BITS \ (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\ | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \ | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR | X86_CR4_PCIDE \ @@ -666,7 +666,7 @@ struct kvm_vcpu_arch { unsigned long cr3; unsigned long cr4; unsigned long cr4_guest_owned_bits; - unsigned long cr4_guest_rsvd_bits; + unsigned long cr4_host_rsvd_bits; unsigned long cr8; u32 host_pkru; u32 pkru; diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index 7065462378e2..02baeb936974 100644 --- a/arch/x86/kvm/cpuid.c +++ b/arch/x86/kvm/cpuid.c @@ -352,8 +352,8 @@ static void kvm_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu) vcpu->arch.reserved_gpa_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu); kvm_pmu_refresh(vcpu); - vcpu->arch.cr4_guest_rsvd_bits = - __cr4_reserved_bits(guest_cpuid_has, vcpu); + vcpu->arch.cr4_host_rsvd_bits = + __cr4_calc_reserved_bits(guest_cpuid_has, vcpu); kvm_hv_set_cpuid(vcpu, kvm_cpuid_has_hyperv(vcpu->arch.cpuid_entries, vcpu->arch.cpuid_nent)); diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index 9dba04b6b019..45f887cfbb89 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -4246,7 +4246,7 @@ void set_cr4_guest_host_mask(struct vcpu_vmx *vmx) struct kvm_vcpu *vcpu = &vmx->vcpu; vcpu->arch.cr4_guest_owned_bits = KVM_POSSIBLE_CR4_GUEST_BITS & - ~vcpu->arch.cr4_guest_rsvd_bits; + ~vcpu->arch.cr4_host_rsvd_bits; if (!enable_ept) { vcpu->arch.cr4_guest_owned_bits &= ~X86_CR4_TLBFLUSH_BITS; vcpu->arch.cr4_guest_owned_bits &= ~X86_CR4_PDPTR_BITS; diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 9cf1ba865562..c608df1d1a20 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -108,7 +108,7 @@ u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA)); static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE); #endif -static u64 __read_mostly cr4_reserved_bits = CR4_RESERVED_BITS; +static u64 __read_mostly cr4_kvm_reserved_bits = CR4_HOST_RESERVED_BITS; #define KVM_EXIT_HYPERCALL_VALID_MASK (1 << KVM_HC_MAP_GPA_RANGE) @@ -1096,10 +1096,10 @@ EXPORT_SYMBOL_GPL(kvm_emulate_xsetbv); bool __kvm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) { - if (cr4 & cr4_reserved_bits) + if (cr4 & cr4_kvm_reserved_bits) return false; - if (cr4 & vcpu->arch.cr4_guest_rsvd_bits) + if (cr4 & vcpu->arch.cr4_host_rsvd_bits) return false; return true; @@ -12260,7 +12260,7 @@ int kvm_arch_hardware_setup(void *opaque) kvm_caps.supported_xss = 0; #define __kvm_cpu_cap_has(UNUSED_, f) kvm_cpu_cap_has(f) - cr4_reserved_bits = __cr4_reserved_bits(__kvm_cpu_cap_has, UNUSED_); + cr4_kvm_reserved_bits = __cr4_calc_reserved_bits(__kvm_cpu_cap_has, UNUSED_); #undef __kvm_cpu_cap_has if (kvm_caps.has_tsc_control) { @@ -12293,8 +12293,8 @@ int kvm_arch_check_processor_compat(void *opaque) WARN_ON(!irqs_disabled()); - if (__cr4_reserved_bits(cpu_has, c) != - __cr4_reserved_bits(cpu_has, &boot_cpu_data)) + if (__cr4_calc_reserved_bits(cpu_has, c) != + __cr4_calc_reserved_bits(cpu_has, &boot_cpu_data)) return -EIO; return ops->check_processor_compatibility(); diff --git a/arch/x86/kvm/x86.h b/arch/x86/kvm/x86.h index 829d3134c1eb..d92e580768e5 100644 --- a/arch/x86/kvm/x86.h +++ b/arch/x86/kvm/x86.h @@ -452,9 +452,9 @@ bool kvm_msr_allowed(struct kvm_vcpu *vcpu, u32 index, u32 type); #define KVM_MSR_RET_INVALID 2 /* in-kernel MSR emulation #GP condition */ #define KVM_MSR_RET_FILTERED 3 /* #GP due to userspace MSR filter */ -#define __cr4_reserved_bits(__cpu_has, __c) \ +#define __cr4_calc_reserved_bits(__cpu_has, __c) \ ({ \ - u64 __reserved_bits = CR4_RESERVED_BITS; \ + u64 __reserved_bits = CR4_HOST_RESERVED_BITS; \ \ if (!__cpu_has(__c, X86_FEATURE_XSAVE)) \ __reserved_bits |= X86_CR4_OSXSAVE; \ From patchwork Thu Nov 10 13:28:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Hoo X-Patchwork-Id: 13038785 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D33CFC43217 for ; Thu, 10 Nov 2022 13:29:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230443AbiKJN3H (ORCPT ); Thu, 10 Nov 2022 08:29:07 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48574 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229809AbiKJN3G (ORCPT ); Thu, 10 Nov 2022 08:29:06 -0500 Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5C18C1A227 for ; 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a="812038324" X-IronPort-AV: E=Sophos;i="5.96,153,1665471600"; d="scan'208";a="812038324" Received: from sqa-gate.sh.intel.com (HELO robert-clx2.tsp.org) ([10.239.48.212]) by orsmga005.jf.intel.com with ESMTP; 10 Nov 2022 05:29:03 -0800 From: Robert Hoo To: pbonzini@redhat.com, seanjc@google.com, kirill.shutemov@linux.intel.com Cc: kvm@vger.kernel.org, Robert Hoo , Jingqi Liu Subject: [PATCH v2 2/9] KVM: x86: Add CR4.LAM_SUP in guest owned bits Date: Thu, 10 Nov 2022 21:28:41 +0800 Message-Id: <20221110132848.330793-3-robert.hu@linux.intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20221110132848.330793-1-robert.hu@linux.intel.com> References: <20221110132848.330793-1-robert.hu@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org If LAM enabled, CR4.LAM_SUP is owned by guest; otherwise, reserved. Signed-off-by: Robert Hoo Reviewed-by: Jingqi Liu --- arch/x86/include/asm/kvm_host.h | 3 ++- arch/x86/kvm/kvm_cache_regs.h | 3 ++- arch/x86/kvm/x86.h | 2 ++ 3 files changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h index ebb318433171..e879082a9416 100644 --- a/arch/x86/include/asm/kvm_host.h +++ b/arch/x86/include/asm/kvm_host.h @@ -120,7 +120,8 @@ | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR | X86_CR4_PCIDE \ | X86_CR4_OSXSAVE | X86_CR4_SMEP | X86_CR4_FSGSBASE \ | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_VMXE \ - | X86_CR4_SMAP | X86_CR4_PKE | X86_CR4_UMIP)) + | X86_CR4_SMAP | X86_CR4_PKE | X86_CR4_UMIP \ + | X86_CR4_LAM_SUP)) #define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR) diff --git a/arch/x86/kvm/kvm_cache_regs.h b/arch/x86/kvm/kvm_cache_regs.h index 3febc342360c..917f1b770839 100644 --- a/arch/x86/kvm/kvm_cache_regs.h +++ b/arch/x86/kvm/kvm_cache_regs.h @@ -7,7 +7,8 @@ #define KVM_POSSIBLE_CR0_GUEST_BITS X86_CR0_TS #define KVM_POSSIBLE_CR4_GUEST_BITS \ (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \ - | X86_CR4_OSXMMEXCPT | X86_CR4_PGE | X86_CR4_TSD | X86_CR4_FSGSBASE) + | X86_CR4_OSXMMEXCPT | X86_CR4_PGE | X86_CR4_TSD | X86_CR4_FSGSBASE \ + | X86_CR4_LAM_SUP) #define X86_CR0_PDPTR_BITS (X86_CR0_CD | X86_CR0_NW | X86_CR0_PG) #define X86_CR4_TLBFLUSH_BITS (X86_CR4_PGE | X86_CR4_PCIDE | X86_CR4_PAE | X86_CR4_SMEP) diff --git a/arch/x86/kvm/x86.h b/arch/x86/kvm/x86.h index d92e580768e5..6c1fbe27616f 100644 --- a/arch/x86/kvm/x86.h +++ b/arch/x86/kvm/x86.h @@ -474,6 +474,8 @@ bool kvm_msr_allowed(struct kvm_vcpu *vcpu, u32 index, u32 type); __reserved_bits |= X86_CR4_VMXE; \ if (!__cpu_has(__c, X86_FEATURE_PCID)) \ __reserved_bits |= X86_CR4_PCIDE; \ + if (!__cpu_has(__c, X86_FEATURE_LAM)) \ + __reserved_bits |= X86_CR4_LAM_SUP; \ __reserved_bits; \ }) From patchwork Thu Nov 10 13:28:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Hoo X-Patchwork-Id: 13038786 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 061B3C4332F for ; Thu, 10 Nov 2022 13:29:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230449AbiKJN3J (ORCPT ); Thu, 10 Nov 2022 08:29:09 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48610 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230445AbiKJN3I (ORCPT ); Thu, 10 Nov 2022 08:29:08 -0500 Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9257C1FCDA for ; Thu, 10 Nov 2022 05:29:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1668086947; x=1699622947; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=aGIu5Eij+QRJOhqsOmflpRmcgZZeo4ZXTJjMKDuPV1s=; b=ijgQtZ8b45xIbN42egti8jb6xVilMjhEIvrBkS8qTktv8JJvLKQhxRdB cZMWljIWxU+vG3ri9Na0znD7yuJez9ivKVTfR4fdwT2M9XQ5FvsBHgJpq EUwZ0HgBqSqYdUrmR1f721uail6JchHVvAaLOeHiaiBV612wxeMSV/5vB MrKR7boIGhlk6g4SBAmYdDJgdGzFbDmBIPN3EKc7jEkKuFrrBZs4wmBTu G0EOZQdwW+UUebQi2A8dLEbtGnKKVGuOU/J1w1UG0WsjtgBMNAoqxMI1k O65WdFUnhgvtZc3sr/V1OpWN+rziONwDcFKYRzpjsaFhSce6gBQLhoZpK A==; X-IronPort-AV: E=McAfee;i="6500,9779,10526"; a="311306325" X-IronPort-AV: E=Sophos;i="5.96,153,1665471600"; d="scan'208";a="311306325" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Nov 2022 05:29:07 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10526"; a="812038332" X-IronPort-AV: E=Sophos;i="5.96,153,1665471600"; d="scan'208";a="812038332" Received: from sqa-gate.sh.intel.com (HELO robert-clx2.tsp.org) ([10.239.48.212]) by orsmga005.jf.intel.com with ESMTP; 10 Nov 2022 05:29:05 -0800 From: Robert Hoo To: pbonzini@redhat.com, seanjc@google.com, kirill.shutemov@linux.intel.com Cc: kvm@vger.kernel.org, Robert Hoo , Jingqi Liu Subject: [PATCH v2 3/9] KVM: x86: MMU: Rename get_cr3() --> get_pgd() and clear high bits for pgd Date: Thu, 10 Nov 2022 21:28:42 +0800 Message-Id: <20221110132848.330793-4-robert.hu@linux.intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20221110132848.330793-1-robert.hu@linux.intel.com> References: <20221110132848.330793-1-robert.hu@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org The get_cr3() is the implementation of kvm_mmu::get_guest_pgd(), well, CR3 cannot be naturally equivalent to pgd, SDM says CR3 high bits are reserved, must be zero. And now, with LAM feature's introduction, bit 61 ~ 62 are used. So, rename get_cr3() --> get_pgd() to better indicate function purpose and in it, filtered out CR3 high bits. Signed-off-by: Robert Hoo Reviewed-by: Jingqi Liu --- arch/x86/include/asm/processor-flags.h | 1 + arch/x86/kvm/mmu/mmu.c | 12 ++++++++---- 2 files changed, 9 insertions(+), 4 deletions(-) diff --git a/arch/x86/include/asm/processor-flags.h b/arch/x86/include/asm/processor-flags.h index d8cccadc83a6..bb0f8dd16956 100644 --- a/arch/x86/include/asm/processor-flags.h +++ b/arch/x86/include/asm/processor-flags.h @@ -38,6 +38,7 @@ #ifdef CONFIG_X86_64 /* Mask off the address space ID and SME encryption bits. */ #define CR3_ADDR_MASK __sme_clr(PHYSICAL_PAGE_MASK) +#define CR3_HIGH_RSVD_MASK GENMASK_ULL(63, 52) #define CR3_PCID_MASK 0xFFFull #define CR3_NOFLUSH BIT_ULL(63) diff --git a/arch/x86/kvm/mmu/mmu.c b/arch/x86/kvm/mmu/mmu.c index 6f81539061d6..04e4b38fe73a 100644 --- a/arch/x86/kvm/mmu/mmu.c +++ b/arch/x86/kvm/mmu/mmu.c @@ -4487,9 +4487,13 @@ void kvm_mmu_new_pgd(struct kvm_vcpu *vcpu, gpa_t new_pgd) } EXPORT_SYMBOL_GPL(kvm_mmu_new_pgd); -static unsigned long get_cr3(struct kvm_vcpu *vcpu) +static unsigned long get_pgd(struct kvm_vcpu *vcpu) { +#ifdef CONFIG_X86_64 + return kvm_read_cr3(vcpu) & ~CR3_HIGH_RSVD_MASK; +#else return kvm_read_cr3(vcpu); +#endif } static bool sync_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, gfn_t gfn, @@ -5042,7 +5046,7 @@ static void init_kvm_tdp_mmu(struct kvm_vcpu *vcpu, context->page_fault = kvm_tdp_page_fault; context->sync_page = nonpaging_sync_page; context->invlpg = NULL; - context->get_guest_pgd = get_cr3; + context->get_guest_pgd = get_pgd; context->get_pdptr = kvm_pdptr_read; context->inject_page_fault = kvm_inject_page_fault; @@ -5192,7 +5196,7 @@ static void init_kvm_softmmu(struct kvm_vcpu *vcpu, kvm_init_shadow_mmu(vcpu, cpu_role); - context->get_guest_pgd = get_cr3; + context->get_guest_pgd = get_pgd; context->get_pdptr = kvm_pdptr_read; context->inject_page_fault = kvm_inject_page_fault; } @@ -5206,7 +5210,7 @@ static void init_kvm_nested_mmu(struct kvm_vcpu *vcpu, return; g_context->cpu_role.as_u64 = new_mode.as_u64; - g_context->get_guest_pgd = get_cr3; + g_context->get_guest_pgd = get_pgd; g_context->get_pdptr = kvm_pdptr_read; g_context->inject_page_fault = kvm_inject_page_fault; From patchwork Thu Nov 10 13:28:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Hoo X-Patchwork-Id: 13038787 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BC12CC433FE for ; Thu, 10 Nov 2022 13:29:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230445AbiKJN3L (ORCPT ); Thu, 10 Nov 2022 08:29:11 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48652 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230455AbiKJN3K (ORCPT ); Thu, 10 Nov 2022 08:29:10 -0500 Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 25624B37 for ; Thu, 10 Nov 2022 05:29:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1668086949; x=1699622949; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ysq0MXQrb7cNxqF4pmzNNwfDEiz/w1vbRXmTb56KTJ4=; b=epWwO+PCNkc86gKcoJL1jRcP07Vv5SM+nUc6hgkzqkm9qCsl12GqpUW1 N98dyOSTa+VhnPmqnFtesgW1K7FICs4vBUhwuFC0R95vLHdXY3D5/rAgm 8tsPJjxkxaiISt4RWqnJkxmiwXha0en/hcyIRR94rfYcSTb15Dm6wKcfO UW9NObtRNBuLzx3phH7UZQj2mUo5iMuPCKeNACyWpEWN6pZvEZ3Gd2pht /npFNp4c/vjbNyrm1vKXj7sgEraAfLSBSBjcNXKWvugIjSYD3VcDVl+jr w/ruC9uvhcLZPFJfAvjRSjea5DgSOB/l5d+ETipv8Mrf1BXRul8f3i22C w==; X-IronPort-AV: E=McAfee;i="6500,9779,10526"; a="311306330" X-IronPort-AV: E=Sophos;i="5.96,153,1665471600"; d="scan'208";a="311306330" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Nov 2022 05:29:09 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10526"; a="812038333" X-IronPort-AV: E=Sophos;i="5.96,153,1665471600"; d="scan'208";a="812038333" Received: from sqa-gate.sh.intel.com (HELO robert-clx2.tsp.org) ([10.239.48.212]) by orsmga005.jf.intel.com with ESMTP; 10 Nov 2022 05:29:07 -0800 From: Robert Hoo To: pbonzini@redhat.com, seanjc@google.com, kirill.shutemov@linux.intel.com Cc: kvm@vger.kernel.org, Robert Hoo Subject: [PATCH v2 4/9] [Trivial] KVM: x86: MMU: Commets update Date: Thu, 10 Nov 2022 21:28:43 +0800 Message-Id: <20221110132848.330793-5-robert.hu@linux.intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20221110132848.330793-1-robert.hu@linux.intel.com> References: <20221110132848.330793-1-robert.hu@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org kvm_mmu_ensure_valid_pgd() is stale. Update the comments according to latest code. No function changes. P.S. Sean firstly noticed this in https://lore.kernel.org/kvm/Yg%2FguAXFLJBmDflh@google.com/. Signed-off-by: Robert Hoo --- arch/x86/kvm/mmu/mmu.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/x86/kvm/mmu/mmu.c b/arch/x86/kvm/mmu/mmu.c index 04e4b38fe73a..7ee6c84934b9 100644 --- a/arch/x86/kvm/mmu/mmu.c +++ b/arch/x86/kvm/mmu/mmu.c @@ -4451,8 +4451,12 @@ void kvm_mmu_new_pgd(struct kvm_vcpu *vcpu, gpa_t new_pgd) struct kvm_mmu *mmu = vcpu->arch.mmu; union kvm_mmu_page_role new_role = mmu->root_role; + /* + * If no root is found in cache, current active root.hpa will be (set) + * INVALID_PAGE, a new root will be set up during vcpu_enter_guest() + * --> kvm_mmu_reload(). + */ if (!fast_pgd_switch(vcpu->kvm, mmu, new_pgd, new_role)) { - /* kvm_mmu_ensure_valid_pgd will set up a new root. */ return; } From patchwork Thu Nov 10 13:28:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Hoo X-Patchwork-Id: 13038788 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 739E1C4332F for ; Thu, 10 Nov 2022 13:29:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230466AbiKJN3N (ORCPT ); Thu, 10 Nov 2022 08:29:13 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48712 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230455AbiKJN3M (ORCPT ); Thu, 10 Nov 2022 08:29:12 -0500 Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 77E1027B30 for ; Thu, 10 Nov 2022 05:29:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1668086951; x=1699622951; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=w5Fdqs5c4YIhd8LVbvf1a1RckudjlmDszQM9kd3Zq9w=; b=mmRQkCN/vLSjqwwPDhr9pqyX1HnUCqUZMUnjqsbLX+ucFKsOSb6KTxQc PD+PVl6A4866bhXvLUQLeuG2aISMnqGnakEZM/KzrBXXmj7rPIoESFFad Wl0fAIvCrZP07G7e/63g7UV5MDvvE+m1crqvydmNooUOFRZJywn1qPuPi vm/PH/Ts9DI9HD8xEd6H1eU1zqYppLLF9GyL2s5D+Q/5lEsJm4AejAKmt UbukCLUYzKJG1nO7nQSX5Nq8UOK/FiDdGbGUUjdmKqHxfXheohbDATk17 sTJFh+Pi0kHcQBkI7Sbh4rNy3Hv6bQADAYHOxusdZQ87DOjrCokGQM34/ Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10526"; a="311306339" X-IronPort-AV: E=Sophos;i="5.96,153,1665471600"; d="scan'208";a="311306339" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Nov 2022 05:29:11 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10526"; a="812038341" X-IronPort-AV: E=Sophos;i="5.96,153,1665471600"; d="scan'208";a="812038341" Received: from sqa-gate.sh.intel.com (HELO robert-clx2.tsp.org) ([10.239.48.212]) by orsmga005.jf.intel.com with ESMTP; 10 Nov 2022 05:29:09 -0800 From: Robert Hoo To: pbonzini@redhat.com, seanjc@google.com, kirill.shutemov@linux.intel.com Cc: kvm@vger.kernel.org, Robert Hoo , Jingqi Liu Subject: [PATCH v2 5/9] KVM: x86: MMU: Integrate LAM bits when build guest CR3 Date: Thu, 10 Nov 2022 21:28:44 +0800 Message-Id: <20221110132848.330793-6-robert.hu@linux.intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20221110132848.330793-1-robert.hu@linux.intel.com> References: <20221110132848.330793-1-robert.hu@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org When calc the new CR3 value, take LAM bits in. Signed-off-by: Robert Hoo Reviewed-by: Jingqi Liu --- arch/x86/kvm/mmu.h | 5 +++++ arch/x86/kvm/vmx/vmx.c | 3 ++- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/x86/kvm/mmu.h b/arch/x86/kvm/mmu.h index 6bdaacb6faa0..866f2b7cb509 100644 --- a/arch/x86/kvm/mmu.h +++ b/arch/x86/kvm/mmu.h @@ -142,6 +142,11 @@ static inline unsigned long kvm_get_active_pcid(struct kvm_vcpu *vcpu) return kvm_get_pcid(vcpu, kvm_read_cr3(vcpu)); } +static inline u64 kvm_get_active_lam(struct kvm_vcpu *vcpu) +{ + return kvm_read_cr3(vcpu) & (X86_CR3_LAM_U48 | X86_CR3_LAM_U57); +} + static inline void kvm_mmu_load_pgd(struct kvm_vcpu *vcpu) { u64 root_hpa = vcpu->arch.mmu->root.hpa; diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index 45f887cfbb89..3cddbb4a2b4a 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -3257,7 +3257,8 @@ static void vmx_load_mmu_pgd(struct kvm_vcpu *vcpu, hpa_t root_hpa, update_guest_cr3 = false; vmx_ept_load_pdptrs(vcpu); } else { - guest_cr3 = root_hpa | kvm_get_active_pcid(vcpu); + guest_cr3 = root_hpa | kvm_get_active_pcid(vcpu) | + kvm_get_active_lam(vcpu); } if (update_guest_cr3) From patchwork Thu Nov 10 13:28:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Hoo X-Patchwork-Id: 13038789 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 810F3C43219 for ; Thu, 10 Nov 2022 13:29:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230505AbiKJN3T (ORCPT ); Thu, 10 Nov 2022 08:29:19 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48828 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230477AbiKJN3P (ORCPT ); Thu, 10 Nov 2022 08:29:15 -0500 Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 68B132B189 for ; Thu, 10 Nov 2022 05:29:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1668086953; x=1699622953; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=WQ91ACDgtUWTSzevCrsxEjQ02oX/ZE3kBN+WSStYk9o=; b=WF6kBPLxAQ3iKMcMahoPQ8SVTSPzOSY2rscjbaTa0YzfGmlsrVcmvYbG lBps/zDZR95u7Ocwboh89lZn9NWSHf3hhHSrVilA3x3YH7kbzr9TifwpO DlKY2jCuREPL2XaErK8VrFitjIGe3ZnS0Wspn8gdVK2RSEW888L7yvxvc /CMI67h6bVEZbhuT5KQDDTxLklEJvF8jT/bqAsMJum5WzPigWHAvgLe3b p//eXHyXHDm26Jte0UJGhrP+94+i0nWNVCcROV/gVENLa0O+LFtnH5h7u XvndL4NdhoLGKDf0nq4HJo4ofVpBgNh2RuqnIrjSvHubGKECGxax0uFLm w==; X-IronPort-AV: E=McAfee;i="6500,9779,10526"; a="311306345" X-IronPort-AV: E=Sophos;i="5.96,153,1665471600"; d="scan'208";a="311306345" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Nov 2022 05:29:13 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10526"; a="812038345" X-IronPort-AV: E=Sophos;i="5.96,153,1665471600"; d="scan'208";a="812038345" Received: from sqa-gate.sh.intel.com (HELO robert-clx2.tsp.org) ([10.239.48.212]) by orsmga005.jf.intel.com with ESMTP; 10 Nov 2022 05:29:11 -0800 From: Robert Hoo To: pbonzini@redhat.com, seanjc@google.com, kirill.shutemov@linux.intel.com Cc: kvm@vger.kernel.org, Robert Hoo , Jingqi Liu Subject: [PATCH v2 6/9] KVM: x86: Untag LAM bits when applicable Date: Thu, 10 Nov 2022 21:28:45 +0800 Message-Id: <20221110132848.330793-7-robert.hu@linux.intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20221110132848.330793-1-robert.hu@linux.intel.com> References: <20221110132848.330793-1-robert.hu@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Define kvm_untagged_addr() per LAM feature spec: Address high bits are sign extended, from highest effective address bit. Note that LAM_U48 and LA57 has some effective bits overlap. This patch gives a WARN() on that case. Now the only applicable possible case that addresses passed down from VM with LAM bits is those for MPX MSRs. Signed-off-by: Robert Hoo Reviewed-by: Jingqi Liu --- arch/x86/kvm/vmx/vmx.c | 3 +++ arch/x86/kvm/x86.c | 5 +++++ arch/x86/kvm/x86.h | 37 +++++++++++++++++++++++++++++++++++++ 3 files changed, 45 insertions(+) diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index 3cddbb4a2b4a..09df7c131bf9 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -2130,6 +2130,9 @@ static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) (!msr_info->host_initiated && !guest_cpuid_has(vcpu, X86_FEATURE_MPX))) return 1; + + data = kvm_untagged_addr(data, vcpu); + if (is_noncanonical_address(data & PAGE_MASK, vcpu) || (data & MSR_IA32_BNDCFGS_RSVD)) return 1; diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index c608df1d1a20..fc1367011fa2 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -1811,6 +1811,11 @@ static int __kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data, case MSR_KERNEL_GS_BASE: case MSR_CSTAR: case MSR_LSTAR: + /* + * LAM applies only addresses used for data accesses. + * Tagged address should never reach here. + * Strict canonical check still applies here. + */ if (is_noncanonical_address(data, vcpu)) return 1; break; diff --git a/arch/x86/kvm/x86.h b/arch/x86/kvm/x86.h index 6c1fbe27616f..f5a2a15783c6 100644 --- a/arch/x86/kvm/x86.h +++ b/arch/x86/kvm/x86.h @@ -195,11 +195,48 @@ static inline u8 vcpu_virt_addr_bits(struct kvm_vcpu *vcpu) return kvm_read_cr4_bits(vcpu, X86_CR4_LA57) ? 57 : 48; } +static inline u64 get_canonical(u64 la, u8 vaddr_bits) +{ + return ((int64_t)la << (64 - vaddr_bits)) >> (64 - vaddr_bits); +} + static inline bool is_noncanonical_address(u64 la, struct kvm_vcpu *vcpu) { return !__is_canonical_address(la, vcpu_virt_addr_bits(vcpu)); } +#ifdef CONFIG_X86_64 +/* untag addr for guest, according to vCPU CR3 and CR4 settings */ +static inline u64 kvm_untagged_addr(u64 addr, struct kvm_vcpu *vcpu) +{ + if (addr >> 63 == 0) { + /* User pointers */ + if (kvm_read_cr3(vcpu) & X86_CR3_LAM_U57) + addr = get_canonical(addr, 57); + else if (kvm_read_cr3(vcpu) & X86_CR3_LAM_U48) { + /* + * If guest enabled 5-level paging and LAM_U48, + * bit 47 should be 0, bit 48:56 contains meta data + * although bit 47:56 are valid 5-level address + * bits. + * If LAM_U48 and 4-level paging, bit47 is 0. + */ + WARN_ON(addr & _BITUL(47)); + addr = get_canonical(addr, 48); + } + } else if (kvm_read_cr4(vcpu) & X86_CR4_LAM_SUP) { /* Supervisor pointers */ + if (kvm_read_cr4(vcpu) & X86_CR4_LA57) + addr = get_canonical(addr, 57); + else + addr = get_canonical(addr, 48); + } + + return addr; +} +#else +#define kvm_untagged_addr(addr, vcpu) (addr) +#endif + static inline void vcpu_cache_mmio_info(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn, unsigned access) { From patchwork Thu Nov 10 13:28:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Hoo X-Patchwork-Id: 13038790 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BF481C4332F for ; Thu, 10 Nov 2022 13:29:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230163AbiKJN3X (ORCPT ); Thu, 10 Nov 2022 08:29:23 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49012 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230498AbiKJN3T (ORCPT ); Thu, 10 Nov 2022 08:29:19 -0500 Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9CA3D6AEDA for ; Thu, 10 Nov 2022 05:29:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1668086955; x=1699622955; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=0KX7u92gIiOsZZYKiQHR0uesKuTfCCz/w2WdPjjpW1Y=; b=n45L/DI/o/56pIhEiz86U8elwGH05idCjK5hvEO3faLrDOWYnZOuwPHI lInGXtRBgkqacelainZcrlJC5OUR0dFbO7uHhnXJWgR4Qsq633A0QS7E0 4qngwv8k//SuVLYTJOuSz1eYbFKzrycbdvGuG3cJtjieLwg19ZdZRgFeI Y6LZLdsaXx48lcQ84mo8foKdcIQek9YFYqkNBgRSZ+myw1Ss/0lr5hYoI qPA7leDGdUO6SFvfIh6twbT7/Pa+Osho5xUoQwsxRgqjdK4CYBv15f3jJ tXGfl62hasuO203bTvnlmacpovI+NhE+5xwb7jC6HdzoA3ecm0udz7bDZ w==; X-IronPort-AV: E=McAfee;i="6500,9779,10526"; a="311306354" X-IronPort-AV: E=Sophos;i="5.96,153,1665471600"; d="scan'208";a="311306354" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Nov 2022 05:29:15 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10526"; a="812038348" X-IronPort-AV: E=Sophos;i="5.96,153,1665471600"; d="scan'208";a="812038348" Received: from sqa-gate.sh.intel.com (HELO robert-clx2.tsp.org) ([10.239.48.212]) by orsmga005.jf.intel.com with ESMTP; 10 Nov 2022 05:29:13 -0800 From: Robert Hoo To: pbonzini@redhat.com, seanjc@google.com, kirill.shutemov@linux.intel.com Cc: kvm@vger.kernel.org, Robert Hoo , Jingqi Liu Subject: [PATCH v2 7/9] KVM: x86: When judging setting CR3 valid or not, consider LAM bits Date: Thu, 10 Nov 2022 21:28:46 +0800 Message-Id: <20221110132848.330793-8-robert.hu@linux.intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20221110132848.330793-1-robert.hu@linux.intel.com> References: <20221110132848.330793-1-robert.hu@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Before apply to kvm_vcpu_is_illegal_gpa(), clear LAM bits if it's valid. Signed-off-by: Robert Hoo Reviewed-by: Jingqi Liu --- arch/x86/kvm/x86.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index fc1367011fa2..5130142fd66d 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -1231,6 +1231,14 @@ static void kvm_invalidate_pcid(struct kvm_vcpu *vcpu, unsigned long pcid) kvm_mmu_free_roots(vcpu->kvm, mmu, roots_to_free); } +static bool kvm_is_valid_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) +{ + if (guest_cpuid_has(vcpu, X86_FEATURE_LAM)) + cr3 &= ~(X86_CR3_LAM_U48 | X86_CR3_LAM_U57); + + return kvm_vcpu_is_legal_gpa(vcpu, cr3); +} + int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) { bool skip_tlb_flush = false; @@ -1254,7 +1262,7 @@ int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) * stuff CR3, e.g. for RSM emulation, and there is no guarantee that * the current vCPU mode is accurate. */ - if (kvm_vcpu_is_illegal_gpa(vcpu, cr3)) + if (!kvm_is_valid_cr3(vcpu, cr3)) return 1; if (is_pae_paging(vcpu) && !load_pdptrs(vcpu, cr3)) From patchwork Thu Nov 10 13:28:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Hoo X-Patchwork-Id: 13038791 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0E070C433FE for ; Thu, 10 Nov 2022 13:29:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230463AbiKJN30 (ORCPT ); Thu, 10 Nov 2022 08:29:26 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49082 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231127AbiKJN3V (ORCPT ); Thu, 10 Nov 2022 08:29:21 -0500 Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3F0A371F08 for ; Thu, 10 Nov 2022 05:29:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1668086957; x=1699622957; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=OwNb7EWZ/D4O23AtKTyi4Vi9E7GSZioQI5bewLzybCk=; b=fJnSsbrmUGKMJg75XdqR4guuF27HbmHmXWnXx7t+iIC45C/jFLMybvym DQfVtOH6BxGwzllkLGvcfJoYo8/bT2ZLC2ACik3/ooH/+mgfsIDcR+MBw 5CybNQ+L2yR4D5K9bICDYK7H9vaICn/0SjHHnDrgahMTMv3OusliBAIaO mdqv2wGQPZpYzEVlzlUybFdfS2kDiL26VT4bc2eBQ72BIQtQmb4CVospW mkBP/0RYg9lQSqifVq+iN39Io3YtG1simdhRBRLZlkwE6OvcMkdDTJ4RA exRBKRjF2f9fm33I78rJ+N20uXTvfUgYruNXGeHhQS4Ekj4huOwizCIQg w==; X-IronPort-AV: E=McAfee;i="6500,9779,10526"; a="311306363" X-IronPort-AV: E=Sophos;i="5.96,153,1665471600"; d="scan'208";a="311306363" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Nov 2022 05:29:17 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10526"; a="812038349" X-IronPort-AV: E=Sophos;i="5.96,153,1665471600"; d="scan'208";a="812038349" Received: from sqa-gate.sh.intel.com (HELO robert-clx2.tsp.org) ([10.239.48.212]) by orsmga005.jf.intel.com with ESMTP; 10 Nov 2022 05:29:15 -0800 From: Robert Hoo To: pbonzini@redhat.com, seanjc@google.com, kirill.shutemov@linux.intel.com Cc: kvm@vger.kernel.org, Robert Hoo Subject: [PATCH v2 8/9] KVM: x86: When guest set CR3, handle LAM bits semantics Date: Thu, 10 Nov 2022 21:28:47 +0800 Message-Id: <20221110132848.330793-9-robert.hu@linux.intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20221110132848.330793-1-robert.hu@linux.intel.com> References: <20221110132848.330793-1-robert.hu@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org When only changes LAM bits, ask next vcpu run to load mmu pgd, so that it will build new CR3 with LAM bits updates. No TLB flush needed on this case. When changes on effective addresses, no matter LAM bits changes or not, go through normal pgd update process. Signed-off-by: Robert Hoo --- arch/x86/kvm/x86.c | 24 ++++++++++++++++++++---- 1 file changed, 20 insertions(+), 4 deletions(-) diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 5130142fd66d..98890c5506da 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -1242,9 +1242,9 @@ static bool kvm_is_valid_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) { bool skip_tlb_flush = false; - unsigned long pcid = 0; + unsigned long pcid = 0, old_cr3; #ifdef CONFIG_X86_64 - bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE); + bool pcid_enabled = !!kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE); if (pcid_enabled) { skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH; @@ -1257,6 +1257,10 @@ int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) if (cr3 == kvm_read_cr3(vcpu) && !is_pae_paging(vcpu)) goto handle_tlb_flush; + if (!guest_cpuid_has(vcpu, X86_FEATURE_LAM) && + (cr3 & (X86_CR3_LAM_U48 | X86_CR3_LAM_U57))) + return 1; + /* * Do not condition the GPA check on long mode, this helper is used to * stuff CR3, e.g. for RSM emulation, and there is no guarantee that @@ -1268,8 +1272,20 @@ int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) if (is_pae_paging(vcpu) && !load_pdptrs(vcpu, cr3)) return 1; - if (cr3 != kvm_read_cr3(vcpu)) - kvm_mmu_new_pgd(vcpu, cr3); + old_cr3 = kvm_read_cr3(vcpu); + if (cr3 != old_cr3) { + if ((cr3 ^ old_cr3) & CR3_ADDR_MASK) { + kvm_mmu_new_pgd(vcpu, cr3 & ~(X86_CR3_LAM_U48 | + X86_CR3_LAM_U57)); + } else { + /* + * Though effective addr no change, mark the + * request so that LAM bits will take effect + * when enter guest. + */ + kvm_make_request(KVM_REQ_LOAD_MMU_PGD, vcpu); + } + } vcpu->arch.cr3 = cr3; kvm_register_mark_dirty(vcpu, VCPU_EXREG_CR3); From patchwork Thu Nov 10 13:28:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Hoo X-Patchwork-Id: 13038792 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F2B0AC4332F for ; Thu, 10 Nov 2022 13:29:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230498AbiKJN32 (ORCPT ); Thu, 10 Nov 2022 08:29:28 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48924 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230494AbiKJN3W (ORCPT ); Thu, 10 Nov 2022 08:29:22 -0500 Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0D4D773761 for ; Thu, 10 Nov 2022 05:29:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1668086959; x=1699622959; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ANvf/+DuZdNP+k0tyUr4KncUf13m/TMY5kMB8zUMcX8=; b=NnlvVX2q9gWTh/lfTuOvA81jNEABCE70LPs2/S8AAtMx5k/MBhk+gujt AWaebejnGmPFCxcbb0NXjV7VtvA5LCaC6+QRm9AUX4Kql2OXesLlyXElJ pNtuAIDjb2RRWDNE9XQI3A3veYxpzWgnCDspXvMwT+V3o0HlH49E8zNuc 6BsI5EGMb3Dl/5qc2/UJ9F2of9uFsHNZU2eicOJsAN33FxT7LZij5j/fB AlZjkNBxB4eN1xPlVo9JCJDcZcRMblyOtFR4Slss+jdCmdsvBAo9c2FVo RcFGhiFksV04vCkyGnfxJnPrKMnVIjR152Fu57PvuxYM/Bgh+73UYx0u3 A==; X-IronPort-AV: E=McAfee;i="6500,9779,10526"; a="311306369" X-IronPort-AV: E=Sophos;i="5.96,153,1665471600"; d="scan'208";a="311306369" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Nov 2022 05:29:18 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10526"; a="812038354" X-IronPort-AV: E=Sophos;i="5.96,153,1665471600"; d="scan'208";a="812038354" Received: from sqa-gate.sh.intel.com (HELO robert-clx2.tsp.org) ([10.239.48.212]) by orsmga005.jf.intel.com with ESMTP; 10 Nov 2022 05:29:17 -0800 From: Robert Hoo To: pbonzini@redhat.com, seanjc@google.com, kirill.shutemov@linux.intel.com Cc: kvm@vger.kernel.org, Robert Hoo , Jingqi Liu Subject: [PATCH v2 9/9] KVM: x86: LAM: Expose LAM CPUID to user space VMM Date: Thu, 10 Nov 2022 21:28:48 +0800 Message-Id: <20221110132848.330793-10-robert.hu@linux.intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20221110132848.330793-1-robert.hu@linux.intel.com> References: <20221110132848.330793-1-robert.hu@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org LAM feature is enumerated by (EAX=07H, ECX=01H):EAX.LAM[bit26]. Signed-off-by: Robert Hoo Reviewed-by: Jingqi Liu --- arch/x86/kvm/cpuid.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index 02baeb936974..49592c699272 100644 --- a/arch/x86/kvm/cpuid.c +++ b/arch/x86/kvm/cpuid.c @@ -657,7 +657,7 @@ void kvm_set_cpu_caps(void) kvm_cpu_cap_set(X86_FEATURE_SPEC_CTRL_SSBD); kvm_cpu_cap_mask(CPUID_7_1_EAX, - F(AVX_VNNI) | F(AVX512_BF16) + F(AVX_VNNI) | F(AVX512_BF16) | F(LAM) ); kvm_cpu_cap_mask(CPUID_D_1_EAX,