From patchwork Thu Nov 10 15:03:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Manna, Animesh" X-Patchwork-Id: 13038890 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B6CC5C43217 for ; Thu, 10 Nov 2022 15:08:16 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C141510E863; Thu, 10 Nov 2022 15:08:14 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 892FE10E85A for ; Thu, 10 Nov 2022 15:08:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1668092885; x=1699628885; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Jtyz+Y4HihmyN+N+GELCC4GeRdywp51ijNVK0JMy+rg=; b=UJNTRbhcCge1dgRJa3CvMgDDNX8f3eGEzRp0H6WsnEyUfoc59MoJRtbl gaT1NKnc4JBohzszqLybKp2YxtdwFSkHmfV4pKw+kAgkt8DMJtqTGk/OQ Xb9Ql22m2yUcGUnHfuw4IurdoZu3o1YYuzir0829H+kXaNSzMGSpbqxLa mCAfvEjzEgurUQYhuTQVk/wOuDVtJuRzPG12hPmDsf4M1KlKCEv3OVpEn ZEh9UsE0TmAnbsDKhPMYWGUyAuEMqAuGBf8/BP3tV0mcC+0OQ8H9wG7jF QWwJ10M9heAD7Ux/C1AZyGbXUSFQ4XbDEGtx8NENyCvZ3LPelw8nO6z3g Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10527"; a="397624598" X-IronPort-AV: E=Sophos;i="5.96,154,1665471600"; d="scan'208";a="397624598" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Nov 2022 07:08:05 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10527"; a="668436509" X-IronPort-AV: E=Sophos;i="5.96,154,1665471600"; d="scan'208";a="668436509" Received: from srr4-3-linux-101-amanna.iind.intel.com ([10.223.74.76]) by orsmga008.jf.intel.com with ESMTP; 10 Nov 2022 07:08:03 -0800 From: Animesh Manna To: intel-gfx@lists.freedesktop.org Date: Thu, 10 Nov 2022 20:33:04 +0530 Message-Id: <20221110150307.3366-2-animesh.manna@intel.com> X-Mailer: git-send-email 2.29.0 In-Reply-To: <20221110150307.3366-1-animesh.manna@intel.com> References: <20221110150307.3366-1-animesh.manna@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 1/4] drm/i915/panelreplay: dpcd register definition for panelreplay X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" DPCD register definition added to check and enable panel replay capability of the sink. Cc: Jouni Högander Signed-off-by: Animesh Manna --- include/drm/display/drm_dp.h | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h index e934aab357be..40995f8c2c2f 100644 --- a/include/drm/display/drm_dp.h +++ b/include/drm/display/drm_dp.h @@ -537,6 +537,10 @@ /* DFP Capability Extension */ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ +#define DP_PANEL_REPLAY_CAP 0x0b0 +# define DP_PANEL_REPLAY_SUPPORT (1 << 0) +# define DP_PR_SELECTIVE_UPDATE_SUPPORT (1 << 1) + /* Link Configuration */ #define DP_LINK_BW_SET 0x100 # define DP_LINK_RATE_TABLE 0x00 /* eDP 1.4 */ @@ -706,6 +710,13 @@ #define DP_BRANCH_DEVICE_CTRL 0x1a1 # define DP_BRANCH_DEVICE_IRQ_HPD (1 << 0) +#define PANEL_REPLAY_CONFIG 0x1b0 +# define DP_PANEL_REPLAY_ENABLE (1 << 0) +# define DP_PR_UNRECOVERABLE_ERROR (1 << 3) +# define DP_PR_RFB_STORAGE_ERROR (1 << 4) +# define DP_PR_ACTIVE_FRAME_CRC_ERROR (1 << 5) +# define DP_PR_SELECTIVE_UPDATE_ENABLE (1 << 6) + #define DP_PAYLOAD_ALLOCATE_SET 0x1c0 #define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1 #define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2 From patchwork Thu Nov 10 15:03:05 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Manna, Animesh" X-Patchwork-Id: 13038889 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DE526C4332F for ; Thu, 10 Nov 2022 15:08:15 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7098910E861; Thu, 10 Nov 2022 15:08:14 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id EA08C10E861 for ; Thu, 10 Nov 2022 15:08:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1668092887; x=1699628887; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Va1qbIrkMXBPrGq0KSauTcpyuA5oQINOU/LJDqiop0M=; b=AmJTnmbpDRWYSN8Ub3wxZnwJdWLQRiYzeqMGTOR7V0wOVGt9z9oB3z/t XUVmHdRK8moekeVXib7QKyO1OACNkE916G34Y9DE4Q+ehgjyO/xVjfQv7 gBGZaG64Uw7sS4OJO+5/IwF1JkNkyJgYpPTcVZTVAns15uTGYIm/ux92F XCqyx4jw5f5xw2I4qwuaF8/LbrkzZ5dIoCZqff6sW2D6b4/j4D7y+L7rv wTmrREIPSNPm9v+X9AvsgxX6/wDxp6qx2j4eIONnObn+utoX/LcRZNSJk I1uvSJCNUGzpwiD4e9QDVSwPhshE6t32qLAAfi8PoRUEnbWfRCH2AGO6g A==; X-IronPort-AV: E=McAfee;i="6500,9779,10527"; a="397624610" X-IronPort-AV: E=Sophos;i="5.96,154,1665471600"; d="scan'208";a="397624610" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Nov 2022 07:08:07 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10527"; a="668436553" X-IronPort-AV: E=Sophos;i="5.96,154,1665471600"; d="scan'208";a="668436553" Received: from srr4-3-linux-101-amanna.iind.intel.com ([10.223.74.76]) by orsmga008.jf.intel.com with ESMTP; 10 Nov 2022 07:08:06 -0800 From: Animesh Manna To: intel-gfx@lists.freedesktop.org Date: Thu, 10 Nov 2022 20:33:05 +0530 Message-Id: <20221110150307.3366-3-animesh.manna@intel.com> X-Mailer: git-send-email 2.29.0 In-Reply-To: <20221110150307.3366-1-animesh.manna@intel.com> References: <20221110150307.3366-1-animesh.manna@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 2/4] drm/i915/panelreplay: Added HAS_PANEL_REPLAY() macro X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Platforms having Display 13 and above will support panel replay feature of DP 2.0 monitor. Added a HAS_PANEL_REPLAY() macro to check for panel replay capability. Cc: Jouni Högander Signed-off-by: Animesh Manna --- drivers/gpu/drm/i915/i915_drv.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 05b3300cc4ed..ba47f4409d0b 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -873,6 +873,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, #define HAS_DDI(dev_priv) (INTEL_INFO(dev_priv)->display.has_ddi) #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->display.has_fpga_dbg) #define HAS_PSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_psr) +#define HAS_PANEL_REPLAY(dev_priv) (DISPLAY_VER(dev_priv) >= 13) #define HAS_PSR_HW_TRACKING(dev_priv) \ (INTEL_INFO(dev_priv)->display.has_psr_hw_tracking) #define HAS_PSR2_SEL_FETCH(dev_priv) (DISPLAY_VER(dev_priv) >= 12) From patchwork Thu Nov 10 15:03:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Manna, Animesh" X-Patchwork-Id: 13038892 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5A16DC433FE for ; Thu, 10 Nov 2022 15:08:38 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1ABF210E86B; Thu, 10 Nov 2022 15:08:37 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 274B410E861 for ; Thu, 10 Nov 2022 15:08:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1668092890; x=1699628890; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=9VT5bWVsI03TqQW7ZktWqDfWSCp/lSdYlTNE7VyoZGE=; b=A0e+m1aKNLWDpwj4O1HeQ232fEY+hn0sKx2GvPpIEPDwU7XxE0CEfYz3 IQSSI1nmw/XQtwRH6ZEkbfiwGq+2jlz5Oretbag20TaPF5S10kgVpYZY8 CznrO3Mi4RtsVzJAcmzL6v0oPvFOLaxpiOTjeQOA2gIWzoZp2FtMW8J/5 16OROrmS0AgRoTJa8ELjEakyRMXrTzPf1VISarKYNzgWjiNJ3TdTFF+lF gonvePRugJID5NWcncFAa6GFGdTOfEIj+7mFsBemQW2YKKgj03yqUnbTs NXo18K0LevWx1HbmQ76jX/a688Jr5p9ZE2ZeQg9EIcEoJHPf+ADYfQktc A==; X-IronPort-AV: E=McAfee;i="6500,9779,10527"; a="397624621" X-IronPort-AV: E=Sophos;i="5.96,154,1665471600"; d="scan'208";a="397624621" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Nov 2022 07:08:09 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10527"; a="668436575" X-IronPort-AV: E=Sophos;i="5.96,154,1665471600"; d="scan'208";a="668436575" Received: from srr4-3-linux-101-amanna.iind.intel.com ([10.223.74.76]) by orsmga008.jf.intel.com with ESMTP; 10 Nov 2022 07:08:08 -0800 From: Animesh Manna To: intel-gfx@lists.freedesktop.org Date: Thu, 10 Nov 2022 20:33:06 +0530 Message-Id: <20221110150307.3366-4-animesh.manna@intel.com> X-Mailer: git-send-email 2.29.0 In-Reply-To: <20221110150307.3366-1-animesh.manna@intel.com> References: <20221110150307.3366-1-animesh.manna@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 3/4] drm/i915/panelreplay: Initializaton and compute config for panel replay X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" As panel replay feature similar to PSR feature of EDP panel, so currently utilized existing psr framework for panel replay. Cc: Jouni Högander Signed-off-by: Animesh Manna --- .../drm/i915/display/intel_display_types.h | 15 +++++++ drivers/gpu/drm/i915/display/intel_dp.c | 44 +++++++++++++++---- drivers/gpu/drm/i915/display/intel_psr.c | 44 ++++++++++++++++++- drivers/gpu/drm/i915/display/intel_psr.h | 1 + 4 files changed, 93 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 8da87cbb172b..3c126bf47119 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1623,6 +1623,8 @@ struct intel_psr { bool irq_aux_error; u16 su_w_granularity; u16 su_y_granularity; + bool source_panel_replay_support; + bool sink_panel_replay_support; u32 dc3co_exitline; u32 dc3co_exit_delay; struct delayed_work dc3co_work; @@ -1926,6 +1928,11 @@ dp_to_lspcon(struct intel_dp *intel_dp) #define CAN_PSR(intel_dp) ((intel_dp)->psr.sink_support && \ (intel_dp)->psr.source_support) +#define CAN_PANEL_REPLAY(intel_dp) ((intel_dp)->psr.sink_panel_replay_support && \ + (intel_dp)->psr.source_panel_replay_support) + +#define IS_PANEL_REPLAY(intel_dp) (!intel_dp_is_edp(intel_dp)) + static inline bool intel_encoder_can_psr(struct intel_encoder *encoder) { if (!intel_encoder_is_dp(encoder)) @@ -1934,6 +1941,14 @@ static inline bool intel_encoder_can_psr(struct intel_encoder *encoder) return CAN_PSR(enc_to_intel_dp(encoder)); } +static inline bool intel_encoder_can_panel_replay(struct intel_encoder *encoder) +{ + if (!intel_encoder_is_dp(encoder)) + return false; + + return CAN_PANEL_REPLAY(enc_to_intel_dp(encoder)); +} + static inline struct intel_digital_port * hdmi_to_dig_port(struct intel_hdmi *intel_hdmi) { diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 7400d6b4c587..25bf18e40b96 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -1726,12 +1726,23 @@ static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); - /* - * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118 - * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/ - * Colorimetry Format indication. - */ - vsc->revision = 0x5; + if (crtc_state->has_psr && conn_state->connector->connector_type != + DRM_MODE_CONNECTOR_eDP) { + /* + * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223 + * VSC SDP supporting 3D stereo, Panel Replay, and Pixel + * Encoding/Colorimetry Format indication. + */ + vsc->revision = 0x7; + } else { + /* + * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118 + * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/ + * Colorimetry Format indication. + */ + vsc->revision = 0x5; + } + vsc->length = 0x13; /* DP 1.4a spec, Table 2-120 */ @@ -1840,6 +1851,21 @@ void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp, vsc->revision = 0x4; vsc->length = 0xe; } + } else if (intel_dp->psr.enabled && IS_PANEL_REPLAY(intel_dp)) { + if (intel_dp->psr.colorimetry_support && + intel_dp_needs_vsc_sdp(crtc_state, conn_state)) { + /* [Panel Replay with colorimetry info] */ + intel_dp_compute_vsc_colorimetry(crtc_state, conn_state, + vsc); + } else { + /* + * [Panel Replay without colorimetry info] + * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223 + * VSC SDP supporting 3D stereo + Panel Replay. + */ + vsc->revision = 0x6; + vsc->length = 0x10; + } } else { /* * [PSR1] @@ -3077,10 +3103,10 @@ static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc, sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */ /* - * Only revision 0x5 supports Pixel Encoding/Colorimetry Format as - * per DP 1.4a spec. + * Revision 0x5 and 0x7 supports Pixel Encoding/Colorimetry Format as + * per DP 1.4a spec and DP 2.0 spec respectively. */ - if (vsc->revision != 0x5) + if (vsc->revision != 0x5 || vsc->revision != 0x7) goto out; /* VSC SDP Payload for DB16 through DB18 */ diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index a75b37851504..50394143c798 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -983,6 +983,8 @@ void intel_psr_compute_config(struct intel_dp *intel_dp, &crtc_state->hw.adjusted_mode; int psr_setup_time; + if (CAN_PANEL_REPLAY(intel_dp)) + goto skip_psr_check; /* * Current PSR panels don't work reliably with VRR enabled * So if VRR is enabled, do not enable PSR. @@ -1026,8 +1028,14 @@ void intel_psr_compute_config(struct intel_dp *intel_dp, return; } +skip_psr_check: crtc_state->has_psr = true; - crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp, crtc_state); + + if (intel_dp_is_edp(intel_dp)) + crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp, crtc_state); + + if (IS_PANEL_REPLAY(intel_dp) && HAS_PSR2_SEL_FETCH(dev_priv)) + crtc_state->has_psr2 = intel_psr2_sel_fetch_config_valid(intel_dp, crtc_state); crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC); intel_dp_compute_psr_vsc_sdp(intel_dp, crtc_state, conn_state, @@ -2390,6 +2398,35 @@ void intel_psr_flush(struct drm_i915_private *dev_priv, } } +/** + * intel_panel_replay_init - Check for sink and source capability. + * @intel_dp: Intel DP + * + * This function is called after the initializing connector. + * (the initializing of connector treats the handling of connector capabilities) + * And it initializes basic panel replay stuff for each DP Encoder. + */ +void intel_panel_replay_init(struct intel_dp *intel_dp) +{ + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); + u8 pr_dpcd = 0; + + if (!(HAS_DP20(dev_priv) && HAS_PANEL_REPLAY(dev_priv))) + return; + + drm_dp_dpcd_readb(&intel_dp->aux, DP_PANEL_REPLAY_CAP, &pr_dpcd); + + if (!(pr_dpcd & DP_PANEL_REPLAY_SUPPORT)) { + drm_dbg_kms(&dev_priv->drm, + "Panel replay is not supported by panel\n"); + return; + } + + drm_dbg_kms(&dev_priv->drm, + "Panel replay is supported by panel\n"); + intel_dp->psr.sink_panel_replay_support = true; +} + /** * intel_psr_init - Init basic PSR work and mutex. * @intel_dp: Intel DP @@ -2404,7 +2441,7 @@ void intel_psr_init(struct intel_dp *intel_dp) struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); - if (!HAS_PSR(dev_priv)) + if (!(HAS_PSR(dev_priv) || HAS_PANEL_REPLAY(dev_priv))) return; /* @@ -2423,6 +2460,7 @@ void intel_psr_init(struct intel_dp *intel_dp) } intel_dp->psr.source_support = true; + intel_dp->psr.source_panel_replay_support = true; /* Set link_standby x link_off defaults */ if (DISPLAY_VER(dev_priv) < 12) @@ -2432,6 +2470,8 @@ void intel_psr_init(struct intel_dp *intel_dp) INIT_WORK(&intel_dp->psr.work, intel_psr_work); INIT_DELAYED_WORK(&intel_dp->psr.dc3co_work, tgl_dc3co_disable_work); mutex_init(&intel_dp->psr.lock); + + intel_panel_replay_init(intel_dp); } static int psr_get_status_and_error_status(struct intel_dp *intel_dp, diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h index 2ac3a46cccc5..38e613990418 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.h +++ b/drivers/gpu/drm/i915/display/intel_psr.h @@ -34,6 +34,7 @@ void intel_psr_flush(struct drm_i915_private *dev_priv, unsigned frontbuffer_bits, enum fb_op_origin origin); void intel_psr_init(struct intel_dp *intel_dp); +void intel_panel_replay_init(struct intel_dp *intel_dp); void intel_psr_compute_config(struct intel_dp *intel_dp, struct intel_crtc_state *crtc_state, struct drm_connector_state *conn_state); From patchwork Thu Nov 10 15:03:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Manna, Animesh" X-Patchwork-Id: 13038891 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CBE0EC4332F for ; Thu, 10 Nov 2022 15:08:27 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id CE21F10E866; Thu, 10 Nov 2022 15:08:26 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id BBAF910E863 for ; Thu, 10 Nov 2022 15:08:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1668092892; x=1699628892; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=d8nlbFFDcwOWBjiLKBCrZjjyqvi+eLmpp4ZMbSHVaFM=; b=e7GoHAbYiSGwSvMeslOt1LlMQkGoVLCOYiZPrH2cmRBb70j/Q66HmzcQ dg8uM+ghJ1RLhdypWWIjdcyHwVi13rvPYXq9svYBynIlw3G3TmzR7sKJ3 HROOT0lz3XjTRE09RxCGD4OgnLmEWo0Grf6uJ11xWtur4AoklIaAKby2F xsRGj0bspPZnfb/i8BhrIJzPRnHzfMOJxw4vQfLH46az1kXyexo6ZgWnv swzB+aKgvOBCrgaHa6Mqf+rl2Xrh/yCamC6svYR48XzDOnNHKKK1IZAkU g+xiVefKqwisyGdywtOYzLOql6yH64dgdqPwfMRfLkMsPJGCjHiR92ovQ g==; X-IronPort-AV: E=McAfee;i="6500,9779,10527"; a="397624625" X-IronPort-AV: E=Sophos;i="5.96,154,1665471600"; d="scan'208";a="397624625" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Nov 2022 07:08:12 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10527"; a="668436586" X-IronPort-AV: E=Sophos;i="5.96,154,1665471600"; d="scan'208";a="668436586" Received: from srr4-3-linux-101-amanna.iind.intel.com ([10.223.74.76]) by orsmga008.jf.intel.com with ESMTP; 10 Nov 2022 07:08:10 -0800 From: Animesh Manna To: intel-gfx@lists.freedesktop.org Date: Thu, 10 Nov 2022 20:33:07 +0530 Message-Id: <20221110150307.3366-5-animesh.manna@intel.com> X-Mailer: git-send-email 2.29.0 In-Reply-To: <20221110150307.3366-1-animesh.manna@intel.com> References: <20221110150307.3366-1-animesh.manna@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 4/4] drm/i915/panelreplay: enable/disable panel replay X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" TRANS_DP2_CTL register is programmed to enable panel replay from source and sink is enabled through panel replay dpcd configuration address. Note: Currently enabled full-screen live active frame update mode of panel replay. Panel replay also can be enabled in selective update mode which will be enabled in a incremental approach. Cc: Jouni Högander Signed-off-by: Animesh Manna --- drivers/gpu/drm/i915/display/intel_psr.c | 30 ++++++++++++++++++++---- 1 file changed, 26 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 50394143c798..b6406c334316 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -395,8 +395,14 @@ static void intel_psr_enable_sink(struct intel_dp *intel_dp) struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); u8 dpcd_val = DP_PSR_ENABLE; - /* Enable ALPM at sink for psr2 */ + if (intel_dp->psr.enabled && IS_PANEL_REPLAY(intel_dp)) { + drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG, + DP_PANEL_REPLAY_ENABLE); + return; + } + if (intel_dp->psr.psr2_enabled) { + /* Enable ALPM at sink for psr2 */ drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG, DP_ALPM_ENABLE | DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE); @@ -526,6 +532,17 @@ static u32 intel_psr2_get_tp_time(struct intel_dp *intel_dp) return val; } +static void dg2_activate_panel_replay(struct intel_dp *intel_dp) +{ + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); + + intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder), + ADLP_PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE); + + intel_de_rmw(dev_priv, TRANS_DP2_CTL(intel_dp->psr.transcoder), 0, + TRANS_DP2_PANEL_REPLAY_ENABLE); +} + static void hsw_activate_psr2(struct intel_dp *intel_dp) { struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); @@ -1101,8 +1118,10 @@ static void intel_psr_activate(struct intel_dp *intel_dp) drm_WARN_ON(&dev_priv->drm, intel_dp->psr.active); lockdep_assert_held(&intel_dp->psr.lock); - /* psr1 and psr2 are mutually exclusive.*/ - if (intel_dp->psr.psr2_enabled) + /* psr1, psr2 and panel-replay are mutually exclusive.*/ + if (intel_dp->psr.enabled && IS_PANEL_REPLAY(intel_dp)) + dg2_activate_panel_replay(intel_dp); + else if (intel_dp->psr.psr2_enabled) hsw_activate_psr2(intel_dp); else hsw_activate_psr1(intel_dp); @@ -1300,7 +1319,10 @@ static void intel_psr_exit(struct intel_dp *intel_dp) return; } - if (intel_dp->psr.psr2_enabled) { + if (intel_dp->psr.enabled && !intel_dp_is_edp(intel_dp)) { + intel_de_rmw(dev_priv, TRANS_DP2_CTL(intel_dp->psr.transcoder), + TRANS_DP2_PANEL_REPLAY_ENABLE, 0); + } else if (intel_dp->psr.psr2_enabled) { tgl_disallow_dc3co_on_psr2_exit(intel_dp); val = intel_de_read(dev_priv, EDP_PSR2_CTL(intel_dp->psr.transcoder));