From patchwork Thu Nov 10 17:17:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akhil R X-Patchwork-Id: 13039027 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1B19EC4332F for ; Thu, 10 Nov 2022 17:18:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231126AbiKJRSk (ORCPT ); Thu, 10 Nov 2022 12:18:40 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43458 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231299AbiKJRSg (ORCPT ); Thu, 10 Nov 2022 12:18:36 -0500 Received: from NAM10-BN7-obe.outbound.protection.outlook.com (mail-bn7nam10on2059.outbound.protection.outlook.com [40.107.92.59]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 38D16260F; Thu, 10 Nov 2022 09:18:29 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=QXyKaW+cjYCrjwV7fTHuOB8rNM7hAdw25m4md4adPnEooX1h+yEs4qgPN5Rjty6s0+vx4uXpg42NN9/jwGeKhbQSz0f3VKX4O3OqR8AfXklIc92Xiec8JK6RKMqsdYIHX74rv1TqJw39YYfVbAsoK7P+XJhXKPimsC+WV4LFMmrVGBjKaO5QcpHOvLXpT+UH9+Ao8HAC411y3wTh3WgMh1B/YH7F8ALNZlV0WrlaqMgc5ntr/ihQPutTnAdlYajM7CJH7kHqHTpVFJrFNLupQd4Bj9wOUmRiXES3TcTCOruu1+fABa4cR6hMXCiBRR91xAB8oPhpdfmSBTCONvJD9w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=CcNsg0PyKRSv1Zk79CE+WFsFraZQObCbC/s1d368nck=; b=QYn+Bt5e4MxI1cEd8f9a7o6NseGGzcCqtM9J0oYP3kwN4rybMNnw0n3rVLc4YYp/fkMw0wYfuzfvby9bFpXSLfA1/aKolPcz70PmfbezHS2vjV7KipuyYU9gKosOosvAAsZc9u+ftRaVp1+VqoGYWf5d856lJuTmszk4TKg8SHBWolykZ7IEMJ5cjcyYGSZtV32JcLut3ZpYa7ISWFZrTZbbI3CUdSMWK7L+rUtV/SgnRMZAqA/EMJbcDtKQDp5Y3il1o52g/MbPMruOUY/0ePBvozv+UDSif4xW3JluOVzbkAK1xOQrnBGtVKLbFgx903MGAW0RIL1TcT+mNX5F+g== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.232) smtp.rcpttodomain=kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=CcNsg0PyKRSv1Zk79CE+WFsFraZQObCbC/s1d368nck=; b=jhsDWBcDkkhNIKz8w2w0+xq48pgQ4BeDqEVv0W5cGDeFe75PVFb5LPbFQPLRJkryI21LQQ7zMLZNji2tRngnEo9fc10cKYiymQVtq6TC0g7KpB9iPPb5GHzXNeUzb3diFfrP7DhHXHK7u6w4g7XOdzZOVz2vg6ozVVDW4ogHpmuCKCeJBdRWFKPOI1lqaInfRb6S/YYGiFaC6NPsr+3pBk15tnIpyhERYpwFvY+/QUoIH0efElTPWfc+QN28JwsQ1CXPuL4d9wF1F52fFcFY5xAXbeHz4Z87XLtxrKVcqpnp+UsmT91rCnuMu4mflrjP9TZBexbcz9Q0RA+z/AOvbA== Received: from DM6PR11CA0036.namprd11.prod.outlook.com (2603:10b6:5:190::49) by CH2PR12MB4972.namprd12.prod.outlook.com (2603:10b6:610:69::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5791.29; Thu, 10 Nov 2022 17:18:27 +0000 Received: from DM6NAM11FT063.eop-nam11.prod.protection.outlook.com (2603:10b6:5:190:cafe::19) by DM6PR11CA0036.outlook.office365.com (2603:10b6:5:190::49) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5813.13 via Frontend Transport; Thu, 10 Nov 2022 17:18:26 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.232) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.232 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.232; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.232) by DM6NAM11FT063.mail.protection.outlook.com (10.13.172.219) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5813.12 via Frontend Transport; Thu, 10 Nov 2022 17:18:26 +0000 Received: from drhqmail203.nvidia.com (10.126.190.182) by mail.nvidia.com (10.127.129.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.26; Thu, 10 Nov 2022 09:18:15 -0800 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail203.nvidia.com (10.126.190.182) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Thu, 10 Nov 2022 09:18:15 -0800 Received: from BUILDSERVER-IO-L4T.nvidia.com (10.127.8.14) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.986.36 via Frontend Transport; Thu, 10 Nov 2022 09:18:11 -0800 From: Akhil R To: , , , , , , , , , , , CC: Subject: [PATCH v4 1/3] dt-bindings: dmaengine: Add dma-channel-mask to Tegra GPCDMA Date: Thu, 10 Nov 2022 22:47:46 +0530 Message-ID: <20221110171748.40304-2-akhilrajeev@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221110171748.40304-1-akhilrajeev@nvidia.com> References: <20221110171748.40304-1-akhilrajeev@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT063:EE_|CH2PR12MB4972:EE_ X-MS-Office365-Filtering-Correlation-Id: f93ce0d5-ae6b-45a6-028b-08dac33f9499 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 3Nsfnm2BJ93V3KqARB+/FbeYI6YCTntmEu8fn/oMRWvosSvePBUzl8S/axbB6uT5UDlDa4cvJMzjztgVVbumNDxPWI3zaUw7kSn5BWOYy8I7FmqnGzcyZkAzKCghjmlnEFJc6iSy52kIRiOFXVqNWoGlqBKPJ6TFOEV/9MIdh60eDxldN4fJcebWSz8urHNBwwi15Efq5Cb0k2ECQIxMBOgG+IHJYq5fMGCPH/UvLNs3ZNXo5M9pveYzT5F7huLc3W5FDH5bdOvOh2a10eVWWO7cXMwU/8CqybQAeRPb4ktDzPpqIbw1K1fOTps/7vjbqkipcxlSYRzoykwD4rQpQiFenSlTB0AiyUg6NPJ9ADLa/zTKoxGOuKsRiVtg7i63i2ndxyGOARONZHma7jK6C/fnsPgbqInhpGV7kTK0iPuNIbx6ERJ1NApo0wZMSOX4NJ0QohkArdNLUl1uioQRQt3P3RMz0Kdfg08EF1OCgosyM8PlNm6/r2CVa4CrWKNEaopGuFb6kb0a5biToKI3dolrUfuQynezwBJT9dUoHkzRuk8fkMPFGoaaDRGkdiwmzYHXy0iDHP3115jGVUS581wO2+HvCZRL3WAb+U+8tDN/YYgw19F66fH38n0kUEwnyvx3B54xFnBsvh87FJ11mjb+rjrsndMqxR7wT3iHUdJSMrOljcLN/5llna442ty58EELv0Wz+xsfHgHbxgDbxGHyasbRuFgWIp1Z/ympmDotRtwR0WEMcy0U25jWDrSsCHVkV7BVNjwF+jXOHiiTbkhq4uqv0OQwP5sRUouUZL0= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230022)(4636009)(376002)(136003)(396003)(346002)(39860400002)(451199015)(40470700004)(46966006)(36840700001)(5660300002)(7416002)(2906002)(110136005)(316002)(82310400005)(82740400003)(41300700001)(8936002)(47076005)(36860700001)(70586007)(70206006)(40480700001)(1076003)(8676002)(6666004)(107886003)(186003)(921005)(36756003)(7696005)(7636003)(86362001)(4326008)(336012)(40460700003)(426003)(83380400001)(478600001)(2616005)(356005)(26005);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Nov 2022 17:18:26.8351 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f93ce0d5-ae6b-45a6-028b-08dac33f9499 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT063.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4972 Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org Add dma-channel-mask property in Tegra GPCDMA document. The property would help to specify the channels to be used in kernel and reserve few for the firmware. This was previously achieved by limiting the channel number to 31 in the driver. This is wrong and does not align with the hardware. Correct this and set the max interrupts to 32. Signed-off-by: Akhil R Acked-by: Thierry Reding Acked-by: Krzysztof Kozlowski --- .../devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml b/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml index c8894476b6ab..851bd50ee67f 100644 --- a/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml +++ b/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml @@ -39,7 +39,7 @@ properties: Should contain all of the per-channel DMA interrupts in ascending order with respect to the DMA channel index. minItems: 1 - maxItems: 31 + maxItems: 32 resets: maxItems: 1 @@ -52,6 +52,9 @@ properties: dma-coherent: true + dma-channel-mask: + maxItems: 1 + required: - compatible - reg @@ -60,6 +63,7 @@ required: - reset-names - "#dma-cells" - iommus + - dma-channel-mask additionalProperties: false @@ -108,5 +112,6 @@ examples: #dma-cells = <1>; iommus = <&smmu TEGRA186_SID_GPCDMA_0>; dma-coherent; + dma-channel-mask = <0xfffffffe>; }; ... From patchwork Thu Nov 10 17:17:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akhil R X-Patchwork-Id: 13039028 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B1EF7C433FE for ; Thu, 10 Nov 2022 17:18:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231277AbiKJRSs (ORCPT ); Thu, 10 Nov 2022 12:18:48 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43208 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231207AbiKJRSk (ORCPT ); Thu, 10 Nov 2022 12:18:40 -0500 Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2064.outbound.protection.outlook.com [40.107.94.64]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5B566389E; Thu, 10 Nov 2022 09:18:37 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=eYpI2ZhAawWlMg1WuX/1EgTI3SWZcfbJupl4a6a3mZTo+y5l7wUeoo84XeSsbbJ1NVjgwDVoBhSUZd9qhbLtZKEMlCX29P4ih3AoHNUpmD8YGZ7hC0IrzJwrU9QUE8BaJ+4pRRRlMRDLVgk7eZJfG7hwmLUfVp20myp5ibzgEuJIctm2a+iGHo0Iti26bx9+G5hGYw0AC7a3J8/Vc/INKCLfDpqNQjzYNVOywXokZVkJpuZiFQdf/Vh0PtD8GouAPWV6hlPz91QyiZ9HrZYbuVgu1tHxpIh239g7F9C+QQp+i0244YFEkMIyd7bk9Crwsx0Zi8BXN0cxvPBnQoYqMQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=X9OUoxiAtDFHGh6iYksq1cMzSmXUw/llWUw8o5SxYjQ=; b=l96vdMkPa9HqLRhD1SxLGVzPy3PwLN/SRg2iJlVCPXON0cYpeX6nOnEmZ+TOYnzWXdznOQP2kEEIWZXwowSJDrFCN/HoyTwx46rgOpO3yhQ8eFoWc/IF5Is7vLvc4ZKLFmxWoLXgVFKjAVsi+948rP7TrFSmKqqo/Ve9DNz6MofAHJQ3x7bJCaPHLpImUnW1mXZRuI4EnXRMNelAVQSXLca+4SkkitnHbFB5nTiwswQTzbt8N8+Tg6A0EUCJCDf9JRmR57KY9WOTtOcHukIzQeb/r2g2ZWOIdRC2CHKj0KcVYCDh3wDbK5FaIACpsBhKFCb7EJB0ErJSrJ3kv9de3w== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.232) smtp.rcpttodomain=kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=X9OUoxiAtDFHGh6iYksq1cMzSmXUw/llWUw8o5SxYjQ=; b=G9nCyEqU788aIIb1TcPbNq09/yBoZf0UPmsl9CX38nh6V93bUnLGna0OIf4wpFif5AP2+mzzX5NtX2E9Sbj5UT6V4UVtc9uC9bTlJsqeaMTj9D0cz90KRqOSvlFSr00V3wy//fa4NmMGATFYQKyEL/SbBGDl2vVK/bYeTkFpJPZOsUSYmQzyCov1UfFA1P2u8ozVeZgz8T/hCdctLQfDu0fD59J09A+IJ0HcZHAs0owv9WpbP1qVjxNI8/Tg4MzsHA26USFZtW1/A2rrof3LWZZ2xZNZJcbl6+J5edmBUd2eEm+NWTvwpNSMLADmSAe/AHVQWJG2SypC6N/0EtMpWg== Received: from DM6PR11CA0002.namprd11.prod.outlook.com (2603:10b6:5:190::15) by PH8PR12MB7328.namprd12.prod.outlook.com (2603:10b6:510:214::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5791.26; Thu, 10 Nov 2022 17:18:35 +0000 Received: from DM6NAM11FT010.eop-nam11.prod.protection.outlook.com (2603:10b6:5:190:cafe::5c) by DM6PR11CA0002.outlook.office365.com (2603:10b6:5:190::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5813.13 via Frontend Transport; Thu, 10 Nov 2022 17:18:35 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.232) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.232 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.232; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.232) by DM6NAM11FT010.mail.protection.outlook.com (10.13.172.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5813.12 via Frontend Transport; Thu, 10 Nov 2022 17:18:35 +0000 Received: from drhqmail201.nvidia.com (10.126.190.180) by mail.nvidia.com (10.127.129.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.26; Thu, 10 Nov 2022 09:18:28 -0800 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail201.nvidia.com (10.126.190.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Thu, 10 Nov 2022 09:18:27 -0800 Received: from BUILDSERVER-IO-L4T.nvidia.com (10.127.8.14) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.986.36 via Frontend Transport; Thu, 10 Nov 2022 09:18:24 -0800 From: Akhil R To: , , , , , , , , , , , CC: Subject: [PATCH v4 2/3] arm64: tegra: Add dma-channel-mask in GPCDMA node Date: Thu, 10 Nov 2022 22:47:47 +0530 Message-ID: <20221110171748.40304-3-akhilrajeev@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221110171748.40304-1-akhilrajeev@nvidia.com> References: <20221110171748.40304-1-akhilrajeev@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT010:EE_|PH8PR12MB7328:EE_ X-MS-Office365-Filtering-Correlation-Id: 81cb2831-7d75-451b-64bb-08dac33f99d6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: DMOEStrb9POMUwUssmkphQDjW2Z6+vEZ/A/x9bNUhu7tNq08MAhavbur4H5pivfPGRoDvgGmvAtN30zg23YUCs1JjQnbDztOVAeBx+0IcgjfcZJ5ZXo4y+8ApNad5CHo2oJ3s8qI0X/DBMX4kpLgM5qWg86Tkddvas3z3Y8g1ezhdhggnJNqIutehQgCoEhrv4GEShw9g6L+yIqra9STrfAMElwOyJ7XfxbaqtXrFDyCl0lO7dVmlgeY2utNXAYggrJrlTtuK1eBhIBvSpR+uf9YwEq3cnjQxAh64T/CmiURP6cYM81FJsmEfRwBR9JvJvsIIcVgI0XUXHCWDoyO+UzWgz+2nXXtHDwv/FCRbeVxQZCuxi9vWsSj6hpqtyriF6DdPWFVKHRCxgFJnXMYJI0H96MNAE4FpJuNks+EzT4w2qQ7cqj+2BNXfW3mDR4I67ojdAkfGqdTPkJNq2pVTNkKXheh0uTWI42lx/cp/whcwl99PuFgb6Ac9WKaLiTI2EfA5YSvIuOB7vLj9fFCKKu4p5Q1+0IpCryCqcjm6MkSYWM1M4JYhIVcW++jH+aeKQW3TeMGHQRKf2pEFyEewAMfXhUSmBs6oWietJUgQ4gVZzhp9qiU7k0zug4TS3cI9bQ42JZBelCgNlbXQJq/UkTn+E/mlBYL9das4gQ8HxKMhB6zXuvzu8T+FFUFK2nWGwoWZC0Mi9BDZep5GtH7usYXFcl9m2uCZsBB0Uea/e+ENveNPgQpe5eZ7SoPvp4/bdiOkHZgIcNJWWTWadbAiXVNHF6PqGfgHDm8L2kv/g4= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230022)(4636009)(376002)(346002)(39860400002)(136003)(396003)(451199015)(46966006)(40470700004)(36840700001)(7636003)(36756003)(36860700001)(82310400005)(40480700001)(921005)(356005)(7696005)(86362001)(40460700003)(82740400003)(316002)(83380400001)(107886003)(8936002)(70586007)(2616005)(110136005)(6666004)(5660300002)(478600001)(26005)(47076005)(426003)(336012)(186003)(70206006)(2906002)(1076003)(7416002)(8676002)(41300700001)(4326008);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Nov 2022 17:18:35.6260 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 81cb2831-7d75-451b-64bb-08dac33f99d6 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT010.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB7328 Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org Add dma-channel-mask property in Tegra GPCDMA device tree node. The property would help to specify the channels to be used in kernel and reserve few for the firmware. This was previously achieved by limiting the channel number to 31 in the driver. This is wrong and does not align with the hardware. Correct this and update the interrupts property to list all 32 interrupts. Signed-off-by: Akhil R --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 4 +++- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 4 +++- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 4 +++- 3 files changed, 9 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 6602fe421ee8..db479064ff72 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -78,7 +78,8 @@ reg = <0x0 0x2600000 0x0 0x210000>; resets = <&bpmp TEGRA186_RESET_GPCDMA>; reset-names = "gpcdma"; - interrupts = , + interrupts = , + , , , , @@ -112,6 +113,7 @@ #dma-cells = <1>; iommus = <&smmu TEGRA186_SID_GPCDMA_0>; dma-coherent; + dma-channel-mask = <0xfffffffe>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 28740c014f1d..fb073c459234 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -142,7 +142,8 @@ reg = <0x2600000 0x210000>; resets = <&bpmp TEGRA194_RESET_GPCDMA>; reset-names = "gpcdma"; - interrupts = , + interrupts = , + , , , , @@ -176,6 +177,7 @@ #dma-cells = <1>; iommus = <&smmu TEGRA194_SID_GPCDMA_0>; dma-coherent; + dma-channel-mask = <0xfffffffe>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index 5d7df32fd159..e1165b75f708 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -28,7 +28,8 @@ reg = <0x2600000 0x210000>; resets = <&bpmp TEGRA234_RESET_GPCDMA>; reset-names = "gpcdma"; - interrupts = , + interrupts = , + , , , , @@ -61,6 +62,7 @@ ; #dma-cells = <1>; iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; + dma-channel-mask = <0xfffffffe>; dma-coherent; }; From patchwork Thu Nov 10 17:17:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akhil R X-Patchwork-Id: 13039029 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E01E6C433FE for ; Thu, 10 Nov 2022 17:18:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231402AbiKJRSy (ORCPT ); Thu, 10 Nov 2022 12:18:54 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43558 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231396AbiKJRSn (ORCPT ); Thu, 10 Nov 2022 12:18:43 -0500 Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2081.outbound.protection.outlook.com [40.107.94.81]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2346864EA; Thu, 10 Nov 2022 09:18:42 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=B13nDrTm/hD7NBJbMft4X9HZ4te1LTNtg56e/LDKPVjdAxH2IUH47bxyEJDfjgcEH+6cVUbLAO5RF3eYowKdWF9YTD3MNyBKpzsJDXmuoXs0vpk9TpFk2DBvy/o8PMoEkTekgws8xxqys7hG+/aCr/aX8Hyhpbmt02MuRP/QDuyMO/kLkkVlAX+m6/qsO7R8R2fwRdr3uBpAonPzvrt/8l9eZV/0x+gFpwbP54+DcmpcWfoW5/faILIquFRHW5GmtmQkd3x5NL9lCW1INneD/d90iTLOs3XnPI2eJ0tENSm8d3TJ1sli0tw9lWXC9jU4sv5/y3v4iBsvVq6rgHaFPQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=YCJZFODP6DFHQ5IF0TtSH2Dr5BEJmkhRdfwwGd20JYQ=; b=NRwz1q9TDgmRbJSYIzmIW2UexdBLuBt7dMFoyN5Lhjy0Pz/Xrr4cT6clNHOwqKvirno1tP33XLmJjeB0F6IP/lUzx5v0D9OgWa804o91TQBiAJuGrYMcs8c0GdtuLbmkXSdPF9QsPIFpNAfyvBrtkeIiNzMvge4UJq1D8r8ObaxZKVo2y6z6Uwvk3yFKQBqGALmzwd7sppyMXn1RdV15A//RKjEwaE59it2BqYzNEo8KbKaxCn5wTVihV0g9YmPhbmLBJR4KutZWMK744u3VTfjPPrMTH0qY/V7ssKSUudkHvRwPnyai2U+L96DOfhTv2kTPJqTDa4DYQg/gYHpDIw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.232) smtp.rcpttodomain=kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=YCJZFODP6DFHQ5IF0TtSH2Dr5BEJmkhRdfwwGd20JYQ=; b=AduzH3ODETbIG3blDgYOfCKiLVG9853PhSpzDethCXo9IQyutdZ3znt9AByYGAVm1QPuXlijS5W//HdszKxsq/ytUl63uElnepMFSbbgOWixSWEQY6QlskFwEjfjInJ8l51Yu57+ALoYrxE3BvgSjKVDmmEDUVGzYp9zYWzA3zJrT1zjzUQPD7010AgDaoatcJddTZlu8fRsTLLg3u546C+fKHFHM3KJcESeAViQn4JZ25T+oWzlbD4HN/A1NPKnpxwQJi9jwWsZD3foJQ4TNbaBYAuP0gOVTrN6Ayq2cs/GvgUP1uT2ITbmbwuAhIc6lqW01EI5t7d/igEpssngyQ== Received: from DM6PR07CA0098.namprd07.prod.outlook.com (2603:10b6:5:337::31) by PH0PR12MB5450.namprd12.prod.outlook.com (2603:10b6:510:e8::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5791.25; Thu, 10 Nov 2022 17:18:39 +0000 Received: from DM6NAM11FT070.eop-nam11.prod.protection.outlook.com (2603:10b6:5:337:cafe::ca) by DM6PR07CA0098.outlook.office365.com (2603:10b6:5:337::31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5813.13 via Frontend Transport; Thu, 10 Nov 2022 17:18:39 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.232) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.232 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.232; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.232) by DM6NAM11FT070.mail.protection.outlook.com (10.13.173.51) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5813.12 via Frontend Transport; Thu, 10 Nov 2022 17:18:39 +0000 Received: from drhqmail201.nvidia.com (10.126.190.180) by mail.nvidia.com (10.127.129.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.26; Thu, 10 Nov 2022 09:18:35 -0800 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail201.nvidia.com (10.126.190.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Thu, 10 Nov 2022 09:18:34 -0800 Received: from BUILDSERVER-IO-L4T.nvidia.com (10.127.8.14) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.986.36 via Frontend Transport; Thu, 10 Nov 2022 09:18:30 -0800 From: Akhil R To: , , , , , , , , , , , CC: Subject: [PATCH v4 3/3] dmaengine: tegra: Add support for dma-channel-mask Date: Thu, 10 Nov 2022 22:47:48 +0530 Message-ID: <20221110171748.40304-4-akhilrajeev@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221110171748.40304-1-akhilrajeev@nvidia.com> References: <20221110171748.40304-1-akhilrajeev@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT070:EE_|PH0PR12MB5450:EE_ X-MS-Office365-Filtering-Correlation-Id: df145f6f-a34f-4b1a-cc32-08dac33f9bf9 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Jwg2EboKOEOtq2GrQOWAbXXLkj/a2trV3PveWPQLapqAEvf41CfWy+SyVgzZKG8iCZLuTXid7S3kwkY3hTizmG0J7fJYR9UbImKiN3RpNczZhHatEcr5BXdEvGjlqWVV0S5r2V+MP9Emdjvjlhsh7v1Au3mmL9aTNb+3H6rl76o0kGw7+iZYGOxDS87red97ZKxMKkhTvCy9TNay0UIm0hr2xoG6tomcuO0+xHQSF3FxVJw9R9Jc0/1GPjMUZFcsbI1PWnrv+SR6uNPbQra5AlOA4pxVZIvqS0+7XluBq5pW58dZ3Yc4XyqoCgSIVroJOFBo3SSupOglyGt/AYqSHbS2856ie4sGA0zNHCWZFlqVZuktzwH1f3kSQDgmUW6FoQFWZFjnI7FzSoec+eVg54Q9//ky8o78Hnism11zacoHScEFlZBFHKPpiVKc5hI7Vv8q9fsNzVJIW/vSwoesbHzNj/cOkiXZTyAA7voxlNfp5jgPJ0tNkzcGsf4Ektez6hKZmZUWBgVBrflJLLoL8jXnhKn1D6MugdtEN0dEd2+87wepQdi7aqgvKM95QnFnMlYWtU6YaopOy632s5H5y4vtWnh/tlGWAT/Y9lYY9m8adkXgy4R20WnXPIAg5akBEe9PbOwo4XhN82v3DnmN/sXyOmswNs2GW/27KNvmOtZsCiucuy9+TeNEpkLelbLQ4ZR7m0sWmZUKkYvROJhlH92+2do0jfHooVmFHuGOdB9aondkthRhSGMueffORn5gadO4Bj5VNMkZbUuXaMcJF/09dhQ90JQTOeUf5tqnxEbQhU7NdeC5z2NzWJg6QdPx9SELYjQpOt485OFQRiwCvrb1kgr89dJsnjFy9Eu7Cq0U1srIOamtRnhUXkb1FylI X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230022)(4636009)(346002)(376002)(136003)(396003)(39860400002)(451199015)(46966006)(36840700001)(40470700004)(70586007)(47076005)(2906002)(336012)(4326008)(316002)(7636003)(356005)(70206006)(7696005)(83380400001)(107886003)(8676002)(6666004)(426003)(966005)(2616005)(40480700001)(478600001)(26005)(186003)(921005)(40460700003)(86362001)(1076003)(110136005)(36756003)(7416002)(5660300002)(8936002)(36860700001)(41300700001)(82740400003)(82310400005);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Nov 2022 17:18:39.2291 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: df145f6f-a34f-4b1a-cc32-08dac33f9bf9 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT070.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB5450 Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org Add support for dma-channel-mask so that only the specified channels are used. This helps to reserve some channels for the firmware. This was initially achieved by limiting the channel number to 31 in the driver and adjusting the register address to skip channel0 which was reserved for a firmware. This is wrong and does not align with the hardware. Now, with this change, the driver can align more to the actual hardware which has 32 channels. But this implies that there will be a break in the ABI and the device tree need to be updated along with this change for the driver to pickup the right interrupt corresponding to the channel Reviewed-by: Jon Hunter Link: https://lore.kernel.org/all/Y2EFoG1H9YpfxRjs@orome/ Signed-off-by: Akhil R --- drivers/dma/tegra186-gpc-dma.c | 37 +++++++++++++++++++++++++++------- 1 file changed, 30 insertions(+), 7 deletions(-) diff --git a/drivers/dma/tegra186-gpc-dma.c b/drivers/dma/tegra186-gpc-dma.c index fa9bda4a2bc6..1d1180db6d4e 100644 --- a/drivers/dma/tegra186-gpc-dma.c +++ b/drivers/dma/tegra186-gpc-dma.c @@ -161,7 +161,10 @@ #define TEGRA_GPCDMA_BURST_COMPLETION_TIMEOUT 5000 /* 5 msec */ /* Channel base address offset from GPCDMA base address */ -#define TEGRA_GPCDMA_CHANNEL_BASE_ADD_OFFSET 0x20000 +#define TEGRA_GPCDMA_CHANNEL_BASE_ADDR_OFFSET 0x10000 + +/* Default channel mask reserving channel0 */ +#define TEGRA_GPCDMA_DEFAULT_CHANNEL_MASK 0xfffffffe struct tegra_dma; struct tegra_dma_channel; @@ -246,6 +249,7 @@ struct tegra_dma { const struct tegra_dma_chip_data *chip_data; unsigned long sid_m2d_reserved; unsigned long sid_d2m_reserved; + u32 chan_mask; void __iomem *base_addr; struct device *dev; struct dma_device dma_dev; @@ -1288,7 +1292,7 @@ static struct dma_chan *tegra_dma_of_xlate(struct of_phandle_args *dma_spec, } static const struct tegra_dma_chip_data tegra186_dma_chip_data = { - .nr_channels = 31, + .nr_channels = 32, .channel_reg_size = SZ_64K, .max_dma_count = SZ_1G, .hw_support_pause = false, @@ -1296,7 +1300,7 @@ static const struct tegra_dma_chip_data tegra186_dma_chip_data = { }; static const struct tegra_dma_chip_data tegra194_dma_chip_data = { - .nr_channels = 31, + .nr_channels = 32, .channel_reg_size = SZ_64K, .max_dma_count = SZ_1G, .hw_support_pause = true, @@ -1304,7 +1308,7 @@ static const struct tegra_dma_chip_data tegra194_dma_chip_data = { }; static const struct tegra_dma_chip_data tegra234_dma_chip_data = { - .nr_channels = 31, + .nr_channels = 32, .channel_reg_size = SZ_64K, .max_dma_count = SZ_1G, .hw_support_pause = true, @@ -1380,15 +1384,28 @@ static int tegra_dma_probe(struct platform_device *pdev) } stream_id = iommu_spec->ids[0] & 0xffff; + ret = device_property_read_u32(&pdev->dev, "dma-channel-mask", + &tdma->chan_mask); + if (ret) { + dev_warn(&pdev->dev, + "Missing dma-channel-mask property, using default channel mask %#x\n", + TEGRA_GPCDMA_DEFAULT_CHANNEL_MASK); + tdma->chan_mask = TEGRA_GPCDMA_DEFAULT_CHANNEL_MASK; + } + INIT_LIST_HEAD(&tdma->dma_dev.channels); for (i = 0; i < cdata->nr_channels; i++) { struct tegra_dma_channel *tdc = &tdma->channels[i]; + /* Check for channel mask */ + if (!(tdma->chan_mask & BIT(i))) + continue; + tdc->irq = platform_get_irq(pdev, i); if (tdc->irq < 0) return tdc->irq; - tdc->chan_base_offset = TEGRA_GPCDMA_CHANNEL_BASE_ADD_OFFSET + + tdc->chan_base_offset = TEGRA_GPCDMA_CHANNEL_BASE_ADDR_OFFSET + i * cdata->channel_reg_size; snprintf(tdc->name, sizeof(tdc->name), "gpcdma.%d", i); tdc->tdma = tdma; @@ -1449,8 +1466,8 @@ static int tegra_dma_probe(struct platform_device *pdev) return ret; } - dev_info(&pdev->dev, "GPC DMA driver register %d channels\n", - cdata->nr_channels); + dev_info(&pdev->dev, "GPC DMA driver register %lu channels\n", + hweight_long(tdma->chan_mask)); return 0; } @@ -1473,6 +1490,9 @@ static int __maybe_unused tegra_dma_pm_suspend(struct device *dev) for (i = 0; i < tdma->chip_data->nr_channels; i++) { struct tegra_dma_channel *tdc = &tdma->channels[i]; + if (!(tdma->chan_mask & BIT(i))) + continue; + if (tdc->dma_desc) { dev_err(tdma->dev, "channel %u busy\n", i); return -EBUSY; @@ -1492,6 +1512,9 @@ static int __maybe_unused tegra_dma_pm_resume(struct device *dev) for (i = 0; i < tdma->chip_data->nr_channels; i++) { struct tegra_dma_channel *tdc = &tdma->channels[i]; + if (!(tdma->chan_mask & BIT(i))) + continue; + tegra_dma_program_sid(tdc, tdc->stream_id); }