From patchwork Fri Nov 11 12:01:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 13040250 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 78556C4167D for ; Fri, 11 Nov 2022 12:02:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233721AbiKKMCJ (ORCPT ); Fri, 11 Nov 2022 07:02:09 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60466 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233520AbiKKMCG (ORCPT ); Fri, 11 Nov 2022 07:02:06 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DB79A82C46; Fri, 11 Nov 2022 04:02:04 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 32F506602A53; Fri, 11 Nov 2022 12:02:02 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1668168123; bh=E58h8dQlq6iyVZeY2ZoYwPMl0h6V46S7j8hkPKDnsBs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=awhAMxu4qfrXwOB6t2GUPEgSm798ULLg98fP0oCTQb43skDUf/q7UKnzDth5LL0pF 3GwsfVN0YHd8PFGNv38P+8Srft23bL1vw5pIkGbgPup9qNxcBaP16CiY89AO2EVpuq VMpL9oyflD5HXAINc9/iRR3q5G/d301dNJK5xSEbE/UrS2exTM7RtxCPCGGJ6rubWW BBrHhaEyVLgPulDdmon6rMcUWsgoaYqYWEC/6hzvRcMw9VoNvUyy313Ypl2imIc0Ey y2ysICl1SQchfmaGhPNinBmOUjzgynIsZbtiEQoUqHezrZdEqEWHBq8wjLhdhi1rRI k7Fq49QHMbYcA== From: AngeloGioacchino Del Regno To: agross@kernel.org Cc: andersson@kernel.org, konrad.dybcio@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, jassisinghbrar@gmail.com, srinivas.kandagatla@linaro.org, jic23@kernel.org, lars@metafoo.de, keescook@chromium.org, tony.luck@intel.com, gpiccoli@igalia.com, evgreen@chromium.org, gregkh@linuxfoundation.org, a39.skl@gmail.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, linux-hardening@vger.kernel.org, marijn.suijten@somainline.org, kernel@collabora.com, luca@z3ntu.xyz, AngeloGioacchino Del Regno , AngeloGioacchino Del Regno , Konrad Dybcio , Krzysztof Kozlowski , Jonathan Cameron Subject: [PATCH v2 01/11] dt-bindings: iio: qcom-spmi-vadc: Add definitions for USB DP/DM VADCs Date: Fri, 11 Nov 2022 13:01:46 +0100 Message-Id: <20221111120156.48040-2-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221111120156.48040-1-angelogioacchino.delregno@collabora.com> References: <20221111120156.48040-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-hardening@vger.kernel.org From: AngeloGioacchino Del Regno Some SoCs do have a USB DP/DM ADC at 0x43, 0x44. Signed-off-by: AngeloGioacchino Del Regno Signed-off-by: Konrad Dybcio Signed-off-by: Marijn Suijten Signed-off-by: AngeloGioacchino Del Regno Acked-by: Krzysztof Kozlowski Acked-by: Jonathan Cameron --- include/dt-bindings/iio/qcom,spmi-vadc.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/dt-bindings/iio/qcom,spmi-vadc.h b/include/dt-bindings/iio/qcom,spmi-vadc.h index 08adfe25964c..c7bb9ef1f9ed 100644 --- a/include/dt-bindings/iio/qcom,spmi-vadc.h +++ b/include/dt-bindings/iio/qcom,spmi-vadc.h @@ -72,6 +72,9 @@ #define VADC_AMUX_PU2 0x3b #define VADC_LR_MUX3_BUF_XO_THERM 0x3c +#define VADC_USB_DP 0x43 +#define VADC_USB_DM 0x44 + #define VADC_LR_MUX1_PU1_BAT_THERM 0x70 #define VADC_LR_MUX2_PU1_BAT_ID 0x71 #define VADC_LR_MUX3_PU1_XO_THERM 0x72 From patchwork Fri Nov 11 12:01:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 13040251 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7BE0BC43219 for ; Fri, 11 Nov 2022 12:02:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233738AbiKKMCM (ORCPT ); Fri, 11 Nov 2022 07:02:12 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60456 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233702AbiKKMCI (ORCPT ); Fri, 11 Nov 2022 07:02:08 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 406F75CD0F; Fri, 11 Nov 2022 04:02:06 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id CE54B6602A59; Fri, 11 Nov 2022 12:02:03 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1668168125; bh=3dwx4sOkXLslHVkjR3ykk6d4Uvy7UTkbpE06rEle/dw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=QJ96edCAiTd0fOiAPzJq+KV6R/VU0T/LQw968kLpBHISad8/slSQJd85gC0u3McGS Oavmkr6X+KjqDvGhtg2ckU/TDdQ7x3vx3uc1tDj4jE3Ya7Q07KkqGQ61TeYtFjCl4Y ewgO0gTBluU5S3LhZdTuocKb4rK30Df5NwgzjcXI0pXm5LKF9HinPAyYPmJ/+UVFDd MyrK1HR9s0S93EOLavgXsvHWXISjwvxQe1gHn4eLoQyst6ISXsvAyRf4rtucWZxsFT qVfpxQjy3GCqXskd//pbinRVJFs/Asyer8+ABM9ZskCIP4neiWZDGIl4pK617HKDSZ xj576czisqjfQ== From: AngeloGioacchino Del Regno To: agross@kernel.org Cc: andersson@kernel.org, konrad.dybcio@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, jassisinghbrar@gmail.com, srinivas.kandagatla@linaro.org, jic23@kernel.org, lars@metafoo.de, keescook@chromium.org, tony.luck@intel.com, gpiccoli@igalia.com, evgreen@chromium.org, gregkh@linuxfoundation.org, a39.skl@gmail.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, linux-hardening@vger.kernel.org, marijn.suijten@somainline.org, kernel@collabora.com, luca@z3ntu.xyz, AngeloGioacchino Del Regno Subject: [PATCH v2 02/11] dt-bindings: nvmem: Fix qcom,qfprom compatibles enum ordering Date: Fri, 11 Nov 2022 13:01:47 +0100 Message-Id: <20221111120156.48040-3-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221111120156.48040-1-angelogioacchino.delregno@collabora.com> References: <20221111120156.48040-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-hardening@vger.kernel.org Move qcom,msm8974-qfprom after qcom,msm8916-qfprom to respect alphabetical ordering. Fixes: c8b336bb1aeb ("dt-bindings: nvmem: Add soc qfprom compatible strings") Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml b/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml index 2eab2f46cb65..474abdbb1ee7 100644 --- a/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml +++ b/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml @@ -19,8 +19,8 @@ properties: - qcom,apq8064-qfprom - qcom,apq8084-qfprom - qcom,ipq8064-qfprom - - qcom,msm8974-qfprom - qcom,msm8916-qfprom + - qcom,msm8974-qfprom - qcom,msm8996-qfprom - qcom,msm8998-qfprom - qcom,qcs404-qfprom From patchwork Fri Nov 11 12:01:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 13040252 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B9FAFC433FE for ; Fri, 11 Nov 2022 12:02:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233048AbiKKMCR (ORCPT ); Fri, 11 Nov 2022 07:02:17 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60390 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233723AbiKKMCJ (ORCPT ); Fri, 11 Nov 2022 07:02:09 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E300465874; Fri, 11 Nov 2022 04:02:07 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 3C4C16602A5A; Fri, 11 Nov 2022 12:02:05 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1668168126; bh=P8u2ntcGviByJMEPenzYCOzfZh3bpvsfyTmQB0928iY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=odTKnM9tQeMUCTuhrGBGze23iGvtSN/JFrx6yMy1cHLvm31m/de3bcCr6kGq9+cLS gC4z9VcvjCv/LLg+zvbCg1yk/8eUmx6aByg7uPJiWON5zhsF4S6p5UycRDWVrKVg4U GEzdeuO6oC/inM4xmn8kROaBnOGmyZ9ognUXb41hrW8+/3SM7ruH34PuaAWZpk71QI G2/EpYCttJesAQZioRbT+lqLVeS1AAHmR4/oiIMqy5K8Mt1qlbnnTdloDLa2HMBHUA JIa2bebOnXtr6ni86ObF5juX/ReB6k2rUxDJqbJyb4SWRLiGwQT0ffJC+mA4nGHep3 XLaOm7zvedHHQ== From: AngeloGioacchino Del Regno To: agross@kernel.org Cc: andersson@kernel.org, konrad.dybcio@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, jassisinghbrar@gmail.com, srinivas.kandagatla@linaro.org, jic23@kernel.org, lars@metafoo.de, keescook@chromium.org, tony.luck@intel.com, gpiccoli@igalia.com, evgreen@chromium.org, gregkh@linuxfoundation.org, a39.skl@gmail.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, linux-hardening@vger.kernel.org, marijn.suijten@somainline.org, kernel@collabora.com, luca@z3ntu.xyz, AngeloGioacchino Del Regno Subject: [PATCH v2 03/11] dt-bindings: nvmem: Add compatible for MSM8976 Date: Fri, 11 Nov 2022 13:01:48 +0100 Message-Id: <20221111120156.48040-4-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221111120156.48040-1-angelogioacchino.delregno@collabora.com> References: <20221111120156.48040-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-hardening@vger.kernel.org From: Marijn Suijten Document generic QFPROM compatibility on MSM8976. Signed-off-by: Marijn Suijten Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml b/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml index 474abdbb1ee7..336cc05c3e32 100644 --- a/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml +++ b/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml @@ -21,6 +21,7 @@ properties: - qcom,ipq8064-qfprom - qcom,msm8916-qfprom - qcom,msm8974-qfprom + - qcom,msm8976-qfprom - qcom,msm8996-qfprom - qcom,msm8998-qfprom - qcom,qcs404-qfprom From patchwork Fri Nov 11 12:01:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 13040253 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7A2FCC433FE for ; Fri, 11 Nov 2022 12:02:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233769AbiKKMCR (ORCPT ); Fri, 11 Nov 2022 07:02:17 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60484 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233730AbiKKMCK (ORCPT ); Fri, 11 Nov 2022 07:02:10 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 405DD82C46; Fri, 11 Nov 2022 04:02:09 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id A64276602A5B; Fri, 11 Nov 2022 12:02:06 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1668168128; bh=T98aXE5Gxw7aRw7ON0gCmgKb2mGLH2ic05MhMNYfOUY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=WpP+xtNsuSXkWyUJ1NNZMdDg0m5HErMcd9yz+7+RAqcXt56kpg7Fq+55QY+rSUoJP 3Kl/ojA/TB2ZjC8k6XHiVgPdGJEUon7NGNeGk+KEuRUbVRmCvS5vq4Sc/JHrAKwVfd XERavFaxjuQJ4Ums4QavO3snoXIge1h9GyRYMDVFwHFEQmxBJPXwSu8MhpXDyaRgy6 Pm4y6kN5rnYzGZ1CBrcoyt+iPspOrtshTaDfJSFidRKYFmVXqr7UvybUx2X79jHTfs 7PYX214fp2F120cpdeY0x9i2nrV6dBZVDhn+2C2Xugkf6PHNd5wyKVHXjOuCPxIRSK RwS3xSSI/h5pg== From: AngeloGioacchino Del Regno To: agross@kernel.org Cc: andersson@kernel.org, konrad.dybcio@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, jassisinghbrar@gmail.com, srinivas.kandagatla@linaro.org, jic23@kernel.org, lars@metafoo.de, keescook@chromium.org, tony.luck@intel.com, gpiccoli@igalia.com, evgreen@chromium.org, gregkh@linuxfoundation.org, a39.skl@gmail.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, linux-hardening@vger.kernel.org, marijn.suijten@somainline.org, kernel@collabora.com, luca@z3ntu.xyz, AngeloGioacchino Del Regno Subject: [PATCH v2 04/11] dt-bindings: sram: qcom,imem: Document MSM8976 Date: Fri, 11 Nov 2022 13:01:49 +0100 Message-Id: <20221111120156.48040-5-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221111120156.48040-1-angelogioacchino.delregno@collabora.com> References: <20221111120156.48040-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-hardening@vger.kernel.org Add compatible for MSM8976 IMEM. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/sram/qcom,imem.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/sram/qcom,imem.yaml b/Documentation/devicetree/bindings/sram/qcom,imem.yaml index 665c06e14f79..e4677e2cb1d7 100644 --- a/Documentation/devicetree/bindings/sram/qcom,imem.yaml +++ b/Documentation/devicetree/bindings/sram/qcom,imem.yaml @@ -19,6 +19,7 @@ properties: - enum: - qcom,apq8064-imem - qcom,msm8974-imem + - qcom,msm8976-imem - qcom,qcs404-imem - qcom,sc7180-imem - qcom,sc7280-imem From patchwork Fri Nov 11 12:01:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 13040255 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D49E4C43217 for ; Fri, 11 Nov 2022 12:02:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233828AbiKKMCZ (ORCPT ); Fri, 11 Nov 2022 07:02:25 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60488 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233687AbiKKMCL (ORCPT ); Fri, 11 Nov 2022 07:02:11 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 86EA482C72; Fri, 11 Nov 2022 04:02:10 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 25E2F6602A5C; Fri, 11 Nov 2022 12:02:08 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1668168129; bh=AAkkSifYGl0AWcU5/uGDAU9aTntWhwpvPnTfOp44Z9k=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=iQLJ+AVuPlThbkdGDox9tD4K0sKEBJ9l8H2bfgvFP3QrDwUHFvxdyYwxMfcfFLLnk nI5pkQYFvnYL2grp37u6B1otNKZQvBF1nt9VJXlzUYwo5Ywah9946EXISj4yWXScMr jZW/RFEKOM6WU27PCgiHnR81LZBtNUbvMWJU9hdpUIrINonxttia95m3I+RXYQt3zV eHDzUktNi1AgwoyXWvt58v/7DEk4xP6YKxlmQFxAEbiMH1TVc9DKAxrieliU0lmKlt iHAOfHX67KQwcuCRgXFq+MpKjaMCEEIrxygeOQKCrvfu2kDeyPw0Vnx1ouLqfeZnN7 X3QD1RBMlgVGw== From: AngeloGioacchino Del Regno To: agross@kernel.org Cc: andersson@kernel.org, konrad.dybcio@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, jassisinghbrar@gmail.com, srinivas.kandagatla@linaro.org, jic23@kernel.org, lars@metafoo.de, keescook@chromium.org, tony.luck@intel.com, gpiccoli@igalia.com, evgreen@chromium.org, gregkh@linuxfoundation.org, a39.skl@gmail.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, linux-hardening@vger.kernel.org, marijn.suijten@somainline.org, kernel@collabora.com, luca@z3ntu.xyz, AngeloGioacchino Del Regno Subject: [PATCH v2 05/11] dt-bindings: mailbox: qcom: Allow syscon on qcom,msm8976-apcs-kpss-global Date: Fri, 11 Nov 2022 13:01:50 +0100 Message-Id: <20221111120156.48040-6-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221111120156.48040-1-angelogioacchino.delregno@collabora.com> References: <20221111120156.48040-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-hardening@vger.kernel.org MSM8976 supports SMSM, which needs this node to also be a syscon: move the compatible to allow that. Fixes: bcc8d70f912d ("dt-bindings: mailbox: Add compatible for the MSM8976") Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Krzysztof Kozlowski --- .../devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml index f24fd84b4b05..e99788879485 100644 --- a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml +++ b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml @@ -20,7 +20,6 @@ properties: - enum: - qcom,ipq6018-apcs-apps-global - qcom,ipq8074-apcs-apps-global - - qcom,msm8976-apcs-kpss-global - qcom,msm8996-apcs-hmss-global - qcom,msm8998-apcs-hmss-global - qcom,qcm2290-apcs-hmss-global @@ -36,6 +35,7 @@ properties: - qcom,msm8916-apcs-kpss-global - qcom,msm8939-apcs-kpss-global - qcom,msm8953-apcs-kpss-global + - qcom,msm8976-apcs-kpss-global - qcom,msm8994-apcs-kpss-global - qcom,qcs404-apcs-apps-global - const: syscon From patchwork Fri Nov 11 12:01:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 13040254 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 33FFEC433FE for ; Fri, 11 Nov 2022 12:02:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233692AbiKKMCY (ORCPT ); Fri, 11 Nov 2022 07:02:24 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60456 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233706AbiKKMCM (ORCPT ); Fri, 11 Nov 2022 07:02:12 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 06B7C85443; Fri, 11 Nov 2022 04:02:12 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 910896602A69; Fri, 11 Nov 2022 12:02:09 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1668168130; bh=e+ArDT2t4PV+LjnK1uWBh1mFJ4Qzmul7ZTkVo8z5z98=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=NlA5/UYUHX3fh8NqK0XR1cDLL/WxVXxdhaegLR0hC6YACWUfzSW/ZFSWte+ek9LGU 6+mfM4ZOA8RUHW/n1fE5uTfBIjkfSLidAwsJHsdQI1c+2B/+k5mVQLZPIkUnQVhFRi jGeESG3//lYsYssu1ivxUu/Bh0t6c0tJS6k9H/79J76n6gtOwAKJifJP3LWbDP/9ux ce7bWV5jVgCBjni8UTXUX9+z84M7dBzDcQaw0uqAvi+CaPHXqQL7oOyA2Bqk5h81O8 N0SADlp8lbNjz3Jbi0Mcf6kP04j3zuX513qscL5igKFGm8PkEzYobNXIN/sQa1H/jy Oa6E//U6hR8xw== From: AngeloGioacchino Del Regno To: agross@kernel.org Cc: andersson@kernel.org, konrad.dybcio@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, jassisinghbrar@gmail.com, srinivas.kandagatla@linaro.org, jic23@kernel.org, lars@metafoo.de, keescook@chromium.org, tony.luck@intel.com, gpiccoli@igalia.com, evgreen@chromium.org, gregkh@linuxfoundation.org, a39.skl@gmail.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, linux-hardening@vger.kernel.org, marijn.suijten@somainline.org, kernel@collabora.com, luca@z3ntu.xyz, AngeloGioacchino Del Regno Subject: [PATCH v2 06/11] dt-bindings: arm: qcom,ids: Add SoC IDs for MSM8956 and MSM8976 Date: Fri, 11 Nov 2022 13:01:51 +0100 Message-Id: <20221111120156.48040-7-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221111120156.48040-1-angelogioacchino.delregno@collabora.com> References: <20221111120156.48040-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-hardening@vger.kernel.org Document the identifier of MSM8956/76. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Konrad Dybcio Acked-by: Krzysztof Kozlowski --- include/dt-bindings/arm/qcom,ids.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/dt-bindings/arm/qcom,ids.h b/include/dt-bindings/arm/qcom,ids.h index 8b1a0f43bd93..91633da5fcf6 100644 --- a/include/dt-bindings/arm/qcom,ids.h +++ b/include/dt-bindings/arm/qcom,ids.h @@ -78,6 +78,8 @@ #define QCOM_ID_MSM8616 250 #define QCOM_ID_MSM8992 251 #define QCOM_ID_APQ8094 253 +#define QCOM_ID_MSM8956 266 +#define QCOM_ID_MSM8976 278 #define QCOM_ID_MDM9607 290 #define QCOM_ID_APQ8096 291 #define QCOM_ID_MSM8998 292 From patchwork Fri Nov 11 12:01:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 13040256 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8B99BC43219 for ; Fri, 11 Nov 2022 12:02:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233249AbiKKMCd (ORCPT ); Fri, 11 Nov 2022 07:02:33 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60478 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233743AbiKKMCO (ORCPT ); Fri, 11 Nov 2022 07:02:14 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 78F0F65874; Fri, 11 Nov 2022 04:02:13 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 141B66602A73; Fri, 11 Nov 2022 12:02:11 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1668168132; bh=zBxBoab4eNo7fafSX9v3S2SsOGhHzPKyMqsyJdaTtfk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=fcrAd0HcjVTZwrwHXk/IZue9rIeyduQ0ZU49K/GKqUPffFxYpxmiIDLDSK3q1fh8I rN2fZWczOKfyH4jbeNjl/WNChrwwWr6GigVbsrHZCbDXYgIJKUj3QBJd1QQMLbf/5Z PdT7Y6dnelB+1D1Ev19NdjwKxzqQn4CXXioBo7tcjIZbqOYDp+S4kJTGU9VEI25Jdo JAXR4/3/DgQNGbzcr2FwmDrkkCMQwTuWTB+RaK8KyOt2LRDYgkBcd3XyT+uCAxvKVW 78zKpDHzbA5S9BmbINuXYPNuN+mcKkPqHLgWVMCwZBOCrxaYo3mJcDavof+DeRemEc IHZQixw7IKCgw== From: AngeloGioacchino Del Regno To: agross@kernel.org Cc: andersson@kernel.org, konrad.dybcio@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, jassisinghbrar@gmail.com, srinivas.kandagatla@linaro.org, jic23@kernel.org, lars@metafoo.de, keescook@chromium.org, tony.luck@intel.com, gpiccoli@igalia.com, evgreen@chromium.org, gregkh@linuxfoundation.org, a39.skl@gmail.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, linux-hardening@vger.kernel.org, marijn.suijten@somainline.org, kernel@collabora.com, luca@z3ntu.xyz, AngeloGioacchino Del Regno Subject: [PATCH v2 07/11] soc: qcom: socinfo: Add MSM8956/76 SoC IDs to the soc_id table Date: Fri, 11 Nov 2022 13:01:52 +0100 Message-Id: <20221111120156.48040-8-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221111120156.48040-1-angelogioacchino.delregno@collabora.com> References: <20221111120156.48040-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-hardening@vger.kernel.org Add SoC ID table entries for MSM8956 and MSM8976 chips. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Konrad Dybcio Reviewed-by: Krzysztof Kozlowski --- drivers/soc/qcom/socinfo.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/soc/qcom/socinfo.c b/drivers/soc/qcom/socinfo.c index 545934aead43..b2f73e9cba9f 100644 --- a/drivers/soc/qcom/socinfo.c +++ b/drivers/soc/qcom/socinfo.c @@ -250,6 +250,8 @@ static const struct soc_id soc_id[] = { { qcom_board_id(MSM8926) }, { qcom_board_id(MSM8326) }, { qcom_board_id(MSM8916) }, + { qcom_board_id(MSM8956) }, + { qcom_board_id(MSM8976) }, { qcom_board_id(MSM8994) }, { qcom_board_id_named(APQ8074PRO_AA, "APQ8074PRO-AA") }, { qcom_board_id_named(APQ8074PRO_AB, "APQ8074PRO-AB") }, From patchwork Fri Nov 11 12:01:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 13040257 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 258CAC4332F for ; Fri, 11 Nov 2022 12:02:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233839AbiKKMCj (ORCPT ); Fri, 11 Nov 2022 07:02:39 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60790 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233758AbiKKMCP (ORCPT ); Fri, 11 Nov 2022 07:02:15 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F06CF623B9; Fri, 11 Nov 2022 04:02:14 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 882886602A65; Fri, 11 Nov 2022 12:02:12 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1668168133; bh=ZoPNicLYVHGTgNwH65ue84RzC68Nv0pG4Fw5r8ZZqFs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=TFdf/ktTqN9jW9MENuQG2qHjZ0zGgIcAomualwByeuFYsC3kc5fH9NaCY70tgphzt in8cnKYspnM2/YZF/NyZqrw9U9IWiFQfeiuFhoYd9EfQcTOceCsV/bYXwOTPMet8ui U1eThTqEWQpJxhRz+hw2RSIInA6MDUtC83am0vvCQRfdWbQxlBpJh55+vZXEPbkq/t caoxljW0rK2ue9GkiWFn8ZeI7BqizrokEfRCp7gXUBOYIt7QrADNoCRICN7cfsTFJS W/v3DSlr9b3tjfvS+Lmg1lljOteleJxE+r7pUj8V+Agi5NvqTPFxPRpktCppEPI1Nc Mbii2NUCvFZgg== From: AngeloGioacchino Del Regno To: agross@kernel.org Cc: andersson@kernel.org, konrad.dybcio@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, jassisinghbrar@gmail.com, srinivas.kandagatla@linaro.org, jic23@kernel.org, lars@metafoo.de, keescook@chromium.org, tony.luck@intel.com, gpiccoli@igalia.com, evgreen@chromium.org, gregkh@linuxfoundation.org, a39.skl@gmail.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, linux-hardening@vger.kernel.org, marijn.suijten@somainline.org, kernel@collabora.com, luca@z3ntu.xyz, AngeloGioacchino Del Regno , Krzysztof Kozlowski Subject: [PATCH v2 08/11] dt-bindings: arm: qcom: Document msm8956 and msm8976 SoC and devices Date: Fri, 11 Nov 2022 13:01:53 +0100 Message-Id: <20221111120156.48040-9-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221111120156.48040-1-angelogioacchino.delregno@collabora.com> References: <20221111120156.48040-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-hardening@vger.kernel.org From: Marijn Suijten Note that msm8976 is omitted as a compatible, since there are currently no boards/devices using it. Signed-off-by: Marijn Suijten Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/qcom.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 97e1d0f07218..a3a546239696 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -35,7 +35,9 @@ description: | mdm9615 msm8226 msm8916 + msm8956 msm8974 + msm8976 msm8992 msm8994 msm8996 @@ -157,6 +159,12 @@ properties: - samsung,s3ve3g - const: qcom,msm8226 + - items: + - enum: + - sony,kugo-row + - sony,suzu-row + - const: qcom,msm8956 + - items: - enum: - qcom,msm8960-cdp @@ -889,6 +897,8 @@ allOf: - qcom,apq8026 - qcom,apq8094 - qcom,apq8096 + - qcom,msm8956 + - qcom,msm8976 - qcom,msm8992 - qcom,msm8994 - qcom,msm8996 From patchwork Fri Nov 11 12:01:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 13040258 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AD8B4C43217 for ; Fri, 11 Nov 2022 12:02:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233870AbiKKMCq (ORCPT ); Fri, 11 Nov 2022 07:02:46 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:32812 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233778AbiKKMCV (ORCPT ); Fri, 11 Nov 2022 07:02:21 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7B5C185450; Fri, 11 Nov 2022 04:02:16 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 0D1836602A7D; Fri, 11 Nov 2022 12:02:13 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1668168135; bh=iz94emL+JF9s4mzYlCcC+kyE/fLPjDpZFpKTPzTyij0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=YdDzoXtJG+U399fxeBf7s7f0HjKbuJD01JUtJ1xhh35X09gSQvSrmi9uJcWwIXEqX wi1ilKPsdphAMeNwAX7Yd2mEy4sBz0Wj6w/7/TzFcpBjSiw5xYaKnYTt+D6gphJuXB IiUifIjwbE0jGJPGVAvdrPY91P2Zl2ioUpBExv01usULFM5vtZ3DUMyTJSvnaDcXFm TPFuSvZa3X4kylce3aZuuTQTfoKfeI9JhzAo+rCbuaTvmoo8XC3B5zco3doLSX5TuS hGumABXjQIBqUq5BAVf6yrxNggwqacia7fCKvXr92a8znQgduvms+8D/1rw5hpUFO8 kUP/+sLuv5jbg== From: AngeloGioacchino Del Regno To: agross@kernel.org Cc: andersson@kernel.org, konrad.dybcio@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, jassisinghbrar@gmail.com, srinivas.kandagatla@linaro.org, jic23@kernel.org, lars@metafoo.de, keescook@chromium.org, tony.luck@intel.com, gpiccoli@igalia.com, evgreen@chromium.org, gregkh@linuxfoundation.org, a39.skl@gmail.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, linux-hardening@vger.kernel.org, marijn.suijten@somainline.org, kernel@collabora.com, luca@z3ntu.xyz, AngeloGioacchino Del Regno , Konrad Dybcio Subject: [PATCH v2 09/11] arm64: dts: qcom: Add configuration for PM8950 peripheral Date: Fri, 11 Nov 2022 13:01:54 +0100 Message-Id: <20221111120156.48040-10-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221111120156.48040-1-angelogioacchino.delregno@collabora.com> References: <20221111120156.48040-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-hardening@vger.kernel.org The PM8950 features integrated peripherals like ADC, GPIO controller, MPPs, PON keys and others. Add them to DT files that will be imported on boards having this PMIC combo (or one of them, anyways). Signed-off-by: Konrad Dybcio Co-developed-by: Marijn Suijten Signed-off-by: Marijn Suijten Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/qcom/pm8950.dtsi | 165 +++++++++++++++++++++++++++ 1 file changed, 165 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/pm8950.dtsi diff --git a/arch/arm64/boot/dts/qcom/pm8950.dtsi b/arch/arm64/boot/dts/qcom/pm8950.dtsi new file mode 100644 index 000000000000..07c3896bd36f --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pm8950.dtsi @@ -0,0 +1,165 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022, AngeloGioacchino Del Regno + * + * Copyright (c) 2022, Marijn Suijten + */ + +#include +#include +#include +#include +#include + +&spmi_bus { + pmic@0 { + compatible = "qcom,pm8950", "qcom,spmi-pmic"; + reg = <0x0 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pon@800 { + compatible = "qcom,pm8916-pon"; + reg = <0x0800>; + mode-bootloader = <0x2>; + mode-recovery = <0x1>; + + pwrkey { + compatible = "qcom,pm8941-pwrkey"; + interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>; + debounce = <15625>; + bias-pull-up; + linux,code = ; + }; + }; + + pm8950_temp: temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400>; + interrupts = <0 0x24 0 IRQ_TYPE_EDGE_RISING>; + io-channels = <&pm8950_vadc VADC_DIE_TEMP>; + io-channel-names = "thermal"; + #thermal-sensor-cells = <0>; + }; + + pm8950_vadc: adc@3100 { + compatible = "qcom,spmi-vadc"; + reg = <0x3100>; + interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + + vcoin@5 { + reg = ; + qcom,pre-scaling = <1 1>; + }; + + vph-pwr@7 { + reg = ; + qcom,pre-scaling = <1 1>; + }; + + die-temp@8 { + reg = ; + qcom,pre-scaling = <1 1>; + }; + + ref-625mv@9 { + reg = ; + qcom,pre-scaling = <1 1>; + }; + + ref-1250mv@a { + reg = ; + qcom,pre-scaling = <1 1>; + }; + + ref-buf-625mv@c { + reg = ; + qcom,pre-scaling = <1 1>; + }; + + ref-gnd@e { + reg = ; + }; + + ref-vdd@f { + reg = ; + }; + + pa-therm1@11 { + reg = ; + qcom,pre-scaling = <1 1>; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + case-therm@13 { + reg = ; + qcom,pre-scaling = <1 1>; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + xo-therm@32 { + reg = ; + qcom,pre-scaling = <1 1>; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + pa-therm0@36 { + reg = ; + qcom,pre-scaling = <1 1>; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + xo-therm-buf@3c { + reg = ; + qcom,pre-scaling = <1 1>; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + }; + + rtc@6000 { + compatible = "qcom,pm8941-rtc"; + reg = <0x6000>; + reg-names = "rtc", "alarm"; + interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>; + }; + + pm8950_mpps: mpps@a000 { + compatible = "qcom,pm8950-mpp", "qcom,spmi-mpp"; + reg = <0xa000>; + gpio-controller; + gpio-ranges = <&pm8950_mpps 0 0 4>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + pm8950_gpio: gpio@c000 { + compatible = "qcom,pm8950-gpio", "qcom,spmi-gpio"; + reg = <0xc000>; + gpio-controller; + gpio-ranges = <&pm8950_gpio 0 0 8>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + pmic@1 { + compatible = "qcom,pm8950", "qcom,spmi-pmic"; + reg = <0x1 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8950_spmi_regulators: regulators { + compatible = "qcom,pm8950-regulators"; + }; + }; +}; From patchwork Fri Nov 11 12:01:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 13040259 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 136A6C43219 for ; Fri, 11 Nov 2022 12:02:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233893AbiKKMC4 (ORCPT ); Fri, 11 Nov 2022 07:02:56 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:32856 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233800AbiKKMCX (ORCPT ); Fri, 11 Nov 2022 07:02:23 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0ECD083BB1; Fri, 11 Nov 2022 04:02:18 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 866EF6602A70; Fri, 11 Nov 2022 12:02:15 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1668168136; bh=NPGEr8qvt6FoYxM6sNRz9AvLpzkroiDAMNHMiS+xFys=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=PdybzW6hzgcmDMCACuI6M92HOaSj2W1FgcaiYaShJoZmve8pRD2NfijWYOS5SctUa kh7MF1Wx+okrTfo1E4DHDfOx8Tmis0nBm9xNPcedHpKWXMkJ/F5IgsZQl5kGwKC5OB NtJb4yG+dxVrgTD5deOkgVpMuFEgR/aNch0NMHoku56jcqG4KrbXuyyKmR2aJH8VFd wtMhobKR75zH4jiWF26BVrTSGARWlkSi3esnDRM+iq6KjW2cR7aiAyvz+BLdVZoAvS OIynJ5oBhzRfXtZKOrs7TyMBHQerq6BilJLCLozkpJJVeHIvSI9L1VBU+RISSI7Z5e 5w/XjOb7+BNtQ== From: AngeloGioacchino Del Regno To: agross@kernel.org Cc: andersson@kernel.org, konrad.dybcio@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, jassisinghbrar@gmail.com, srinivas.kandagatla@linaro.org, jic23@kernel.org, lars@metafoo.de, keescook@chromium.org, tony.luck@intel.com, gpiccoli@igalia.com, evgreen@chromium.org, gregkh@linuxfoundation.org, a39.skl@gmail.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, linux-hardening@vger.kernel.org, marijn.suijten@somainline.org, kernel@collabora.com, luca@z3ntu.xyz, AngeloGioacchino Del Regno , Konrad Dybcio Subject: [PATCH v2 10/11] arm64: dts: qcom: Add DTS for MSM8976 and MSM8956 SoCs Date: Fri, 11 Nov 2022 13:01:55 +0100 Message-Id: <20221111120156.48040-11-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221111120156.48040-1-angelogioacchino.delregno@collabora.com> References: <20221111120156.48040-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-hardening@vger.kernel.org This commit adds device trees for MSM8956 and MSM8976 SoCs. They are *almost* identical, with minor differences, such as MSM8956 having two A72 cores less. However, there is a bug in Sony Loire bootloader that requires presence of all 8 cores in the cpu{} node, so these will not be deleted. Co-developed-by: Konrad Dybcio Signed-off-by: Konrad Dybcio Co-developed-by: Marijn Suijten Signed-off-by: Marijn Suijten Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/qcom/msm8956.dtsi | 18 + arch/arm64/boot/dts/qcom/msm8976.dtsi | 1198 +++++++++++++++++++++++++ 2 files changed, 1216 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/msm8956.dtsi create mode 100644 arch/arm64/boot/dts/qcom/msm8976.dtsi diff --git a/arch/arm64/boot/dts/qcom/msm8956.dtsi b/arch/arm64/boot/dts/qcom/msm8956.dtsi new file mode 100644 index 000000000000..e432512d8716 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8956.dtsi @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2016-2022, AngeloGioacchino Del Regno + * + * Copyright (c) 2022, Konrad Dybcio + * Copyright (c) 2022, Marijn Suijten + */ + +#include "msm8976.dtsi" + +&pmu { + interrupts = ; +}; + +/* + * You might be wondering.. why is it so empty out there? + * Well, the SoCs are almost identical. + */ diff --git a/arch/arm64/boot/dts/qcom/msm8976.dtsi b/arch/arm64/boot/dts/qcom/msm8976.dtsi new file mode 100644 index 000000000000..d621d3c9ab3b --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8976.dtsi @@ -0,0 +1,1198 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2016-2022, AngeloGioacchino Del Regno + * + * Copyright (c) 2022, Konrad Dybcio + * Copyright (c) 2022, Marijn Suijten + */ + +#include +#include +#include +#include +#include +#include + +/ { + interrupt-parent = <&intc>; + #address-cells = <2>; + #size-cells = <2>; + + chosen { }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0>; + enable-method = "psci"; + cpu-idle-states = <&little_cpu_sleep_0>; + capacity-dmips-mhz = <573>; + next-level-cache = <&l2_0>; + #cooling-cells = <2>; + }; + + CPU1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x1>; + enable-method = "psci"; + cpu-idle-states = <&little_cpu_sleep_0>; + capacity-dmips-mhz = <573>; + next-level-cache = <&l2_0>; + #cooling-cells = <2>; + }; + + CPU2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x2>; + enable-method = "psci"; + cpu-idle-states = <&little_cpu_sleep_0>; + capacity-dmips-mhz = <573>; + next-level-cache = <&l2_0>; + #cooling-cells = <2>; + }; + + CPU3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x3>; + enable-method = "psci"; + cpu-idle-states = <&little_cpu_sleep_0>; + capacity-dmips-mhz = <573>; + next-level-cache = <&l2_0>; + #cooling-cells = <2>; + }; + + CPU4: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x100>; + enable-method = "psci"; + cpu-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; + capacity-dmips-mhz = <1024>; + next-level-cache = <&l2_1>; + #cooling-cells = <2>; + }; + + CPU5: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x101>; + enable-method = "psci"; + cpu-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; + capacity-dmips-mhz = <1024>; + next-level-cache = <&l2_1>; + #cooling-cells = <2>; + }; + + CPU6: cpu@102 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x102>; + enable-method = "psci"; + cpu-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; + capacity-dmips-mhz = <1024>; + next-level-cache = <&l2_1>; + #cooling-cells = <2>; + }; + + CPU7: cpu@103 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x103>; + enable-method = "psci"; + cpu-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; + capacity-dmips-mhz = <1024>; + next-level-cache = <&l2_1>; + #cooling-cells = <2>; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + }; + + cluster1 { + core0 { + cpu = <&CPU4>; + }; + + core1 { + cpu = <&CPU5>; + }; + + core2 { + cpu = <&CPU6>; + }; + + core3 { + cpu = <&CPU7>; + }; + }; + }; + + idle-states { + entry-method = "psci"; + + little_cpu_sleep_0: cpu-sleep-0-0 { + compatible = "arm,idle-state"; + idle-state-name = "little-power-collapse"; + arm,psci-suspend-param = <0x40000003>; + entry-latency-us = <181>; + exit-latency-us = <149>; + min-residency-us = <703>; + local-timer-stop; + }; + + big_cpu_sleep_0: cpu-sleep-1-0 { + compatible = "arm,idle-state"; + idle-state-name = "big-retention"; + arm,psci-suspend-param = <0x00000002>; + entry-latency-us = <142>; + exit-latency-us = <99>; + min-residency-us = <242>; + }; + + big_cpu_sleep_1: cpu-sleep-1-1 { + compatible = "arm,idle-state"; + idle-state-name = "big-power-collapse"; + arm,psci-suspend-param = <0x40000003>; + entry-latency-us = <158>; + exit-latency-us = <144>; + min-residency-us = <863>; + local-timer-stop; + }; + }; + + l2_0: l2-cache0 { + compatible = "cache"; + cache-level = <2>; + }; + + l2_1: l2-cache1 { + compatible = "cache"; + cache-level = <2>; + }; + }; + + firmware { + scm: scm { + compatible = "qcom,scm-msm8976", "qcom,scm"; + clocks = <&gcc GCC_CRYPTO_CLK>, + <&gcc GCC_CRYPTO_AXI_CLK>, + <&gcc GCC_CRYPTO_AHB_CLK>; + clock-names = "core", "bus", "iface"; + #reset-cells = <1>; + + qcom,dload-mode = <&tcsr 0x6100>; + }; + }; + + memory@80000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the size */ + reg = <0x0 0x80000000 0x0 0x0>; + }; + + pmu: pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = ; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ext-region@85b00000 { + reg = <0x0 0x85b00000 0x0 0x500000>; + no-map; + }; + + smem@86300000 { + compatible = "qcom,smem"; + reg = <0x0 0x86300000 0x0 0x100000>; + no-map; + + hwlocks = <&tcsr_mutex 3>; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + }; + + reserved@86400000 { + reg = <0x0 0x86400000 0x0 0x800000>; + no-map; + }; + + mpss_mem: mpss@86c00000 { + reg = <0x0 0x86c00000 0x0 0x5600000>; + no-map; + }; + + lpass_mem: lpass@8c200000 { + reg = <0x0 0x8c200000 0x0 0x1800000>; + no-map; + }; + + venus_mem: memory@8da00000 { + reg = <0x0 0x8da00000 0x0 0x2600000>; + no-map; + }; + + tz-apps@8dd00000 { + reg = <0x0 0x8dd00000 0x0 0x1400000>; + no-map; + }; + }; + + smp2p-hexagon { + compatible = "qcom,smp2p"; + interrupts = ; + qcom,ipc = <&apcs 8 10>; + + qcom,local-pid = <0>; + qcom,remote-pid = <2>; + qcom,smem = <443>, <429>; + + adsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + + #qcom,smem-state-cells = <1>; + }; + + adsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smp2p-modem { + compatible = "qcom,smp2p"; + interrupts = ; + qcom,ipc = <&apcs 8 13>; + + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + qcom,smem = <435>, <428>; + + modem_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + + #qcom,smem-state-cells = <1>; + }; + + modem_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smp2p-wcnss { + compatible = "qcom,smp2p"; + interrupts = ; + qcom,ipc = <&apcs 8 17>; + + qcom,local-pid = <0>; + qcom,remote-pid = <4>; + qcom,smem = <451>, <431>; + + wcnss_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + + #qcom,smem-state-cells = <1>; + }; + + wcnss_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smd { + compatible = "qcom,smd"; + + rpm { + interrupts = ; + qcom,ipc = <&apcs 8 0>; + qcom,smd-edge = <15>; + + rpm_requests: rpm-requests { + compatible = "qcom,rpm-msm8976"; + qcom,smd-channels = "rpm_requests"; + + rpmcc: clock-controller { + compatible = "qcom,rpmcc-msm8976", "qcom,rpmcc"; + #clock-cells = <1>; + }; + + rpmpd: power-controller { + compatible = "qcom,msm8976-rpmpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmpd_opp_table>; + + rpmpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmpd_opp_ret: opp1 { + opp-level = ; + }; + + rpmpd_opp_ret_plus: opp2 { + opp-level = ; + }; + + rpmpd_opp_min_svs: opp3 { + opp-level = ; + }; + + rpmpd_opp_low_svs: opp4 { + opp-level = ; + }; + + rpmpd_opp_svs: opp5 { + opp-level = ; + }; + + rpmpd_opp_svs_plus: opp6 { + opp-level = ; + }; + + rpmpd_opp_nom: opp7 { + opp-level = ; + }; + + rpmpd_opp_nom_plus: opp8 { + opp-level = ; + }; + + rpmpd_opp_turbo: opp9 { + opp-level = ; + }; + + rpmpd_opp_turbo_no_cpr: opp10 { + opp-level = ; + }; + + rpmpd_opp_turbo_high: opp111 { + opp-level = ; + }; + }; + }; + }; + }; + }; + + smsm { + compatible = "qcom,smsm"; + + #address-cells = <1>; + #size-cells = <0>; + + qcom,ipc-1 = <&apcs 8 12>; + qcom,ipc-2 = <&apcs 8 9>; + qcom,ipc-3 = <&apcs 8 18>; + + apps_smsm: apps@0 { + reg = <0>; + #qcom,smem-state-cells = <1>; + }; + + hexagon_smsm: hexagon@1 { + reg = <1>; + interrupts = <0 290 IRQ_TYPE_EDGE_RISING>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + wcnss_smsm: wcnss@6 { + reg = <6>; + interrupts = ; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + soc: soc@0 { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + compatible = "simple-bus"; + + rng@22000 { + compatible = "qcom,prng"; + reg = <0x00022000 0x140>; + clocks = <&gcc GCC_PRNG_AHB_CLK>; + clock-names = "core"; + }; + + rpm_msg_ram: sram@60000 { + compatible = "qcom,rpm-msg-ram"; + reg = <0x00060000 0x8000>; + }; + + usb_hs_phy: phy@6c000 { + compatible = "qcom,usb-hs-28nm-femtophy"; + reg = <0x0006c000 0x200>; + #phy-cells = <0>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, + <&gcc GCC_USB2A_PHY_SLEEP_CLK>; + clock-names = "ref", "ahb", "sleep"; + resets = <&gcc RST_QUSB2_PHY_BCR>, + <&gcc RST_USB2_HS_PHY_ONLY_BCR>; + reset-names = "phy", "por"; + status = "disabled"; + }; + + qfprom: qfprom@a4000 { + compatible = "qcom,msm8976-qfprom", "qcom,qfprom"; + reg = <0x000a4000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + tsens_caldata: caldata@218 { + reg = <0x218 0x18>; + }; + }; + + tsens: thermal-sensor@4a9000 { + compatible = "qcom,msm8976-tsens", "qcom,tsens-v1"; + reg = <0x004a9000 0x1000>, /* TM */ + <0x004a8000 0x1000>; /* SROT */ + interrupts = ; + interrupt-names = "uplow"; + nvmem-cells = <&tsens_caldata>; + nvmem-cell-names = "calib"; + #qcom,sensors = <11>; + #thermal-sensor-cells = <1>; + }; + + tlmm: pinctrl@1000000 { + compatible = "qcom,msm8976-pinctrl"; + reg = <0x01000000 0x300000>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&tlmm 0 0 145>; + interrupt-controller; + #interrupt-cells = <2>; + + spi1_default: spi0-default-state { + spi-pins { + pins = "gpio0", "gpio1", "gpio3"; + function = "blsp_spi1"; + drive-strength = <12>; + bias-disable; + }; + + cs-pins { + pins = "gpio2"; + function = "blsp_spi1"; + drive-strength = <2>; + bias-disable; + }; + }; + + spi1_sleep: spi0-sleep-state { + spi-pins { + pins = "gpio0", "gpio1", "gpio3"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + cs-pins { + pins = "gpio2"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_i2c2_default: blsp1-i2c2-default-state { + pins = "gpio6", "gpio7"; + function = "blsp_i2c2"; + drive-strength = <2>; + bias-disable; + }; + + blsp1_i2c2_sleep: blsp1-i2c2-sleep-state { + pins = "gpio6", "gpio7"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + blsp1_i2c4_default: blsp1-i2c4-default-state { + pins = "gpio14", "gpio15"; + function = "blsp_i2c4"; + drive-strength = <2>; + bias-disable; + }; + + blsp1_i2c4_sleep: blsp1-i2c4-sleep-state { + pins = "gpio14", "gpio15"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + blsp2_uart2_active: blsp2-uart2-active-state { + pins = "gpio20", "gpio21"; + function = "blsp_uart6"; + drive-strength = <4>; + bias-disable; + }; + + blsp2_uart2_sleep: blsp2-uart2-sleep-state { + pins = "gpio20", "gpio21"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + /* 4 (not 6!) interfaces per QUP, BLSP2 indexes are numbered (n)+4 */ + blsp2_i2c2_default: blsp2-i2c2-default-state { + pins = "gpio22", "gpio23"; + function = "blsp_i2c6"; + drive-strength = <2>; + bias-disable; + }; + + blsp2_i2c2_sleep: blsp2-i2c2-sleep-state { + pins = "gpio22", "gpio23"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + blsp2_i2c4_default: blsp2-i2c4-default-state { + pins = "gpio18", "gpio19"; + function = "blsp_i2c8"; + drive-strength = <2>; + bias-disable; + }; + + blsp2_i2c4_sleep: blsp2-i2c4-sleep-state { + pins = "gpio18", "gpio19"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + }; + + gcc: clock-controller@1800000 { + compatible = "qcom,gcc-msm8976"; + reg = <0x01800000 0x80000>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + + assigned-clocks = <&gcc GPLL3>; + assigned-clock-rates = <1100000000>; + + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&rpmcc RPM_SMD_XO_A_CLK_SRC>, + <0>, + <0>, + <0>, + <0>; + clock-names = "xo", + "xo_a", + "dsi0pll", + "dsi0pllbyte", + "dsi1pll", + "dsi1pllbyte"; + }; + + tcsr_mutex: hwlock@1905000 { + compatible = "qcom,tcsr-mutex"; + reg = <0x01905000 0x20000>; + #hwlock-cells = <1>; + }; + + tcsr: syscon@1937000 { + compatible = "qcom,msm8976-tcsr", "syscon"; + reg = <0x01937000 0x30000>; + }; + + spmi_bus: spmi@200f000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0x0200f000 0x1000>, + <0x02400000 0x800000>, + <0x02c00000 0x800000>, + <0x03800000 0x200000>, + <0x0200a000 0x2100>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupts = ; + interrupt-names = "periph_irq"; + qcom,channel = <0>; + qcom,ee = <0>; + + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + cell-index = <0>; + }; + + sdhc_1: mmc@7824000 { + compatible = "qcom,msm8976-sdhci", "qcom,sdhci-msm-v4"; + reg = <0x07824900 0x500>, <0x07824000 0x800>; + reg-names = "hc", "core"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "iface", "core", "xo"; + status = "disabled"; + }; + + sdhc_2: mmc@7864000 { + compatible = "qcom,msm8976-sdhci", "qcom,sdhci-msm-v4"; + reg = <0x07864900 0x11c>, <0x07864000 0x800>; + reg-names = "hc", "core"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "iface", "core", "xo"; + status = "disabled"; + }; + + blsp1_dma: dma-controller@7884000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0x07884000 0x1f000>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + }; + + blsp1_uart1: serial@78af000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x078af000 0x200>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp1_dma 0>, <&blsp1_dma 1>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + blsp1_uart2: serial@78b0000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x078b0000 0x200>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp1_dma 2>, <&blsp1_dma 3>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + blsp1_spi1: spi@78b5000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x078b5000 0x500>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp1_dma 4>, <&blsp1_dma 5>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&spi1_default>; + pinctrl-1 = <&spi1_sleep>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp1_i2c2: i2c@78b6000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x078b6000 0x500>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + clock-frequency = <400000>; + dmas = <&blsp1_dma 6>, <&blsp1_dma 7>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp1_i2c2_default>; + pinctrl-1 = <&blsp1_i2c2_default>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp1_i2c4: i2c@78b8000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x078b8000 0x500>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + clock-frequency = <400000>; + dmas = <&blsp1_dma 10>, <&blsp1_dma 11>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp1_i2c4_default>; + pinctrl-1 = <&blsp1_i2c4_sleep>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + otg: usb@78db000 { + compatible = "qcom,ci-hdrc"; + reg = <0x078db000 0x200>, + <0x078db200 0x200>; + interrupts = , + ; + clocks = <&gcc GCC_USB_HS_AHB_CLK>, <&gcc GCC_USB_HS_SYSTEM_CLK>; + clock-names = "iface", "core"; + assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>; + assigned-clock-rates = <80000000>; + resets = <&gcc RST_USB_HS_BCR>; + reset-names = "core"; + ahb-burst-config = <0>; + dr_mode = "peripheral"; + phy_type = "ulpi"; + phy-names = "usb-phy"; + phys = <&usb_hs_phy>; + status = "disabled"; + #reset-cells = <1>; + }; + + sdhc_3: mmc@7a24000 { + compatible = "qcom,msm8976-sdhci", "qcom,sdhci-msm-v4"; + reg = <0x07a24900 0x11c>, <0x07a24000 0x800>; + reg-names = "hc", "core"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC3_AHB_CLK>, + <&gcc GCC_SDCC3_APPS_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "iface", "core", "xo"; + + status = "disabled"; + }; + + blsp2_dma: dma-controller@7ac4000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0x07ac4000 0x1f000>; + interrupts = ; + clocks = <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + }; + + blsp2_uart2: serial@7af0000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x07af0000 0x200>; + interrupts = ; + clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp2_dma 0>, <&blsp2_dma 1>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + blsp2_i2c2: i2c@7af6000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x07af6000 0x600>; + interrupts = ; + clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; + clock-frequency = <400000>; + dmas = <&blsp2_dma 6>, <&blsp2_dma 7>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp2_i2c2_default>; + pinctrl-1 = <&blsp2_i2c2_sleep>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp2_i2c4: i2c@7af8000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x07af8000 0x600>; + interrupts = ; + clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; + clock-frequency = <400000>; + dmas = <&blsp2_dma 10>, <&blsp2_dma 11>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp2_i2c4_default>; + pinctrl-1 = <&blsp2_i2c4_sleep>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + intc: interrupt-controller@b000000 { + compatible = "qcom,msm-qgic2"; + reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>; + interrupt-controller; + #interrupt-cells = <3>; + }; + + apcs: mailbox@b011000 { + compatible = "qcom,msm8976-apcs-kpss-global", "syscon"; + reg = <0x0b011000 0x1000>; + #mbox-cells = <1>; + }; + + timer@b120000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x0b120000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clock-frequency = <19200000>; + + frame@b121000 { + reg = <0x0b121000 0x1000>, <0x0b122000 0x1000>; + interrupts = , + ; + frame-number = <0>; + }; + + frame@b123000 { + reg = <0x0b123000 0x1000>; + interrupts = ; + frame-number = <1>; + status = "disabled"; + }; + + frame@b124000 { + reg = <0x0b124000 0x1000>; + interrupts = ; + frame-number = <2>; + status = "disabled"; + }; + + frame@b125000 { + reg = <0x0b125000 0x1000>; + interrupts = ; + frame-number = <3>; + status = "disabled"; + }; + + frame@b126000 { + reg = <0x0b126000 0x1000>; + interrupts = ; + frame-number = <4>; + status = "disabled"; + }; + + frame@b127000 { + reg = <0x0b127000 0x1000>; + interrupts = ; + frame-number = <5>; + status = "disabled"; + }; + + frame@b128000 { + reg = <0x0b128000 0x1000>; + interrupts = ; + frame-number = <6>; + status = "disabled"; + }; + }; + + imem: sram@8600000 { + compatible = "qcom,msm8976-imem", "syscon", "simple-mfd"; + reg = <0x08600000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + ranges = <0 0x08600000 0x1000>; + + pil-reloc@94c { + compatible = "qcom,pil-reloc-info"; + reg = <0x94c 0xc8>; + }; + }; + }; + + thermal-zones { + aoss0-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 0>; + + trips { + aoss0_alert0: trip-point0 { + temperature = <75000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + modem-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 1>; + trips { + modem_alert0: trip-point0 { + temperature = <75000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + qdsp-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 2>; + trips { + qdsp_alert0: trip-point0 { + temperature = <75000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + cam-isp-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 3>; + trips { + cam_isp_alert0: trip-point0 { + temperature = <75000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + cpu4-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsens 4>; + + trips { + cpu4_alert0: trip-point0 { + temperature = <50000>; + hysteresis = <2000>; + type = "hot"; + }; + cpu4_alert1: trip-point1 { + temperature = <55000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu4_crit: cpu-crit { + temperature = <75000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpu5-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsens 5>; + + trips { + cpu5_alert0: trip-point0 { + temperature = <50000>; + hysteresis = <2000>; + type = "hot"; + }; + cpu5_alert1: trip-point1 { + temperature = <55000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu5_crit: cpu-crit { + temperature = <75000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpu6-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsens 6>; + + trips { + cpu6_alert0: trip-point0 { + temperature = <50000>; + hysteresis = <2000>; + type = "hot"; + }; + cpu6_alert1: trip-point1 { + temperature = <55000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu6_crit: cpu-crit { + temperature = <75000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpu7-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsens 7>; + + trips { + cpu7_alert0: trip-point0 { + temperature = <50000>; + hysteresis = <2000>; + type = "hot"; + }; + cpu7_alert1: trip-point1 { + temperature = <55000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu7_crit: cpu-crit { + temperature = <75000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + big-l2-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsens 8>; + + trips { + l2_alert0: trip-point0 { + temperature = <50000>; + hysteresis = <2000>; + type = "hot"; + }; + l2_alert1: trip-point1 { + temperature = <55000>; + hysteresis = <2000>; + type = "passive"; + }; + l2_crit: l2-crit { + temperature = <75000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpu0-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsens 9>; + + trips { + cpu0_alert0: trip-point0 { + temperature = <50000>; + hysteresis = <2000>; + type = "hot"; + }; + cpu0_alert1: trip-point1 { + temperature = <55000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu0_crit: cpu-crit { + temperature = <75000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + gpu-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsens 10>; + + trips { + gpu_alert0: trip-point0 { + temperature = <50000>; + hysteresis = <2000>; + type = "hot"; + }; + gpu_alert1: trip-point1 { + temperature = <55000>; + hysteresis = <2000>; + type = "passive"; + }; + gpu_crit: gpu-crit { + temperature = <75000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + clock-frequency = <19200000>; + }; +}; From patchwork Fri Nov 11 12:01:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 13040260 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EFE18C433FE for ; Fri, 11 Nov 2022 12:03:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233941AbiKKMDD (ORCPT ); Fri, 11 Nov 2022 07:03:03 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:32876 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233812AbiKKMCX (ORCPT ); Fri, 11 Nov 2022 07:02:23 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 94FED83BB5; Fri, 11 Nov 2022 04:02:19 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 0B8906602A75; Fri, 11 Nov 2022 12:02:17 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1668168138; bh=f4Aue5KIvWxSDWyXRdIF6E0zJ3fvnZG1mtColmLVY2I=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=I/hmnBqiY8GfIIALHWRg+cmglxp4u5NvP7Cj0eXI3efU7/W+4a3R+ZadY4sas1CAX Vzl2z+KgBbBgnMCJE+kvh3NxqzsZ2oXoNsFD33Szkw3mNsTnW1HC6nl6fL6KtC62ma dX0/cgayyN1mbIWXKV1qkjLmFUKd8GFXxF380vI0BNdEkS+ap3lq0f5gxQgHqOUXEN +P3A9kbpvPw3ixNp2qnmGamtrOxSYP2hiytwb5EsJVbtvjwrCVr3MCfH+XyUJsvoF7 Z1+siH+WaYfX/RCZ+d355nQ7XAhv9M7Ic/FnC6szU26LsBMy1LKq6Bc7tM9rKu3HEI ZDV7xFdBocRUQ== From: AngeloGioacchino Del Regno To: agross@kernel.org Cc: andersson@kernel.org, konrad.dybcio@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, jassisinghbrar@gmail.com, srinivas.kandagatla@linaro.org, jic23@kernel.org, lars@metafoo.de, keescook@chromium.org, tony.luck@intel.com, gpiccoli@igalia.com, evgreen@chromium.org, gregkh@linuxfoundation.org, a39.skl@gmail.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, linux-hardening@vger.kernel.org, marijn.suijten@somainline.org, kernel@collabora.com, luca@z3ntu.xyz, AngeloGioacchino Del Regno , Konrad Dybcio Subject: [PATCH v2 11/11] arm64: dts: qcom: Add support for SONY Xperia X/X Compact Date: Fri, 11 Nov 2022 13:01:56 +0100 Message-Id: <20221111120156.48040-12-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221111120156.48040-1-angelogioacchino.delregno@collabora.com> References: <20221111120156.48040-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-hardening@vger.kernel.org This adds support for the Sony Xperia Loire/SmartLoire platform with a base configuration that is common across all of the devices that are based on this project. Also adds a base DT configuration for the Xperia X and Xperia X Compact (respectively, Suzu and Kugo) which is valid for both their RoW (single-sim), DSDS (dual-sim) and other regional variants of these two smartphones, that makes us able to boot to a UART console. Please note that, currently, the APC0/1 (cluster 0/1) vregs are set to a safe voltage in order to ensure boot stability until a proper solution for CPU DVFS scaling lands. Co-developed-by: Konrad Dybcio Signed-off-by: Konrad Dybcio Co-developed-by: Marijn Suijten Signed-off-by: Marijn Suijten Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/qcom/Makefile | 2 + .../qcom/msm8956-sony-xperia-loire-kugo.dts | 35 +++ .../qcom/msm8956-sony-xperia-loire-suzu.dts | 17 ++ .../dts/qcom/msm8956-sony-xperia-loire.dtsi | 282 ++++++++++++++++++ 4 files changed, 336 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/msm8956-sony-xperia-loire-kugo.dts create mode 100644 arch/arm64/boot/dts/qcom/msm8956-sony-xperia-loire-suzu.dts create mode 100644 arch/arm64/boot/dts/qcom/msm8956-sony-xperia-loire.dtsi diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index d534888bcfe5..70ba5cb7d835 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -21,6 +21,8 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-grandmax.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-j5.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-serranove.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-wingtech-wt88047.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8956-sony-xperia-loire-kugo.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8956-sony-xperia-loire-suzu.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8992-lg-bullhead-rev-10.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8992-lg-bullhead-rev-101.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8992-msft-lumia-octagon-talkman.dtb diff --git a/arch/arm64/boot/dts/qcom/msm8956-sony-xperia-loire-kugo.dts b/arch/arm64/boot/dts/qcom/msm8956-sony-xperia-loire-kugo.dts new file mode 100644 index 000000000000..3fb8e23e4330 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8956-sony-xperia-loire-kugo.dts @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2016-2022, AngeloGioacchino Del Regno + * + * Copyright (c) 2022, Konrad Dybcio + * Copyright (c) 2022, Marijn Suijten + */ + +/dts-v1/; + +#include "msm8956-sony-xperia-loire.dtsi" + +/ { + model = "Sony Xperia X Compact"; + compatible = "sony,kugo-row", "qcom,msm8956"; + chassis-type = "handset"; +}; + +&blsp2_i2c2 { + status = "okay"; + + /* FUSB301 USB-C Controller */ +}; + +&blsp2_i2c4 { + status = "okay"; + + /* ST STMVL53L0 ToF @ 29 */ + /* AMS TCS349 RGBCIR @ 72 */ +}; + +&pm8950_l1 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8956-sony-xperia-loire-suzu.dts b/arch/arm64/boot/dts/qcom/msm8956-sony-xperia-loire-suzu.dts new file mode 100644 index 000000000000..87d657f6806b --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8956-sony-xperia-loire-suzu.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2016-2022, AngeloGioacchino Del Regno + * + * Copyright (c) 2022, Konrad Dybcio + * Copyright (c) 2022, Marijn Suijten + */ + +/dts-v1/; + +#include "msm8956-sony-xperia-loire.dtsi" + +/ { + model = "Sony Xperia X"; + compatible = "sony,suzu-row", "qcom,msm8956"; + chassis-type = "handset"; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8956-sony-xperia-loire.dtsi b/arch/arm64/boot/dts/qcom/msm8956-sony-xperia-loire.dtsi new file mode 100644 index 000000000000..67baced639c9 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8956-sony-xperia-loire.dtsi @@ -0,0 +1,282 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2016-2022, AngeloGioacchino Del Regno + * + * Copyright (c) 2022, Konrad Dybcio + * Copyright (c) 2022, Marijn Suijten + */ + +#include "msm8956.dtsi" + +#include "pm8004.dtsi" +#include "pm8950.dtsi" +#include "pmi8950.dtsi" + +/ { + qcom,msm-id = <266 0x10001>; /* MSM8956 v1.1 */ + qcom,board-id = <8 0>; + + aliases { + mmc0 = &sdhc_1; /* SDC1 eMMC slot */ + mmc1 = &sdhc_2; /* SDC2 SD card slot */ + mmc2 = &sdhc_3; /* SDC3 SDIO card slot */ + serial0 = &blsp2_uart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + reserved-memory { + cont-splash@83000000 { + reg = <0x0 0x83000000 0x0 0x2800000>; + }; + + ramoops@57f00000 { + compatible = "ramoops"; + reg = <0 0x57f00000 0 0x100000>; + record-size = <0x20000>; + console-size = <0x40000>; + ftrace-size = <0x20000>; + pmsg-size = <0x20000>; + ecc-size = <16>; + }; + }; + + usbphy_1p2: regulator-usbphy-1p2 { + compatible = "regulator-fixed"; + regulator-name = "usbphy-1p2"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + vin-supply = <&vph_pwr>; + }; + + vph_pwr: regulator-vph-pwr { + compatible = "regulator-fixed"; + regulator-name = "vph-pwr"; + regulator-always-on; + regulator-boot-on; + }; +}; + +&blsp1_i2c4 { + status = "okay"; + + /* Synaptics RMI4 @ 2c */ +}; + +&blsp2_uart2 { + status = "okay"; +}; + +&gcc { + vdd_gfx-supply = <&pm8004_s5>; +}; + +&otg { + status = "okay"; +}; + +&pm8004_spmi_regulators { + vdd_s2-supply = <&vph_pwr>; + vdd_s5-supply = <&vph_pwr>; + + /* Cluster 1 supply */ + pm8004_s2: s2 { + /* regulator-min-microvolt = <500000>; */ + /* Set .95V to prevent unstabilities until CPR for this SoC is done */ + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1165000>; + regulator-name = "vdd_apc1"; + /* Set always on until the CPU PLL is done */ + regulator-always-on; + regulator-boot-on; + }; + + pm8004_s5: s5 { + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1165000>; + regulator-enable-ramp-delay = <500>; + regulator-name = "vdd_gfx"; + /* Hack this on until the gpu driver is ready for it */ + regulator-always-on; + }; +}; + +&pm8950_spmi_regulators { + vdd_s5-supply = <&vph_pwr>; + + /* Cluster 0 supply */ + pm8950_spmi_s5: s5 { + /* Set .95V to prevent unstabilities until CPR for this SoC is done */ + /* regulator-min-microvolt = <790000>; */ + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1165000>; + regulator-name = "vdd_apc0"; + /* Set always on until the CPU PLL is done */ + regulator-always-on; + regulator-boot-on; + }; +}; + +&rpm_requests { + pm8950_regulators: regulators { + compatible = "qcom,rpm-pm8950-regulators"; + + vdd_s1-supply = <&vph_pwr>; + vdd_s2-supply = <&vph_pwr>; + vdd_s3-supply = <&vph_pwr>; + vdd_s4-supply = <&vph_pwr>; + vdd_s6-supply = <&vph_pwr>; + vdd_l1_l19-supply = <&pm8950_s3>; + vdd_l2_l23-supply = <&pm8950_s3>; + vdd_l3-supply = <&pm8950_s3>; + vdd_l5_l6_l7_l16-supply = <&pm8950_s4>; + vdd_l8_l11_l12_l17_l22-supply = <&vph_pwr>; + + pm8950_s1: s1 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1162500>; + }; + + pm8950_s3: s3 { + regulator-min-microvolt = <1325000>; + regulator-max-microvolt = <1325000>; + regulator-always-on; + }; + + pm8950_s4: s4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + pm8950_l1: l1 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1100000>; + }; + + pm8950_l2: l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + pm8950_l3: l3 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1200000>; + }; + + pm8950_l5: l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-system-load = <290000>; + regulator-allow-set-load; + }; + + pm8950_l6: l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8950_l7: l7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8950_l8: l8 { + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + regulator-system-load = <130000>; + regulator-allow-set-load; + }; + + pm8950_l9: l9 { + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2400000>; + }; + + pm8950_l10: l10 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2900000>; + }; + + pm8950_l11: l11 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + regulator-system-load = <60000>; + regulator-allow-set-load; + }; + + pm8950_l12: l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + regulator-system-load = <100000>; + regulator-allow-set-load; + }; + + pm8950_l13: l13 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + }; + + pm8950_l14: l14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + pm8950_l15: l15 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + pm8950_l16: l16 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8950_l17: l17 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2900000>; + }; + + pm8950_l22: l22 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + pm8950_l23: l23 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + }; +}; + +&sdhc_1 { + /* Toshiba THGBMHG8C4LBAU7 (032G34) */ + bus-width = <8>; + non-removable; + vmmc-supply = <&pm8950_l8>; + vqmmc-supply = <&pm8950_l5>; + status = "okay"; +}; + +&sdhc_2 { + bus-width = <4>; + cd-gpios = <&tlmm 100 GPIO_ACTIVE_HIGH>; + vmmc-supply = <&pm8950_l11>; + vqmmc-supply = <&pm8950_l12>; + status = "okay"; +}; + +&tlmm { + gpio-reserved-ranges = <0 4>; +}; + +&usb_hs_phy { + vdd-supply = <&usbphy_1p2>; + vdda1p8-supply = <&pm8950_l7>; + vdda3p3-supply = <&pm8950_l13>; + status = "okay"; +};